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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i8_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vsrl.vv v8, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8.nxv1i8(15 <vscale x 1 x i8> poison,16 <vscale x 1 x i8> %0,17 <vscale x 1 x i8> %1,18 iXLen %2)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i8_nxv1i8_nxv1i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu27; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8.nxv1i8(31 <vscale x 1 x i8> %0,32 <vscale x 1 x i8> %1,33 <vscale x 1 x i8> %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x i8> %a38}39 40define <vscale x 2 x i8> @intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i8_nxv2i8_nxv2i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma44; CHECK-NEXT: vsrl.vv v8, v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8.nxv2i8(48 <vscale x 2 x i8> poison,49 <vscale x 2 x i8> %0,50 <vscale x 2 x i8> %1,51 iXLen %2)52 53 ret <vscale x 2 x i8> %a54}55 56define <vscale x 2 x i8> @intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i8_nxv2i8_nxv2i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu60; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8.nxv2i8(64 <vscale x 2 x i8> %0,65 <vscale x 2 x i8> %1,66 <vscale x 2 x i8> %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x i8> %a71}72 73define <vscale x 4 x i8> @intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i8_nxv4i8_nxv4i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma77; CHECK-NEXT: vsrl.vv v8, v8, v978; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8.nxv4i8(81 <vscale x 4 x i8> poison,82 <vscale x 4 x i8> %0,83 <vscale x 4 x i8> %1,84 iXLen %2)85 86 ret <vscale x 4 x i8> %a87}88 89define <vscale x 4 x i8> @intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i8_nxv4i8_nxv4i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu93; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8.nxv4i8(97 <vscale x 4 x i8> %0,98 <vscale x 4 x i8> %1,99 <vscale x 4 x i8> %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i8_nxv8i8_nxv8i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma110; CHECK-NEXT: vsrl.vv v8, v8, v9111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8.nxv8i8(114 <vscale x 8 x i8> poison,115 <vscale x 8 x i8> %0,116 <vscale x 8 x i8> %1,117 iXLen %2)118 119 ret <vscale x 8 x i8> %a120}121 122define <vscale x 8 x i8> @intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i8_nxv8i8_nxv8i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu126; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8.nxv8i8(130 <vscale x 8 x i8> %0,131 <vscale x 8 x i8> %1,132 <vscale x 8 x i8> %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 1)135 136 ret <vscale x 8 x i8> %a137}138 139define <vscale x 16 x i8> @intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i8_nxv16i8_nxv16i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma143; CHECK-NEXT: vsrl.vv v8, v8, v10144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8.nxv16i8(147 <vscale x 16 x i8> poison,148 <vscale x 16 x i8> %0,149 <vscale x 16 x i8> %1,150 iXLen %2)151 152 ret <vscale x 16 x i8> %a153}154 155define <vscale x 16 x i8> @intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i8_nxv16i8_nxv16i8:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu159; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8.nxv16i8(163 <vscale x 16 x i8> %0,164 <vscale x 16 x i8> %1,165 <vscale x 16 x i8> %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 1)168 169 ret <vscale x 16 x i8> %a170}171 172define <vscale x 32 x i8> @intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i8_nxv32i8_nxv32i8:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma176; CHECK-NEXT: vsrl.vv v8, v8, v12177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8.nxv32i8(180 <vscale x 32 x i8> poison,181 <vscale x 32 x i8> %0,182 <vscale x 32 x i8> %1,183 iXLen %2)184 185 ret <vscale x 32 x i8> %a186}187 188define <vscale x 32 x i8> @intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i8_nxv32i8_nxv32i8:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu192; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8.nxv32i8(196 <vscale x 32 x i8> %0,197 <vscale x 32 x i8> %1,198 <vscale x 32 x i8> %2,199 <vscale x 32 x i1> %3,200 iXLen %4, iXLen 1)201 202 ret <vscale x 32 x i8> %a203}204 205define <vscale x 64 x i8> @intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {206; CHECK-LABEL: intrinsic_vsrl_vv_nxv64i8_nxv64i8_nxv64i8:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma209; CHECK-NEXT: vsrl.vv v8, v8, v16210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8.nxv64i8(213 <vscale x 64 x i8> poison,214 <vscale x 64 x i8> %0,215 <vscale x 64 x i8> %1,216 iXLen %2)217 218 ret <vscale x 64 x i8> %a219}220 221define <vscale x 64 x i8> @intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv64i8_nxv64i8_nxv64i8:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vl8r.v v24, (a0)225; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu226; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t227; CHECK-NEXT: ret228entry:229 %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8.nxv64i8(230 <vscale x 64 x i8> %0,231 <vscale x 64 x i8> %1,232 <vscale x 64 x i8> %2,233 <vscale x 64 x i1> %3,234 iXLen %4, iXLen 1)235 236 ret <vscale x 64 x i8> %a237}238 239define <vscale x 1 x i16> @intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {240; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i16_nxv1i16_nxv1i16:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma243; CHECK-NEXT: vsrl.vv v8, v8, v9244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16.nxv1i16(247 <vscale x 1 x i16> poison,248 <vscale x 1 x i16> %0,249 <vscale x 1 x i16> %1,250 iXLen %2)251 252 ret <vscale x 1 x i16> %a253}254 255define <vscale x 1 x i16> @intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {256; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i16_nxv1i16_nxv1i16:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu259; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16.nxv1i16(263 <vscale x 1 x i16> %0,264 <vscale x 1 x i16> %1,265 <vscale x 1 x i16> %2,266 <vscale x 1 x i1> %3,267 iXLen %4, iXLen 1)268 269 ret <vscale x 1 x i16> %a270}271 272define <vscale x 2 x i16> @intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {273; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i16_nxv2i16_nxv2i16:274; CHECK: # %bb.0: # %entry275; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma276; CHECK-NEXT: vsrl.vv v8, v8, v9277; CHECK-NEXT: ret278entry:279 %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16.nxv2i16(280 <vscale x 2 x i16> poison,281 <vscale x 2 x i16> %0,282 <vscale x 2 x i16> %1,283 iXLen %2)284 285 ret <vscale x 2 x i16> %a286}287 288define <vscale x 2 x i16> @intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {289; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i16_nxv2i16_nxv2i16:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu292; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t293; CHECK-NEXT: ret294entry:295 %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16.nxv2i16(296 <vscale x 2 x i16> %0,297 <vscale x 2 x i16> %1,298 <vscale x 2 x i16> %2,299 <vscale x 2 x i1> %3,300 iXLen %4, iXLen 1)301 302 ret <vscale x 2 x i16> %a303}304 305define <vscale x 4 x i16> @intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {306; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i16_nxv4i16_nxv4i16:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma309; CHECK-NEXT: vsrl.vv v8, v8, v9310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16.nxv4i16(313 <vscale x 4 x i16> poison,314 <vscale x 4 x i16> %0,315 <vscale x 4 x i16> %1,316 iXLen %2)317 318 ret <vscale x 4 x i16> %a319}320 321define <vscale x 4 x i16> @intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i16_nxv4i16_nxv4i16:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu325; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t326; CHECK-NEXT: ret327entry:328 %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16.nxv4i16(329 <vscale x 4 x i16> %0,330 <vscale x 4 x i16> %1,331 <vscale x 4 x i16> %2,332 <vscale x 4 x i1> %3,333 iXLen %4, iXLen 1)334 335 ret <vscale x 4 x i16> %a336}337 338define <vscale x 8 x i16> @intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {339; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i16_nxv8i16_nxv8i16:340; CHECK: # %bb.0: # %entry341; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma342; CHECK-NEXT: vsrl.vv v8, v8, v10343; CHECK-NEXT: ret344entry:345 %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16.nxv8i16(346 <vscale x 8 x i16> poison,347 <vscale x 8 x i16> %0,348 <vscale x 8 x i16> %1,349 iXLen %2)350 351 ret <vscale x 8 x i16> %a352}353 354define <vscale x 8 x i16> @intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {355; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i16_nxv8i16_nxv8i16:356; CHECK: # %bb.0: # %entry357; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu358; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t359; CHECK-NEXT: ret360entry:361 %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16.nxv8i16(362 <vscale x 8 x i16> %0,363 <vscale x 8 x i16> %1,364 <vscale x 8 x i16> %2,365 <vscale x 8 x i1> %3,366 iXLen %4, iXLen 1)367 368 ret <vscale x 8 x i16> %a369}370 371define <vscale x 16 x i16> @intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {372; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i16_nxv16i16_nxv16i16:373; CHECK: # %bb.0: # %entry374; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma375; CHECK-NEXT: vsrl.vv v8, v8, v12376; CHECK-NEXT: ret377entry:378 %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16.nxv16i16(379 <vscale x 16 x i16> poison,380 <vscale x 16 x i16> %0,381 <vscale x 16 x i16> %1,382 iXLen %2)383 384 ret <vscale x 16 x i16> %a385}386 387define <vscale x 16 x i16> @intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {388; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i16_nxv16i16_nxv16i16:389; CHECK: # %bb.0: # %entry390; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu391; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t392; CHECK-NEXT: ret393entry:394 %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16.nxv16i16(395 <vscale x 16 x i16> %0,396 <vscale x 16 x i16> %1,397 <vscale x 16 x i16> %2,398 <vscale x 16 x i1> %3,399 iXLen %4, iXLen 1)400 401 ret <vscale x 16 x i16> %a402}403 404define <vscale x 32 x i16> @intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {405; CHECK-LABEL: intrinsic_vsrl_vv_nxv32i16_nxv32i16_nxv32i16:406; CHECK: # %bb.0: # %entry407; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma408; CHECK-NEXT: vsrl.vv v8, v8, v16409; CHECK-NEXT: ret410entry:411 %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16.nxv32i16(412 <vscale x 32 x i16> poison,413 <vscale x 32 x i16> %0,414 <vscale x 32 x i16> %1,415 iXLen %2)416 417 ret <vscale x 32 x i16> %a418}419 420define <vscale x 32 x i16> @intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {421; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv32i16_nxv32i16_nxv32i16:422; CHECK: # %bb.0: # %entry423; CHECK-NEXT: vl8re16.v v24, (a0)424; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu425; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t426; CHECK-NEXT: ret427entry:428 %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16.nxv32i16(429 <vscale x 32 x i16> %0,430 <vscale x 32 x i16> %1,431 <vscale x 32 x i16> %2,432 <vscale x 32 x i1> %3,433 iXLen %4, iXLen 1)434 435 ret <vscale x 32 x i16> %a436}437 438define <vscale x 1 x i32> @intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {439; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i32_nxv1i32_nxv1i32:440; CHECK: # %bb.0: # %entry441; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma442; CHECK-NEXT: vsrl.vv v8, v8, v9443; CHECK-NEXT: ret444entry:445 %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32.nxv1i32(446 <vscale x 1 x i32> poison,447 <vscale x 1 x i32> %0,448 <vscale x 1 x i32> %1,449 iXLen %2)450 451 ret <vscale x 1 x i32> %a452}453 454define <vscale x 1 x i32> @intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {455; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i32_nxv1i32_nxv1i32:456; CHECK: # %bb.0: # %entry457; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu458; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t459; CHECK-NEXT: ret460entry:461 %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32.nxv1i32(462 <vscale x 1 x i32> %0,463 <vscale x 1 x i32> %1,464 <vscale x 1 x i32> %2,465 <vscale x 1 x i1> %3,466 iXLen %4, iXLen 1)467 468 ret <vscale x 1 x i32> %a469}470 471define <vscale x 2 x i32> @intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {472; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i32_nxv2i32_nxv2i32:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma475; CHECK-NEXT: vsrl.vv v8, v8, v9476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32.nxv2i32(479 <vscale x 2 x i32> poison,480 <vscale x 2 x i32> %0,481 <vscale x 2 x i32> %1,482 iXLen %2)483 484 ret <vscale x 2 x i32> %a485}486 487define <vscale x 2 x i32> @intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {488; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i32_nxv2i32_nxv2i32:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu491; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t492; CHECK-NEXT: ret493entry:494 %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32.nxv2i32(495 <vscale x 2 x i32> %0,496 <vscale x 2 x i32> %1,497 <vscale x 2 x i32> %2,498 <vscale x 2 x i1> %3,499 iXLen %4, iXLen 1)500 501 ret <vscale x 2 x i32> %a502}503 504define <vscale x 4 x i32> @intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {505; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i32_nxv4i32_nxv4i32:506; CHECK: # %bb.0: # %entry507; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma508; CHECK-NEXT: vsrl.vv v8, v8, v10509; CHECK-NEXT: ret510entry:511 %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32.nxv4i32(512 <vscale x 4 x i32> poison,513 <vscale x 4 x i32> %0,514 <vscale x 4 x i32> %1,515 iXLen %2)516 517 ret <vscale x 4 x i32> %a518}519 520define <vscale x 4 x i32> @intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {521; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i32_nxv4i32_nxv4i32:522; CHECK: # %bb.0: # %entry523; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu524; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t525; CHECK-NEXT: ret526entry:527 %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32.nxv4i32(528 <vscale x 4 x i32> %0,529 <vscale x 4 x i32> %1,530 <vscale x 4 x i32> %2,531 <vscale x 4 x i1> %3,532 iXLen %4, iXLen 1)533 534 ret <vscale x 4 x i32> %a535}536 537define <vscale x 8 x i32> @intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {538; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i32_nxv8i32_nxv8i32:539; CHECK: # %bb.0: # %entry540; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma541; CHECK-NEXT: vsrl.vv v8, v8, v12542; CHECK-NEXT: ret543entry:544 %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32.nxv8i32(545 <vscale x 8 x i32> poison,546 <vscale x 8 x i32> %0,547 <vscale x 8 x i32> %1,548 iXLen %2)549 550 ret <vscale x 8 x i32> %a551}552 553define <vscale x 8 x i32> @intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {554; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i32_nxv8i32_nxv8i32:555; CHECK: # %bb.0: # %entry556; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu557; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t558; CHECK-NEXT: ret559entry:560 %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32.nxv8i32(561 <vscale x 8 x i32> %0,562 <vscale x 8 x i32> %1,563 <vscale x 8 x i32> %2,564 <vscale x 8 x i1> %3,565 iXLen %4, iXLen 1)566 567 ret <vscale x 8 x i32> %a568}569 570define <vscale x 16 x i32> @intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {571; CHECK-LABEL: intrinsic_vsrl_vv_nxv16i32_nxv16i32_nxv16i32:572; CHECK: # %bb.0: # %entry573; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma574; CHECK-NEXT: vsrl.vv v8, v8, v16575; CHECK-NEXT: ret576entry:577 %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32.nxv16i32(578 <vscale x 16 x i32> poison,579 <vscale x 16 x i32> %0,580 <vscale x 16 x i32> %1,581 iXLen %2)582 583 ret <vscale x 16 x i32> %a584}585 586define <vscale x 16 x i32> @intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {587; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv16i32_nxv16i32_nxv16i32:588; CHECK: # %bb.0: # %entry589; CHECK-NEXT: vl8re32.v v24, (a0)590; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu591; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t592; CHECK-NEXT: ret593entry:594 %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32.nxv16i32(595 <vscale x 16 x i32> %0,596 <vscale x 16 x i32> %1,597 <vscale x 16 x i32> %2,598 <vscale x 16 x i1> %3,599 iXLen %4, iXLen 1)600 601 ret <vscale x 16 x i32> %a602}603 604define <vscale x 1 x i64> @intrinsic_vsrl_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {605; CHECK-LABEL: intrinsic_vsrl_vv_nxv1i64_nxv1i64_nxv1i64:606; CHECK: # %bb.0: # %entry607; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma608; CHECK-NEXT: vsrl.vv v8, v8, v9609; CHECK-NEXT: ret610entry:611 %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64.nxv1i64(612 <vscale x 1 x i64> poison,613 <vscale x 1 x i64> %0,614 <vscale x 1 x i64> %1,615 iXLen %2)616 617 ret <vscale x 1 x i64> %a618}619 620define <vscale x 1 x i64> @intrinsic_vsrl_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {621; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv1i64_nxv1i64_nxv1i64:622; CHECK: # %bb.0: # %entry623; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu624; CHECK-NEXT: vsrl.vv v8, v9, v10, v0.t625; CHECK-NEXT: ret626entry:627 %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64.nxv1i64(628 <vscale x 1 x i64> %0,629 <vscale x 1 x i64> %1,630 <vscale x 1 x i64> %2,631 <vscale x 1 x i1> %3,632 iXLen %4, iXLen 1)633 634 ret <vscale x 1 x i64> %a635}636 637define <vscale x 2 x i64> @intrinsic_vsrl_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {638; CHECK-LABEL: intrinsic_vsrl_vv_nxv2i64_nxv2i64_nxv2i64:639; CHECK: # %bb.0: # %entry640; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma641; CHECK-NEXT: vsrl.vv v8, v8, v10642; CHECK-NEXT: ret643entry:644 %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64.nxv2i64(645 <vscale x 2 x i64> poison,646 <vscale x 2 x i64> %0,647 <vscale x 2 x i64> %1,648 iXLen %2)649 650 ret <vscale x 2 x i64> %a651}652 653define <vscale x 2 x i64> @intrinsic_vsrl_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {654; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv2i64_nxv2i64_nxv2i64:655; CHECK: # %bb.0: # %entry656; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu657; CHECK-NEXT: vsrl.vv v8, v10, v12, v0.t658; CHECK-NEXT: ret659entry:660 %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64.nxv2i64(661 <vscale x 2 x i64> %0,662 <vscale x 2 x i64> %1,663 <vscale x 2 x i64> %2,664 <vscale x 2 x i1> %3,665 iXLen %4, iXLen 1)666 667 ret <vscale x 2 x i64> %a668}669 670define <vscale x 4 x i64> @intrinsic_vsrl_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vsrl_vv_nxv4i64_nxv4i64_nxv4i64:672; CHECK: # %bb.0: # %entry673; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma674; CHECK-NEXT: vsrl.vv v8, v8, v12675; CHECK-NEXT: ret676entry:677 %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64.nxv4i64(678 <vscale x 4 x i64> poison,679 <vscale x 4 x i64> %0,680 <vscale x 4 x i64> %1,681 iXLen %2)682 683 ret <vscale x 4 x i64> %a684}685 686define <vscale x 4 x i64> @intrinsic_vsrl_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {687; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv4i64_nxv4i64_nxv4i64:688; CHECK: # %bb.0: # %entry689; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu690; CHECK-NEXT: vsrl.vv v8, v12, v16, v0.t691; CHECK-NEXT: ret692entry:693 %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64.nxv4i64(694 <vscale x 4 x i64> %0,695 <vscale x 4 x i64> %1,696 <vscale x 4 x i64> %2,697 <vscale x 4 x i1> %3,698 iXLen %4, iXLen 1)699 700 ret <vscale x 4 x i64> %a701}702 703define <vscale x 8 x i64> @intrinsic_vsrl_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {704; CHECK-LABEL: intrinsic_vsrl_vv_nxv8i64_nxv8i64_nxv8i64:705; CHECK: # %bb.0: # %entry706; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma707; CHECK-NEXT: vsrl.vv v8, v8, v16708; CHECK-NEXT: ret709entry:710 %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64.nxv8i64(711 <vscale x 8 x i64> poison,712 <vscale x 8 x i64> %0,713 <vscale x 8 x i64> %1,714 iXLen %2)715 716 ret <vscale x 8 x i64> %a717}718 719define <vscale x 8 x i64> @intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {720; CHECK-LABEL: intrinsic_vsrl_mask_vv_nxv8i64_nxv8i64_nxv8i64:721; CHECK: # %bb.0: # %entry722; CHECK-NEXT: vl8re64.v v24, (a0)723; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu724; CHECK-NEXT: vsrl.vv v8, v16, v24, v0.t725; CHECK-NEXT: ret726entry:727 %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64.nxv8i64(728 <vscale x 8 x i64> %0,729 <vscale x 8 x i64> %1,730 <vscale x 8 x i64> %2,731 <vscale x 8 x i1> %3,732 iXLen %4, iXLen 1)733 734 ret <vscale x 8 x i64> %a735}736 737define <vscale x 1 x i8> @intrinsic_vsrl_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, iXLen %2) nounwind {738; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i8_nxv1i8:739; CHECK: # %bb.0: # %entry740; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma741; CHECK-NEXT: vsrl.vx v8, v8, a0742; CHECK-NEXT: ret743entry:744 %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(745 <vscale x 1 x i8> poison,746 <vscale x 1 x i8> %0,747 iXLen %1,748 iXLen %2)749 750 ret <vscale x 1 x i8> %a751}752 753define <vscale x 1 x i8> @intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {754; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i8_nxv1i8:755; CHECK: # %bb.0: # %entry756; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu757; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t758; CHECK-NEXT: ret759entry:760 %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(761 <vscale x 1 x i8> %0,762 <vscale x 1 x i8> %1,763 iXLen %2,764 <vscale x 1 x i1> %3,765 iXLen %4, iXLen 1)766 767 ret <vscale x 1 x i8> %a768}769 770define <vscale x 2 x i8> @intrinsic_vsrl_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, iXLen %1, iXLen %2) nounwind {771; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i8_nxv2i8:772; CHECK: # %bb.0: # %entry773; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma774; CHECK-NEXT: vsrl.vx v8, v8, a0775; CHECK-NEXT: ret776entry:777 %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(778 <vscale x 2 x i8> poison,779 <vscale x 2 x i8> %0,780 iXLen %1,781 iXLen %2)782 783 ret <vscale x 2 x i8> %a784}785 786define <vscale x 2 x i8> @intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {787; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i8_nxv2i8:788; CHECK: # %bb.0: # %entry789; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu790; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t791; CHECK-NEXT: ret792entry:793 %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(794 <vscale x 2 x i8> %0,795 <vscale x 2 x i8> %1,796 iXLen %2,797 <vscale x 2 x i1> %3,798 iXLen %4, iXLen 1)799 800 ret <vscale x 2 x i8> %a801}802 803define <vscale x 4 x i8> @intrinsic_vsrl_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, iXLen %1, iXLen %2) nounwind {804; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i8_nxv4i8:805; CHECK: # %bb.0: # %entry806; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma807; CHECK-NEXT: vsrl.vx v8, v8, a0808; CHECK-NEXT: ret809entry:810 %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(811 <vscale x 4 x i8> poison,812 <vscale x 4 x i8> %0,813 iXLen %1,814 iXLen %2)815 816 ret <vscale x 4 x i8> %a817}818 819define <vscale x 4 x i8> @intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {820; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i8_nxv4i8:821; CHECK: # %bb.0: # %entry822; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu823; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t824; CHECK-NEXT: ret825entry:826 %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(827 <vscale x 4 x i8> %0,828 <vscale x 4 x i8> %1,829 iXLen %2,830 <vscale x 4 x i1> %3,831 iXLen %4, iXLen 1)832 833 ret <vscale x 4 x i8> %a834}835 836define <vscale x 8 x i8> @intrinsic_vsrl_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, iXLen %1, iXLen %2) nounwind {837; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i8_nxv8i8:838; CHECK: # %bb.0: # %entry839; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma840; CHECK-NEXT: vsrl.vx v8, v8, a0841; CHECK-NEXT: ret842entry:843 %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(844 <vscale x 8 x i8> poison,845 <vscale x 8 x i8> %0,846 iXLen %1,847 iXLen %2)848 849 ret <vscale x 8 x i8> %a850}851 852define <vscale x 8 x i8> @intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {853; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i8_nxv8i8:854; CHECK: # %bb.0: # %entry855; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu856; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t857; CHECK-NEXT: ret858entry:859 %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(860 <vscale x 8 x i8> %0,861 <vscale x 8 x i8> %1,862 iXLen %2,863 <vscale x 8 x i1> %3,864 iXLen %4, iXLen 1)865 866 ret <vscale x 8 x i8> %a867}868 869define <vscale x 16 x i8> @intrinsic_vsrl_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, iXLen %1, iXLen %2) nounwind {870; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i8_nxv16i8:871; CHECK: # %bb.0: # %entry872; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma873; CHECK-NEXT: vsrl.vx v8, v8, a0874; CHECK-NEXT: ret875entry:876 %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(877 <vscale x 16 x i8> poison,878 <vscale x 16 x i8> %0,879 iXLen %1,880 iXLen %2)881 882 ret <vscale x 16 x i8> %a883}884 885define <vscale x 16 x i8> @intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {886; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i8_nxv16i8:887; CHECK: # %bb.0: # %entry888; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu889; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t890; CHECK-NEXT: ret891entry:892 %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(893 <vscale x 16 x i8> %0,894 <vscale x 16 x i8> %1,895 iXLen %2,896 <vscale x 16 x i1> %3,897 iXLen %4, iXLen 1)898 899 ret <vscale x 16 x i8> %a900}901 902define <vscale x 32 x i8> @intrinsic_vsrl_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, iXLen %1, iXLen %2) nounwind {903; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i8_nxv32i8:904; CHECK: # %bb.0: # %entry905; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma906; CHECK-NEXT: vsrl.vx v8, v8, a0907; CHECK-NEXT: ret908entry:909 %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(910 <vscale x 32 x i8> poison,911 <vscale x 32 x i8> %0,912 iXLen %1,913 iXLen %2)914 915 ret <vscale x 32 x i8> %a916}917 918define <vscale x 32 x i8> @intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {919; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i8_nxv32i8:920; CHECK: # %bb.0: # %entry921; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu922; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t923; CHECK-NEXT: ret924entry:925 %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(926 <vscale x 32 x i8> %0,927 <vscale x 32 x i8> %1,928 iXLen %2,929 <vscale x 32 x i1> %3,930 iXLen %4, iXLen 1)931 932 ret <vscale x 32 x i8> %a933}934 935define <vscale x 64 x i8> @intrinsic_vsrl_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, iXLen %1, iXLen %2) nounwind {936; CHECK-LABEL: intrinsic_vsrl_vx_nxv64i8_nxv64i8:937; CHECK: # %bb.0: # %entry938; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma939; CHECK-NEXT: vsrl.vx v8, v8, a0940; CHECK-NEXT: ret941entry:942 %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(943 <vscale x 64 x i8> poison,944 <vscale x 64 x i8> %0,945 iXLen %1,946 iXLen %2)947 948 ret <vscale x 64 x i8> %a949}950 951define <vscale x 64 x i8> @intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {952; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv64i8_nxv64i8:953; CHECK: # %bb.0: # %entry954; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu955; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t956; CHECK-NEXT: ret957entry:958 %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(959 <vscale x 64 x i8> %0,960 <vscale x 64 x i8> %1,961 iXLen %2,962 <vscale x 64 x i1> %3,963 iXLen %4, iXLen 1)964 965 ret <vscale x 64 x i8> %a966}967 968define <vscale x 1 x i16> @intrinsic_vsrl_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1, iXLen %2) nounwind {969; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i16_nxv1i16:970; CHECK: # %bb.0: # %entry971; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma972; CHECK-NEXT: vsrl.vx v8, v8, a0973; CHECK-NEXT: ret974entry:975 %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(976 <vscale x 1 x i16> poison,977 <vscale x 1 x i16> %0,978 iXLen %1,979 iXLen %2)980 981 ret <vscale x 1 x i16> %a982}983 984define <vscale x 1 x i16> @intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {985; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i16_nxv1i16:986; CHECK: # %bb.0: # %entry987; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu988; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t989; CHECK-NEXT: ret990entry:991 %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(992 <vscale x 1 x i16> %0,993 <vscale x 1 x i16> %1,994 iXLen %2,995 <vscale x 1 x i1> %3,996 iXLen %4, iXLen 1)997 998 ret <vscale x 1 x i16> %a999}1000 1001define <vscale x 2 x i16> @intrinsic_vsrl_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1, iXLen %2) nounwind {1002; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i16_nxv2i16:1003; CHECK: # %bb.0: # %entry1004; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1005; CHECK-NEXT: vsrl.vx v8, v8, a01006; CHECK-NEXT: ret1007entry:1008 %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(1009 <vscale x 2 x i16> poison,1010 <vscale x 2 x i16> %0,1011 iXLen %1,1012 iXLen %2)1013 1014 ret <vscale x 2 x i16> %a1015}1016 1017define <vscale x 2 x i16> @intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1018; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i16_nxv2i16:1019; CHECK: # %bb.0: # %entry1020; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1021; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t1022; CHECK-NEXT: ret1023entry:1024 %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(1025 <vscale x 2 x i16> %0,1026 <vscale x 2 x i16> %1,1027 iXLen %2,1028 <vscale x 2 x i1> %3,1029 iXLen %4, iXLen 1)1030 1031 ret <vscale x 2 x i16> %a1032}1033 1034define <vscale x 4 x i16> @intrinsic_vsrl_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1, iXLen %2) nounwind {1035; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i16_nxv4i16:1036; CHECK: # %bb.0: # %entry1037; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1038; CHECK-NEXT: vsrl.vx v8, v8, a01039; CHECK-NEXT: ret1040entry:1041 %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(1042 <vscale x 4 x i16> poison,1043 <vscale x 4 x i16> %0,1044 iXLen %1,1045 iXLen %2)1046 1047 ret <vscale x 4 x i16> %a1048}1049 1050define <vscale x 4 x i16> @intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1051; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i16_nxv4i16:1052; CHECK: # %bb.0: # %entry1053; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1054; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t1055; CHECK-NEXT: ret1056entry:1057 %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(1058 <vscale x 4 x i16> %0,1059 <vscale x 4 x i16> %1,1060 iXLen %2,1061 <vscale x 4 x i1> %3,1062 iXLen %4, iXLen 1)1063 1064 ret <vscale x 4 x i16> %a1065}1066 1067define <vscale x 8 x i16> @intrinsic_vsrl_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1, iXLen %2) nounwind {1068; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i16_nxv8i16:1069; CHECK: # %bb.0: # %entry1070; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1071; CHECK-NEXT: vsrl.vx v8, v8, a01072; CHECK-NEXT: ret1073entry:1074 %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(1075 <vscale x 8 x i16> poison,1076 <vscale x 8 x i16> %0,1077 iXLen %1,1078 iXLen %2)1079 1080 ret <vscale x 8 x i16> %a1081}1082 1083define <vscale x 8 x i16> @intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1084; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i16_nxv8i16:1085; CHECK: # %bb.0: # %entry1086; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1087; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t1088; CHECK-NEXT: ret1089entry:1090 %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(1091 <vscale x 8 x i16> %0,1092 <vscale x 8 x i16> %1,1093 iXLen %2,1094 <vscale x 8 x i1> %3,1095 iXLen %4, iXLen 1)1096 1097 ret <vscale x 8 x i16> %a1098}1099 1100define <vscale x 16 x i16> @intrinsic_vsrl_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1, iXLen %2) nounwind {1101; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i16_nxv16i16:1102; CHECK: # %bb.0: # %entry1103; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1104; CHECK-NEXT: vsrl.vx v8, v8, a01105; CHECK-NEXT: ret1106entry:1107 %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(1108 <vscale x 16 x i16> poison,1109 <vscale x 16 x i16> %0,1110 iXLen %1,1111 iXLen %2)1112 1113 ret <vscale x 16 x i16> %a1114}1115 1116define <vscale x 16 x i16> @intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1117; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i16_nxv16i16:1118; CHECK: # %bb.0: # %entry1119; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1120; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t1121; CHECK-NEXT: ret1122entry:1123 %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(1124 <vscale x 16 x i16> %0,1125 <vscale x 16 x i16> %1,1126 iXLen %2,1127 <vscale x 16 x i1> %3,1128 iXLen %4, iXLen 1)1129 1130 ret <vscale x 16 x i16> %a1131}1132 1133define <vscale x 32 x i16> @intrinsic_vsrl_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1, iXLen %2) nounwind {1134; CHECK-LABEL: intrinsic_vsrl_vx_nxv32i16_nxv32i16:1135; CHECK: # %bb.0: # %entry1136; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1137; CHECK-NEXT: vsrl.vx v8, v8, a01138; CHECK-NEXT: ret1139entry:1140 %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(1141 <vscale x 32 x i16> poison,1142 <vscale x 32 x i16> %0,1143 iXLen %1,1144 iXLen %2)1145 1146 ret <vscale x 32 x i16> %a1147}1148 1149define <vscale x 32 x i16> @intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1150; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv32i16_nxv32i16:1151; CHECK: # %bb.0: # %entry1152; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu1153; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t1154; CHECK-NEXT: ret1155entry:1156 %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(1157 <vscale x 32 x i16> %0,1158 <vscale x 32 x i16> %1,1159 iXLen %2,1160 <vscale x 32 x i1> %3,1161 iXLen %4, iXLen 1)1162 1163 ret <vscale x 32 x i16> %a1164}1165 1166define <vscale x 1 x i32> @intrinsic_vsrl_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1, iXLen %2) nounwind {1167; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i32_nxv1i32:1168; CHECK: # %bb.0: # %entry1169; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1170; CHECK-NEXT: vsrl.vx v8, v8, a01171; CHECK-NEXT: ret1172entry:1173 %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(1174 <vscale x 1 x i32> poison,1175 <vscale x 1 x i32> %0,1176 iXLen %1,1177 iXLen %2)1178 1179 ret <vscale x 1 x i32> %a1180}1181 1182define <vscale x 1 x i32> @intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1183; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i32_nxv1i32:1184; CHECK: # %bb.0: # %entry1185; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1186; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t1187; CHECK-NEXT: ret1188entry:1189 %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(1190 <vscale x 1 x i32> %0,1191 <vscale x 1 x i32> %1,1192 iXLen %2,1193 <vscale x 1 x i1> %3,1194 iXLen %4, iXLen 1)1195 1196 ret <vscale x 1 x i32> %a1197}1198 1199define <vscale x 2 x i32> @intrinsic_vsrl_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1, iXLen %2) nounwind {1200; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i32_nxv2i32:1201; CHECK: # %bb.0: # %entry1202; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1203; CHECK-NEXT: vsrl.vx v8, v8, a01204; CHECK-NEXT: ret1205entry:1206 %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(1207 <vscale x 2 x i32> poison,1208 <vscale x 2 x i32> %0,1209 iXLen %1,1210 iXLen %2)1211 1212 ret <vscale x 2 x i32> %a1213}1214 1215define <vscale x 2 x i32> @intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1216; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i32_nxv2i32:1217; CHECK: # %bb.0: # %entry1218; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1219; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t1220; CHECK-NEXT: ret1221entry:1222 %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(1223 <vscale x 2 x i32> %0,1224 <vscale x 2 x i32> %1,1225 iXLen %2,1226 <vscale x 2 x i1> %3,1227 iXLen %4, iXLen 1)1228 1229 ret <vscale x 2 x i32> %a1230}1231 1232define <vscale x 4 x i32> @intrinsic_vsrl_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1, iXLen %2) nounwind {1233; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i32_nxv4i32:1234; CHECK: # %bb.0: # %entry1235; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1236; CHECK-NEXT: vsrl.vx v8, v8, a01237; CHECK-NEXT: ret1238entry:1239 %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(1240 <vscale x 4 x i32> poison,1241 <vscale x 4 x i32> %0,1242 iXLen %1,1243 iXLen %2)1244 1245 ret <vscale x 4 x i32> %a1246}1247 1248define <vscale x 4 x i32> @intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1249; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i32_nxv4i32:1250; CHECK: # %bb.0: # %entry1251; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1252; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t1253; CHECK-NEXT: ret1254entry:1255 %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(1256 <vscale x 4 x i32> %0,1257 <vscale x 4 x i32> %1,1258 iXLen %2,1259 <vscale x 4 x i1> %3,1260 iXLen %4, iXLen 1)1261 1262 ret <vscale x 4 x i32> %a1263}1264 1265define <vscale x 8 x i32> @intrinsic_vsrl_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1, iXLen %2) nounwind {1266; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i32_nxv8i32:1267; CHECK: # %bb.0: # %entry1268; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1269; CHECK-NEXT: vsrl.vx v8, v8, a01270; CHECK-NEXT: ret1271entry:1272 %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(1273 <vscale x 8 x i32> poison,1274 <vscale x 8 x i32> %0,1275 iXLen %1,1276 iXLen %2)1277 1278 ret <vscale x 8 x i32> %a1279}1280 1281define <vscale x 8 x i32> @intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1282; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i32_nxv8i32:1283; CHECK: # %bb.0: # %entry1284; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1285; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t1286; CHECK-NEXT: ret1287entry:1288 %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(1289 <vscale x 8 x i32> %0,1290 <vscale x 8 x i32> %1,1291 iXLen %2,1292 <vscale x 8 x i1> %3,1293 iXLen %4, iXLen 1)1294 1295 ret <vscale x 8 x i32> %a1296}1297 1298define <vscale x 16 x i32> @intrinsic_vsrl_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1, iXLen %2) nounwind {1299; CHECK-LABEL: intrinsic_vsrl_vx_nxv16i32_nxv16i32:1300; CHECK: # %bb.0: # %entry1301; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1302; CHECK-NEXT: vsrl.vx v8, v8, a01303; CHECK-NEXT: ret1304entry:1305 %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(1306 <vscale x 16 x i32> poison,1307 <vscale x 16 x i32> %0,1308 iXLen %1,1309 iXLen %2)1310 1311 ret <vscale x 16 x i32> %a1312}1313 1314define <vscale x 16 x i32> @intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1315; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv16i32_nxv16i32:1316; CHECK: # %bb.0: # %entry1317; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu1318; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t1319; CHECK-NEXT: ret1320entry:1321 %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(1322 <vscale x 16 x i32> %0,1323 <vscale x 16 x i32> %1,1324 iXLen %2,1325 <vscale x 16 x i1> %3,1326 iXLen %4, iXLen 1)1327 1328 ret <vscale x 16 x i32> %a1329}1330 1331define <vscale x 1 x i64> @intrinsic_vsrl_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1, iXLen %2) nounwind {1332; CHECK-LABEL: intrinsic_vsrl_vx_nxv1i64_nxv1i64:1333; CHECK: # %bb.0: # %entry1334; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma1335; CHECK-NEXT: vsrl.vx v8, v8, a01336; CHECK-NEXT: ret1337entry:1338 %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64(1339 <vscale x 1 x i64> poison,1340 <vscale x 1 x i64> %0,1341 iXLen %1,1342 iXLen %2)1343 1344 ret <vscale x 1 x i64> %a1345}1346 1347define <vscale x 1 x i64> @intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1348; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv1i64_nxv1i64:1349; CHECK: # %bb.0: # %entry1350; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu1351; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t1352; CHECK-NEXT: ret1353entry:1354 %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64(1355 <vscale x 1 x i64> %0,1356 <vscale x 1 x i64> %1,1357 iXLen %2,1358 <vscale x 1 x i1> %3,1359 iXLen %4, iXLen 1)1360 1361 ret <vscale x 1 x i64> %a1362}1363 1364define <vscale x 2 x i64> @intrinsic_vsrl_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1, iXLen %2) nounwind {1365; CHECK-LABEL: intrinsic_vsrl_vx_nxv2i64_nxv2i64:1366; CHECK: # %bb.0: # %entry1367; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma1368; CHECK-NEXT: vsrl.vx v8, v8, a01369; CHECK-NEXT: ret1370entry:1371 %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64(1372 <vscale x 2 x i64> poison,1373 <vscale x 2 x i64> %0,1374 iXLen %1,1375 iXLen %2)1376 1377 ret <vscale x 2 x i64> %a1378}1379 1380define <vscale x 2 x i64> @intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1381; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv2i64_nxv2i64:1382; CHECK: # %bb.0: # %entry1383; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu1384; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t1385; CHECK-NEXT: ret1386entry:1387 %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64(1388 <vscale x 2 x i64> %0,1389 <vscale x 2 x i64> %1,1390 iXLen %2,1391 <vscale x 2 x i1> %3,1392 iXLen %4, iXLen 1)1393 1394 ret <vscale x 2 x i64> %a1395}1396 1397define <vscale x 4 x i64> @intrinsic_vsrl_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1, iXLen %2) nounwind {1398; CHECK-LABEL: intrinsic_vsrl_vx_nxv4i64_nxv4i64:1399; CHECK: # %bb.0: # %entry1400; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1401; CHECK-NEXT: vsrl.vx v8, v8, a01402; CHECK-NEXT: ret1403entry:1404 %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64(1405 <vscale x 4 x i64> poison,1406 <vscale x 4 x i64> %0,1407 iXLen %1,1408 iXLen %2)1409 1410 ret <vscale x 4 x i64> %a1411}1412 1413define <vscale x 4 x i64> @intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1414; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv4i64_nxv4i64:1415; CHECK: # %bb.0: # %entry1416; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu1417; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t1418; CHECK-NEXT: ret1419entry:1420 %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64(1421 <vscale x 4 x i64> %0,1422 <vscale x 4 x i64> %1,1423 iXLen %2,1424 <vscale x 4 x i1> %3,1425 iXLen %4, iXLen 1)1426 1427 ret <vscale x 4 x i64> %a1428}1429 1430define <vscale x 8 x i64> @intrinsic_vsrl_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1, iXLen %2) nounwind {1431; CHECK-LABEL: intrinsic_vsrl_vx_nxv8i64_nxv8i64:1432; CHECK: # %bb.0: # %entry1433; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1434; CHECK-NEXT: vsrl.vx v8, v8, a01435; CHECK-NEXT: ret1436entry:1437 %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64(1438 <vscale x 8 x i64> poison,1439 <vscale x 8 x i64> %0,1440 iXLen %1,1441 iXLen %2)1442 1443 ret <vscale x 8 x i64> %a1444}1445 1446define <vscale x 8 x i64> @intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1447; CHECK-LABEL: intrinsic_vsrl_mask_vx_nxv8i64_nxv8i64:1448; CHECK: # %bb.0: # %entry1449; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu1450; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t1451; CHECK-NEXT: ret1452entry:1453 %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64(1454 <vscale x 8 x i64> %0,1455 <vscale x 8 x i64> %1,1456 iXLen %2,1457 <vscale x 8 x i1> %3,1458 iXLen %4, iXLen 1)1459 1460 ret <vscale x 8 x i64> %a1461}1462 1463define <vscale x 1 x i8> @intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {1464; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i8_nxv1i8_i8:1465; CHECK: # %bb.0: # %entry1466; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1467; CHECK-NEXT: vsrl.vi v8, v8, 91468; CHECK-NEXT: ret1469entry:1470 %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.nxv1i8(1471 <vscale x 1 x i8> poison,1472 <vscale x 1 x i8> %0,1473 iXLen 9,1474 iXLen %1)1475 1476 ret <vscale x 1 x i8> %a1477}1478 1479define <vscale x 1 x i8> @intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1480; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i8_nxv1i8_i8:1481; CHECK: # %bb.0: # %entry1482; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu1483; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1484; CHECK-NEXT: ret1485entry:1486 %a = call <vscale x 1 x i8> @llvm.riscv.vsrl.mask.nxv1i8(1487 <vscale x 1 x i8> %0,1488 <vscale x 1 x i8> %1,1489 iXLen 9,1490 <vscale x 1 x i1> %2,1491 iXLen %3, iXLen 1)1492 1493 ret <vscale x 1 x i8> %a1494}1495 1496define <vscale x 2 x i8> @intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {1497; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i8_nxv2i8_i8:1498; CHECK: # %bb.0: # %entry1499; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1500; CHECK-NEXT: vsrl.vi v8, v8, 91501; CHECK-NEXT: ret1502entry:1503 %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.nxv2i8(1504 <vscale x 2 x i8> poison,1505 <vscale x 2 x i8> %0,1506 iXLen 9,1507 iXLen %1)1508 1509 ret <vscale x 2 x i8> %a1510}1511 1512define <vscale x 2 x i8> @intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1513; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i8_nxv2i8_i8:1514; CHECK: # %bb.0: # %entry1515; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu1516; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1517; CHECK-NEXT: ret1518entry:1519 %a = call <vscale x 2 x i8> @llvm.riscv.vsrl.mask.nxv2i8(1520 <vscale x 2 x i8> %0,1521 <vscale x 2 x i8> %1,1522 iXLen 9,1523 <vscale x 2 x i1> %2,1524 iXLen %3, iXLen 1)1525 1526 ret <vscale x 2 x i8> %a1527}1528 1529define <vscale x 4 x i8> @intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {1530; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i8_nxv4i8_i8:1531; CHECK: # %bb.0: # %entry1532; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma1533; CHECK-NEXT: vsrl.vi v8, v8, 91534; CHECK-NEXT: ret1535entry:1536 %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.nxv4i8(1537 <vscale x 4 x i8> poison,1538 <vscale x 4 x i8> %0,1539 iXLen 9,1540 iXLen %1)1541 1542 ret <vscale x 4 x i8> %a1543}1544 1545define <vscale x 4 x i8> @intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1546; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i8_nxv4i8_i8:1547; CHECK: # %bb.0: # %entry1548; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu1549; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1550; CHECK-NEXT: ret1551entry:1552 %a = call <vscale x 4 x i8> @llvm.riscv.vsrl.mask.nxv4i8(1553 <vscale x 4 x i8> %0,1554 <vscale x 4 x i8> %1,1555 iXLen 9,1556 <vscale x 4 x i1> %2,1557 iXLen %3, iXLen 1)1558 1559 ret <vscale x 4 x i8> %a1560}1561 1562define <vscale x 8 x i8> @intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {1563; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i8_nxv8i8_i8:1564; CHECK: # %bb.0: # %entry1565; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma1566; CHECK-NEXT: vsrl.vi v8, v8, 91567; CHECK-NEXT: ret1568entry:1569 %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.nxv8i8(1570 <vscale x 8 x i8> poison,1571 <vscale x 8 x i8> %0,1572 iXLen 9,1573 iXLen %1)1574 1575 ret <vscale x 8 x i8> %a1576}1577 1578define <vscale x 8 x i8> @intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1579; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i8_nxv8i8_i8:1580; CHECK: # %bb.0: # %entry1581; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu1582; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1583; CHECK-NEXT: ret1584entry:1585 %a = call <vscale x 8 x i8> @llvm.riscv.vsrl.mask.nxv8i8(1586 <vscale x 8 x i8> %0,1587 <vscale x 8 x i8> %1,1588 iXLen 9,1589 <vscale x 8 x i1> %2,1590 iXLen %3, iXLen 1)1591 1592 ret <vscale x 8 x i8> %a1593}1594 1595define <vscale x 16 x i8> @intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {1596; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i8_nxv16i8_i8:1597; CHECK: # %bb.0: # %entry1598; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1599; CHECK-NEXT: vsrl.vi v8, v8, 91600; CHECK-NEXT: ret1601entry:1602 %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.nxv16i8(1603 <vscale x 16 x i8> poison,1604 <vscale x 16 x i8> %0,1605 iXLen 9,1606 iXLen %1)1607 1608 ret <vscale x 16 x i8> %a1609}1610 1611define <vscale x 16 x i8> @intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1612; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i8_nxv16i8_i8:1613; CHECK: # %bb.0: # %entry1614; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu1615; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t1616; CHECK-NEXT: ret1617entry:1618 %a = call <vscale x 16 x i8> @llvm.riscv.vsrl.mask.nxv16i8(1619 <vscale x 16 x i8> %0,1620 <vscale x 16 x i8> %1,1621 iXLen 9,1622 <vscale x 16 x i1> %2,1623 iXLen %3, iXLen 1)1624 1625 ret <vscale x 16 x i8> %a1626}1627 1628define <vscale x 32 x i8> @intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {1629; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i8_nxv32i8_i8:1630; CHECK: # %bb.0: # %entry1631; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma1632; CHECK-NEXT: vsrl.vi v8, v8, 91633; CHECK-NEXT: ret1634entry:1635 %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.nxv32i8(1636 <vscale x 32 x i8> poison,1637 <vscale x 32 x i8> %0,1638 iXLen 9,1639 iXLen %1)1640 1641 ret <vscale x 32 x i8> %a1642}1643 1644define <vscale x 32 x i8> @intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1645; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i8_nxv32i8_i8:1646; CHECK: # %bb.0: # %entry1647; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu1648; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t1649; CHECK-NEXT: ret1650entry:1651 %a = call <vscale x 32 x i8> @llvm.riscv.vsrl.mask.nxv32i8(1652 <vscale x 32 x i8> %0,1653 <vscale x 32 x i8> %1,1654 iXLen 9,1655 <vscale x 32 x i1> %2,1656 iXLen %3, iXLen 1)1657 1658 ret <vscale x 32 x i8> %a1659}1660 1661define <vscale x 64 x i8> @intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {1662; CHECK-LABEL: intrinsic_vsrl_vi_nxv64i8_nxv64i8_i8:1663; CHECK: # %bb.0: # %entry1664; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1665; CHECK-NEXT: vsrl.vi v8, v8, 91666; CHECK-NEXT: ret1667entry:1668 %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.nxv64i8(1669 <vscale x 64 x i8> poison,1670 <vscale x 64 x i8> %0,1671 iXLen 9,1672 iXLen %1)1673 1674 ret <vscale x 64 x i8> %a1675}1676 1677define <vscale x 64 x i8> @intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {1678; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv64i8_nxv64i8_i8:1679; CHECK: # %bb.0: # %entry1680; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu1681; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t1682; CHECK-NEXT: ret1683entry:1684 %a = call <vscale x 64 x i8> @llvm.riscv.vsrl.mask.nxv64i8(1685 <vscale x 64 x i8> %0,1686 <vscale x 64 x i8> %1,1687 iXLen 9,1688 <vscale x 64 x i1> %2,1689 iXLen %3, iXLen 1)1690 1691 ret <vscale x 64 x i8> %a1692}1693 1694define <vscale x 1 x i16> @intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {1695; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i16_nxv1i16_i16:1696; CHECK: # %bb.0: # %entry1697; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1698; CHECK-NEXT: vsrl.vi v8, v8, 91699; CHECK-NEXT: ret1700entry:1701 %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.nxv1i16(1702 <vscale x 1 x i16> poison,1703 <vscale x 1 x i16> %0,1704 iXLen 9,1705 iXLen %1)1706 1707 ret <vscale x 1 x i16> %a1708}1709 1710define <vscale x 1 x i16> @intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1711; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i16_nxv1i16_i16:1712; CHECK: # %bb.0: # %entry1713; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1714; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1715; CHECK-NEXT: ret1716entry:1717 %a = call <vscale x 1 x i16> @llvm.riscv.vsrl.mask.nxv1i16(1718 <vscale x 1 x i16> %0,1719 <vscale x 1 x i16> %1,1720 iXLen 9,1721 <vscale x 1 x i1> %2,1722 iXLen %3, iXLen 1)1723 1724 ret <vscale x 1 x i16> %a1725}1726 1727define <vscale x 2 x i16> @intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {1728; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i16_nxv2i16_i16:1729; CHECK: # %bb.0: # %entry1730; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1731; CHECK-NEXT: vsrl.vi v8, v8, 91732; CHECK-NEXT: ret1733entry:1734 %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.nxv2i16(1735 <vscale x 2 x i16> poison,1736 <vscale x 2 x i16> %0,1737 iXLen 9,1738 iXLen %1)1739 1740 ret <vscale x 2 x i16> %a1741}1742 1743define <vscale x 2 x i16> @intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1744; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i16_nxv2i16_i16:1745; CHECK: # %bb.0: # %entry1746; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1747; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1748; CHECK-NEXT: ret1749entry:1750 %a = call <vscale x 2 x i16> @llvm.riscv.vsrl.mask.nxv2i16(1751 <vscale x 2 x i16> %0,1752 <vscale x 2 x i16> %1,1753 iXLen 9,1754 <vscale x 2 x i1> %2,1755 iXLen %3, iXLen 1)1756 1757 ret <vscale x 2 x i16> %a1758}1759 1760define <vscale x 4 x i16> @intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {1761; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i16_nxv4i16_i16:1762; CHECK: # %bb.0: # %entry1763; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1764; CHECK-NEXT: vsrl.vi v8, v8, 91765; CHECK-NEXT: ret1766entry:1767 %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.nxv4i16(1768 <vscale x 4 x i16> poison,1769 <vscale x 4 x i16> %0,1770 iXLen 9,1771 iXLen %1)1772 1773 ret <vscale x 4 x i16> %a1774}1775 1776define <vscale x 4 x i16> @intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1777; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i16_nxv4i16_i16:1778; CHECK: # %bb.0: # %entry1779; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1780; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1781; CHECK-NEXT: ret1782entry:1783 %a = call <vscale x 4 x i16> @llvm.riscv.vsrl.mask.nxv4i16(1784 <vscale x 4 x i16> %0,1785 <vscale x 4 x i16> %1,1786 iXLen 9,1787 <vscale x 4 x i1> %2,1788 iXLen %3, iXLen 1)1789 1790 ret <vscale x 4 x i16> %a1791}1792 1793define <vscale x 8 x i16> @intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {1794; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i16_nxv8i16_i16:1795; CHECK: # %bb.0: # %entry1796; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1797; CHECK-NEXT: vsrl.vi v8, v8, 91798; CHECK-NEXT: ret1799entry:1800 %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.nxv8i16(1801 <vscale x 8 x i16> poison,1802 <vscale x 8 x i16> %0,1803 iXLen 9,1804 iXLen %1)1805 1806 ret <vscale x 8 x i16> %a1807}1808 1809define <vscale x 8 x i16> @intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1810; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i16_nxv8i16_i16:1811; CHECK: # %bb.0: # %entry1812; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1813; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t1814; CHECK-NEXT: ret1815entry:1816 %a = call <vscale x 8 x i16> @llvm.riscv.vsrl.mask.nxv8i16(1817 <vscale x 8 x i16> %0,1818 <vscale x 8 x i16> %1,1819 iXLen 9,1820 <vscale x 8 x i1> %2,1821 iXLen %3, iXLen 1)1822 1823 ret <vscale x 8 x i16> %a1824}1825 1826define <vscale x 16 x i16> @intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {1827; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i16_nxv16i16_i16:1828; CHECK: # %bb.0: # %entry1829; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1830; CHECK-NEXT: vsrl.vi v8, v8, 91831; CHECK-NEXT: ret1832entry:1833 %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.nxv16i16(1834 <vscale x 16 x i16> poison,1835 <vscale x 16 x i16> %0,1836 iXLen 9,1837 iXLen %1)1838 1839 ret <vscale x 16 x i16> %a1840}1841 1842define <vscale x 16 x i16> @intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1843; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i16_nxv16i16_i16:1844; CHECK: # %bb.0: # %entry1845; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1846; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t1847; CHECK-NEXT: ret1848entry:1849 %a = call <vscale x 16 x i16> @llvm.riscv.vsrl.mask.nxv16i16(1850 <vscale x 16 x i16> %0,1851 <vscale x 16 x i16> %1,1852 iXLen 9,1853 <vscale x 16 x i1> %2,1854 iXLen %3, iXLen 1)1855 1856 ret <vscale x 16 x i16> %a1857}1858 1859define <vscale x 32 x i16> @intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {1860; CHECK-LABEL: intrinsic_vsrl_vi_nxv32i16_nxv32i16_i16:1861; CHECK: # %bb.0: # %entry1862; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1863; CHECK-NEXT: vsrl.vi v8, v8, 91864; CHECK-NEXT: ret1865entry:1866 %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.nxv32i16(1867 <vscale x 32 x i16> poison,1868 <vscale x 32 x i16> %0,1869 iXLen 9,1870 iXLen %1)1871 1872 ret <vscale x 32 x i16> %a1873}1874 1875define <vscale x 32 x i16> @intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1876; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv32i16_nxv32i16_i16:1877; CHECK: # %bb.0: # %entry1878; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu1879; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t1880; CHECK-NEXT: ret1881entry:1882 %a = call <vscale x 32 x i16> @llvm.riscv.vsrl.mask.nxv32i16(1883 <vscale x 32 x i16> %0,1884 <vscale x 32 x i16> %1,1885 iXLen 9,1886 <vscale x 32 x i1> %2,1887 iXLen %3, iXLen 1)1888 1889 ret <vscale x 32 x i16> %a1890}1891 1892define <vscale x 1 x i32> @intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {1893; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i32_nxv1i32_i32:1894; CHECK: # %bb.0: # %entry1895; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1896; CHECK-NEXT: vsrl.vi v8, v8, 91897; CHECK-NEXT: ret1898entry:1899 %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.nxv1i32(1900 <vscale x 1 x i32> poison,1901 <vscale x 1 x i32> %0,1902 iXLen 9,1903 iXLen %1)1904 1905 ret <vscale x 1 x i32> %a1906}1907 1908define <vscale x 1 x i32> @intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1909; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i32_nxv1i32_i32:1910; CHECK: # %bb.0: # %entry1911; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu1912; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1913; CHECK-NEXT: ret1914entry:1915 %a = call <vscale x 1 x i32> @llvm.riscv.vsrl.mask.nxv1i32(1916 <vscale x 1 x i32> %0,1917 <vscale x 1 x i32> %1,1918 iXLen 9,1919 <vscale x 1 x i1> %2,1920 iXLen %3, iXLen 1)1921 1922 ret <vscale x 1 x i32> %a1923}1924 1925define <vscale x 2 x i32> @intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {1926; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i32_nxv2i32_i32:1927; CHECK: # %bb.0: # %entry1928; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1929; CHECK-NEXT: vsrl.vi v8, v8, 91930; CHECK-NEXT: ret1931entry:1932 %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.nxv2i32(1933 <vscale x 2 x i32> poison,1934 <vscale x 2 x i32> %0,1935 iXLen 9,1936 iXLen %1)1937 1938 ret <vscale x 2 x i32> %a1939}1940 1941define <vscale x 2 x i32> @intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1942; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i32_nxv2i32_i32:1943; CHECK: # %bb.0: # %entry1944; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu1945; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t1946; CHECK-NEXT: ret1947entry:1948 %a = call <vscale x 2 x i32> @llvm.riscv.vsrl.mask.nxv2i32(1949 <vscale x 2 x i32> %0,1950 <vscale x 2 x i32> %1,1951 iXLen 9,1952 <vscale x 2 x i1> %2,1953 iXLen %3, iXLen 1)1954 1955 ret <vscale x 2 x i32> %a1956}1957 1958define <vscale x 4 x i32> @intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {1959; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i32_nxv4i32_i32:1960; CHECK: # %bb.0: # %entry1961; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1962; CHECK-NEXT: vsrl.vi v8, v8, 91963; CHECK-NEXT: ret1964entry:1965 %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.nxv4i32(1966 <vscale x 4 x i32> poison,1967 <vscale x 4 x i32> %0,1968 iXLen 9,1969 iXLen %1)1970 1971 ret <vscale x 4 x i32> %a1972}1973 1974define <vscale x 4 x i32> @intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1975; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i32_nxv4i32_i32:1976; CHECK: # %bb.0: # %entry1977; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu1978; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t1979; CHECK-NEXT: ret1980entry:1981 %a = call <vscale x 4 x i32> @llvm.riscv.vsrl.mask.nxv4i32(1982 <vscale x 4 x i32> %0,1983 <vscale x 4 x i32> %1,1984 iXLen 9,1985 <vscale x 4 x i1> %2,1986 iXLen %3, iXLen 1)1987 1988 ret <vscale x 4 x i32> %a1989}1990 1991define <vscale x 8 x i32> @intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {1992; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i32_nxv8i32_i32:1993; CHECK: # %bb.0: # %entry1994; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1995; CHECK-NEXT: vsrl.vi v8, v8, 91996; CHECK-NEXT: ret1997entry:1998 %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.nxv8i32(1999 <vscale x 8 x i32> poison,2000 <vscale x 8 x i32> %0,2001 iXLen 9,2002 iXLen %1)2003 2004 ret <vscale x 8 x i32> %a2005}2006 2007define <vscale x 8 x i32> @intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2008; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i32_nxv8i32_i32:2009; CHECK: # %bb.0: # %entry2010; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu2011; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t2012; CHECK-NEXT: ret2013entry:2014 %a = call <vscale x 8 x i32> @llvm.riscv.vsrl.mask.nxv8i32(2015 <vscale x 8 x i32> %0,2016 <vscale x 8 x i32> %1,2017 iXLen 9,2018 <vscale x 8 x i1> %2,2019 iXLen %3, iXLen 1)2020 2021 ret <vscale x 8 x i32> %a2022}2023 2024define <vscale x 16 x i32> @intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {2025; CHECK-LABEL: intrinsic_vsrl_vi_nxv16i32_nxv16i32_i32:2026; CHECK: # %bb.0: # %entry2027; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma2028; CHECK-NEXT: vsrl.vi v8, v8, 92029; CHECK-NEXT: ret2030entry:2031 %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.nxv16i32(2032 <vscale x 16 x i32> poison,2033 <vscale x 16 x i32> %0,2034 iXLen 9,2035 iXLen %1)2036 2037 ret <vscale x 16 x i32> %a2038}2039 2040define <vscale x 16 x i32> @intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {2041; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv16i32_nxv16i32_i32:2042; CHECK: # %bb.0: # %entry2043; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu2044; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t2045; CHECK-NEXT: ret2046entry:2047 %a = call <vscale x 16 x i32> @llvm.riscv.vsrl.mask.nxv16i32(2048 <vscale x 16 x i32> %0,2049 <vscale x 16 x i32> %1,2050 iXLen 9,2051 <vscale x 16 x i1> %2,2052 iXLen %3, iXLen 1)2053 2054 ret <vscale x 16 x i32> %a2055}2056 2057define <vscale x 1 x i64> @intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {2058; CHECK-LABEL: intrinsic_vsrl_vi_nxv1i64_nxv1i64_i64:2059; CHECK: # %bb.0: # %entry2060; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma2061; CHECK-NEXT: vsrl.vi v8, v8, 92062; CHECK-NEXT: ret2063entry:2064 %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.nxv1i64(2065 <vscale x 1 x i64> poison,2066 <vscale x 1 x i64> %0,2067 iXLen 9,2068 iXLen %1)2069 2070 ret <vscale x 1 x i64> %a2071}2072 2073define <vscale x 1 x i64> @intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2074; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv1i64_nxv1i64_i64:2075; CHECK: # %bb.0: # %entry2076; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu2077; CHECK-NEXT: vsrl.vi v8, v9, 9, v0.t2078; CHECK-NEXT: ret2079entry:2080 %a = call <vscale x 1 x i64> @llvm.riscv.vsrl.mask.nxv1i64(2081 <vscale x 1 x i64> %0,2082 <vscale x 1 x i64> %1,2083 iXLen 9,2084 <vscale x 1 x i1> %2,2085 iXLen %3, iXLen 1)2086 2087 ret <vscale x 1 x i64> %a2088}2089 2090define <vscale x 2 x i64> @intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {2091; CHECK-LABEL: intrinsic_vsrl_vi_nxv2i64_nxv2i64_i64:2092; CHECK: # %bb.0: # %entry2093; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma2094; CHECK-NEXT: vsrl.vi v8, v8, 92095; CHECK-NEXT: ret2096entry:2097 %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.nxv2i64(2098 <vscale x 2 x i64> poison,2099 <vscale x 2 x i64> %0,2100 iXLen 9,2101 iXLen %1)2102 2103 ret <vscale x 2 x i64> %a2104}2105 2106define <vscale x 2 x i64> @intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2107; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv2i64_nxv2i64_i64:2108; CHECK: # %bb.0: # %entry2109; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu2110; CHECK-NEXT: vsrl.vi v8, v10, 9, v0.t2111; CHECK-NEXT: ret2112entry:2113 %a = call <vscale x 2 x i64> @llvm.riscv.vsrl.mask.nxv2i64(2114 <vscale x 2 x i64> %0,2115 <vscale x 2 x i64> %1,2116 iXLen 9,2117 <vscale x 2 x i1> %2,2118 iXLen %3, iXLen 1)2119 2120 ret <vscale x 2 x i64> %a2121}2122 2123define <vscale x 4 x i64> @intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {2124; CHECK-LABEL: intrinsic_vsrl_vi_nxv4i64_nxv4i64_i64:2125; CHECK: # %bb.0: # %entry2126; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma2127; CHECK-NEXT: vsrl.vi v8, v8, 92128; CHECK-NEXT: ret2129entry:2130 %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.nxv4i64(2131 <vscale x 4 x i64> poison,2132 <vscale x 4 x i64> %0,2133 iXLen 9,2134 iXLen %1)2135 2136 ret <vscale x 4 x i64> %a2137}2138 2139define <vscale x 4 x i64> @intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2140; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv4i64_nxv4i64_i64:2141; CHECK: # %bb.0: # %entry2142; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu2143; CHECK-NEXT: vsrl.vi v8, v12, 9, v0.t2144; CHECK-NEXT: ret2145entry:2146 %a = call <vscale x 4 x i64> @llvm.riscv.vsrl.mask.nxv4i64(2147 <vscale x 4 x i64> %0,2148 <vscale x 4 x i64> %1,2149 iXLen 9,2150 <vscale x 4 x i1> %2,2151 iXLen %3, iXLen 1)2152 2153 ret <vscale x 4 x i64> %a2154}2155 2156define <vscale x 8 x i64> @intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {2157; CHECK-LABEL: intrinsic_vsrl_vi_nxv8i64_nxv8i64_i64:2158; CHECK: # %bb.0: # %entry2159; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma2160; CHECK-NEXT: vsrl.vi v8, v8, 92161; CHECK-NEXT: ret2162entry:2163 %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.nxv8i64(2164 <vscale x 8 x i64> poison,2165 <vscale x 8 x i64> %0,2166 iXLen 9,2167 iXLen %1)2168 2169 ret <vscale x 8 x i64> %a2170}2171 2172define <vscale x 8 x i64> @intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2173; CHECK-LABEL: intrinsic_vsrl_mask_vi_nxv8i64_nxv8i64_i64:2174; CHECK: # %bb.0: # %entry2175; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu2176; CHECK-NEXT: vsrl.vi v8, v16, 9, v0.t2177; CHECK-NEXT: ret2178entry:2179 %a = call <vscale x 8 x i64> @llvm.riscv.vsrl.mask.nxv8i64(2180 <vscale x 8 x i64> %0,2181 <vscale x 8 x i64> %1,2182 iXLen 9,2183 <vscale x 8 x i1> %2,2184 iXLen %3, iXLen 1)2185 2186 ret <vscale x 8 x i64> %a2187}2188