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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define void @intrinsic_vsse_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vsse_v_nxv1i64_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma11; CHECK-NEXT: vsse64.v v8, (a0), a112; CHECK-NEXT: ret13entry:14 call void @llvm.riscv.vsse.nxv1i64(15 <vscale x 1 x i64> %0,16 ptr %1,17 iXLen %2,18 iXLen %3)19 20 ret void21}22 23define void @intrinsic_vsse_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i64_nxv1i64:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma27; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t28; CHECK-NEXT: ret29entry:30 call void @llvm.riscv.vsse.mask.nxv1i64(31 <vscale x 1 x i64> %0,32 ptr %1,33 iXLen %2,34 <vscale x 1 x i1> %3,35 iXLen %4)36 37 ret void38}39 40define void @intrinsic_vsse_allonesmask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {41; CHECK-LABEL: intrinsic_vsse_allonesmask_v_nxv1i64_nxv1i64:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma44; CHECK-NEXT: vsse64.v v8, (a0), a145; CHECK-NEXT: ret46entry:47 call void @llvm.riscv.vsse.mask.nxv1i64(48 <vscale x 1 x i64> %0,49 ptr %1,50 iXLen %2,51 <vscale x 1 x i1> splat (i1 true),52 iXLen %4)53 54 ret void55}56 57define void @intrinsic_vsse_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, iXLen %2, iXLen %3) nounwind {58; CHECK-LABEL: intrinsic_vsse_v_nxv2i64_nxv2i64:59; CHECK: # %bb.0: # %entry60; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma61; CHECK-NEXT: vsse64.v v8, (a0), a162; CHECK-NEXT: ret63entry:64 call void @llvm.riscv.vsse.nxv2i64(65 <vscale x 2 x i64> %0,66 ptr %1,67 iXLen %2,68 iXLen %3)69 70 ret void71}72 73define void @intrinsic_vsse_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {74; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i64_nxv2i64:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma77; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t78; CHECK-NEXT: ret79entry:80 call void @llvm.riscv.vsse.mask.nxv2i64(81 <vscale x 2 x i64> %0,82 ptr %1,83 iXLen %2,84 <vscale x 2 x i1> %3,85 iXLen %4)86 87 ret void88}89 90define void @intrinsic_vsse_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, iXLen %2, iXLen %3) nounwind {91; CHECK-LABEL: intrinsic_vsse_v_nxv4i64_nxv4i64:92; CHECK: # %bb.0: # %entry93; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma94; CHECK-NEXT: vsse64.v v8, (a0), a195; CHECK-NEXT: ret96entry:97 call void @llvm.riscv.vsse.nxv4i64(98 <vscale x 4 x i64> %0,99 ptr %1,100 iXLen %2,101 iXLen %3)102 103 ret void104}105 106define void @intrinsic_vsse_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {107; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i64_nxv4i64:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma110; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t111; CHECK-NEXT: ret112entry:113 call void @llvm.riscv.vsse.mask.nxv4i64(114 <vscale x 4 x i64> %0,115 ptr %1,116 iXLen %2,117 <vscale x 4 x i1> %3,118 iXLen %4)119 120 ret void121}122 123define void @intrinsic_vsse_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, iXLen %2, iXLen %3) nounwind {124; CHECK-LABEL: intrinsic_vsse_v_nxv8i64_nxv8i64:125; CHECK: # %bb.0: # %entry126; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma127; CHECK-NEXT: vsse64.v v8, (a0), a1128; CHECK-NEXT: ret129entry:130 call void @llvm.riscv.vsse.nxv8i64(131 <vscale x 8 x i64> %0,132 ptr %1,133 iXLen %2,134 iXLen %3)135 136 ret void137}138 139define void @intrinsic_vsse_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {140; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i64_nxv8i64:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma143; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t144; CHECK-NEXT: ret145entry:146 call void @llvm.riscv.vsse.mask.nxv8i64(147 <vscale x 8 x i64> %0,148 ptr %1,149 iXLen %2,150 <vscale x 8 x i1> %3,151 iXLen %4)152 153 ret void154}155 156define void @intrinsic_vsse_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, iXLen %2, iXLen %3) nounwind {157; CHECK-LABEL: intrinsic_vsse_v_nxv1f64_nxv1f64:158; CHECK: # %bb.0: # %entry159; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma160; CHECK-NEXT: vsse64.v v8, (a0), a1161; CHECK-NEXT: ret162entry:163 call void @llvm.riscv.vsse.nxv1f64(164 <vscale x 1 x double> %0,165 ptr %1,166 iXLen %2,167 iXLen %3)168 169 ret void170}171 172define void @intrinsic_vsse_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {173; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f64_nxv1f64:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, ma176; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t177; CHECK-NEXT: ret178entry:179 call void @llvm.riscv.vsse.mask.nxv1f64(180 <vscale x 1 x double> %0,181 ptr %1,182 iXLen %2,183 <vscale x 1 x i1> %3,184 iXLen %4)185 186 ret void187}188 189define void @intrinsic_vsse_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, iXLen %2, iXLen %3) nounwind {190; CHECK-LABEL: intrinsic_vsse_v_nxv2f64_nxv2f64:191; CHECK: # %bb.0: # %entry192; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma193; CHECK-NEXT: vsse64.v v8, (a0), a1194; CHECK-NEXT: ret195entry:196 call void @llvm.riscv.vsse.nxv2f64(197 <vscale x 2 x double> %0,198 ptr %1,199 iXLen %2,200 iXLen %3)201 202 ret void203}204 205define void @intrinsic_vsse_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {206; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f64_nxv2f64:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, ma209; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t210; CHECK-NEXT: ret211entry:212 call void @llvm.riscv.vsse.mask.nxv2f64(213 <vscale x 2 x double> %0,214 ptr %1,215 iXLen %2,216 <vscale x 2 x i1> %3,217 iXLen %4)218 219 ret void220}221 222define void @intrinsic_vsse_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, iXLen %2, iXLen %3) nounwind {223; CHECK-LABEL: intrinsic_vsse_v_nxv4f64_nxv4f64:224; CHECK: # %bb.0: # %entry225; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma226; CHECK-NEXT: vsse64.v v8, (a0), a1227; CHECK-NEXT: ret228entry:229 call void @llvm.riscv.vsse.nxv4f64(230 <vscale x 4 x double> %0,231 ptr %1,232 iXLen %2,233 iXLen %3)234 235 ret void236}237 238define void @intrinsic_vsse_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {239; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f64_nxv4f64:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, ma242; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t243; CHECK-NEXT: ret244entry:245 call void @llvm.riscv.vsse.mask.nxv4f64(246 <vscale x 4 x double> %0,247 ptr %1,248 iXLen %2,249 <vscale x 4 x i1> %3,250 iXLen %4)251 252 ret void253}254 255define void @intrinsic_vsse_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, iXLen %2, iXLen %3) nounwind {256; CHECK-LABEL: intrinsic_vsse_v_nxv8f64_nxv8f64:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma259; CHECK-NEXT: vsse64.v v8, (a0), a1260; CHECK-NEXT: ret261entry:262 call void @llvm.riscv.vsse.nxv8f64(263 <vscale x 8 x double> %0,264 ptr %1,265 iXLen %2,266 iXLen %3)267 268 ret void269}270 271define void @intrinsic_vsse_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {272; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f64_nxv8f64:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma275; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t276; CHECK-NEXT: ret277entry:278 call void @llvm.riscv.vsse.mask.nxv8f64(279 <vscale x 8 x double> %0,280 ptr %1,281 iXLen %2,282 <vscale x 8 x i1> %3,283 iXLen %4)284 285 ret void286}287 288define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, iXLen %2, iXLen %3) nounwind {289; CHECK-LABEL: intrinsic_vsse_v_nxv1i32_nxv1i32:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma292; CHECK-NEXT: vsse32.v v8, (a0), a1293; CHECK-NEXT: ret294entry:295 call void @llvm.riscv.vsse.nxv1i32(296 <vscale x 1 x i32> %0,297 ptr %1,298 iXLen %2,299 iXLen %3)300 301 ret void302}303 304define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {305; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i32_nxv1i32:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma308; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t309; CHECK-NEXT: ret310entry:311 call void @llvm.riscv.vsse.mask.nxv1i32(312 <vscale x 1 x i32> %0,313 ptr %1,314 iXLen %2,315 <vscale x 1 x i1> %3,316 iXLen %4)317 318 ret void319}320 321define void @intrinsic_vsse_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, iXLen %2, iXLen %3) nounwind {322; CHECK-LABEL: intrinsic_vsse_v_nxv2i32_nxv2i32:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma325; CHECK-NEXT: vsse32.v v8, (a0), a1326; CHECK-NEXT: ret327entry:328 call void @llvm.riscv.vsse.nxv2i32(329 <vscale x 2 x i32> %0,330 ptr %1,331 iXLen %2,332 iXLen %3)333 334 ret void335}336 337define void @intrinsic_vsse_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {338; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i32_nxv2i32:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma341; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t342; CHECK-NEXT: ret343entry:344 call void @llvm.riscv.vsse.mask.nxv2i32(345 <vscale x 2 x i32> %0,346 ptr %1,347 iXLen %2,348 <vscale x 2 x i1> %3,349 iXLen %4)350 351 ret void352}353 354define void @intrinsic_vsse_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, iXLen %2, iXLen %3) nounwind {355; CHECK-LABEL: intrinsic_vsse_v_nxv4i32_nxv4i32:356; CHECK: # %bb.0: # %entry357; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma358; CHECK-NEXT: vsse32.v v8, (a0), a1359; CHECK-NEXT: ret360entry:361 call void @llvm.riscv.vsse.nxv4i32(362 <vscale x 4 x i32> %0,363 ptr %1,364 iXLen %2,365 iXLen %3)366 367 ret void368}369 370define void @intrinsic_vsse_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {371; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i32_nxv4i32:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma374; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t375; CHECK-NEXT: ret376entry:377 call void @llvm.riscv.vsse.mask.nxv4i32(378 <vscale x 4 x i32> %0,379 ptr %1,380 iXLen %2,381 <vscale x 4 x i1> %3,382 iXLen %4)383 384 ret void385}386 387define void @intrinsic_vsse_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, iXLen %2, iXLen %3) nounwind {388; CHECK-LABEL: intrinsic_vsse_v_nxv8i32_nxv8i32:389; CHECK: # %bb.0: # %entry390; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma391; CHECK-NEXT: vsse32.v v8, (a0), a1392; CHECK-NEXT: ret393entry:394 call void @llvm.riscv.vsse.nxv8i32(395 <vscale x 8 x i32> %0,396 ptr %1,397 iXLen %2,398 iXLen %3)399 400 ret void401}402 403define void @intrinsic_vsse_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {404; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i32_nxv8i32:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma407; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t408; CHECK-NEXT: ret409entry:410 call void @llvm.riscv.vsse.mask.nxv8i32(411 <vscale x 8 x i32> %0,412 ptr %1,413 iXLen %2,414 <vscale x 8 x i1> %3,415 iXLen %4)416 417 ret void418}419 420define void @intrinsic_vsse_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, iXLen %2, iXLen %3) nounwind {421; CHECK-LABEL: intrinsic_vsse_v_nxv16i32_nxv16i32:422; CHECK: # %bb.0: # %entry423; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma424; CHECK-NEXT: vsse32.v v8, (a0), a1425; CHECK-NEXT: ret426entry:427 call void @llvm.riscv.vsse.nxv16i32(428 <vscale x 16 x i32> %0,429 ptr %1,430 iXLen %2,431 iXLen %3)432 433 ret void434}435 436define void @intrinsic_vsse_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {437; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i32_nxv16i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma440; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t441; CHECK-NEXT: ret442entry:443 call void @llvm.riscv.vsse.mask.nxv16i32(444 <vscale x 16 x i32> %0,445 ptr %1,446 iXLen %2,447 <vscale x 16 x i1> %3,448 iXLen %4)449 450 ret void451}452 453define void @intrinsic_vsse_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, iXLen %2, iXLen %3) nounwind {454; CHECK-LABEL: intrinsic_vsse_v_nxv1f32_nxv1f32:455; CHECK: # %bb.0: # %entry456; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma457; CHECK-NEXT: vsse32.v v8, (a0), a1458; CHECK-NEXT: ret459entry:460 call void @llvm.riscv.vsse.nxv1f32(461 <vscale x 1 x float> %0,462 ptr %1,463 iXLen %2,464 iXLen %3)465 466 ret void467}468 469define void @intrinsic_vsse_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {470; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f32_nxv1f32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, ma473; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t474; CHECK-NEXT: ret475entry:476 call void @llvm.riscv.vsse.mask.nxv1f32(477 <vscale x 1 x float> %0,478 ptr %1,479 iXLen %2,480 <vscale x 1 x i1> %3,481 iXLen %4)482 483 ret void484}485 486define void @intrinsic_vsse_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, iXLen %2, iXLen %3) nounwind {487; CHECK-LABEL: intrinsic_vsse_v_nxv2f32_nxv2f32:488; CHECK: # %bb.0: # %entry489; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma490; CHECK-NEXT: vsse32.v v8, (a0), a1491; CHECK-NEXT: ret492entry:493 call void @llvm.riscv.vsse.nxv2f32(494 <vscale x 2 x float> %0,495 ptr %1,496 iXLen %2,497 iXLen %3)498 499 ret void500}501 502define void @intrinsic_vsse_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {503; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f32_nxv2f32:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma506; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t507; CHECK-NEXT: ret508entry:509 call void @llvm.riscv.vsse.mask.nxv2f32(510 <vscale x 2 x float> %0,511 ptr %1,512 iXLen %2,513 <vscale x 2 x i1> %3,514 iXLen %4)515 516 ret void517}518 519define void @intrinsic_vsse_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, iXLen %2, iXLen %3) nounwind {520; CHECK-LABEL: intrinsic_vsse_v_nxv4f32_nxv4f32:521; CHECK: # %bb.0: # %entry522; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma523; CHECK-NEXT: vsse32.v v8, (a0), a1524; CHECK-NEXT: ret525entry:526 call void @llvm.riscv.vsse.nxv4f32(527 <vscale x 4 x float> %0,528 ptr %1,529 iXLen %2,530 iXLen %3)531 532 ret void533}534 535define void @intrinsic_vsse_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {536; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f32_nxv4f32:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, ma539; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t540; CHECK-NEXT: ret541entry:542 call void @llvm.riscv.vsse.mask.nxv4f32(543 <vscale x 4 x float> %0,544 ptr %1,545 iXLen %2,546 <vscale x 4 x i1> %3,547 iXLen %4)548 549 ret void550}551 552define void @intrinsic_vsse_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, iXLen %2, iXLen %3) nounwind {553; CHECK-LABEL: intrinsic_vsse_v_nxv8f32_nxv8f32:554; CHECK: # %bb.0: # %entry555; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma556; CHECK-NEXT: vsse32.v v8, (a0), a1557; CHECK-NEXT: ret558entry:559 call void @llvm.riscv.vsse.nxv8f32(560 <vscale x 8 x float> %0,561 ptr %1,562 iXLen %2,563 iXLen %3)564 565 ret void566}567 568define void @intrinsic_vsse_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {569; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f32_nxv8f32:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma572; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t573; CHECK-NEXT: ret574entry:575 call void @llvm.riscv.vsse.mask.nxv8f32(576 <vscale x 8 x float> %0,577 ptr %1,578 iXLen %2,579 <vscale x 8 x i1> %3,580 iXLen %4)581 582 ret void583}584 585define void @intrinsic_vsse_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, iXLen %2, iXLen %3) nounwind {586; CHECK-LABEL: intrinsic_vsse_v_nxv16f32_nxv16f32:587; CHECK: # %bb.0: # %entry588; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma589; CHECK-NEXT: vsse32.v v8, (a0), a1590; CHECK-NEXT: ret591entry:592 call void @llvm.riscv.vsse.nxv16f32(593 <vscale x 16 x float> %0,594 ptr %1,595 iXLen %2,596 iXLen %3)597 598 ret void599}600 601define void @intrinsic_vsse_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {602; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f32_nxv16f32:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma605; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t606; CHECK-NEXT: ret607entry:608 call void @llvm.riscv.vsse.mask.nxv16f32(609 <vscale x 16 x float> %0,610 ptr %1,611 iXLen %2,612 <vscale x 16 x i1> %3,613 iXLen %4)614 615 ret void616}617 618define void @intrinsic_vsse_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, iXLen %2, iXLen %3) nounwind {619; CHECK-LABEL: intrinsic_vsse_v_nxv1i16_nxv1i16:620; CHECK: # %bb.0: # %entry621; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma622; CHECK-NEXT: vsse16.v v8, (a0), a1623; CHECK-NEXT: ret624entry:625 call void @llvm.riscv.vsse.nxv1i16(626 <vscale x 1 x i16> %0,627 ptr %1,628 iXLen %2,629 iXLen %3)630 631 ret void632}633 634define void @intrinsic_vsse_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {635; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i16_nxv1i16:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma638; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t639; CHECK-NEXT: ret640entry:641 call void @llvm.riscv.vsse.mask.nxv1i16(642 <vscale x 1 x i16> %0,643 ptr %1,644 iXLen %2,645 <vscale x 1 x i1> %3,646 iXLen %4)647 648 ret void649}650 651define void @intrinsic_vsse_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, iXLen %2, iXLen %3) nounwind {652; CHECK-LABEL: intrinsic_vsse_v_nxv2i16_nxv2i16:653; CHECK: # %bb.0: # %entry654; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma655; CHECK-NEXT: vsse16.v v8, (a0), a1656; CHECK-NEXT: ret657entry:658 call void @llvm.riscv.vsse.nxv2i16(659 <vscale x 2 x i16> %0,660 ptr %1,661 iXLen %2,662 iXLen %3)663 664 ret void665}666 667define void @intrinsic_vsse_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {668; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i16_nxv2i16:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma671; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t672; CHECK-NEXT: ret673entry:674 call void @llvm.riscv.vsse.mask.nxv2i16(675 <vscale x 2 x i16> %0,676 ptr %1,677 iXLen %2,678 <vscale x 2 x i1> %3,679 iXLen %4)680 681 ret void682}683 684define void @intrinsic_vsse_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, iXLen %2, iXLen %3) nounwind {685; CHECK-LABEL: intrinsic_vsse_v_nxv4i16_nxv4i16:686; CHECK: # %bb.0: # %entry687; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma688; CHECK-NEXT: vsse16.v v8, (a0), a1689; CHECK-NEXT: ret690entry:691 call void @llvm.riscv.vsse.nxv4i16(692 <vscale x 4 x i16> %0,693 ptr %1,694 iXLen %2,695 iXLen %3)696 697 ret void698}699 700define void @intrinsic_vsse_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {701; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i16_nxv4i16:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma704; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t705; CHECK-NEXT: ret706entry:707 call void @llvm.riscv.vsse.mask.nxv4i16(708 <vscale x 4 x i16> %0,709 ptr %1,710 iXLen %2,711 <vscale x 4 x i1> %3,712 iXLen %4)713 714 ret void715}716 717define void @intrinsic_vsse_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, iXLen %2, iXLen %3) nounwind {718; CHECK-LABEL: intrinsic_vsse_v_nxv8i16_nxv8i16:719; CHECK: # %bb.0: # %entry720; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma721; CHECK-NEXT: vsse16.v v8, (a0), a1722; CHECK-NEXT: ret723entry:724 call void @llvm.riscv.vsse.nxv8i16(725 <vscale x 8 x i16> %0,726 ptr %1,727 iXLen %2,728 iXLen %3)729 730 ret void731}732 733define void @intrinsic_vsse_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {734; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i16_nxv8i16:735; CHECK: # %bb.0: # %entry736; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma737; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t738; CHECK-NEXT: ret739entry:740 call void @llvm.riscv.vsse.mask.nxv8i16(741 <vscale x 8 x i16> %0,742 ptr %1,743 iXLen %2,744 <vscale x 8 x i1> %3,745 iXLen %4)746 747 ret void748}749 750define void @intrinsic_vsse_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, iXLen %2, iXLen %3) nounwind {751; CHECK-LABEL: intrinsic_vsse_v_nxv16i16_nxv16i16:752; CHECK: # %bb.0: # %entry753; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma754; CHECK-NEXT: vsse16.v v8, (a0), a1755; CHECK-NEXT: ret756entry:757 call void @llvm.riscv.vsse.nxv16i16(758 <vscale x 16 x i16> %0,759 ptr %1,760 iXLen %2,761 iXLen %3)762 763 ret void764}765 766define void @intrinsic_vsse_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {767; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i16_nxv16i16:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma770; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t771; CHECK-NEXT: ret772entry:773 call void @llvm.riscv.vsse.mask.nxv16i16(774 <vscale x 16 x i16> %0,775 ptr %1,776 iXLen %2,777 <vscale x 16 x i1> %3,778 iXLen %4)779 780 ret void781}782 783define void @intrinsic_vsse_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, iXLen %2, iXLen %3) nounwind {784; CHECK-LABEL: intrinsic_vsse_v_nxv32i16_nxv32i16:785; CHECK: # %bb.0: # %entry786; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma787; CHECK-NEXT: vsse16.v v8, (a0), a1788; CHECK-NEXT: ret789entry:790 call void @llvm.riscv.vsse.nxv32i16(791 <vscale x 32 x i16> %0,792 ptr %1,793 iXLen %2,794 iXLen %3)795 796 ret void797}798 799define void @intrinsic_vsse_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {800; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i16_nxv32i16:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma803; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t804; CHECK-NEXT: ret805entry:806 call void @llvm.riscv.vsse.mask.nxv32i16(807 <vscale x 32 x i16> %0,808 ptr %1,809 iXLen %2,810 <vscale x 32 x i1> %3,811 iXLen %4)812 813 ret void814}815 816define void @intrinsic_vsse_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, iXLen %2, iXLen %3) nounwind {817; CHECK-LABEL: intrinsic_vsse_v_nxv1f16_nxv1f16:818; CHECK: # %bb.0: # %entry819; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma820; CHECK-NEXT: vsse16.v v8, (a0), a1821; CHECK-NEXT: ret822entry:823 call void @llvm.riscv.vsse.nxv1f16(824 <vscale x 1 x half> %0,825 ptr %1,826 iXLen %2,827 iXLen %3)828 829 ret void830}831 832define void @intrinsic_vsse_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {833; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f16_nxv1f16:834; CHECK: # %bb.0: # %entry835; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma836; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t837; CHECK-NEXT: ret838entry:839 call void @llvm.riscv.vsse.mask.nxv1f16(840 <vscale x 1 x half> %0,841 ptr %1,842 iXLen %2,843 <vscale x 1 x i1> %3,844 iXLen %4)845 846 ret void847}848 849define void @intrinsic_vsse_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, iXLen %2, iXLen %3) nounwind {850; CHECK-LABEL: intrinsic_vsse_v_nxv2f16_nxv2f16:851; CHECK: # %bb.0: # %entry852; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma853; CHECK-NEXT: vsse16.v v8, (a0), a1854; CHECK-NEXT: ret855entry:856 call void @llvm.riscv.vsse.nxv2f16(857 <vscale x 2 x half> %0,858 ptr %1,859 iXLen %2,860 iXLen %3)861 862 ret void863}864 865define void @intrinsic_vsse_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {866; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f16_nxv2f16:867; CHECK: # %bb.0: # %entry868; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma869; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t870; CHECK-NEXT: ret871entry:872 call void @llvm.riscv.vsse.mask.nxv2f16(873 <vscale x 2 x half> %0,874 ptr %1,875 iXLen %2,876 <vscale x 2 x i1> %3,877 iXLen %4)878 879 ret void880}881 882define void @intrinsic_vsse_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, iXLen %2, iXLen %3) nounwind {883; CHECK-LABEL: intrinsic_vsse_v_nxv4f16_nxv4f16:884; CHECK: # %bb.0: # %entry885; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma886; CHECK-NEXT: vsse16.v v8, (a0), a1887; CHECK-NEXT: ret888entry:889 call void @llvm.riscv.vsse.nxv4f16(890 <vscale x 4 x half> %0,891 ptr %1,892 iXLen %2,893 iXLen %3)894 895 ret void896}897 898define void @intrinsic_vsse_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {899; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f16_nxv4f16:900; CHECK: # %bb.0: # %entry901; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma902; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t903; CHECK-NEXT: ret904entry:905 call void @llvm.riscv.vsse.mask.nxv4f16(906 <vscale x 4 x half> %0,907 ptr %1,908 iXLen %2,909 <vscale x 4 x i1> %3,910 iXLen %4)911 912 ret void913}914 915define void @intrinsic_vsse_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, iXLen %2, iXLen %3) nounwind {916; CHECK-LABEL: intrinsic_vsse_v_nxv8f16_nxv8f16:917; CHECK: # %bb.0: # %entry918; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma919; CHECK-NEXT: vsse16.v v8, (a0), a1920; CHECK-NEXT: ret921entry:922 call void @llvm.riscv.vsse.nxv8f16(923 <vscale x 8 x half> %0,924 ptr %1,925 iXLen %2,926 iXLen %3)927 928 ret void929}930 931define void @intrinsic_vsse_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {932; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f16_nxv8f16:933; CHECK: # %bb.0: # %entry934; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma935; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t936; CHECK-NEXT: ret937entry:938 call void @llvm.riscv.vsse.mask.nxv8f16(939 <vscale x 8 x half> %0,940 ptr %1,941 iXLen %2,942 <vscale x 8 x i1> %3,943 iXLen %4)944 945 ret void946}947 948define void @intrinsic_vsse_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, iXLen %2, iXLen %3) nounwind {949; CHECK-LABEL: intrinsic_vsse_v_nxv16f16_nxv16f16:950; CHECK: # %bb.0: # %entry951; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma952; CHECK-NEXT: vsse16.v v8, (a0), a1953; CHECK-NEXT: ret954entry:955 call void @llvm.riscv.vsse.nxv16f16(956 <vscale x 16 x half> %0,957 ptr %1,958 iXLen %2,959 iXLen %3)960 961 ret void962}963 964define void @intrinsic_vsse_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {965; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f16_nxv16f16:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma968; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t969; CHECK-NEXT: ret970entry:971 call void @llvm.riscv.vsse.mask.nxv16f16(972 <vscale x 16 x half> %0,973 ptr %1,974 iXLen %2,975 <vscale x 16 x i1> %3,976 iXLen %4)977 978 ret void979}980 981define void @intrinsic_vsse_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, iXLen %2, iXLen %3) nounwind {982; CHECK-LABEL: intrinsic_vsse_v_nxv32f16_nxv32f16:983; CHECK: # %bb.0: # %entry984; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma985; CHECK-NEXT: vsse16.v v8, (a0), a1986; CHECK-NEXT: ret987entry:988 call void @llvm.riscv.vsse.nxv32f16(989 <vscale x 32 x half> %0,990 ptr %1,991 iXLen %2,992 iXLen %3)993 994 ret void995}996 997define void @intrinsic_vsse_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {998; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32f16_nxv32f16:999; CHECK: # %bb.0: # %entry1000; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma1001; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t1002; CHECK-NEXT: ret1003entry:1004 call void @llvm.riscv.vsse.mask.nxv32f16(1005 <vscale x 32 x half> %0,1006 ptr %1,1007 iXLen %2,1008 <vscale x 32 x i1> %3,1009 iXLen %4)1010 1011 ret void1012}1013 1014define void @intrinsic_vsse_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1015; CHECK-LABEL: intrinsic_vsse_v_nxv1bf16_nxv1bf16:1016; CHECK: # %bb.0: # %entry1017; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma1018; CHECK-NEXT: vsse16.v v8, (a0), a11019; CHECK-NEXT: ret1020entry:1021 call void @llvm.riscv.vsse.nxv1bf16(1022 <vscale x 1 x bfloat> %0,1023 ptr %1,1024 iXLen %2,1025 iXLen %3)1026 1027 ret void1028}1029 1030define void @intrinsic_vsse_mask_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1031; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1bf16_nxv1bf16:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, ma1034; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t1035; CHECK-NEXT: ret1036entry:1037 call void @llvm.riscv.vsse.mask.nxv1bf16(1038 <vscale x 1 x bfloat> %0,1039 ptr %1,1040 iXLen %2,1041 <vscale x 1 x i1> %3,1042 iXLen %4)1043 1044 ret void1045}1046 1047define void @intrinsic_vsse_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1048; CHECK-LABEL: intrinsic_vsse_v_nxv2bf16_nxv2bf16:1049; CHECK: # %bb.0: # %entry1050; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma1051; CHECK-NEXT: vsse16.v v8, (a0), a11052; CHECK-NEXT: ret1053entry:1054 call void @llvm.riscv.vsse.nxv2bf16(1055 <vscale x 2 x bfloat> %0,1056 ptr %1,1057 iXLen %2,1058 iXLen %3)1059 1060 ret void1061}1062 1063define void @intrinsic_vsse_mask_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1064; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2bf16_nxv2bf16:1065; CHECK: # %bb.0: # %entry1066; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, ma1067; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t1068; CHECK-NEXT: ret1069entry:1070 call void @llvm.riscv.vsse.mask.nxv2bf16(1071 <vscale x 2 x bfloat> %0,1072 ptr %1,1073 iXLen %2,1074 <vscale x 2 x i1> %3,1075 iXLen %4)1076 1077 ret void1078}1079 1080define void @intrinsic_vsse_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1081; CHECK-LABEL: intrinsic_vsse_v_nxv4bf16_nxv4bf16:1082; CHECK: # %bb.0: # %entry1083; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma1084; CHECK-NEXT: vsse16.v v8, (a0), a11085; CHECK-NEXT: ret1086entry:1087 call void @llvm.riscv.vsse.nxv4bf16(1088 <vscale x 4 x bfloat> %0,1089 ptr %1,1090 iXLen %2,1091 iXLen %3)1092 1093 ret void1094}1095 1096define void @intrinsic_vsse_mask_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1097; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4bf16_nxv4bf16:1098; CHECK: # %bb.0: # %entry1099; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, ma1100; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t1101; CHECK-NEXT: ret1102entry:1103 call void @llvm.riscv.vsse.mask.nxv4bf16(1104 <vscale x 4 x bfloat> %0,1105 ptr %1,1106 iXLen %2,1107 <vscale x 4 x i1> %3,1108 iXLen %4)1109 1110 ret void1111}1112 1113define void @intrinsic_vsse_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1114; CHECK-LABEL: intrinsic_vsse_v_nxv8bf16_nxv8bf16:1115; CHECK: # %bb.0: # %entry1116; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma1117; CHECK-NEXT: vsse16.v v8, (a0), a11118; CHECK-NEXT: ret1119entry:1120 call void @llvm.riscv.vsse.nxv8bf16(1121 <vscale x 8 x bfloat> %0,1122 ptr %1,1123 iXLen %2,1124 iXLen %3)1125 1126 ret void1127}1128 1129define void @intrinsic_vsse_mask_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1130; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8bf16_nxv8bf16:1131; CHECK: # %bb.0: # %entry1132; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, ma1133; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t1134; CHECK-NEXT: ret1135entry:1136 call void @llvm.riscv.vsse.mask.nxv8bf16(1137 <vscale x 8 x bfloat> %0,1138 ptr %1,1139 iXLen %2,1140 <vscale x 8 x i1> %3,1141 iXLen %4)1142 1143 ret void1144}1145 1146define void @intrinsic_vsse_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1147; CHECK-LABEL: intrinsic_vsse_v_nxv16bf16_nxv16bf16:1148; CHECK: # %bb.0: # %entry1149; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma1150; CHECK-NEXT: vsse16.v v8, (a0), a11151; CHECK-NEXT: ret1152entry:1153 call void @llvm.riscv.vsse.nxv16bf16(1154 <vscale x 16 x bfloat> %0,1155 ptr %1,1156 iXLen %2,1157 iXLen %3)1158 1159 ret void1160}1161 1162define void @intrinsic_vsse_mask_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1163; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16bf16_nxv16bf16:1164; CHECK: # %bb.0: # %entry1165; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma1166; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t1167; CHECK-NEXT: ret1168entry:1169 call void @llvm.riscv.vsse.mask.nxv16bf16(1170 <vscale x 16 x bfloat> %0,1171 ptr %1,1172 iXLen %2,1173 <vscale x 16 x i1> %3,1174 iXLen %4)1175 1176 ret void1177}1178 1179define void @intrinsic_vsse_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1180; CHECK-LABEL: intrinsic_vsse_v_nxv32bf16_nxv32bf16:1181; CHECK: # %bb.0: # %entry1182; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma1183; CHECK-NEXT: vsse16.v v8, (a0), a11184; CHECK-NEXT: ret1185entry:1186 call void @llvm.riscv.vsse.nxv32bf16(1187 <vscale x 32 x bfloat> %0,1188 ptr %1,1189 iXLen %2,1190 iXLen %3)1191 1192 ret void1193}1194 1195define void @intrinsic_vsse_mask_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1196; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32bf16_nxv32bf16:1197; CHECK: # %bb.0: # %entry1198; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma1199; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t1200; CHECK-NEXT: ret1201entry:1202 call void @llvm.riscv.vsse.mask.nxv32bf16(1203 <vscale x 32 x bfloat> %0,1204 ptr %1,1205 iXLen %2,1206 <vscale x 32 x i1> %3,1207 iXLen %4)1208 1209 ret void1210}1211 1212define void @intrinsic_vsse_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1213; CHECK-LABEL: intrinsic_vsse_v_nxv1i8_nxv1i8:1214; CHECK: # %bb.0: # %entry1215; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma1216; CHECK-NEXT: vsse8.v v8, (a0), a11217; CHECK-NEXT: ret1218entry:1219 call void @llvm.riscv.vsse.nxv1i8(1220 <vscale x 1 x i8> %0,1221 ptr %1,1222 iXLen %2,1223 iXLen %3)1224 1225 ret void1226}1227 1228define void @intrinsic_vsse_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1229; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i8_nxv1i8:1230; CHECK: # %bb.0: # %entry1231; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, ma1232; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t1233; CHECK-NEXT: ret1234entry:1235 call void @llvm.riscv.vsse.mask.nxv1i8(1236 <vscale x 1 x i8> %0,1237 ptr %1,1238 iXLen %2,1239 <vscale x 1 x i1> %3,1240 iXLen %4)1241 1242 ret void1243}1244 1245define void @intrinsic_vsse_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1246; CHECK-LABEL: intrinsic_vsse_v_nxv2i8_nxv2i8:1247; CHECK: # %bb.0: # %entry1248; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma1249; CHECK-NEXT: vsse8.v v8, (a0), a11250; CHECK-NEXT: ret1251entry:1252 call void @llvm.riscv.vsse.nxv2i8(1253 <vscale x 2 x i8> %0,1254 ptr %1,1255 iXLen %2,1256 iXLen %3)1257 1258 ret void1259}1260 1261define void @intrinsic_vsse_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1262; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i8_nxv2i8:1263; CHECK: # %bb.0: # %entry1264; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, ma1265; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t1266; CHECK-NEXT: ret1267entry:1268 call void @llvm.riscv.vsse.mask.nxv2i8(1269 <vscale x 2 x i8> %0,1270 ptr %1,1271 iXLen %2,1272 <vscale x 2 x i1> %3,1273 iXLen %4)1274 1275 ret void1276}1277 1278define void @intrinsic_vsse_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1279; CHECK-LABEL: intrinsic_vsse_v_nxv4i8_nxv4i8:1280; CHECK: # %bb.0: # %entry1281; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma1282; CHECK-NEXT: vsse8.v v8, (a0), a11283; CHECK-NEXT: ret1284entry:1285 call void @llvm.riscv.vsse.nxv4i8(1286 <vscale x 4 x i8> %0,1287 ptr %1,1288 iXLen %2,1289 iXLen %3)1290 1291 ret void1292}1293 1294define void @intrinsic_vsse_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1295; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i8_nxv4i8:1296; CHECK: # %bb.0: # %entry1297; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, ma1298; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t1299; CHECK-NEXT: ret1300entry:1301 call void @llvm.riscv.vsse.mask.nxv4i8(1302 <vscale x 4 x i8> %0,1303 ptr %1,1304 iXLen %2,1305 <vscale x 4 x i1> %3,1306 iXLen %4)1307 1308 ret void1309}1310 1311define void @intrinsic_vsse_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1312; CHECK-LABEL: intrinsic_vsse_v_nxv8i8_nxv8i8:1313; CHECK: # %bb.0: # %entry1314; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma1315; CHECK-NEXT: vsse8.v v8, (a0), a11316; CHECK-NEXT: ret1317entry:1318 call void @llvm.riscv.vsse.nxv8i8(1319 <vscale x 8 x i8> %0,1320 ptr %1,1321 iXLen %2,1322 iXLen %3)1323 1324 ret void1325}1326 1327define void @intrinsic_vsse_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1328; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i8_nxv8i8:1329; CHECK: # %bb.0: # %entry1330; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma1331; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t1332; CHECK-NEXT: ret1333entry:1334 call void @llvm.riscv.vsse.mask.nxv8i8(1335 <vscale x 8 x i8> %0,1336 ptr %1,1337 iXLen %2,1338 <vscale x 8 x i1> %3,1339 iXLen %4)1340 1341 ret void1342}1343 1344define void @intrinsic_vsse_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1345; CHECK-LABEL: intrinsic_vsse_v_nxv16i8_nxv16i8:1346; CHECK: # %bb.0: # %entry1347; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma1348; CHECK-NEXT: vsse8.v v8, (a0), a11349; CHECK-NEXT: ret1350entry:1351 call void @llvm.riscv.vsse.nxv16i8(1352 <vscale x 16 x i8> %0,1353 ptr %1,1354 iXLen %2,1355 iXLen %3)1356 1357 ret void1358}1359 1360define void @intrinsic_vsse_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1361; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i8_nxv16i8:1362; CHECK: # %bb.0: # %entry1363; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma1364; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t1365; CHECK-NEXT: ret1366entry:1367 call void @llvm.riscv.vsse.mask.nxv16i8(1368 <vscale x 16 x i8> %0,1369 ptr %1,1370 iXLen %2,1371 <vscale x 16 x i1> %3,1372 iXLen %4)1373 1374 ret void1375}1376 1377define void @intrinsic_vsse_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1378; CHECK-LABEL: intrinsic_vsse_v_nxv32i8_nxv32i8:1379; CHECK: # %bb.0: # %entry1380; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma1381; CHECK-NEXT: vsse8.v v8, (a0), a11382; CHECK-NEXT: ret1383entry:1384 call void @llvm.riscv.vsse.nxv32i8(1385 <vscale x 32 x i8> %0,1386 ptr %1,1387 iXLen %2,1388 iXLen %3)1389 1390 ret void1391}1392 1393define void @intrinsic_vsse_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1394; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i8_nxv32i8:1395; CHECK: # %bb.0: # %entry1396; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma1397; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t1398; CHECK-NEXT: ret1399entry:1400 call void @llvm.riscv.vsse.mask.nxv32i8(1401 <vscale x 32 x i8> %0,1402 ptr %1,1403 iXLen %2,1404 <vscale x 32 x i1> %3,1405 iXLen %4)1406 1407 ret void1408}1409 1410define void @intrinsic_vsse_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, iXLen %2, iXLen %3) nounwind {1411; CHECK-LABEL: intrinsic_vsse_v_nxv64i8_nxv64i8:1412; CHECK: # %bb.0: # %entry1413; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma1414; CHECK-NEXT: vsse8.v v8, (a0), a11415; CHECK-NEXT: ret1416entry:1417 call void @llvm.riscv.vsse.nxv64i8(1418 <vscale x 64 x i8> %0,1419 ptr %1,1420 iXLen %2,1421 iXLen %3)1422 1423 ret void1424}1425 1426define void @intrinsic_vsse_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, iXLen %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {1427; CHECK-LABEL: intrinsic_vsse_mask_v_nxv64i8_nxv64i8:1428; CHECK: # %bb.0: # %entry1429; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma1430; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t1431; CHECK-NEXT: ret1432entry:1433 call void @llvm.riscv.vsse.mask.nxv64i8(1434 <vscale x 64 x i8> %0,1435 ptr %1,1436 iXLen %2,1437 <vscale x 64 x i1> %3,1438 iXLen %4)1439 1440 ret void1441}1442