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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs \3; RUN: < %s | FileCheck %s4 5define <vscale x 1 x i8> @test_vssrl_vv_u8mf8(<vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 %vl) {6; CHECK-LABEL: test_vssrl_vv_u8mf8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: csrwi vxrm, 09; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma10; CHECK-NEXT: vssrl.vv v8, v8, v911; CHECK-NEXT: ret12entry:13 %0 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 0, i64 %vl)14 ret <vscale x 1 x i8> %015}16 17define <vscale x 1 x i8> @test_vssrl_vx_u8mf8(<vscale x 1 x i8> %op1, i64 %shift, i64 %vl) {18; CHECK-LABEL: test_vssrl_vx_u8mf8:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: csrwi vxrm, 021; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma22; CHECK-NEXT: vssrl.vx v8, v8, a023; CHECK-NEXT: ret24entry:25 %0 = call <vscale x 1 x i8> @llvm.riscv.vssrl.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %op1, i64 %shift, i64 0, i64 %vl)26 ret <vscale x 1 x i8> %027}28 29define <vscale x 2 x i8> @test_vssrl_vv_u8mf4(<vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 %vl) {30; CHECK-LABEL: test_vssrl_vv_u8mf4:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: csrwi vxrm, 033; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma34; CHECK-NEXT: vssrl.vv v8, v8, v935; CHECK-NEXT: ret36entry:37 %0 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 0, i64 %vl)38 ret <vscale x 2 x i8> %039}40 41define <vscale x 2 x i8> @test_vssrl_vx_u8mf4(<vscale x 2 x i8> %op1, i64 %shift, i64 %vl) {42; CHECK-LABEL: test_vssrl_vx_u8mf4:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: csrwi vxrm, 045; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma46; CHECK-NEXT: vssrl.vx v8, v8, a047; CHECK-NEXT: ret48entry:49 %0 = call <vscale x 2 x i8> @llvm.riscv.vssrl.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %op1, i64 %shift, i64 0, i64 %vl)50 ret <vscale x 2 x i8> %051}52 53define <vscale x 4 x i8> @test_vssrl_vv_u8mf2(<vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 %vl) {54; CHECK-LABEL: test_vssrl_vv_u8mf2:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: csrwi vxrm, 057; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma58; CHECK-NEXT: vssrl.vv v8, v8, v959; CHECK-NEXT: ret60entry:61 %0 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 0, i64 %vl)62 ret <vscale x 4 x i8> %063}64 65define <vscale x 4 x i8> @test_vssrl_vx_u8mf2(<vscale x 4 x i8> %op1, i64 %shift, i64 %vl) {66; CHECK-LABEL: test_vssrl_vx_u8mf2:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: csrwi vxrm, 069; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma70; CHECK-NEXT: vssrl.vx v8, v8, a071; CHECK-NEXT: ret72entry:73 %0 = call <vscale x 4 x i8> @llvm.riscv.vssrl.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %op1, i64 %shift, i64 0, i64 %vl)74 ret <vscale x 4 x i8> %075}76 77define <vscale x 8 x i8> @test_vssrl_vv_u8m1(<vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 %vl) {78; CHECK-LABEL: test_vssrl_vv_u8m1:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: csrwi vxrm, 081; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma82; CHECK-NEXT: vssrl.vv v8, v8, v983; CHECK-NEXT: ret84entry:85 %0 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 0, i64 %vl)86 ret <vscale x 8 x i8> %087}88 89define <vscale x 8 x i8> @test_vssrl_vx_u8m1(<vscale x 8 x i8> %op1, i64 %shift, i64 %vl) {90; CHECK-LABEL: test_vssrl_vx_u8m1:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: csrwi vxrm, 093; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma94; CHECK-NEXT: vssrl.vx v8, v8, a095; CHECK-NEXT: ret96entry:97 %0 = call <vscale x 8 x i8> @llvm.riscv.vssrl.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %op1, i64 %shift, i64 0, i64 %vl)98 ret <vscale x 8 x i8> %099}100 101define <vscale x 16 x i8> @test_vssrl_vv_u8m2(<vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 %vl) {102; CHECK-LABEL: test_vssrl_vv_u8m2:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: csrwi vxrm, 0105; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma106; CHECK-NEXT: vssrl.vv v8, v8, v10107; CHECK-NEXT: ret108entry:109 %0 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 0, i64 %vl)110 ret <vscale x 16 x i8> %0111}112 113define <vscale x 16 x i8> @test_vssrl_vx_u8m2(<vscale x 16 x i8> %op1, i64 %shift, i64 %vl) {114; CHECK-LABEL: test_vssrl_vx_u8m2:115; CHECK: # %bb.0: # %entry116; CHECK-NEXT: csrwi vxrm, 0117; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma118; CHECK-NEXT: vssrl.vx v8, v8, a0119; CHECK-NEXT: ret120entry:121 %0 = call <vscale x 16 x i8> @llvm.riscv.vssrl.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %op1, i64 %shift, i64 0, i64 %vl)122 ret <vscale x 16 x i8> %0123}124 125define <vscale x 32 x i8> @test_vssrl_vv_u8m4(<vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 %vl) {126; CHECK-LABEL: test_vssrl_vv_u8m4:127; CHECK: # %bb.0: # %entry128; CHECK-NEXT: csrwi vxrm, 0129; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma130; CHECK-NEXT: vssrl.vv v8, v8, v12131; CHECK-NEXT: ret132entry:133 %0 = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 0, i64 %vl)134 ret <vscale x 32 x i8> %0135}136 137define <vscale x 32 x i8> @test_vssrl_vx_u8m4(<vscale x 32 x i8> %op1, i64 %shift, i64 %vl) {138; CHECK-LABEL: test_vssrl_vx_u8m4:139; CHECK: # %bb.0: # %entry140; CHECK-NEXT: csrwi vxrm, 0141; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma142; CHECK-NEXT: vssrl.vx v8, v8, a0143; CHECK-NEXT: ret144entry:145 %0 = call <vscale x 32 x i8> @llvm.riscv.vssrl.nxv32i8.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %op1, i64 %shift, i64 0, i64 %vl)146 ret <vscale x 32 x i8> %0147}148 149define <vscale x 64 x i8> @test_vssrl_vv_u8m8(<vscale x 64 x i8> %op1, <vscale x 64 x i8> %shift, i64 %vl) {150; CHECK-LABEL: test_vssrl_vv_u8m8:151; CHECK: # %bb.0: # %entry152; CHECK-NEXT: csrwi vxrm, 0153; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma154; CHECK-NEXT: vssrl.vv v8, v8, v16155; CHECK-NEXT: ret156entry:157 %0 = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %op1, <vscale x 64 x i8> %shift, i64 0, i64 %vl)158 ret <vscale x 64 x i8> %0159}160 161define <vscale x 64 x i8> @test_vssrl_vx_u8m8(<vscale x 64 x i8> %op1, i64 %shift, i64 %vl) {162; CHECK-LABEL: test_vssrl_vx_u8m8:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: csrwi vxrm, 0165; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma166; CHECK-NEXT: vssrl.vx v8, v8, a0167; CHECK-NEXT: ret168entry:169 %0 = call <vscale x 64 x i8> @llvm.riscv.vssrl.nxv64i8.i64.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %op1, i64 %shift, i64 0, i64 %vl)170 ret <vscale x 64 x i8> %0171}172 173define <vscale x 1 x i16> @test_vssrl_vv_u16mf4(<vscale x 1 x i16> %op1, <vscale x 1 x i16> %shift, i64 %vl) {174; CHECK-LABEL: test_vssrl_vv_u16mf4:175; CHECK: # %bb.0: # %entry176; CHECK-NEXT: csrwi vxrm, 0177; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma178; CHECK-NEXT: vssrl.vv v8, v8, v9179; CHECK-NEXT: ret180entry:181 %0 = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %op1, <vscale x 1 x i16> %shift, i64 0, i64 %vl)182 ret <vscale x 1 x i16> %0183}184 185define <vscale x 1 x i16> @test_vssrl_vx_u16mf4(<vscale x 1 x i16> %op1, i64 %shift, i64 %vl) {186; CHECK-LABEL: test_vssrl_vx_u16mf4:187; CHECK: # %bb.0: # %entry188; CHECK-NEXT: csrwi vxrm, 0189; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma190; CHECK-NEXT: vssrl.vx v8, v8, a0191; CHECK-NEXT: ret192entry:193 %0 = call <vscale x 1 x i16> @llvm.riscv.vssrl.nxv1i16.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %op1, i64 %shift, i64 0, i64 %vl)194 ret <vscale x 1 x i16> %0195}196 197define <vscale x 2 x i16> @test_vssrl_vv_u16mf2(<vscale x 2 x i16> %op1, <vscale x 2 x i16> %shift, i64 %vl) {198; CHECK-LABEL: test_vssrl_vv_u16mf2:199; CHECK: # %bb.0: # %entry200; CHECK-NEXT: csrwi vxrm, 0201; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma202; CHECK-NEXT: vssrl.vv v8, v8, v9203; CHECK-NEXT: ret204entry:205 %0 = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %op1, <vscale x 2 x i16> %shift, i64 0, i64 %vl)206 ret <vscale x 2 x i16> %0207}208 209define <vscale x 2 x i16> @test_vssrl_vx_u16mf2(<vscale x 2 x i16> %op1, i64 %shift, i64 %vl) {210; CHECK-LABEL: test_vssrl_vx_u16mf2:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: csrwi vxrm, 0213; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma214; CHECK-NEXT: vssrl.vx v8, v8, a0215; CHECK-NEXT: ret216entry:217 %0 = call <vscale x 2 x i16> @llvm.riscv.vssrl.nxv2i16.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %op1, i64 %shift, i64 0, i64 %vl)218 ret <vscale x 2 x i16> %0219}220 221define <vscale x 4 x i16> @test_vssrl_vv_u16m1(<vscale x 4 x i16> %op1, <vscale x 4 x i16> %shift, i64 %vl) {222; CHECK-LABEL: test_vssrl_vv_u16m1:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: csrwi vxrm, 0225; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma226; CHECK-NEXT: vssrl.vv v8, v8, v9227; CHECK-NEXT: ret228entry:229 %0 = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %op1, <vscale x 4 x i16> %shift, i64 0, i64 %vl)230 ret <vscale x 4 x i16> %0231}232 233define <vscale x 4 x i16> @test_vssrl_vx_u16m1(<vscale x 4 x i16> %op1, i64 %shift, i64 %vl) {234; CHECK-LABEL: test_vssrl_vx_u16m1:235; CHECK: # %bb.0: # %entry236; CHECK-NEXT: csrwi vxrm, 0237; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma238; CHECK-NEXT: vssrl.vx v8, v8, a0239; CHECK-NEXT: ret240entry:241 %0 = call <vscale x 4 x i16> @llvm.riscv.vssrl.nxv4i16.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %op1, i64 %shift, i64 0, i64 %vl)242 ret <vscale x 4 x i16> %0243}244 245define <vscale x 8 x i16> @test_vssrl_vv_u16m2(<vscale x 8 x i16> %op1, <vscale x 8 x i16> %shift, i64 %vl) {246; CHECK-LABEL: test_vssrl_vv_u16m2:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: csrwi vxrm, 0249; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma250; CHECK-NEXT: vssrl.vv v8, v8, v10251; CHECK-NEXT: ret252entry:253 %0 = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %shift, i64 0, i64 %vl)254 ret <vscale x 8 x i16> %0255}256 257define <vscale x 8 x i16> @test_vssrl_vx_u16m2(<vscale x 8 x i16> %op1, i64 %shift, i64 %vl) {258; CHECK-LABEL: test_vssrl_vx_u16m2:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: csrwi vxrm, 0261; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma262; CHECK-NEXT: vssrl.vx v8, v8, a0263; CHECK-NEXT: ret264entry:265 %0 = call <vscale x 8 x i16> @llvm.riscv.vssrl.nxv8i16.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %op1, i64 %shift, i64 0, i64 %vl)266 ret <vscale x 8 x i16> %0267}268 269define <vscale x 16 x i16> @test_vssrl_vv_u16m4(<vscale x 16 x i16> %op1, <vscale x 16 x i16> %shift, i64 %vl) {270; CHECK-LABEL: test_vssrl_vv_u16m4:271; CHECK: # %bb.0: # %entry272; CHECK-NEXT: csrwi vxrm, 0273; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma274; CHECK-NEXT: vssrl.vv v8, v8, v12275; CHECK-NEXT: ret276entry:277 %0 = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %op1, <vscale x 16 x i16> %shift, i64 0, i64 %vl)278 ret <vscale x 16 x i16> %0279}280 281define <vscale x 16 x i16> @test_vssrl_vx_u16m4(<vscale x 16 x i16> %op1, i64 %shift, i64 %vl) {282; CHECK-LABEL: test_vssrl_vx_u16m4:283; CHECK: # %bb.0: # %entry284; CHECK-NEXT: csrwi vxrm, 0285; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma286; CHECK-NEXT: vssrl.vx v8, v8, a0287; CHECK-NEXT: ret288entry:289 %0 = call <vscale x 16 x i16> @llvm.riscv.vssrl.nxv16i16.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %op1, i64 %shift, i64 0, i64 %vl)290 ret <vscale x 16 x i16> %0291}292 293define <vscale x 32 x i16> @test_vssrl_vv_u16m8(<vscale x 32 x i16> %op1, <vscale x 32 x i16> %shift, i64 %vl) {294; CHECK-LABEL: test_vssrl_vv_u16m8:295; CHECK: # %bb.0: # %entry296; CHECK-NEXT: csrwi vxrm, 0297; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma298; CHECK-NEXT: vssrl.vv v8, v8, v16299; CHECK-NEXT: ret300entry:301 %0 = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %op1, <vscale x 32 x i16> %shift, i64 0, i64 %vl)302 ret <vscale x 32 x i16> %0303}304 305define <vscale x 32 x i16> @test_vssrl_vx_u16m8(<vscale x 32 x i16> %op1, i64 %shift, i64 %vl) {306; CHECK-LABEL: test_vssrl_vx_u16m8:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: csrwi vxrm, 0309; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma310; CHECK-NEXT: vssrl.vx v8, v8, a0311; CHECK-NEXT: ret312entry:313 %0 = call <vscale x 32 x i16> @llvm.riscv.vssrl.nxv32i16.i64.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %op1, i64 %shift, i64 0, i64 %vl)314 ret <vscale x 32 x i16> %0315}316 317define <vscale x 1 x i32> @test_vssrl_vv_u32mf2(<vscale x 1 x i32> %op1, <vscale x 1 x i32> %shift, i64 %vl) {318; CHECK-LABEL: test_vssrl_vv_u32mf2:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: csrwi vxrm, 0321; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma322; CHECK-NEXT: vssrl.vv v8, v8, v9323; CHECK-NEXT: ret324entry:325 %0 = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %op1, <vscale x 1 x i32> %shift, i64 0, i64 %vl)326 ret <vscale x 1 x i32> %0327}328 329define <vscale x 1 x i32> @test_vssrl_vx_u32mf2(<vscale x 1 x i32> %op1, i64 %shift, i64 %vl) {330; CHECK-LABEL: test_vssrl_vx_u32mf2:331; CHECK: # %bb.0: # %entry332; CHECK-NEXT: csrwi vxrm, 0333; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma334; CHECK-NEXT: vssrl.vx v8, v8, a0335; CHECK-NEXT: ret336entry:337 %0 = call <vscale x 1 x i32> @llvm.riscv.vssrl.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %op1, i64 %shift, i64 0, i64 %vl)338 ret <vscale x 1 x i32> %0339}340 341define <vscale x 2 x i32> @test_vssrl_vv_u32m1(<vscale x 2 x i32> %op1, <vscale x 2 x i32> %shift, i64 %vl) {342; CHECK-LABEL: test_vssrl_vv_u32m1:343; CHECK: # %bb.0: # %entry344; CHECK-NEXT: csrwi vxrm, 0345; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma346; CHECK-NEXT: vssrl.vv v8, v8, v9347; CHECK-NEXT: ret348entry:349 %0 = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %op1, <vscale x 2 x i32> %shift, i64 0, i64 %vl)350 ret <vscale x 2 x i32> %0351}352 353define <vscale x 2 x i32> @test_vssrl_vx_u32m1(<vscale x 2 x i32> %op1, i64 %shift, i64 %vl) {354; CHECK-LABEL: test_vssrl_vx_u32m1:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: csrwi vxrm, 0357; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma358; CHECK-NEXT: vssrl.vx v8, v8, a0359; CHECK-NEXT: ret360entry:361 %0 = call <vscale x 2 x i32> @llvm.riscv.vssrl.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %op1, i64 %shift, i64 0, i64 %vl)362 ret <vscale x 2 x i32> %0363}364 365define <vscale x 4 x i32> @test_vssrl_vv_u32m2(<vscale x 4 x i32> %op1, <vscale x 4 x i32> %shift, i64 %vl) {366; CHECK-LABEL: test_vssrl_vv_u32m2:367; CHECK: # %bb.0: # %entry368; CHECK-NEXT: csrwi vxrm, 0369; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma370; CHECK-NEXT: vssrl.vv v8, v8, v10371; CHECK-NEXT: ret372entry:373 %0 = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %shift, i64 0, i64 %vl)374 ret <vscale x 4 x i32> %0375}376 377define <vscale x 4 x i32> @test_vssrl_vx_u32m2(<vscale x 4 x i32> %op1, i64 %shift, i64 %vl) {378; CHECK-LABEL: test_vssrl_vx_u32m2:379; CHECK: # %bb.0: # %entry380; CHECK-NEXT: csrwi vxrm, 0381; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma382; CHECK-NEXT: vssrl.vx v8, v8, a0383; CHECK-NEXT: ret384entry:385 %0 = call <vscale x 4 x i32> @llvm.riscv.vssrl.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %op1, i64 %shift, i64 0, i64 %vl)386 ret <vscale x 4 x i32> %0387}388 389define <vscale x 8 x i32> @test_vssrl_vv_u32m4(<vscale x 8 x i32> %op1, <vscale x 8 x i32> %shift, i64 %vl) {390; CHECK-LABEL: test_vssrl_vv_u32m4:391; CHECK: # %bb.0: # %entry392; CHECK-NEXT: csrwi vxrm, 0393; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma394; CHECK-NEXT: vssrl.vv v8, v8, v12395; CHECK-NEXT: ret396entry:397 %0 = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %op1, <vscale x 8 x i32> %shift, i64 0, i64 %vl)398 ret <vscale x 8 x i32> %0399}400 401define <vscale x 8 x i32> @test_vssrl_vx_u32m4(<vscale x 8 x i32> %op1, i64 %shift, i64 %vl) {402; CHECK-LABEL: test_vssrl_vx_u32m4:403; CHECK: # %bb.0: # %entry404; CHECK-NEXT: csrwi vxrm, 0405; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma406; CHECK-NEXT: vssrl.vx v8, v8, a0407; CHECK-NEXT: ret408entry:409 %0 = call <vscale x 8 x i32> @llvm.riscv.vssrl.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %op1, i64 %shift, i64 0, i64 %vl)410 ret <vscale x 8 x i32> %0411}412 413define <vscale x 16 x i32> @test_vssrl_vv_u32m8(<vscale x 16 x i32> %op1, <vscale x 16 x i32> %shift, i64 %vl) {414; CHECK-LABEL: test_vssrl_vv_u32m8:415; CHECK: # %bb.0: # %entry416; CHECK-NEXT: csrwi vxrm, 0417; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma418; CHECK-NEXT: vssrl.vv v8, v8, v16419; CHECK-NEXT: ret420entry:421 %0 = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %op1, <vscale x 16 x i32> %shift, i64 0, i64 %vl)422 ret <vscale x 16 x i32> %0423}424 425define <vscale x 16 x i32> @test_vssrl_vx_u32m8(<vscale x 16 x i32> %op1, i64 %shift, i64 %vl) {426; CHECK-LABEL: test_vssrl_vx_u32m8:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: csrwi vxrm, 0429; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma430; CHECK-NEXT: vssrl.vx v8, v8, a0431; CHECK-NEXT: ret432entry:433 %0 = call <vscale x 16 x i32> @llvm.riscv.vssrl.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %op1, i64 %shift, i64 0, i64 %vl)434 ret <vscale x 16 x i32> %0435}436 437define <vscale x 1 x i64> @test_vssrl_vv_u64m1(<vscale x 1 x i64> %op1, <vscale x 1 x i64> %shift, i64 %vl) {438; CHECK-LABEL: test_vssrl_vv_u64m1:439; CHECK: # %bb.0: # %entry440; CHECK-NEXT: csrwi vxrm, 0441; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma442; CHECK-NEXT: vssrl.vv v8, v8, v9443; CHECK-NEXT: ret444entry:445 %0 = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %shift, i64 0, i64 %vl)446 ret <vscale x 1 x i64> %0447}448 449define <vscale x 1 x i64> @test_vssrl_vx_u64m1(<vscale x 1 x i64> %op1, i64 %shift, i64 %vl) {450; CHECK-LABEL: test_vssrl_vx_u64m1:451; CHECK: # %bb.0: # %entry452; CHECK-NEXT: csrwi vxrm, 0453; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma454; CHECK-NEXT: vssrl.vx v8, v8, a0455; CHECK-NEXT: ret456entry:457 %0 = call <vscale x 1 x i64> @llvm.riscv.vssrl.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %op1, i64 %shift, i64 0, i64 %vl)458 ret <vscale x 1 x i64> %0459}460 461define <vscale x 2 x i64> @test_vssrl_vv_u64m2(<vscale x 2 x i64> %op1, <vscale x 2 x i64> %shift, i64 %vl) {462; CHECK-LABEL: test_vssrl_vv_u64m2:463; CHECK: # %bb.0: # %entry464; CHECK-NEXT: csrwi vxrm, 0465; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma466; CHECK-NEXT: vssrl.vv v8, v8, v10467; CHECK-NEXT: ret468entry:469 %0 = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %shift, i64 0, i64 %vl)470 ret <vscale x 2 x i64> %0471}472 473define <vscale x 2 x i64> @test_vssrl_vx_u64m2(<vscale x 2 x i64> %op1, i64 %shift, i64 %vl) {474; CHECK-LABEL: test_vssrl_vx_u64m2:475; CHECK: # %bb.0: # %entry476; CHECK-NEXT: csrwi vxrm, 0477; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma478; CHECK-NEXT: vssrl.vx v8, v8, a0479; CHECK-NEXT: ret480entry:481 %0 = call <vscale x 2 x i64> @llvm.riscv.vssrl.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %op1, i64 %shift, i64 0, i64 %vl)482 ret <vscale x 2 x i64> %0483}484 485define <vscale x 4 x i64> @test_vssrl_vv_u64m4(<vscale x 4 x i64> %op1, <vscale x 4 x i64> %shift, i64 %vl) {486; CHECK-LABEL: test_vssrl_vv_u64m4:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: csrwi vxrm, 0489; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma490; CHECK-NEXT: vssrl.vv v8, v8, v12491; CHECK-NEXT: ret492entry:493 %0 = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %op1, <vscale x 4 x i64> %shift, i64 0, i64 %vl)494 ret <vscale x 4 x i64> %0495}496 497define <vscale x 4 x i64> @test_vssrl_vx_u64m4(<vscale x 4 x i64> %op1, i64 %shift, i64 %vl) {498; CHECK-LABEL: test_vssrl_vx_u64m4:499; CHECK: # %bb.0: # %entry500; CHECK-NEXT: csrwi vxrm, 0501; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma502; CHECK-NEXT: vssrl.vx v8, v8, a0503; CHECK-NEXT: ret504entry:505 %0 = call <vscale x 4 x i64> @llvm.riscv.vssrl.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %op1, i64 %shift, i64 0, i64 %vl)506 ret <vscale x 4 x i64> %0507}508 509define <vscale x 8 x i64> @test_vssrl_vv_u64m8(<vscale x 8 x i64> %op1, <vscale x 8 x i64> %shift, i64 %vl) {510; CHECK-LABEL: test_vssrl_vv_u64m8:511; CHECK: # %bb.0: # %entry512; CHECK-NEXT: csrwi vxrm, 0513; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma514; CHECK-NEXT: vssrl.vv v8, v8, v16515; CHECK-NEXT: ret516entry:517 %0 = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %op1, <vscale x 8 x i64> %shift, i64 0, i64 %vl)518 ret <vscale x 8 x i64> %0519}520 521define <vscale x 8 x i64> @test_vssrl_vx_u64m8(<vscale x 8 x i64> %op1, i64 %shift, i64 %vl) {522; CHECK-LABEL: test_vssrl_vx_u64m8:523; CHECK: # %bb.0: # %entry524; CHECK-NEXT: csrwi vxrm, 0525; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma526; CHECK-NEXT: vssrl.vx v8, v8, a0527; CHECK-NEXT: ret528entry:529 %0 = call <vscale x 8 x i64> @llvm.riscv.vssrl.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %op1, i64 %shift, i64 0, i64 %vl)530 ret <vscale x 8 x i64> %0531}532 533define <vscale x 1 x i8> @test_vssrl_vv_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, i64 %vl) {534; CHECK-LABEL: test_vssrl_vv_u8mf8_m:535; CHECK: # %bb.0: # %entry536; CHECK-NEXT: csrwi vxrm, 0537; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma538; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t539; CHECK-NEXT: ret540entry:541 %0 = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %op1, <vscale x 1 x i8> %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)542 ret <vscale x 1 x i8> %0543}544 545define <vscale x 1 x i8> @test_vssrl_vx_u8mf8_m(<vscale x 1 x i1> %mask, <vscale x 1 x i8> %op1, i64 %shift, i64 %vl) {546; CHECK-LABEL: test_vssrl_vx_u8mf8_m:547; CHECK: # %bb.0: # %entry548; CHECK-NEXT: csrwi vxrm, 0549; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma550; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t551; CHECK-NEXT: ret552entry:553 %0 = call <vscale x 1 x i8> @llvm.riscv.vssrl.mask.nxv1i8.i64.i64(<vscale x 1 x i8> poison, <vscale x 1 x i8> %op1, i64 %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)554 ret <vscale x 1 x i8> %0555}556 557define <vscale x 2 x i8> @test_vssrl_vv_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, i64 %vl) {558; CHECK-LABEL: test_vssrl_vv_u8mf4_m:559; CHECK: # %bb.0: # %entry560; CHECK-NEXT: csrwi vxrm, 0561; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma562; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t563; CHECK-NEXT: ret564entry:565 %0 = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.nxv2i8.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %op1, <vscale x 2 x i8> %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)566 ret <vscale x 2 x i8> %0567}568 569define <vscale x 2 x i8> @test_vssrl_vx_u8mf4_m(<vscale x 2 x i1> %mask, <vscale x 2 x i8> %op1, i64 %shift, i64 %vl) {570; CHECK-LABEL: test_vssrl_vx_u8mf4_m:571; CHECK: # %bb.0: # %entry572; CHECK-NEXT: csrwi vxrm, 0573; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma574; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t575; CHECK-NEXT: ret576entry:577 %0 = call <vscale x 2 x i8> @llvm.riscv.vssrl.mask.nxv2i8.i64.i64(<vscale x 2 x i8> poison, <vscale x 2 x i8> %op1, i64 %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)578 ret <vscale x 2 x i8> %0579}580 581define <vscale x 4 x i8> @test_vssrl_vv_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, i64 %vl) {582; CHECK-LABEL: test_vssrl_vv_u8mf2_m:583; CHECK: # %bb.0: # %entry584; CHECK-NEXT: csrwi vxrm, 0585; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma586; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t587; CHECK-NEXT: ret588entry:589 %0 = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.nxv4i8.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %op1, <vscale x 4 x i8> %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)590 ret <vscale x 4 x i8> %0591}592 593define <vscale x 4 x i8> @test_vssrl_vx_u8mf2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i8> %op1, i64 %shift, i64 %vl) {594; CHECK-LABEL: test_vssrl_vx_u8mf2_m:595; CHECK: # %bb.0: # %entry596; CHECK-NEXT: csrwi vxrm, 0597; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma598; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t599; CHECK-NEXT: ret600entry:601 %0 = call <vscale x 4 x i8> @llvm.riscv.vssrl.mask.nxv4i8.i64.i64(<vscale x 4 x i8> poison, <vscale x 4 x i8> %op1, i64 %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)602 ret <vscale x 4 x i8> %0603}604 605define <vscale x 8 x i8> @test_vssrl_vv_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, i64 %vl) {606; CHECK-LABEL: test_vssrl_vv_u8m1_m:607; CHECK: # %bb.0: # %entry608; CHECK-NEXT: csrwi vxrm, 0609; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma610; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t611; CHECK-NEXT: ret612entry:613 %0 = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.nxv8i8.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %op1, <vscale x 8 x i8> %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)614 ret <vscale x 8 x i8> %0615}616 617define <vscale x 8 x i8> @test_vssrl_vx_u8m1_m(<vscale x 8 x i1> %mask, <vscale x 8 x i8> %op1, i64 %shift, i64 %vl) {618; CHECK-LABEL: test_vssrl_vx_u8m1_m:619; CHECK: # %bb.0: # %entry620; CHECK-NEXT: csrwi vxrm, 0621; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma622; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t623; CHECK-NEXT: ret624entry:625 %0 = call <vscale x 8 x i8> @llvm.riscv.vssrl.mask.nxv8i8.i64.i64(<vscale x 8 x i8> poison, <vscale x 8 x i8> %op1, i64 %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)626 ret <vscale x 8 x i8> %0627}628 629define <vscale x 16 x i8> @test_vssrl_vv_u8m2_m(<vscale x 16 x i1> %mask, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, i64 %vl) {630; CHECK-LABEL: test_vssrl_vv_u8m2_m:631; CHECK: # %bb.0: # %entry632; CHECK-NEXT: csrwi vxrm, 0633; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma634; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t635; CHECK-NEXT: ret636entry:637 %0 = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.nxv16i8.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %op1, <vscale x 16 x i8> %shift, <vscale x 16 x i1> %mask, i64 0, i64 %vl, i64 3)638 ret <vscale x 16 x i8> %0639}640 641define <vscale x 16 x i8> @test_vssrl_vx_u8m2_m(<vscale x 16 x i1> %mask, <vscale x 16 x i8> %op1, i64 %shift, i64 %vl) {642; CHECK-LABEL: test_vssrl_vx_u8m2_m:643; CHECK: # %bb.0: # %entry644; CHECK-NEXT: csrwi vxrm, 0645; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma646; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t647; CHECK-NEXT: ret648entry:649 %0 = call <vscale x 16 x i8> @llvm.riscv.vssrl.mask.nxv16i8.i64.i64(<vscale x 16 x i8> poison, <vscale x 16 x i8> %op1, i64 %shift, <vscale x 16 x i1> %mask, i64 0, i64 %vl, i64 3)650 ret <vscale x 16 x i8> %0651}652 653define <vscale x 32 x i8> @test_vssrl_vv_u8m4_m(<vscale x 32 x i1> %mask, <vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, i64 %vl) {654; CHECK-LABEL: test_vssrl_vv_u8m4_m:655; CHECK: # %bb.0: # %entry656; CHECK-NEXT: csrwi vxrm, 0657; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma658; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t659; CHECK-NEXT: ret660entry:661 %0 = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.nxv32i8.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %op1, <vscale x 32 x i8> %shift, <vscale x 32 x i1> %mask, i64 0, i64 %vl, i64 3)662 ret <vscale x 32 x i8> %0663}664 665define <vscale x 32 x i8> @test_vssrl_vx_u8m4_m(<vscale x 32 x i1> %mask, <vscale x 32 x i8> %op1, i64 %shift, i64 %vl) {666; CHECK-LABEL: test_vssrl_vx_u8m4_m:667; CHECK: # %bb.0: # %entry668; CHECK-NEXT: csrwi vxrm, 0669; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma670; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t671; CHECK-NEXT: ret672entry:673 %0 = call <vscale x 32 x i8> @llvm.riscv.vssrl.mask.nxv32i8.i64.i64(<vscale x 32 x i8> poison, <vscale x 32 x i8> %op1, i64 %shift, <vscale x 32 x i1> %mask, i64 0, i64 %vl, i64 3)674 ret <vscale x 32 x i8> %0675}676 677define <vscale x 64 x i8> @test_vssrl_vv_u8m8_m(<vscale x 64 x i1> %mask, <vscale x 64 x i8> %op1, <vscale x 64 x i8> %shift, i64 %vl) {678; CHECK-LABEL: test_vssrl_vv_u8m8_m:679; CHECK: # %bb.0: # %entry680; CHECK-NEXT: csrwi vxrm, 0681; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma682; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t683; CHECK-NEXT: ret684entry:685 %0 = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %op1, <vscale x 64 x i8> %shift, <vscale x 64 x i1> %mask, i64 0, i64 %vl, i64 3)686 ret <vscale x 64 x i8> %0687}688 689define <vscale x 64 x i8> @test_vssrl_vx_u8m8_m(<vscale x 64 x i1> %mask, <vscale x 64 x i8> %op1, i64 %shift, i64 %vl) {690; CHECK-LABEL: test_vssrl_vx_u8m8_m:691; CHECK: # %bb.0: # %entry692; CHECK-NEXT: csrwi vxrm, 0693; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma694; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t695; CHECK-NEXT: ret696entry:697 %0 = call <vscale x 64 x i8> @llvm.riscv.vssrl.mask.nxv64i8.i64.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %op1, i64 %shift, <vscale x 64 x i1> %mask, i64 0, i64 %vl, i64 3)698 ret <vscale x 64 x i8> %0699}700 701define <vscale x 1 x i16> @test_vssrl_vv_u16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x i16> %op1, <vscale x 1 x i16> %shift, i64 %vl) {702; CHECK-LABEL: test_vssrl_vv_u16mf4_m:703; CHECK: # %bb.0: # %entry704; CHECK-NEXT: csrwi vxrm, 0705; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma706; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t707; CHECK-NEXT: ret708entry:709 %0 = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.nxv1i16.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %op1, <vscale x 1 x i16> %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)710 ret <vscale x 1 x i16> %0711}712 713define <vscale x 1 x i16> @test_vssrl_vx_u16mf4_m(<vscale x 1 x i1> %mask, <vscale x 1 x i16> %op1, i64 %shift, i64 %vl) {714; CHECK-LABEL: test_vssrl_vx_u16mf4_m:715; CHECK: # %bb.0: # %entry716; CHECK-NEXT: csrwi vxrm, 0717; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma718; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t719; CHECK-NEXT: ret720entry:721 %0 = call <vscale x 1 x i16> @llvm.riscv.vssrl.mask.nxv1i16.i64.i64(<vscale x 1 x i16> poison, <vscale x 1 x i16> %op1, i64 %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)722 ret <vscale x 1 x i16> %0723}724 725define <vscale x 2 x i16> @test_vssrl_vv_u16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i16> %op1, <vscale x 2 x i16> %shift, i64 %vl) {726; CHECK-LABEL: test_vssrl_vv_u16mf2_m:727; CHECK: # %bb.0: # %entry728; CHECK-NEXT: csrwi vxrm, 0729; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma730; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t731; CHECK-NEXT: ret732entry:733 %0 = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.nxv2i16.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %op1, <vscale x 2 x i16> %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)734 ret <vscale x 2 x i16> %0735}736 737define <vscale x 2 x i16> @test_vssrl_vx_u16mf2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i16> %op1, i64 %shift, i64 %vl) {738; CHECK-LABEL: test_vssrl_vx_u16mf2_m:739; CHECK: # %bb.0: # %entry740; CHECK-NEXT: csrwi vxrm, 0741; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma742; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t743; CHECK-NEXT: ret744entry:745 %0 = call <vscale x 2 x i16> @llvm.riscv.vssrl.mask.nxv2i16.i64.i64(<vscale x 2 x i16> poison, <vscale x 2 x i16> %op1, i64 %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)746 ret <vscale x 2 x i16> %0747}748 749define <vscale x 4 x i16> @test_vssrl_vv_u16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x i16> %op1, <vscale x 4 x i16> %shift, i64 %vl) {750; CHECK-LABEL: test_vssrl_vv_u16m1_m:751; CHECK: # %bb.0: # %entry752; CHECK-NEXT: csrwi vxrm, 0753; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma754; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t755; CHECK-NEXT: ret756entry:757 %0 = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.nxv4i16.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %op1, <vscale x 4 x i16> %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)758 ret <vscale x 4 x i16> %0759}760 761define <vscale x 4 x i16> @test_vssrl_vx_u16m1_m(<vscale x 4 x i1> %mask, <vscale x 4 x i16> %op1, i64 %shift, i64 %vl) {762; CHECK-LABEL: test_vssrl_vx_u16m1_m:763; CHECK: # %bb.0: # %entry764; CHECK-NEXT: csrwi vxrm, 0765; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma766; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t767; CHECK-NEXT: ret768entry:769 %0 = call <vscale x 4 x i16> @llvm.riscv.vssrl.mask.nxv4i16.i64.i64(<vscale x 4 x i16> poison, <vscale x 4 x i16> %op1, i64 %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)770 ret <vscale x 4 x i16> %0771}772 773define <vscale x 8 x i16> @test_vssrl_vv_u16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %shift, i64 %vl) {774; CHECK-LABEL: test_vssrl_vv_u16m2_m:775; CHECK: # %bb.0: # %entry776; CHECK-NEXT: csrwi vxrm, 0777; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma778; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t779; CHECK-NEXT: ret780entry:781 %0 = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.nxv8i16.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %op1, <vscale x 8 x i16> %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)782 ret <vscale x 8 x i16> %0783}784 785define <vscale x 8 x i16> @test_vssrl_vx_u16m2_m(<vscale x 8 x i1> %mask, <vscale x 8 x i16> %op1, i64 %shift, i64 %vl) {786; CHECK-LABEL: test_vssrl_vx_u16m2_m:787; CHECK: # %bb.0: # %entry788; CHECK-NEXT: csrwi vxrm, 0789; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma790; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t791; CHECK-NEXT: ret792entry:793 %0 = call <vscale x 8 x i16> @llvm.riscv.vssrl.mask.nxv8i16.i64.i64(<vscale x 8 x i16> poison, <vscale x 8 x i16> %op1, i64 %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)794 ret <vscale x 8 x i16> %0795}796 797define <vscale x 16 x i16> @test_vssrl_vv_u16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i16> %op1, <vscale x 16 x i16> %shift, i64 %vl) {798; CHECK-LABEL: test_vssrl_vv_u16m4_m:799; CHECK: # %bb.0: # %entry800; CHECK-NEXT: csrwi vxrm, 0801; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma802; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t803; CHECK-NEXT: ret804entry:805 %0 = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.nxv16i16.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %op1, <vscale x 16 x i16> %shift, <vscale x 16 x i1> %mask, i64 0, i64 %vl, i64 3)806 ret <vscale x 16 x i16> %0807}808 809define <vscale x 16 x i16> @test_vssrl_vx_u16m4_m(<vscale x 16 x i1> %mask, <vscale x 16 x i16> %op1, i64 %shift, i64 %vl) {810; CHECK-LABEL: test_vssrl_vx_u16m4_m:811; CHECK: # %bb.0: # %entry812; CHECK-NEXT: csrwi vxrm, 0813; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma814; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t815; CHECK-NEXT: ret816entry:817 %0 = call <vscale x 16 x i16> @llvm.riscv.vssrl.mask.nxv16i16.i64.i64(<vscale x 16 x i16> poison, <vscale x 16 x i16> %op1, i64 %shift, <vscale x 16 x i1> %mask, i64 0, i64 %vl, i64 3)818 ret <vscale x 16 x i16> %0819}820 821define <vscale x 32 x i16> @test_vssrl_vv_u16m8_m(<vscale x 32 x i1> %mask, <vscale x 32 x i16> %op1, <vscale x 32 x i16> %shift, i64 %vl) {822; CHECK-LABEL: test_vssrl_vv_u16m8_m:823; CHECK: # %bb.0: # %entry824; CHECK-NEXT: csrwi vxrm, 0825; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma826; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t827; CHECK-NEXT: ret828entry:829 %0 = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %op1, <vscale x 32 x i16> %shift, <vscale x 32 x i1> %mask, i64 0, i64 %vl, i64 3)830 ret <vscale x 32 x i16> %0831}832 833define <vscale x 32 x i16> @test_vssrl_vx_u16m8_m(<vscale x 32 x i1> %mask, <vscale x 32 x i16> %op1, i64 %shift, i64 %vl) {834; CHECK-LABEL: test_vssrl_vx_u16m8_m:835; CHECK: # %bb.0: # %entry836; CHECK-NEXT: csrwi vxrm, 0837; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma838; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t839; CHECK-NEXT: ret840entry:841 %0 = call <vscale x 32 x i16> @llvm.riscv.vssrl.mask.nxv32i16.i64.i64(<vscale x 32 x i16> poison, <vscale x 32 x i16> %op1, i64 %shift, <vscale x 32 x i1> %mask, i64 0, i64 %vl, i64 3)842 ret <vscale x 32 x i16> %0843}844 845define <vscale x 1 x i32> @test_vssrl_vv_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %op1, <vscale x 1 x i32> %shift, i64 %vl) {846; CHECK-LABEL: test_vssrl_vv_u32mf2_m:847; CHECK: # %bb.0: # %entry848; CHECK-NEXT: csrwi vxrm, 0849; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma850; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t851; CHECK-NEXT: ret852entry:853 %0 = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %op1, <vscale x 1 x i32> %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)854 ret <vscale x 1 x i32> %0855}856 857define <vscale x 1 x i32> @test_vssrl_vx_u32mf2_m(<vscale x 1 x i1> %mask, <vscale x 1 x i32> %op1, i64 %shift, i64 %vl) {858; CHECK-LABEL: test_vssrl_vx_u32mf2_m:859; CHECK: # %bb.0: # %entry860; CHECK-NEXT: csrwi vxrm, 0861; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma862; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t863; CHECK-NEXT: ret864entry:865 %0 = call <vscale x 1 x i32> @llvm.riscv.vssrl.mask.nxv1i32.i64.i64(<vscale x 1 x i32> poison, <vscale x 1 x i32> %op1, i64 %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)866 ret <vscale x 1 x i32> %0867}868 869define <vscale x 2 x i32> @test_vssrl_vv_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i32> %op1, <vscale x 2 x i32> %shift, i64 %vl) {870; CHECK-LABEL: test_vssrl_vv_u32m1_m:871; CHECK: # %bb.0: # %entry872; CHECK-NEXT: csrwi vxrm, 0873; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma874; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t875; CHECK-NEXT: ret876entry:877 %0 = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %op1, <vscale x 2 x i32> %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)878 ret <vscale x 2 x i32> %0879}880 881define <vscale x 2 x i32> @test_vssrl_vx_u32m1_m(<vscale x 2 x i1> %mask, <vscale x 2 x i32> %op1, i64 %shift, i64 %vl) {882; CHECK-LABEL: test_vssrl_vx_u32m1_m:883; CHECK: # %bb.0: # %entry884; CHECK-NEXT: csrwi vxrm, 0885; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma886; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t887; CHECK-NEXT: ret888entry:889 %0 = call <vscale x 2 x i32> @llvm.riscv.vssrl.mask.nxv2i32.i64.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> %op1, i64 %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)890 ret <vscale x 2 x i32> %0891}892 893define <vscale x 4 x i32> @test_vssrl_vv_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %shift, i64 %vl) {894; CHECK-LABEL: test_vssrl_vv_u32m2_m:895; CHECK: # %bb.0: # %entry896; CHECK-NEXT: csrwi vxrm, 0897; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma898; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t899; CHECK-NEXT: ret900entry:901 %0 = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %op1, <vscale x 4 x i32> %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)902 ret <vscale x 4 x i32> %0903}904 905define <vscale x 4 x i32> @test_vssrl_vx_u32m2_m(<vscale x 4 x i1> %mask, <vscale x 4 x i32> %op1, i64 %shift, i64 %vl) {906; CHECK-LABEL: test_vssrl_vx_u32m2_m:907; CHECK: # %bb.0: # %entry908; CHECK-NEXT: csrwi vxrm, 0909; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma910; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t911; CHECK-NEXT: ret912entry:913 %0 = call <vscale x 4 x i32> @llvm.riscv.vssrl.mask.nxv4i32.i64.i64(<vscale x 4 x i32> poison, <vscale x 4 x i32> %op1, i64 %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)914 ret <vscale x 4 x i32> %0915}916 917define <vscale x 8 x i32> @test_vssrl_vv_u32m4_m(<vscale x 8 x i1> %mask, <vscale x 8 x i32> %op1, <vscale x 8 x i32> %shift, i64 %vl) {918; CHECK-LABEL: test_vssrl_vv_u32m4_m:919; CHECK: # %bb.0: # %entry920; CHECK-NEXT: csrwi vxrm, 0921; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma922; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t923; CHECK-NEXT: ret924entry:925 %0 = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %op1, <vscale x 8 x i32> %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)926 ret <vscale x 8 x i32> %0927}928 929define <vscale x 8 x i32> @test_vssrl_vx_u32m4_m(<vscale x 8 x i1> %mask, <vscale x 8 x i32> %op1, i64 %shift, i64 %vl) {930; CHECK-LABEL: test_vssrl_vx_u32m4_m:931; CHECK: # %bb.0: # %entry932; CHECK-NEXT: csrwi vxrm, 0933; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma934; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t935; CHECK-NEXT: ret936entry:937 %0 = call <vscale x 8 x i32> @llvm.riscv.vssrl.mask.nxv8i32.i64.i64(<vscale x 8 x i32> poison, <vscale x 8 x i32> %op1, i64 %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)938 ret <vscale x 8 x i32> %0939}940 941define <vscale x 16 x i32> @test_vssrl_vv_u32m8_m(<vscale x 16 x i1> %mask, <vscale x 16 x i32> %op1, <vscale x 16 x i32> %shift, i64 %vl) {942; CHECK-LABEL: test_vssrl_vv_u32m8_m:943; CHECK: # %bb.0: # %entry944; CHECK-NEXT: csrwi vxrm, 0945; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma946; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t947; CHECK-NEXT: ret948entry:949 %0 = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %op1, <vscale x 16 x i32> %shift, <vscale x 16 x i1> %mask, i64 0, i64 %vl, i64 3)950 ret <vscale x 16 x i32> %0951}952 953define <vscale x 16 x i32> @test_vssrl_vx_u32m8_m(<vscale x 16 x i1> %mask, <vscale x 16 x i32> %op1, i64 %shift, i64 %vl) {954; CHECK-LABEL: test_vssrl_vx_u32m8_m:955; CHECK: # %bb.0: # %entry956; CHECK-NEXT: csrwi vxrm, 0957; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma958; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t959; CHECK-NEXT: ret960entry:961 %0 = call <vscale x 16 x i32> @llvm.riscv.vssrl.mask.nxv16i32.i64.i64(<vscale x 16 x i32> poison, <vscale x 16 x i32> %op1, i64 %shift, <vscale x 16 x i1> %mask, i64 0, i64 %vl, i64 3)962 ret <vscale x 16 x i32> %0963}964 965define <vscale x 1 x i64> @test_vssrl_vv_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %shift, i64 %vl) {966; CHECK-LABEL: test_vssrl_vv_u64m1_m:967; CHECK: # %bb.0: # %entry968; CHECK-NEXT: csrwi vxrm, 0969; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma970; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t971; CHECK-NEXT: ret972entry:973 %0 = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %op1, <vscale x 1 x i64> %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)974 ret <vscale x 1 x i64> %0975}976 977define <vscale x 1 x i64> @test_vssrl_vx_u64m1_m(<vscale x 1 x i1> %mask, <vscale x 1 x i64> %op1, i64 %shift, i64 %vl) {978; CHECK-LABEL: test_vssrl_vx_u64m1_m:979; CHECK: # %bb.0: # %entry980; CHECK-NEXT: csrwi vxrm, 0981; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma982; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t983; CHECK-NEXT: ret984entry:985 %0 = call <vscale x 1 x i64> @llvm.riscv.vssrl.mask.nxv1i64.i64.i64(<vscale x 1 x i64> poison, <vscale x 1 x i64> %op1, i64 %shift, <vscale x 1 x i1> %mask, i64 0, i64 %vl, i64 3)986 ret <vscale x 1 x i64> %0987}988 989define <vscale x 2 x i64> @test_vssrl_vv_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %shift, i64 %vl) {990; CHECK-LABEL: test_vssrl_vv_u64m2_m:991; CHECK: # %bb.0: # %entry992; CHECK-NEXT: csrwi vxrm, 0993; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma994; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t995; CHECK-NEXT: ret996entry:997 %0 = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %op1, <vscale x 2 x i64> %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)998 ret <vscale x 2 x i64> %0999}1000 1001define <vscale x 2 x i64> @test_vssrl_vx_u64m2_m(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %op1, i64 %shift, i64 %vl) {1002; CHECK-LABEL: test_vssrl_vx_u64m2_m:1003; CHECK: # %bb.0: # %entry1004; CHECK-NEXT: csrwi vxrm, 01005; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma1006; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t1007; CHECK-NEXT: ret1008entry:1009 %0 = call <vscale x 2 x i64> @llvm.riscv.vssrl.mask.nxv2i64.i64.i64(<vscale x 2 x i64> poison, <vscale x 2 x i64> %op1, i64 %shift, <vscale x 2 x i1> %mask, i64 0, i64 %vl, i64 3)1010 ret <vscale x 2 x i64> %01011}1012 1013define <vscale x 4 x i64> @test_vssrl_vv_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %op1, <vscale x 4 x i64> %shift, i64 %vl) {1014; CHECK-LABEL: test_vssrl_vv_u64m4_m:1015; CHECK: # %bb.0: # %entry1016; CHECK-NEXT: csrwi vxrm, 01017; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1018; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t1019; CHECK-NEXT: ret1020entry:1021 %0 = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %op1, <vscale x 4 x i64> %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)1022 ret <vscale x 4 x i64> %01023}1024 1025define <vscale x 4 x i64> @test_vssrl_vx_u64m4_m(<vscale x 4 x i1> %mask, <vscale x 4 x i64> %op1, i64 %shift, i64 %vl) {1026; CHECK-LABEL: test_vssrl_vx_u64m4_m:1027; CHECK: # %bb.0: # %entry1028; CHECK-NEXT: csrwi vxrm, 01029; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1030; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t1031; CHECK-NEXT: ret1032entry:1033 %0 = call <vscale x 4 x i64> @llvm.riscv.vssrl.mask.nxv4i64.i64.i64(<vscale x 4 x i64> poison, <vscale x 4 x i64> %op1, i64 %shift, <vscale x 4 x i1> %mask, i64 0, i64 %vl, i64 3)1034 ret <vscale x 4 x i64> %01035}1036 1037define <vscale x 8 x i64> @test_vssrl_vv_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %op1, <vscale x 8 x i64> %shift, i64 %vl) {1038; CHECK-LABEL: test_vssrl_vv_u64m8_m:1039; CHECK: # %bb.0: # %entry1040; CHECK-NEXT: csrwi vxrm, 01041; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1042; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t1043; CHECK-NEXT: ret1044entry:1045 %0 = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %op1, <vscale x 8 x i64> %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)1046 ret <vscale x 8 x i64> %01047}1048 1049define <vscale x 8 x i64> @test_vssrl_vx_u64m8_m(<vscale x 8 x i1> %mask, <vscale x 8 x i64> %op1, i64 %shift, i64 %vl) {1050; CHECK-LABEL: test_vssrl_vx_u64m8_m:1051; CHECK: # %bb.0: # %entry1052; CHECK-NEXT: csrwi vxrm, 01053; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1054; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t1055; CHECK-NEXT: ret1056entry:1057 %0 = call <vscale x 8 x i64> @llvm.riscv.vssrl.mask.nxv8i64.i64.i64(<vscale x 8 x i64> poison, <vscale x 8 x i64> %op1, i64 %shift, <vscale x 8 x i1> %mask, i64 0, i64 %vl, i64 3)1058 ret <vscale x 8 x i64> %01059}1060 1061