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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 8 x i7> @vssub_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: vssub_vx_nxv8i7:9; CHECK:       # %bb.0:10; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma11; CHECK-NEXT:    vadd.vv v8, v8, v812; CHECK-NEXT:    vsra.vi v8, v8, 113; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t14; CHECK-NEXT:    li a0, 6315; CHECK-NEXT:    vmin.vx v8, v8, a0, v0.t16; CHECK-NEXT:    li a0, 19217; CHECK-NEXT:    vmax.vx v8, v8, a0, v0.t18; CHECK-NEXT:    ret19  %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 020  %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer21  %v = call <vscale x 8 x i7> @llvm.vp.ssub.sat.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)22  ret <vscale x 8 x i7> %v23}24 25define <vscale x 1 x i8> @vssub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {26; CHECK-LABEL: vssub_vv_nxv1i8:27; CHECK:       # %bb.0:28; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma29; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t30; CHECK-NEXT:    ret31  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)32  ret <vscale x 1 x i8> %v33}34 35define <vscale x 1 x i8> @vssub_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {36; CHECK-LABEL: vssub_vv_nxv1i8_unmasked:37; CHECK:       # %bb.0:38; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma39; CHECK-NEXT:    vssub.vv v8, v8, v940; CHECK-NEXT:    ret41  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)42  ret <vscale x 1 x i8> %v43}44 45define <vscale x 1 x i8> @vssub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {46; CHECK-LABEL: vssub_vx_nxv1i8:47; CHECK:       # %bb.0:48; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma49; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t50; CHECK-NEXT:    ret51  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 052  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer53  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)54  ret <vscale x 1 x i8> %v55}56 57define <vscale x 1 x i8> @vssub_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {58; CHECK-LABEL: vssub_vx_nxv1i8_commute:59; CHECK:       # %bb.0:60; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma61; CHECK-NEXT:    vmv.v.x v9, a062; CHECK-NEXT:    vssub.vv v8, v9, v8, v0.t63; CHECK-NEXT:    ret64  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 065  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer66  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)67  ret <vscale x 1 x i8> %v68}69 70define <vscale x 1 x i8> @vssub_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {71; CHECK-LABEL: vssub_vx_nxv1i8_unmasked:72; CHECK:       # %bb.0:73; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma74; CHECK-NEXT:    vssub.vx v8, v8, a075; CHECK-NEXT:    ret76  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 077  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer78  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)79  ret <vscale x 1 x i8> %v80}81 82define <vscale x 1 x i8> @vssub_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {83; CHECK-LABEL: vssub_vi_nxv1i8:84; CHECK:       # %bb.0:85; CHECK-NEXT:    li a1, -186; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma87; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t88; CHECK-NEXT:    ret89  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)90  ret <vscale x 1 x i8> %v91}92 93define <vscale x 1 x i8> @vssub_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {94; CHECK-LABEL: vssub_vi_nxv1i8_unmasked:95; CHECK:       # %bb.0:96; CHECK-NEXT:    li a1, -197; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma98; CHECK-NEXT:    vssub.vx v8, v8, a199; CHECK-NEXT:    ret100  %v = call <vscale x 1 x i8> @llvm.vp.ssub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)101  ret <vscale x 1 x i8> %v102}103 104define <vscale x 2 x i8> @vssub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {105; CHECK-LABEL: vssub_vv_nxv2i8:106; CHECK:       # %bb.0:107; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma108; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t109; CHECK-NEXT:    ret110  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)111  ret <vscale x 2 x i8> %v112}113 114define <vscale x 2 x i8> @vssub_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {115; CHECK-LABEL: vssub_vv_nxv2i8_unmasked:116; CHECK:       # %bb.0:117; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma118; CHECK-NEXT:    vssub.vv v8, v8, v9119; CHECK-NEXT:    ret120  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)121  ret <vscale x 2 x i8> %v122}123 124define <vscale x 2 x i8> @vssub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {125; CHECK-LABEL: vssub_vx_nxv2i8:126; CHECK:       # %bb.0:127; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma128; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t129; CHECK-NEXT:    ret130  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0131  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer132  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)133  ret <vscale x 2 x i8> %v134}135 136define <vscale x 2 x i8> @vssub_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {137; CHECK-LABEL: vssub_vx_nxv2i8_unmasked:138; CHECK:       # %bb.0:139; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma140; CHECK-NEXT:    vssub.vx v8, v8, a0141; CHECK-NEXT:    ret142  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0143  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer144  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)145  ret <vscale x 2 x i8> %v146}147 148define <vscale x 2 x i8> @vssub_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {149; CHECK-LABEL: vssub_vi_nxv2i8:150; CHECK:       # %bb.0:151; CHECK-NEXT:    li a1, -1152; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma153; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t154; CHECK-NEXT:    ret155  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)156  ret <vscale x 2 x i8> %v157}158 159define <vscale x 2 x i8> @vssub_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {160; CHECK-LABEL: vssub_vi_nxv2i8_unmasked:161; CHECK:       # %bb.0:162; CHECK-NEXT:    li a1, -1163; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma164; CHECK-NEXT:    vssub.vx v8, v8, a1165; CHECK-NEXT:    ret166  %v = call <vscale x 2 x i8> @llvm.vp.ssub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)167  ret <vscale x 2 x i8> %v168}169 170define <vscale x 3 x i8> @vssub_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {171; CHECK-LABEL: vssub_vv_nxv3i8:172; CHECK:       # %bb.0:173; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma174; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t175; CHECK-NEXT:    ret176  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)177  ret <vscale x 3 x i8> %v178}179 180define <vscale x 3 x i8> @vssub_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {181; CHECK-LABEL: vssub_vv_nxv3i8_unmasked:182; CHECK:       # %bb.0:183; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma184; CHECK-NEXT:    vssub.vv v8, v8, v9185; CHECK-NEXT:    ret186  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)187  ret <vscale x 3 x i8> %v188}189 190define <vscale x 3 x i8> @vssub_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {191; CHECK-LABEL: vssub_vx_nxv3i8:192; CHECK:       # %bb.0:193; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma194; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t195; CHECK-NEXT:    ret196  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0197  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer198  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl)199  ret <vscale x 3 x i8> %v200}201 202define <vscale x 3 x i8> @vssub_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {203; CHECK-LABEL: vssub_vx_nxv3i8_unmasked:204; CHECK:       # %bb.0:205; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma206; CHECK-NEXT:    vssub.vx v8, v8, a0207; CHECK-NEXT:    ret208  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0209  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer210  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl)211  ret <vscale x 3 x i8> %v212}213 214define <vscale x 3 x i8> @vssub_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {215; CHECK-LABEL: vssub_vi_nxv3i8:216; CHECK:       # %bb.0:217; CHECK-NEXT:    li a1, -1218; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma219; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t220; CHECK-NEXT:    ret221  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)222  ret <vscale x 3 x i8> %v223}224 225define <vscale x 3 x i8> @vssub_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {226; CHECK-LABEL: vssub_vi_nxv3i8_unmasked:227; CHECK:       # %bb.0:228; CHECK-NEXT:    li a1, -1229; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma230; CHECK-NEXT:    vssub.vx v8, v8, a1231; CHECK-NEXT:    ret232  %v = call <vscale x 3 x i8> @llvm.vp.ssub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)233  ret <vscale x 3 x i8> %v234}235 236define <vscale x 4 x i8> @vssub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {237; CHECK-LABEL: vssub_vv_nxv4i8:238; CHECK:       # %bb.0:239; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma240; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t241; CHECK-NEXT:    ret242  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)243  ret <vscale x 4 x i8> %v244}245 246define <vscale x 4 x i8> @vssub_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {247; CHECK-LABEL: vssub_vv_nxv4i8_unmasked:248; CHECK:       # %bb.0:249; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma250; CHECK-NEXT:    vssub.vv v8, v8, v9251; CHECK-NEXT:    ret252  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)253  ret <vscale x 4 x i8> %v254}255 256define <vscale x 4 x i8> @vssub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {257; CHECK-LABEL: vssub_vx_nxv4i8:258; CHECK:       # %bb.0:259; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma260; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t261; CHECK-NEXT:    ret262  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0263  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer264  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)265  ret <vscale x 4 x i8> %v266}267 268define <vscale x 4 x i8> @vssub_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {269; CHECK-LABEL: vssub_vx_nxv4i8_unmasked:270; CHECK:       # %bb.0:271; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma272; CHECK-NEXT:    vssub.vx v8, v8, a0273; CHECK-NEXT:    ret274  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0275  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer276  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)277  ret <vscale x 4 x i8> %v278}279 280define <vscale x 4 x i8> @vssub_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {281; CHECK-LABEL: vssub_vi_nxv4i8:282; CHECK:       # %bb.0:283; CHECK-NEXT:    li a1, -1284; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma285; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t286; CHECK-NEXT:    ret287  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)288  ret <vscale x 4 x i8> %v289}290 291define <vscale x 4 x i8> @vssub_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {292; CHECK-LABEL: vssub_vi_nxv4i8_unmasked:293; CHECK:       # %bb.0:294; CHECK-NEXT:    li a1, -1295; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma296; CHECK-NEXT:    vssub.vx v8, v8, a1297; CHECK-NEXT:    ret298  %v = call <vscale x 4 x i8> @llvm.vp.ssub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)299  ret <vscale x 4 x i8> %v300}301 302define <vscale x 8 x i8> @vssub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {303; CHECK-LABEL: vssub_vv_nxv8i8:304; CHECK:       # %bb.0:305; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma306; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t307; CHECK-NEXT:    ret308  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)309  ret <vscale x 8 x i8> %v310}311 312define <vscale x 8 x i8> @vssub_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {313; CHECK-LABEL: vssub_vv_nxv8i8_unmasked:314; CHECK:       # %bb.0:315; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma316; CHECK-NEXT:    vssub.vv v8, v8, v9317; CHECK-NEXT:    ret318  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)319  ret <vscale x 8 x i8> %v320}321 322define <vscale x 8 x i8> @vssub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {323; CHECK-LABEL: vssub_vx_nxv8i8:324; CHECK:       # %bb.0:325; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma326; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t327; CHECK-NEXT:    ret328  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0329  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer330  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)331  ret <vscale x 8 x i8> %v332}333 334define <vscale x 8 x i8> @vssub_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {335; CHECK-LABEL: vssub_vx_nxv8i8_unmasked:336; CHECK:       # %bb.0:337; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma338; CHECK-NEXT:    vssub.vx v8, v8, a0339; CHECK-NEXT:    ret340  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0341  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer342  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)343  ret <vscale x 8 x i8> %v344}345 346define <vscale x 8 x i8> @vssub_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {347; CHECK-LABEL: vssub_vi_nxv8i8:348; CHECK:       # %bb.0:349; CHECK-NEXT:    li a1, -1350; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma351; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t352; CHECK-NEXT:    ret353  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)354  ret <vscale x 8 x i8> %v355}356 357define <vscale x 8 x i8> @vssub_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {358; CHECK-LABEL: vssub_vi_nxv8i8_unmasked:359; CHECK:       # %bb.0:360; CHECK-NEXT:    li a1, -1361; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma362; CHECK-NEXT:    vssub.vx v8, v8, a1363; CHECK-NEXT:    ret364  %v = call <vscale x 8 x i8> @llvm.vp.ssub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)365  ret <vscale x 8 x i8> %v366}367 368define <vscale x 16 x i8> @vssub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {369; CHECK-LABEL: vssub_vv_nxv16i8:370; CHECK:       # %bb.0:371; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma372; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t373; CHECK-NEXT:    ret374  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)375  ret <vscale x 16 x i8> %v376}377 378define <vscale x 16 x i8> @vssub_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {379; CHECK-LABEL: vssub_vv_nxv16i8_unmasked:380; CHECK:       # %bb.0:381; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma382; CHECK-NEXT:    vssub.vv v8, v8, v10383; CHECK-NEXT:    ret384  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)385  ret <vscale x 16 x i8> %v386}387 388define <vscale x 16 x i8> @vssub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {389; CHECK-LABEL: vssub_vx_nxv16i8:390; CHECK:       # %bb.0:391; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma392; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t393; CHECK-NEXT:    ret394  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0395  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer396  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)397  ret <vscale x 16 x i8> %v398}399 400define <vscale x 16 x i8> @vssub_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {401; CHECK-LABEL: vssub_vx_nxv16i8_unmasked:402; CHECK:       # %bb.0:403; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma404; CHECK-NEXT:    vssub.vx v8, v8, a0405; CHECK-NEXT:    ret406  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0407  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer408  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)409  ret <vscale x 16 x i8> %v410}411 412define <vscale x 16 x i8> @vssub_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {413; CHECK-LABEL: vssub_vi_nxv16i8:414; CHECK:       # %bb.0:415; CHECK-NEXT:    li a1, -1416; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma417; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t418; CHECK-NEXT:    ret419  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)420  ret <vscale x 16 x i8> %v421}422 423define <vscale x 16 x i8> @vssub_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {424; CHECK-LABEL: vssub_vi_nxv16i8_unmasked:425; CHECK:       # %bb.0:426; CHECK-NEXT:    li a1, -1427; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma428; CHECK-NEXT:    vssub.vx v8, v8, a1429; CHECK-NEXT:    ret430  %v = call <vscale x 16 x i8> @llvm.vp.ssub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)431  ret <vscale x 16 x i8> %v432}433 434define <vscale x 32 x i8> @vssub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {435; CHECK-LABEL: vssub_vv_nxv32i8:436; CHECK:       # %bb.0:437; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma438; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t439; CHECK-NEXT:    ret440  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)441  ret <vscale x 32 x i8> %v442}443 444define <vscale x 32 x i8> @vssub_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {445; CHECK-LABEL: vssub_vv_nxv32i8_unmasked:446; CHECK:       # %bb.0:447; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma448; CHECK-NEXT:    vssub.vv v8, v8, v12449; CHECK-NEXT:    ret450  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)451  ret <vscale x 32 x i8> %v452}453 454define <vscale x 32 x i8> @vssub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {455; CHECK-LABEL: vssub_vx_nxv32i8:456; CHECK:       # %bb.0:457; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma458; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t459; CHECK-NEXT:    ret460  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0461  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer462  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)463  ret <vscale x 32 x i8> %v464}465 466define <vscale x 32 x i8> @vssub_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {467; CHECK-LABEL: vssub_vx_nxv32i8_unmasked:468; CHECK:       # %bb.0:469; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma470; CHECK-NEXT:    vssub.vx v8, v8, a0471; CHECK-NEXT:    ret472  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0473  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer474  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)475  ret <vscale x 32 x i8> %v476}477 478define <vscale x 32 x i8> @vssub_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {479; CHECK-LABEL: vssub_vi_nxv32i8:480; CHECK:       # %bb.0:481; CHECK-NEXT:    li a1, -1482; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma483; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t484; CHECK-NEXT:    ret485  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)486  ret <vscale x 32 x i8> %v487}488 489define <vscale x 32 x i8> @vssub_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {490; CHECK-LABEL: vssub_vi_nxv32i8_unmasked:491; CHECK:       # %bb.0:492; CHECK-NEXT:    li a1, -1493; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma494; CHECK-NEXT:    vssub.vx v8, v8, a1495; CHECK-NEXT:    ret496  %v = call <vscale x 32 x i8> @llvm.vp.ssub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)497  ret <vscale x 32 x i8> %v498}499 500define <vscale x 64 x i8> @vssub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {501; CHECK-LABEL: vssub_vv_nxv64i8:502; CHECK:       # %bb.0:503; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma504; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t505; CHECK-NEXT:    ret506  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)507  ret <vscale x 64 x i8> %v508}509 510define <vscale x 64 x i8> @vssub_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {511; CHECK-LABEL: vssub_vv_nxv64i8_unmasked:512; CHECK:       # %bb.0:513; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma514; CHECK-NEXT:    vssub.vv v8, v8, v16515; CHECK-NEXT:    ret516  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)517  ret <vscale x 64 x i8> %v518}519 520define <vscale x 64 x i8> @vssub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {521; CHECK-LABEL: vssub_vx_nxv64i8:522; CHECK:       # %bb.0:523; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma524; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t525; CHECK-NEXT:    ret526  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0527  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer528  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)529  ret <vscale x 64 x i8> %v530}531 532define <vscale x 64 x i8> @vssub_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {533; CHECK-LABEL: vssub_vx_nxv64i8_unmasked:534; CHECK:       # %bb.0:535; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma536; CHECK-NEXT:    vssub.vx v8, v8, a0537; CHECK-NEXT:    ret538  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0539  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer540  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)541  ret <vscale x 64 x i8> %v542}543 544define <vscale x 64 x i8> @vssub_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {545; CHECK-LABEL: vssub_vi_nxv64i8:546; CHECK:       # %bb.0:547; CHECK-NEXT:    li a1, -1548; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma549; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t550; CHECK-NEXT:    ret551  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)552  ret <vscale x 64 x i8> %v553}554 555define <vscale x 64 x i8> @vssub_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {556; CHECK-LABEL: vssub_vi_nxv64i8_unmasked:557; CHECK:       # %bb.0:558; CHECK-NEXT:    li a1, -1559; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma560; CHECK-NEXT:    vssub.vx v8, v8, a1561; CHECK-NEXT:    ret562  %v = call <vscale x 64 x i8> @llvm.vp.ssub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)563  ret <vscale x 64 x i8> %v564}565 566; Test that split-legalization works when the mask itself needs splitting.567 568define <vscale x 128 x i8> @vssub_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {569; CHECK-LABEL: vssub_vi_nxv128i8:570; CHECK:       # %bb.0:571; CHECK-NEXT:    vsetvli a2, zero, e8, m8, ta, ma572; CHECK-NEXT:    vmv1r.v v24, v0573; CHECK-NEXT:    vlm.v v0, (a0)574; CHECK-NEXT:    csrr a0, vlenb575; CHECK-NEXT:    slli a0, a0, 3576; CHECK-NEXT:    sub a2, a1, a0577; CHECK-NEXT:    sltu a3, a1, a2578; CHECK-NEXT:    addi a3, a3, -1579; CHECK-NEXT:    and a3, a3, a2580; CHECK-NEXT:    li a2, -1581; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma582; CHECK-NEXT:    vssub.vx v16, v16, a2, v0.t583; CHECK-NEXT:    bltu a1, a0, .LBB50_2584; CHECK-NEXT:  # %bb.1:585; CHECK-NEXT:    mv a1, a0586; CHECK-NEXT:  .LBB50_2:587; CHECK-NEXT:    vmv1r.v v0, v24588; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma589; CHECK-NEXT:    vssub.vx v8, v8, a2, v0.t590; CHECK-NEXT:    ret591  %v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)592  ret <vscale x 128 x i8> %v593}594 595define <vscale x 128 x i8> @vssub_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {596; CHECK-LABEL: vssub_vi_nxv128i8_unmasked:597; CHECK:       # %bb.0:598; CHECK-NEXT:    csrr a1, vlenb599; CHECK-NEXT:    slli a1, a1, 3600; CHECK-NEXT:    sub a2, a0, a1601; CHECK-NEXT:    sltu a3, a0, a2602; CHECK-NEXT:    addi a3, a3, -1603; CHECK-NEXT:    and a3, a3, a2604; CHECK-NEXT:    li a2, -1605; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma606; CHECK-NEXT:    vssub.vx v16, v16, a2607; CHECK-NEXT:    bltu a0, a1, .LBB51_2608; CHECK-NEXT:  # %bb.1:609; CHECK-NEXT:    mv a0, a1610; CHECK-NEXT:  .LBB51_2:611; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma612; CHECK-NEXT:    vssub.vx v8, v8, a2613; CHECK-NEXT:    ret614  %v = call <vscale x 128 x i8> @llvm.vp.ssub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)615  ret <vscale x 128 x i8> %v616}617 618define <vscale x 1 x i16> @vssub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {619; CHECK-LABEL: vssub_vv_nxv1i16:620; CHECK:       # %bb.0:621; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma622; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t623; CHECK-NEXT:    ret624  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)625  ret <vscale x 1 x i16> %v626}627 628define <vscale x 1 x i16> @vssub_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {629; CHECK-LABEL: vssub_vv_nxv1i16_unmasked:630; CHECK:       # %bb.0:631; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma632; CHECK-NEXT:    vssub.vv v8, v8, v9633; CHECK-NEXT:    ret634  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)635  ret <vscale x 1 x i16> %v636}637 638define <vscale x 1 x i16> @vssub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {639; CHECK-LABEL: vssub_vx_nxv1i16:640; CHECK:       # %bb.0:641; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma642; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t643; CHECK-NEXT:    ret644  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0645  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer646  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)647  ret <vscale x 1 x i16> %v648}649 650define <vscale x 1 x i16> @vssub_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {651; CHECK-LABEL: vssub_vx_nxv1i16_unmasked:652; CHECK:       # %bb.0:653; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma654; CHECK-NEXT:    vssub.vx v8, v8, a0655; CHECK-NEXT:    ret656  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0657  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer658  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)659  ret <vscale x 1 x i16> %v660}661 662define <vscale x 1 x i16> @vssub_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {663; CHECK-LABEL: vssub_vi_nxv1i16:664; CHECK:       # %bb.0:665; CHECK-NEXT:    li a1, -1666; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma667; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t668; CHECK-NEXT:    ret669  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)670  ret <vscale x 1 x i16> %v671}672 673define <vscale x 1 x i16> @vssub_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {674; CHECK-LABEL: vssub_vi_nxv1i16_unmasked:675; CHECK:       # %bb.0:676; CHECK-NEXT:    li a1, -1677; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma678; CHECK-NEXT:    vssub.vx v8, v8, a1679; CHECK-NEXT:    ret680  %v = call <vscale x 1 x i16> @llvm.vp.ssub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)681  ret <vscale x 1 x i16> %v682}683 684define <vscale x 2 x i16> @vssub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {685; CHECK-LABEL: vssub_vv_nxv2i16:686; CHECK:       # %bb.0:687; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma688; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t689; CHECK-NEXT:    ret690  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)691  ret <vscale x 2 x i16> %v692}693 694define <vscale x 2 x i16> @vssub_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {695; CHECK-LABEL: vssub_vv_nxv2i16_unmasked:696; CHECK:       # %bb.0:697; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma698; CHECK-NEXT:    vssub.vv v8, v8, v9699; CHECK-NEXT:    ret700  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)701  ret <vscale x 2 x i16> %v702}703 704define <vscale x 2 x i16> @vssub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {705; CHECK-LABEL: vssub_vx_nxv2i16:706; CHECK:       # %bb.0:707; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma708; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t709; CHECK-NEXT:    ret710  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0711  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer712  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)713  ret <vscale x 2 x i16> %v714}715 716define <vscale x 2 x i16> @vssub_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {717; CHECK-LABEL: vssub_vx_nxv2i16_unmasked:718; CHECK:       # %bb.0:719; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma720; CHECK-NEXT:    vssub.vx v8, v8, a0721; CHECK-NEXT:    ret722  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0723  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer724  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)725  ret <vscale x 2 x i16> %v726}727 728define <vscale x 2 x i16> @vssub_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {729; CHECK-LABEL: vssub_vi_nxv2i16:730; CHECK:       # %bb.0:731; CHECK-NEXT:    li a1, -1732; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma733; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t734; CHECK-NEXT:    ret735  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)736  ret <vscale x 2 x i16> %v737}738 739define <vscale x 2 x i16> @vssub_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {740; CHECK-LABEL: vssub_vi_nxv2i16_unmasked:741; CHECK:       # %bb.0:742; CHECK-NEXT:    li a1, -1743; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma744; CHECK-NEXT:    vssub.vx v8, v8, a1745; CHECK-NEXT:    ret746  %v = call <vscale x 2 x i16> @llvm.vp.ssub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)747  ret <vscale x 2 x i16> %v748}749 750define <vscale x 4 x i16> @vssub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {751; CHECK-LABEL: vssub_vv_nxv4i16:752; CHECK:       # %bb.0:753; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma754; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t755; CHECK-NEXT:    ret756  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)757  ret <vscale x 4 x i16> %v758}759 760define <vscale x 4 x i16> @vssub_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {761; CHECK-LABEL: vssub_vv_nxv4i16_unmasked:762; CHECK:       # %bb.0:763; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma764; CHECK-NEXT:    vssub.vv v8, v8, v9765; CHECK-NEXT:    ret766  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)767  ret <vscale x 4 x i16> %v768}769 770define <vscale x 4 x i16> @vssub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {771; CHECK-LABEL: vssub_vx_nxv4i16:772; CHECK:       # %bb.0:773; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma774; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t775; CHECK-NEXT:    ret776  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0777  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer778  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)779  ret <vscale x 4 x i16> %v780}781 782define <vscale x 4 x i16> @vssub_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {783; CHECK-LABEL: vssub_vx_nxv4i16_unmasked:784; CHECK:       # %bb.0:785; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma786; CHECK-NEXT:    vssub.vx v8, v8, a0787; CHECK-NEXT:    ret788  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0789  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer790  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)791  ret <vscale x 4 x i16> %v792}793 794define <vscale x 4 x i16> @vssub_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {795; CHECK-LABEL: vssub_vi_nxv4i16:796; CHECK:       # %bb.0:797; CHECK-NEXT:    li a1, -1798; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma799; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t800; CHECK-NEXT:    ret801  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)802  ret <vscale x 4 x i16> %v803}804 805define <vscale x 4 x i16> @vssub_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {806; CHECK-LABEL: vssub_vi_nxv4i16_unmasked:807; CHECK:       # %bb.0:808; CHECK-NEXT:    li a1, -1809; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma810; CHECK-NEXT:    vssub.vx v8, v8, a1811; CHECK-NEXT:    ret812  %v = call <vscale x 4 x i16> @llvm.vp.ssub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)813  ret <vscale x 4 x i16> %v814}815 816define <vscale x 8 x i16> @vssub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {817; CHECK-LABEL: vssub_vv_nxv8i16:818; CHECK:       # %bb.0:819; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma820; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t821; CHECK-NEXT:    ret822  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)823  ret <vscale x 8 x i16> %v824}825 826define <vscale x 8 x i16> @vssub_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {827; CHECK-LABEL: vssub_vv_nxv8i16_unmasked:828; CHECK:       # %bb.0:829; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma830; CHECK-NEXT:    vssub.vv v8, v8, v10831; CHECK-NEXT:    ret832  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)833  ret <vscale x 8 x i16> %v834}835 836define <vscale x 8 x i16> @vssub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {837; CHECK-LABEL: vssub_vx_nxv8i16:838; CHECK:       # %bb.0:839; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma840; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t841; CHECK-NEXT:    ret842  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0843  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer844  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)845  ret <vscale x 8 x i16> %v846}847 848define <vscale x 8 x i16> @vssub_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {849; CHECK-LABEL: vssub_vx_nxv8i16_unmasked:850; CHECK:       # %bb.0:851; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma852; CHECK-NEXT:    vssub.vx v8, v8, a0853; CHECK-NEXT:    ret854  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0855  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer856  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)857  ret <vscale x 8 x i16> %v858}859 860define <vscale x 8 x i16> @vssub_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {861; CHECK-LABEL: vssub_vi_nxv8i16:862; CHECK:       # %bb.0:863; CHECK-NEXT:    li a1, -1864; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma865; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t866; CHECK-NEXT:    ret867  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)868  ret <vscale x 8 x i16> %v869}870 871define <vscale x 8 x i16> @vssub_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {872; CHECK-LABEL: vssub_vi_nxv8i16_unmasked:873; CHECK:       # %bb.0:874; CHECK-NEXT:    li a1, -1875; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma876; CHECK-NEXT:    vssub.vx v8, v8, a1877; CHECK-NEXT:    ret878  %v = call <vscale x 8 x i16> @llvm.vp.ssub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)879  ret <vscale x 8 x i16> %v880}881 882define <vscale x 16 x i16> @vssub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {883; CHECK-LABEL: vssub_vv_nxv16i16:884; CHECK:       # %bb.0:885; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma886; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t887; CHECK-NEXT:    ret888  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)889  ret <vscale x 16 x i16> %v890}891 892define <vscale x 16 x i16> @vssub_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {893; CHECK-LABEL: vssub_vv_nxv16i16_unmasked:894; CHECK:       # %bb.0:895; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma896; CHECK-NEXT:    vssub.vv v8, v8, v12897; CHECK-NEXT:    ret898  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)899  ret <vscale x 16 x i16> %v900}901 902define <vscale x 16 x i16> @vssub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {903; CHECK-LABEL: vssub_vx_nxv16i16:904; CHECK:       # %bb.0:905; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma906; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t907; CHECK-NEXT:    ret908  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0909  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer910  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)911  ret <vscale x 16 x i16> %v912}913 914define <vscale x 16 x i16> @vssub_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {915; CHECK-LABEL: vssub_vx_nxv16i16_unmasked:916; CHECK:       # %bb.0:917; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma918; CHECK-NEXT:    vssub.vx v8, v8, a0919; CHECK-NEXT:    ret920  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0921  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer922  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)923  ret <vscale x 16 x i16> %v924}925 926define <vscale x 16 x i16> @vssub_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {927; CHECK-LABEL: vssub_vi_nxv16i16:928; CHECK:       # %bb.0:929; CHECK-NEXT:    li a1, -1930; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma931; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t932; CHECK-NEXT:    ret933  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)934  ret <vscale x 16 x i16> %v935}936 937define <vscale x 16 x i16> @vssub_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {938; CHECK-LABEL: vssub_vi_nxv16i16_unmasked:939; CHECK:       # %bb.0:940; CHECK-NEXT:    li a1, -1941; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma942; CHECK-NEXT:    vssub.vx v8, v8, a1943; CHECK-NEXT:    ret944  %v = call <vscale x 16 x i16> @llvm.vp.ssub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)945  ret <vscale x 16 x i16> %v946}947 948define <vscale x 32 x i16> @vssub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {949; CHECK-LABEL: vssub_vv_nxv32i16:950; CHECK:       # %bb.0:951; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma952; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t953; CHECK-NEXT:    ret954  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)955  ret <vscale x 32 x i16> %v956}957 958define <vscale x 32 x i16> @vssub_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {959; CHECK-LABEL: vssub_vv_nxv32i16_unmasked:960; CHECK:       # %bb.0:961; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma962; CHECK-NEXT:    vssub.vv v8, v8, v16963; CHECK-NEXT:    ret964  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)965  ret <vscale x 32 x i16> %v966}967 968define <vscale x 32 x i16> @vssub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {969; CHECK-LABEL: vssub_vx_nxv32i16:970; CHECK:       # %bb.0:971; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma972; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t973; CHECK-NEXT:    ret974  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0975  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer976  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)977  ret <vscale x 32 x i16> %v978}979 980define <vscale x 32 x i16> @vssub_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {981; CHECK-LABEL: vssub_vx_nxv32i16_unmasked:982; CHECK:       # %bb.0:983; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma984; CHECK-NEXT:    vssub.vx v8, v8, a0985; CHECK-NEXT:    ret986  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0987  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer988  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)989  ret <vscale x 32 x i16> %v990}991 992define <vscale x 32 x i16> @vssub_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {993; CHECK-LABEL: vssub_vi_nxv32i16:994; CHECK:       # %bb.0:995; CHECK-NEXT:    li a1, -1996; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma997; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t998; CHECK-NEXT:    ret999  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)1000  ret <vscale x 32 x i16> %v1001}1002 1003define <vscale x 32 x i16> @vssub_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {1004; CHECK-LABEL: vssub_vi_nxv32i16_unmasked:1005; CHECK:       # %bb.0:1006; CHECK-NEXT:    li a1, -11007; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1008; CHECK-NEXT:    vssub.vx v8, v8, a11009; CHECK-NEXT:    ret1010  %v = call <vscale x 32 x i16> @llvm.vp.ssub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1011  ret <vscale x 32 x i16> %v1012}1013 1014define <vscale x 1 x i32> @vssub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1015; CHECK-LABEL: vssub_vv_nxv1i32:1016; CHECK:       # %bb.0:1017; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1018; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t1019; CHECK-NEXT:    ret1020  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)1021  ret <vscale x 1 x i32> %v1022}1023 1024define <vscale x 1 x i32> @vssub_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {1025; CHECK-LABEL: vssub_vv_nxv1i32_unmasked:1026; CHECK:       # %bb.0:1027; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1028; CHECK-NEXT:    vssub.vv v8, v8, v91029; CHECK-NEXT:    ret1030  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1031  ret <vscale x 1 x i32> %v1032}1033 1034define <vscale x 1 x i32> @vssub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1035; CHECK-LABEL: vssub_vx_nxv1i32:1036; CHECK:       # %bb.0:1037; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1038; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t1039; CHECK-NEXT:    ret1040  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01041  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1042  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)1043  ret <vscale x 1 x i32> %v1044}1045 1046define <vscale x 1 x i32> @vssub_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {1047; CHECK-LABEL: vssub_vx_nxv1i32_unmasked:1048; CHECK:       # %bb.0:1049; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1050; CHECK-NEXT:    vssub.vx v8, v8, a01051; CHECK-NEXT:    ret1052  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01053  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1054  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1055  ret <vscale x 1 x i32> %v1056}1057 1058define <vscale x 1 x i32> @vssub_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1059; CHECK-LABEL: vssub_vi_nxv1i32:1060; CHECK:       # %bb.0:1061; CHECK-NEXT:    li a1, -11062; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1063; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1064; CHECK-NEXT:    ret1065  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)1066  ret <vscale x 1 x i32> %v1067}1068 1069define <vscale x 1 x i32> @vssub_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {1070; CHECK-LABEL: vssub_vi_nxv1i32_unmasked:1071; CHECK:       # %bb.0:1072; CHECK-NEXT:    li a1, -11073; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1074; CHECK-NEXT:    vssub.vx v8, v8, a11075; CHECK-NEXT:    ret1076  %v = call <vscale x 1 x i32> @llvm.vp.ssub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1077  ret <vscale x 1 x i32> %v1078}1079 1080define <vscale x 2 x i32> @vssub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1081; CHECK-LABEL: vssub_vv_nxv2i32:1082; CHECK:       # %bb.0:1083; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1084; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t1085; CHECK-NEXT:    ret1086  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)1087  ret <vscale x 2 x i32> %v1088}1089 1090define <vscale x 2 x i32> @vssub_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {1091; CHECK-LABEL: vssub_vv_nxv2i32_unmasked:1092; CHECK:       # %bb.0:1093; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1094; CHECK-NEXT:    vssub.vv v8, v8, v91095; CHECK-NEXT:    ret1096  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1097  ret <vscale x 2 x i32> %v1098}1099 1100define <vscale x 2 x i32> @vssub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1101; CHECK-LABEL: vssub_vx_nxv2i32:1102; CHECK:       # %bb.0:1103; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1104; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t1105; CHECK-NEXT:    ret1106  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01107  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1108  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)1109  ret <vscale x 2 x i32> %v1110}1111 1112define <vscale x 2 x i32> @vssub_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {1113; CHECK-LABEL: vssub_vx_nxv2i32_unmasked:1114; CHECK:       # %bb.0:1115; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1116; CHECK-NEXT:    vssub.vx v8, v8, a01117; CHECK-NEXT:    ret1118  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01119  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1120  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1121  ret <vscale x 2 x i32> %v1122}1123 1124define <vscale x 2 x i32> @vssub_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1125; CHECK-LABEL: vssub_vi_nxv2i32:1126; CHECK:       # %bb.0:1127; CHECK-NEXT:    li a1, -11128; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1129; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1130; CHECK-NEXT:    ret1131  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)1132  ret <vscale x 2 x i32> %v1133}1134 1135define <vscale x 2 x i32> @vssub_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {1136; CHECK-LABEL: vssub_vi_nxv2i32_unmasked:1137; CHECK:       # %bb.0:1138; CHECK-NEXT:    li a1, -11139; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1140; CHECK-NEXT:    vssub.vx v8, v8, a11141; CHECK-NEXT:    ret1142  %v = call <vscale x 2 x i32> @llvm.vp.ssub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1143  ret <vscale x 2 x i32> %v1144}1145 1146define <vscale x 4 x i32> @vssub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1147; CHECK-LABEL: vssub_vv_nxv4i32:1148; CHECK:       # %bb.0:1149; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1150; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t1151; CHECK-NEXT:    ret1152  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)1153  ret <vscale x 4 x i32> %v1154}1155 1156define <vscale x 4 x i32> @vssub_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {1157; CHECK-LABEL: vssub_vv_nxv4i32_unmasked:1158; CHECK:       # %bb.0:1159; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1160; CHECK-NEXT:    vssub.vv v8, v8, v101161; CHECK-NEXT:    ret1162  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1163  ret <vscale x 4 x i32> %v1164}1165 1166define <vscale x 4 x i32> @vssub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1167; CHECK-LABEL: vssub_vx_nxv4i32:1168; CHECK:       # %bb.0:1169; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1170; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t1171; CHECK-NEXT:    ret1172  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01173  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1174  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)1175  ret <vscale x 4 x i32> %v1176}1177 1178define <vscale x 4 x i32> @vssub_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {1179; CHECK-LABEL: vssub_vx_nxv4i32_unmasked:1180; CHECK:       # %bb.0:1181; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1182; CHECK-NEXT:    vssub.vx v8, v8, a01183; CHECK-NEXT:    ret1184  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01185  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1186  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1187  ret <vscale x 4 x i32> %v1188}1189 1190define <vscale x 4 x i32> @vssub_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1191; CHECK-LABEL: vssub_vi_nxv4i32:1192; CHECK:       # %bb.0:1193; CHECK-NEXT:    li a1, -11194; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1195; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1196; CHECK-NEXT:    ret1197  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)1198  ret <vscale x 4 x i32> %v1199}1200 1201define <vscale x 4 x i32> @vssub_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1202; CHECK-LABEL: vssub_vi_nxv4i32_unmasked:1203; CHECK:       # %bb.0:1204; CHECK-NEXT:    li a1, -11205; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1206; CHECK-NEXT:    vssub.vx v8, v8, a11207; CHECK-NEXT:    ret1208  %v = call <vscale x 4 x i32> @llvm.vp.ssub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1209  ret <vscale x 4 x i32> %v1210}1211 1212define <vscale x 8 x i32> @vssub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1213; CHECK-LABEL: vssub_vv_nxv8i32:1214; CHECK:       # %bb.0:1215; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1216; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t1217; CHECK-NEXT:    ret1218  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)1219  ret <vscale x 8 x i32> %v1220}1221 1222define <vscale x 8 x i32> @vssub_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {1223; CHECK-LABEL: vssub_vv_nxv8i32_unmasked:1224; CHECK:       # %bb.0:1225; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1226; CHECK-NEXT:    vssub.vv v8, v8, v121227; CHECK-NEXT:    ret1228  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1229  ret <vscale x 8 x i32> %v1230}1231 1232define <vscale x 8 x i32> @vssub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1233; CHECK-LABEL: vssub_vx_nxv8i32:1234; CHECK:       # %bb.0:1235; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1236; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t1237; CHECK-NEXT:    ret1238  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01239  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1240  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)1241  ret <vscale x 8 x i32> %v1242}1243 1244define <vscale x 8 x i32> @vssub_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {1245; CHECK-LABEL: vssub_vx_nxv8i32_unmasked:1246; CHECK:       # %bb.0:1247; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1248; CHECK-NEXT:    vssub.vx v8, v8, a01249; CHECK-NEXT:    ret1250  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01251  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1252  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1253  ret <vscale x 8 x i32> %v1254}1255 1256define <vscale x 8 x i32> @vssub_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1257; CHECK-LABEL: vssub_vi_nxv8i32:1258; CHECK:       # %bb.0:1259; CHECK-NEXT:    li a1, -11260; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1261; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1262; CHECK-NEXT:    ret1263  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)1264  ret <vscale x 8 x i32> %v1265}1266 1267define <vscale x 8 x i32> @vssub_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1268; CHECK-LABEL: vssub_vi_nxv8i32_unmasked:1269; CHECK:       # %bb.0:1270; CHECK-NEXT:    li a1, -11271; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1272; CHECK-NEXT:    vssub.vx v8, v8, a11273; CHECK-NEXT:    ret1274  %v = call <vscale x 8 x i32> @llvm.vp.ssub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1275  ret <vscale x 8 x i32> %v1276}1277 1278define <vscale x 16 x i32> @vssub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1279; CHECK-LABEL: vssub_vv_nxv16i32:1280; CHECK:       # %bb.0:1281; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1282; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t1283; CHECK-NEXT:    ret1284  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)1285  ret <vscale x 16 x i32> %v1286}1287 1288define <vscale x 16 x i32> @vssub_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {1289; CHECK-LABEL: vssub_vv_nxv16i32_unmasked:1290; CHECK:       # %bb.0:1291; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1292; CHECK-NEXT:    vssub.vv v8, v8, v161293; CHECK-NEXT:    ret1294  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1295  ret <vscale x 16 x i32> %v1296}1297 1298define <vscale x 16 x i32> @vssub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1299; CHECK-LABEL: vssub_vx_nxv16i32:1300; CHECK:       # %bb.0:1301; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1302; CHECK-NEXT:    vssub.vx v8, v8, a0, v0.t1303; CHECK-NEXT:    ret1304  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01305  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1306  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)1307  ret <vscale x 16 x i32> %v1308}1309 1310define <vscale x 16 x i32> @vssub_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {1311; CHECK-LABEL: vssub_vx_nxv16i32_unmasked:1312; CHECK:       # %bb.0:1313; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1314; CHECK-NEXT:    vssub.vx v8, v8, a01315; CHECK-NEXT:    ret1316  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01317  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1318  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1319  ret <vscale x 16 x i32> %v1320}1321 1322define <vscale x 16 x i32> @vssub_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1323; CHECK-LABEL: vssub_vi_nxv16i32:1324; CHECK:       # %bb.0:1325; CHECK-NEXT:    li a1, -11326; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1327; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1328; CHECK-NEXT:    ret1329  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)1330  ret <vscale x 16 x i32> %v1331}1332 1333define <vscale x 16 x i32> @vssub_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1334; CHECK-LABEL: vssub_vi_nxv16i32_unmasked:1335; CHECK:       # %bb.0:1336; CHECK-NEXT:    li a1, -11337; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1338; CHECK-NEXT:    vssub.vx v8, v8, a11339; CHECK-NEXT:    ret1340  %v = call <vscale x 16 x i32> @llvm.vp.ssub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)1341  ret <vscale x 16 x i32> %v1342}1343 1344; Test that split-legalization works then the mask needs manual splitting.1345 1346define <vscale x 32 x i32> @vssub_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {1347; CHECK-LABEL: vssub_vi_nxv32i32:1348; CHECK:       # %bb.0:1349; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma1350; CHECK-NEXT:    vmv1r.v v24, v01351; CHECK-NEXT:    csrr a1, vlenb1352; CHECK-NEXT:    srli a2, a1, 21353; CHECK-NEXT:    slli a1, a1, 11354; CHECK-NEXT:    vslidedown.vx v0, v0, a21355; CHECK-NEXT:    sub a2, a0, a11356; CHECK-NEXT:    sltu a3, a0, a21357; CHECK-NEXT:    addi a3, a3, -11358; CHECK-NEXT:    and a3, a3, a21359; CHECK-NEXT:    li a2, -11360; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma1361; CHECK-NEXT:    vssub.vx v16, v16, a2, v0.t1362; CHECK-NEXT:    bltu a0, a1, .LBB118_21363; CHECK-NEXT:  # %bb.1:1364; CHECK-NEXT:    mv a0, a11365; CHECK-NEXT:  .LBB118_2:1366; CHECK-NEXT:    vmv1r.v v0, v241367; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1368; CHECK-NEXT:    vssub.vx v8, v8, a2, v0.t1369; CHECK-NEXT:    ret1370  %v = call <vscale x 32 x i32> @llvm.vp.ssub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)1371  ret <vscale x 32 x i32> %v1372}1373 1374define <vscale x 32 x i32> @vssub_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {1375; CHECK-LABEL: vssub_vi_nxv32i32_unmasked:1376; CHECK:       # %bb.0:1377; CHECK-NEXT:    csrr a1, vlenb1378; CHECK-NEXT:    slli a1, a1, 11379; CHECK-NEXT:    sub a2, a0, a11380; CHECK-NEXT:    sltu a3, a0, a21381; CHECK-NEXT:    addi a3, a3, -11382; CHECK-NEXT:    and a3, a3, a21383; CHECK-NEXT:    li a2, -11384; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma1385; CHECK-NEXT:    vssub.vx v16, v16, a21386; CHECK-NEXT:    bltu a0, a1, .LBB119_21387; CHECK-NEXT:  # %bb.1:1388; CHECK-NEXT:    mv a0, a11389; CHECK-NEXT:  .LBB119_2:1390; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1391; CHECK-NEXT:    vssub.vx v8, v8, a21392; CHECK-NEXT:    ret1393  %v = call <vscale x 32 x i32> @llvm.vp.ssub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1394  ret <vscale x 32 x i32> %v1395}1396 1397define <vscale x 1 x i64> @vssub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1398; CHECK-LABEL: vssub_vv_nxv1i64:1399; CHECK:       # %bb.0:1400; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1401; CHECK-NEXT:    vssub.vv v8, v8, v9, v0.t1402; CHECK-NEXT:    ret1403  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)1404  ret <vscale x 1 x i64> %v1405}1406 1407define <vscale x 1 x i64> @vssub_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {1408; CHECK-LABEL: vssub_vv_nxv1i64_unmasked:1409; CHECK:       # %bb.0:1410; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1411; CHECK-NEXT:    vssub.vv v8, v8, v91412; CHECK-NEXT:    ret1413  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1414  ret <vscale x 1 x i64> %v1415}1416 1417define <vscale x 1 x i64> @vssub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1418; RV32-LABEL: vssub_vx_nxv1i64:1419; RV32:       # %bb.0:1420; RV32-NEXT:    addi sp, sp, -161421; RV32-NEXT:    .cfi_def_cfa_offset 161422; RV32-NEXT:    sw a0, 8(sp)1423; RV32-NEXT:    sw a1, 12(sp)1424; RV32-NEXT:    addi a0, sp, 81425; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1426; RV32-NEXT:    vlse64.v v9, (a0), zero1427; RV32-NEXT:    vssub.vv v8, v8, v9, v0.t1428; RV32-NEXT:    addi sp, sp, 161429; RV32-NEXT:    .cfi_def_cfa_offset 01430; RV32-NEXT:    ret1431;1432; RV64-LABEL: vssub_vx_nxv1i64:1433; RV64:       # %bb.0:1434; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1435; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t1436; RV64-NEXT:    ret1437  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01438  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1439  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)1440  ret <vscale x 1 x i64> %v1441}1442 1443define <vscale x 1 x i64> @vssub_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {1444; RV32-LABEL: vssub_vx_nxv1i64_unmasked:1445; RV32:       # %bb.0:1446; RV32-NEXT:    addi sp, sp, -161447; RV32-NEXT:    .cfi_def_cfa_offset 161448; RV32-NEXT:    sw a0, 8(sp)1449; RV32-NEXT:    sw a1, 12(sp)1450; RV32-NEXT:    addi a0, sp, 81451; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1452; RV32-NEXT:    vlse64.v v9, (a0), zero1453; RV32-NEXT:    vssub.vv v8, v8, v91454; RV32-NEXT:    addi sp, sp, 161455; RV32-NEXT:    .cfi_def_cfa_offset 01456; RV32-NEXT:    ret1457;1458; RV64-LABEL: vssub_vx_nxv1i64_unmasked:1459; RV64:       # %bb.0:1460; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1461; RV64-NEXT:    vssub.vx v8, v8, a01462; RV64-NEXT:    ret1463  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01464  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1465  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1466  ret <vscale x 1 x i64> %v1467}1468 1469define <vscale x 1 x i64> @vssub_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1470; CHECK-LABEL: vssub_vi_nxv1i64:1471; CHECK:       # %bb.0:1472; CHECK-NEXT:    li a1, -11473; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1474; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1475; CHECK-NEXT:    ret1476  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)1477  ret <vscale x 1 x i64> %v1478}1479 1480define <vscale x 1 x i64> @vssub_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1481; CHECK-LABEL: vssub_vi_nxv1i64_unmasked:1482; CHECK:       # %bb.0:1483; CHECK-NEXT:    li a1, -11484; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1485; CHECK-NEXT:    vssub.vx v8, v8, a11486; CHECK-NEXT:    ret1487  %v = call <vscale x 1 x i64> @llvm.vp.ssub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1488  ret <vscale x 1 x i64> %v1489}1490 1491define <vscale x 2 x i64> @vssub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1492; CHECK-LABEL: vssub_vv_nxv2i64:1493; CHECK:       # %bb.0:1494; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1495; CHECK-NEXT:    vssub.vv v8, v8, v10, v0.t1496; CHECK-NEXT:    ret1497  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)1498  ret <vscale x 2 x i64> %v1499}1500 1501define <vscale x 2 x i64> @vssub_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {1502; CHECK-LABEL: vssub_vv_nxv2i64_unmasked:1503; CHECK:       # %bb.0:1504; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1505; CHECK-NEXT:    vssub.vv v8, v8, v101506; CHECK-NEXT:    ret1507  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1508  ret <vscale x 2 x i64> %v1509}1510 1511define <vscale x 2 x i64> @vssub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1512; RV32-LABEL: vssub_vx_nxv2i64:1513; RV32:       # %bb.0:1514; RV32-NEXT:    addi sp, sp, -161515; RV32-NEXT:    .cfi_def_cfa_offset 161516; RV32-NEXT:    sw a0, 8(sp)1517; RV32-NEXT:    sw a1, 12(sp)1518; RV32-NEXT:    addi a0, sp, 81519; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1520; RV32-NEXT:    vlse64.v v10, (a0), zero1521; RV32-NEXT:    vssub.vv v8, v8, v10, v0.t1522; RV32-NEXT:    addi sp, sp, 161523; RV32-NEXT:    .cfi_def_cfa_offset 01524; RV32-NEXT:    ret1525;1526; RV64-LABEL: vssub_vx_nxv2i64:1527; RV64:       # %bb.0:1528; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1529; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t1530; RV64-NEXT:    ret1531  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01532  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1533  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)1534  ret <vscale x 2 x i64> %v1535}1536 1537define <vscale x 2 x i64> @vssub_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {1538; RV32-LABEL: vssub_vx_nxv2i64_unmasked:1539; RV32:       # %bb.0:1540; RV32-NEXT:    addi sp, sp, -161541; RV32-NEXT:    .cfi_def_cfa_offset 161542; RV32-NEXT:    sw a0, 8(sp)1543; RV32-NEXT:    sw a1, 12(sp)1544; RV32-NEXT:    addi a0, sp, 81545; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1546; RV32-NEXT:    vlse64.v v10, (a0), zero1547; RV32-NEXT:    vssub.vv v8, v8, v101548; RV32-NEXT:    addi sp, sp, 161549; RV32-NEXT:    .cfi_def_cfa_offset 01550; RV32-NEXT:    ret1551;1552; RV64-LABEL: vssub_vx_nxv2i64_unmasked:1553; RV64:       # %bb.0:1554; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1555; RV64-NEXT:    vssub.vx v8, v8, a01556; RV64-NEXT:    ret1557  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01558  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1559  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1560  ret <vscale x 2 x i64> %v1561}1562 1563define <vscale x 2 x i64> @vssub_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1564; CHECK-LABEL: vssub_vi_nxv2i64:1565; CHECK:       # %bb.0:1566; CHECK-NEXT:    li a1, -11567; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1568; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1569; CHECK-NEXT:    ret1570  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)1571  ret <vscale x 2 x i64> %v1572}1573 1574define <vscale x 2 x i64> @vssub_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1575; CHECK-LABEL: vssub_vi_nxv2i64_unmasked:1576; CHECK:       # %bb.0:1577; CHECK-NEXT:    li a1, -11578; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1579; CHECK-NEXT:    vssub.vx v8, v8, a11580; CHECK-NEXT:    ret1581  %v = call <vscale x 2 x i64> @llvm.vp.ssub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1582  ret <vscale x 2 x i64> %v1583}1584 1585define <vscale x 4 x i64> @vssub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1586; CHECK-LABEL: vssub_vv_nxv4i64:1587; CHECK:       # %bb.0:1588; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1589; CHECK-NEXT:    vssub.vv v8, v8, v12, v0.t1590; CHECK-NEXT:    ret1591  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)1592  ret <vscale x 4 x i64> %v1593}1594 1595define <vscale x 4 x i64> @vssub_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {1596; CHECK-LABEL: vssub_vv_nxv4i64_unmasked:1597; CHECK:       # %bb.0:1598; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1599; CHECK-NEXT:    vssub.vv v8, v8, v121600; CHECK-NEXT:    ret1601  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1602  ret <vscale x 4 x i64> %v1603}1604 1605define <vscale x 4 x i64> @vssub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1606; RV32-LABEL: vssub_vx_nxv4i64:1607; RV32:       # %bb.0:1608; RV32-NEXT:    addi sp, sp, -161609; RV32-NEXT:    .cfi_def_cfa_offset 161610; RV32-NEXT:    sw a0, 8(sp)1611; RV32-NEXT:    sw a1, 12(sp)1612; RV32-NEXT:    addi a0, sp, 81613; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1614; RV32-NEXT:    vlse64.v v12, (a0), zero1615; RV32-NEXT:    vssub.vv v8, v8, v12, v0.t1616; RV32-NEXT:    addi sp, sp, 161617; RV32-NEXT:    .cfi_def_cfa_offset 01618; RV32-NEXT:    ret1619;1620; RV64-LABEL: vssub_vx_nxv4i64:1621; RV64:       # %bb.0:1622; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1623; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t1624; RV64-NEXT:    ret1625  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01626  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1627  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)1628  ret <vscale x 4 x i64> %v1629}1630 1631define <vscale x 4 x i64> @vssub_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {1632; RV32-LABEL: vssub_vx_nxv4i64_unmasked:1633; RV32:       # %bb.0:1634; RV32-NEXT:    addi sp, sp, -161635; RV32-NEXT:    .cfi_def_cfa_offset 161636; RV32-NEXT:    sw a0, 8(sp)1637; RV32-NEXT:    sw a1, 12(sp)1638; RV32-NEXT:    addi a0, sp, 81639; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1640; RV32-NEXT:    vlse64.v v12, (a0), zero1641; RV32-NEXT:    vssub.vv v8, v8, v121642; RV32-NEXT:    addi sp, sp, 161643; RV32-NEXT:    .cfi_def_cfa_offset 01644; RV32-NEXT:    ret1645;1646; RV64-LABEL: vssub_vx_nxv4i64_unmasked:1647; RV64:       # %bb.0:1648; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1649; RV64-NEXT:    vssub.vx v8, v8, a01650; RV64-NEXT:    ret1651  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01652  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1653  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1654  ret <vscale x 4 x i64> %v1655}1656 1657define <vscale x 4 x i64> @vssub_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1658; CHECK-LABEL: vssub_vi_nxv4i64:1659; CHECK:       # %bb.0:1660; CHECK-NEXT:    li a1, -11661; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1662; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1663; CHECK-NEXT:    ret1664  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)1665  ret <vscale x 4 x i64> %v1666}1667 1668define <vscale x 4 x i64> @vssub_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1669; CHECK-LABEL: vssub_vi_nxv4i64_unmasked:1670; CHECK:       # %bb.0:1671; CHECK-NEXT:    li a1, -11672; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1673; CHECK-NEXT:    vssub.vx v8, v8, a11674; CHECK-NEXT:    ret1675  %v = call <vscale x 4 x i64> @llvm.vp.ssub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1676  ret <vscale x 4 x i64> %v1677}1678 1679define <vscale x 8 x i64> @vssub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1680; CHECK-LABEL: vssub_vv_nxv8i64:1681; CHECK:       # %bb.0:1682; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1683; CHECK-NEXT:    vssub.vv v8, v8, v16, v0.t1684; CHECK-NEXT:    ret1685  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)1686  ret <vscale x 8 x i64> %v1687}1688 1689define <vscale x 8 x i64> @vssub_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {1690; CHECK-LABEL: vssub_vv_nxv8i64_unmasked:1691; CHECK:       # %bb.0:1692; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1693; CHECK-NEXT:    vssub.vv v8, v8, v161694; CHECK-NEXT:    ret1695  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1696  ret <vscale x 8 x i64> %v1697}1698 1699define <vscale x 8 x i64> @vssub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1700; RV32-LABEL: vssub_vx_nxv8i64:1701; RV32:       # %bb.0:1702; RV32-NEXT:    addi sp, sp, -161703; RV32-NEXT:    .cfi_def_cfa_offset 161704; RV32-NEXT:    sw a0, 8(sp)1705; RV32-NEXT:    sw a1, 12(sp)1706; RV32-NEXT:    addi a0, sp, 81707; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1708; RV32-NEXT:    vlse64.v v16, (a0), zero1709; RV32-NEXT:    vssub.vv v8, v8, v16, v0.t1710; RV32-NEXT:    addi sp, sp, 161711; RV32-NEXT:    .cfi_def_cfa_offset 01712; RV32-NEXT:    ret1713;1714; RV64-LABEL: vssub_vx_nxv8i64:1715; RV64:       # %bb.0:1716; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1717; RV64-NEXT:    vssub.vx v8, v8, a0, v0.t1718; RV64-NEXT:    ret1719  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01720  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1721  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)1722  ret <vscale x 8 x i64> %v1723}1724 1725define <vscale x 8 x i64> @vssub_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {1726; RV32-LABEL: vssub_vx_nxv8i64_unmasked:1727; RV32:       # %bb.0:1728; RV32-NEXT:    addi sp, sp, -161729; RV32-NEXT:    .cfi_def_cfa_offset 161730; RV32-NEXT:    sw a0, 8(sp)1731; RV32-NEXT:    sw a1, 12(sp)1732; RV32-NEXT:    addi a0, sp, 81733; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1734; RV32-NEXT:    vlse64.v v16, (a0), zero1735; RV32-NEXT:    vssub.vv v8, v8, v161736; RV32-NEXT:    addi sp, sp, 161737; RV32-NEXT:    .cfi_def_cfa_offset 01738; RV32-NEXT:    ret1739;1740; RV64-LABEL: vssub_vx_nxv8i64_unmasked:1741; RV64:       # %bb.0:1742; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1743; RV64-NEXT:    vssub.vx v8, v8, a01744; RV64-NEXT:    ret1745  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01746  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1747  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1748  ret <vscale x 8 x i64> %v1749}1750 1751define <vscale x 8 x i64> @vssub_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1752; CHECK-LABEL: vssub_vi_nxv8i64:1753; CHECK:       # %bb.0:1754; CHECK-NEXT:    li a1, -11755; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1756; CHECK-NEXT:    vssub.vx v8, v8, a1, v0.t1757; CHECK-NEXT:    ret1758  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)1759  ret <vscale x 8 x i64> %v1760}1761 1762define <vscale x 8 x i64> @vssub_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1763; CHECK-LABEL: vssub_vi_nxv8i64_unmasked:1764; CHECK:       # %bb.0:1765; CHECK-NEXT:    li a1, -11766; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1767; CHECK-NEXT:    vssub.vx v8, v8, a11768; CHECK-NEXT:    ret1769  %v = call <vscale x 8 x i64> @llvm.vp.ssub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1770  ret <vscale x 8 x i64> %v1771}1772