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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @usub_nxv1i8_vv(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b) {8; CHECK-LABEL: usub_nxv1i8_vv:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vssubu.vv v8, v8, v912; CHECK-NEXT: ret13 %v = call <vscale x 1 x i8> @llvm.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b)14 ret <vscale x 1 x i8> %v15}16 17define <vscale x 1 x i8> @usub_nxv1i8_vx(<vscale x 1 x i8> %va, i8 %b) {18; CHECK-LABEL: usub_nxv1i8_vx:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma21; CHECK-NEXT: vssubu.vx v8, v8, a022; CHECK-NEXT: ret23 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 024 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer25 %v = call <vscale x 1 x i8> @llvm.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb)26 ret <vscale x 1 x i8> %v27}28 29define <vscale x 1 x i8> @usub_nxv1i8_vi(<vscale x 1 x i8> %va) {30; CHECK-LABEL: usub_nxv1i8_vi:31; CHECK: # %bb.0:32; CHECK-NEXT: li a0, 233; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma34; CHECK-NEXT: vssubu.vx v8, v8, a035; CHECK-NEXT: ret36 %v = call <vscale x 1 x i8> @llvm.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 2))37 ret <vscale x 1 x i8> %v38}39 40define <vscale x 2 x i8> @usub_nxv2i8_vv(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b) {41; CHECK-LABEL: usub_nxv2i8_vv:42; CHECK: # %bb.0:43; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma44; CHECK-NEXT: vssubu.vv v8, v8, v945; CHECK-NEXT: ret46 %v = call <vscale x 2 x i8> @llvm.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b)47 ret <vscale x 2 x i8> %v48}49 50define <vscale x 2 x i8> @usub_nxv2i8_vx(<vscale x 2 x i8> %va, i8 %b) {51; CHECK-LABEL: usub_nxv2i8_vx:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma54; CHECK-NEXT: vssubu.vx v8, v8, a055; CHECK-NEXT: ret56 %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 057 %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer58 %v = call <vscale x 2 x i8> @llvm.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb)59 ret <vscale x 2 x i8> %v60}61 62define <vscale x 2 x i8> @usub_nxv2i8_vi(<vscale x 2 x i8> %va) {63; CHECK-LABEL: usub_nxv2i8_vi:64; CHECK: # %bb.0:65; CHECK-NEXT: li a0, 266; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma67; CHECK-NEXT: vssubu.vx v8, v8, a068; CHECK-NEXT: ret69 %v = call <vscale x 2 x i8> @llvm.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 2))70 ret <vscale x 2 x i8> %v71}72 73define <vscale x 4 x i8> @usub_nxv4i8_vv(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b) {74; CHECK-LABEL: usub_nxv4i8_vv:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma77; CHECK-NEXT: vssubu.vv v8, v8, v978; CHECK-NEXT: ret79 %v = call <vscale x 4 x i8> @llvm.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b)80 ret <vscale x 4 x i8> %v81}82 83define <vscale x 4 x i8> @usub_nxv4i8_vx(<vscale x 4 x i8> %va, i8 %b) {84; CHECK-LABEL: usub_nxv4i8_vx:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma87; CHECK-NEXT: vssubu.vx v8, v8, a088; CHECK-NEXT: ret89 %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 090 %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer91 %v = call <vscale x 4 x i8> @llvm.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb)92 ret <vscale x 4 x i8> %v93}94 95define <vscale x 4 x i8> @usub_nxv4i8_vi(<vscale x 4 x i8> %va) {96; CHECK-LABEL: usub_nxv4i8_vi:97; CHECK: # %bb.0:98; CHECK-NEXT: li a0, 299; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma100; CHECK-NEXT: vssubu.vx v8, v8, a0101; CHECK-NEXT: ret102 %v = call <vscale x 4 x i8> @llvm.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 2))103 ret <vscale x 4 x i8> %v104}105 106define <vscale x 8 x i8> @usub_nxv8i8_vv(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b) {107; CHECK-LABEL: usub_nxv8i8_vv:108; CHECK: # %bb.0:109; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma110; CHECK-NEXT: vssubu.vv v8, v8, v9111; CHECK-NEXT: ret112 %v = call <vscale x 8 x i8> @llvm.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b)113 ret <vscale x 8 x i8> %v114}115 116define <vscale x 8 x i8> @usub_nxv8i8_vx(<vscale x 8 x i8> %va, i8 %b) {117; CHECK-LABEL: usub_nxv8i8_vx:118; CHECK: # %bb.0:119; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma120; CHECK-NEXT: vssubu.vx v8, v8, a0121; CHECK-NEXT: ret122 %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0123 %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer124 %v = call <vscale x 8 x i8> @llvm.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb)125 ret <vscale x 8 x i8> %v126}127 128define <vscale x 8 x i8> @usub_nxv8i8_vi(<vscale x 8 x i8> %va) {129; CHECK-LABEL: usub_nxv8i8_vi:130; CHECK: # %bb.0:131; CHECK-NEXT: li a0, 2132; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma133; CHECK-NEXT: vssubu.vx v8, v8, a0134; CHECK-NEXT: ret135 %v = call <vscale x 8 x i8> @llvm.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 2))136 ret <vscale x 8 x i8> %v137}138 139define <vscale x 16 x i8> @usub_nxv16i8_vv(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b) {140; CHECK-LABEL: usub_nxv16i8_vv:141; CHECK: # %bb.0:142; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma143; CHECK-NEXT: vssubu.vv v8, v8, v10144; CHECK-NEXT: ret145 %v = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b)146 ret <vscale x 16 x i8> %v147}148 149define <vscale x 16 x i8> @usub_nxv16i8_vx(<vscale x 16 x i8> %va, i8 %b) {150; CHECK-LABEL: usub_nxv16i8_vx:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma153; CHECK-NEXT: vssubu.vx v8, v8, a0154; CHECK-NEXT: ret155 %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0156 %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer157 %v = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb)158 ret <vscale x 16 x i8> %v159}160 161define <vscale x 16 x i8> @usub_nxv16i8_vi(<vscale x 16 x i8> %va) {162; CHECK-LABEL: usub_nxv16i8_vi:163; CHECK: # %bb.0:164; CHECK-NEXT: li a0, 2165; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma166; CHECK-NEXT: vssubu.vx v8, v8, a0167; CHECK-NEXT: ret168 %v = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 2))169 ret <vscale x 16 x i8> %v170}171 172define <vscale x 32 x i8> @usub_nxv32i8_vv(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b) {173; CHECK-LABEL: usub_nxv32i8_vv:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma176; CHECK-NEXT: vssubu.vv v8, v8, v12177; CHECK-NEXT: ret178 %v = call <vscale x 32 x i8> @llvm.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b)179 ret <vscale x 32 x i8> %v180}181 182define <vscale x 32 x i8> @usub_nxv32i8_vx(<vscale x 32 x i8> %va, i8 %b) {183; CHECK-LABEL: usub_nxv32i8_vx:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma186; CHECK-NEXT: vssubu.vx v8, v8, a0187; CHECK-NEXT: ret188 %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0189 %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer190 %v = call <vscale x 32 x i8> @llvm.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb)191 ret <vscale x 32 x i8> %v192}193 194define <vscale x 32 x i8> @usub_nxv32i8_vi(<vscale x 32 x i8> %va) {195; CHECK-LABEL: usub_nxv32i8_vi:196; CHECK: # %bb.0:197; CHECK-NEXT: li a0, 2198; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma199; CHECK-NEXT: vssubu.vx v8, v8, a0200; CHECK-NEXT: ret201 %v = call <vscale x 32 x i8> @llvm.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 2))202 ret <vscale x 32 x i8> %v203}204 205define <vscale x 64 x i8> @usub_nxv64i8_vv(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b) {206; CHECK-LABEL: usub_nxv64i8_vv:207; CHECK: # %bb.0:208; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma209; CHECK-NEXT: vssubu.vv v8, v8, v16210; CHECK-NEXT: ret211 %v = call <vscale x 64 x i8> @llvm.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b)212 ret <vscale x 64 x i8> %v213}214 215define <vscale x 64 x i8> @usub_nxv64i8_vx(<vscale x 64 x i8> %va, i8 %b) {216; CHECK-LABEL: usub_nxv64i8_vx:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma219; CHECK-NEXT: vssubu.vx v8, v8, a0220; CHECK-NEXT: ret221 %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0222 %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer223 %v = call <vscale x 64 x i8> @llvm.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb)224 ret <vscale x 64 x i8> %v225}226 227define <vscale x 64 x i8> @usub_nxv64i8_vi(<vscale x 64 x i8> %va) {228; CHECK-LABEL: usub_nxv64i8_vi:229; CHECK: # %bb.0:230; CHECK-NEXT: li a0, 2231; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma232; CHECK-NEXT: vssubu.vx v8, v8, a0233; CHECK-NEXT: ret234 %v = call <vscale x 64 x i8> @llvm.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 2))235 ret <vscale x 64 x i8> %v236}237 238define <vscale x 1 x i16> @usub_nxv1i16_vv(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b) {239; CHECK-LABEL: usub_nxv1i16_vv:240; CHECK: # %bb.0:241; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma242; CHECK-NEXT: vssubu.vv v8, v8, v9243; CHECK-NEXT: ret244 %v = call <vscale x 1 x i16> @llvm.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b)245 ret <vscale x 1 x i16> %v246}247 248define <vscale x 1 x i16> @usub_nxv1i16_vx(<vscale x 1 x i16> %va, i16 %b) {249; CHECK-LABEL: usub_nxv1i16_vx:250; CHECK: # %bb.0:251; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma252; CHECK-NEXT: vssubu.vx v8, v8, a0253; CHECK-NEXT: ret254 %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0255 %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer256 %v = call <vscale x 1 x i16> @llvm.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb)257 ret <vscale x 1 x i16> %v258}259 260define <vscale x 1 x i16> @usub_nxv1i16_vi(<vscale x 1 x i16> %va) {261; CHECK-LABEL: usub_nxv1i16_vi:262; CHECK: # %bb.0:263; CHECK-NEXT: li a0, 2264; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma265; CHECK-NEXT: vssubu.vx v8, v8, a0266; CHECK-NEXT: ret267 %v = call <vscale x 1 x i16> @llvm.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 2))268 ret <vscale x 1 x i16> %v269}270 271define <vscale x 2 x i16> @usub_nxv2i16_vv(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b) {272; CHECK-LABEL: usub_nxv2i16_vv:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma275; CHECK-NEXT: vssubu.vv v8, v8, v9276; CHECK-NEXT: ret277 %v = call <vscale x 2 x i16> @llvm.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b)278 ret <vscale x 2 x i16> %v279}280 281define <vscale x 2 x i16> @usub_nxv2i16_vx(<vscale x 2 x i16> %va, i16 %b) {282; CHECK-LABEL: usub_nxv2i16_vx:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma285; CHECK-NEXT: vssubu.vx v8, v8, a0286; CHECK-NEXT: ret287 %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0288 %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer289 %v = call <vscale x 2 x i16> @llvm.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb)290 ret <vscale x 2 x i16> %v291}292 293define <vscale x 2 x i16> @usub_nxv2i16_vi(<vscale x 2 x i16> %va) {294; CHECK-LABEL: usub_nxv2i16_vi:295; CHECK: # %bb.0:296; CHECK-NEXT: li a0, 2297; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma298; CHECK-NEXT: vssubu.vx v8, v8, a0299; CHECK-NEXT: ret300 %v = call <vscale x 2 x i16> @llvm.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 2))301 ret <vscale x 2 x i16> %v302}303 304define <vscale x 4 x i16> @usub_nxv4i16_vv(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b) {305; CHECK-LABEL: usub_nxv4i16_vv:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma308; CHECK-NEXT: vssubu.vv v8, v8, v9309; CHECK-NEXT: ret310 %v = call <vscale x 4 x i16> @llvm.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b)311 ret <vscale x 4 x i16> %v312}313 314define <vscale x 4 x i16> @usub_nxv4i16_vx(<vscale x 4 x i16> %va, i16 %b) {315; CHECK-LABEL: usub_nxv4i16_vx:316; CHECK: # %bb.0:317; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma318; CHECK-NEXT: vssubu.vx v8, v8, a0319; CHECK-NEXT: ret320 %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0321 %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer322 %v = call <vscale x 4 x i16> @llvm.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb)323 ret <vscale x 4 x i16> %v324}325 326define <vscale x 4 x i16> @usub_nxv4i16_vi(<vscale x 4 x i16> %va) {327; CHECK-LABEL: usub_nxv4i16_vi:328; CHECK: # %bb.0:329; CHECK-NEXT: li a0, 2330; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma331; CHECK-NEXT: vssubu.vx v8, v8, a0332; CHECK-NEXT: ret333 %v = call <vscale x 4 x i16> @llvm.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 2))334 ret <vscale x 4 x i16> %v335}336 337define <vscale x 8 x i16> @usub_nxv8i16_vv(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b) {338; CHECK-LABEL: usub_nxv8i16_vv:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma341; CHECK-NEXT: vssubu.vv v8, v8, v10342; CHECK-NEXT: ret343 %v = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b)344 ret <vscale x 8 x i16> %v345}346 347define <vscale x 8 x i16> @usub_nxv8i16_vx(<vscale x 8 x i16> %va, i16 %b) {348; CHECK-LABEL: usub_nxv8i16_vx:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma351; CHECK-NEXT: vssubu.vx v8, v8, a0352; CHECK-NEXT: ret353 %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0354 %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer355 %v = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb)356 ret <vscale x 8 x i16> %v357}358 359define <vscale x 8 x i16> @usub_nxv8i16_vi(<vscale x 8 x i16> %va) {360; CHECK-LABEL: usub_nxv8i16_vi:361; CHECK: # %bb.0:362; CHECK-NEXT: li a0, 2363; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma364; CHECK-NEXT: vssubu.vx v8, v8, a0365; CHECK-NEXT: ret366 %v = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 2))367 ret <vscale x 8 x i16> %v368}369 370define <vscale x 16 x i16> @usub_nxv16i16_vv(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b) {371; CHECK-LABEL: usub_nxv16i16_vv:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma374; CHECK-NEXT: vssubu.vv v8, v8, v12375; CHECK-NEXT: ret376 %v = call <vscale x 16 x i16> @llvm.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b)377 ret <vscale x 16 x i16> %v378}379 380define <vscale x 16 x i16> @usub_nxv16i16_vx(<vscale x 16 x i16> %va, i16 %b) {381; CHECK-LABEL: usub_nxv16i16_vx:382; CHECK: # %bb.0:383; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma384; CHECK-NEXT: vssubu.vx v8, v8, a0385; CHECK-NEXT: ret386 %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0387 %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer388 %v = call <vscale x 16 x i16> @llvm.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb)389 ret <vscale x 16 x i16> %v390}391 392define <vscale x 16 x i16> @usub_nxv16i16_vi(<vscale x 16 x i16> %va) {393; CHECK-LABEL: usub_nxv16i16_vi:394; CHECK: # %bb.0:395; CHECK-NEXT: li a0, 2396; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma397; CHECK-NEXT: vssubu.vx v8, v8, a0398; CHECK-NEXT: ret399 %v = call <vscale x 16 x i16> @llvm.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 2))400 ret <vscale x 16 x i16> %v401}402 403define <vscale x 32 x i16> @usub_nxv32i16_vv(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b) {404; CHECK-LABEL: usub_nxv32i16_vv:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma407; CHECK-NEXT: vssubu.vv v8, v8, v16408; CHECK-NEXT: ret409 %v = call <vscale x 32 x i16> @llvm.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b)410 ret <vscale x 32 x i16> %v411}412 413define <vscale x 32 x i16> @usub_nxv32i16_vx(<vscale x 32 x i16> %va, i16 %b) {414; CHECK-LABEL: usub_nxv32i16_vx:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma417; CHECK-NEXT: vssubu.vx v8, v8, a0418; CHECK-NEXT: ret419 %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0420 %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer421 %v = call <vscale x 32 x i16> @llvm.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb)422 ret <vscale x 32 x i16> %v423}424 425define <vscale x 32 x i16> @usub_nxv32i16_vi(<vscale x 32 x i16> %va) {426; CHECK-LABEL: usub_nxv32i16_vi:427; CHECK: # %bb.0:428; CHECK-NEXT: li a0, 2429; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma430; CHECK-NEXT: vssubu.vx v8, v8, a0431; CHECK-NEXT: ret432 %v = call <vscale x 32 x i16> @llvm.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 2))433 ret <vscale x 32 x i16> %v434}435 436define <vscale x 1 x i32> @usub_nxv1i32_vv(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b) {437; CHECK-LABEL: usub_nxv1i32_vv:438; CHECK: # %bb.0:439; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma440; CHECK-NEXT: vssubu.vv v8, v8, v9441; CHECK-NEXT: ret442 %v = call <vscale x 1 x i32> @llvm.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b)443 ret <vscale x 1 x i32> %v444}445 446define <vscale x 1 x i32> @usub_nxv1i32_vx(<vscale x 1 x i32> %va, i32 %b) {447; CHECK-LABEL: usub_nxv1i32_vx:448; CHECK: # %bb.0:449; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma450; CHECK-NEXT: vssubu.vx v8, v8, a0451; CHECK-NEXT: ret452 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0453 %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer454 %v = call <vscale x 1 x i32> @llvm.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb)455 ret <vscale x 1 x i32> %v456}457 458define <vscale x 1 x i32> @usub_nxv1i32_vi(<vscale x 1 x i32> %va) {459; CHECK-LABEL: usub_nxv1i32_vi:460; CHECK: # %bb.0:461; CHECK-NEXT: li a0, 2462; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma463; CHECK-NEXT: vssubu.vx v8, v8, a0464; CHECK-NEXT: ret465 %v = call <vscale x 1 x i32> @llvm.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 2))466 ret <vscale x 1 x i32> %v467}468 469define <vscale x 2 x i32> @usub_nxv2i32_vv(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b) {470; CHECK-LABEL: usub_nxv2i32_vv:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma473; CHECK-NEXT: vssubu.vv v8, v8, v9474; CHECK-NEXT: ret475 %v = call <vscale x 2 x i32> @llvm.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b)476 ret <vscale x 2 x i32> %v477}478 479define <vscale x 2 x i32> @usub_nxv2i32_vx(<vscale x 2 x i32> %va, i32 %b) {480; CHECK-LABEL: usub_nxv2i32_vx:481; CHECK: # %bb.0:482; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma483; CHECK-NEXT: vssubu.vx v8, v8, a0484; CHECK-NEXT: ret485 %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0486 %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer487 %v = call <vscale x 2 x i32> @llvm.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb)488 ret <vscale x 2 x i32> %v489}490 491define <vscale x 2 x i32> @usub_nxv2i32_vi(<vscale x 2 x i32> %va) {492; CHECK-LABEL: usub_nxv2i32_vi:493; CHECK: # %bb.0:494; CHECK-NEXT: li a0, 2495; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma496; CHECK-NEXT: vssubu.vx v8, v8, a0497; CHECK-NEXT: ret498 %v = call <vscale x 2 x i32> @llvm.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 2))499 ret <vscale x 2 x i32> %v500}501 502define <vscale x 4 x i32> @usub_nxv4i32_vv(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b) {503; CHECK-LABEL: usub_nxv4i32_vv:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma506; CHECK-NEXT: vssubu.vv v8, v8, v10507; CHECK-NEXT: ret508 %v = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b)509 ret <vscale x 4 x i32> %v510}511 512define <vscale x 4 x i32> @usub_nxv4i32_vx(<vscale x 4 x i32> %va, i32 %b) {513; CHECK-LABEL: usub_nxv4i32_vx:514; CHECK: # %bb.0:515; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma516; CHECK-NEXT: vssubu.vx v8, v8, a0517; CHECK-NEXT: ret518 %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0519 %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer520 %v = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb)521 ret <vscale x 4 x i32> %v522}523 524define <vscale x 4 x i32> @usub_nxv4i32_vi(<vscale x 4 x i32> %va) {525; CHECK-LABEL: usub_nxv4i32_vi:526; CHECK: # %bb.0:527; CHECK-NEXT: li a0, 2528; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma529; CHECK-NEXT: vssubu.vx v8, v8, a0530; CHECK-NEXT: ret531 %v = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 2))532 ret <vscale x 4 x i32> %v533}534 535define <vscale x 8 x i32> @usub_nxv8i32_vv(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b) {536; CHECK-LABEL: usub_nxv8i32_vv:537; CHECK: # %bb.0:538; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma539; CHECK-NEXT: vssubu.vv v8, v8, v12540; CHECK-NEXT: ret541 %v = call <vscale x 8 x i32> @llvm.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b)542 ret <vscale x 8 x i32> %v543}544 545define <vscale x 8 x i32> @usub_nxv8i32_vx(<vscale x 8 x i32> %va, i32 %b) {546; CHECK-LABEL: usub_nxv8i32_vx:547; CHECK: # %bb.0:548; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma549; CHECK-NEXT: vssubu.vx v8, v8, a0550; CHECK-NEXT: ret551 %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0552 %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer553 %v = call <vscale x 8 x i32> @llvm.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb)554 ret <vscale x 8 x i32> %v555}556 557define <vscale x 8 x i32> @usub_nxv8i32_vi(<vscale x 8 x i32> %va) {558; CHECK-LABEL: usub_nxv8i32_vi:559; CHECK: # %bb.0:560; CHECK-NEXT: li a0, 2561; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma562; CHECK-NEXT: vssubu.vx v8, v8, a0563; CHECK-NEXT: ret564 %v = call <vscale x 8 x i32> @llvm.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 2))565 ret <vscale x 8 x i32> %v566}567 568define <vscale x 16 x i32> @usub_nxv16i32_vv(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b) {569; CHECK-LABEL: usub_nxv16i32_vv:570; CHECK: # %bb.0:571; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma572; CHECK-NEXT: vssubu.vv v8, v8, v16573; CHECK-NEXT: ret574 %v = call <vscale x 16 x i32> @llvm.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b)575 ret <vscale x 16 x i32> %v576}577 578define <vscale x 16 x i32> @usub_nxv16i32_vx(<vscale x 16 x i32> %va, i32 %b) {579; CHECK-LABEL: usub_nxv16i32_vx:580; CHECK: # %bb.0:581; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma582; CHECK-NEXT: vssubu.vx v8, v8, a0583; CHECK-NEXT: ret584 %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0585 %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer586 %v = call <vscale x 16 x i32> @llvm.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb)587 ret <vscale x 16 x i32> %v588}589 590define <vscale x 16 x i32> @usub_nxv16i32_vi(<vscale x 16 x i32> %va) {591; CHECK-LABEL: usub_nxv16i32_vi:592; CHECK: # %bb.0:593; CHECK-NEXT: li a0, 2594; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma595; CHECK-NEXT: vssubu.vx v8, v8, a0596; CHECK-NEXT: ret597 %v = call <vscale x 16 x i32> @llvm.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 2))598 ret <vscale x 16 x i32> %v599}600 601define <vscale x 1 x i64> @usub_nxv1i64_vv(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b) {602; CHECK-LABEL: usub_nxv1i64_vv:603; CHECK: # %bb.0:604; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma605; CHECK-NEXT: vssubu.vv v8, v8, v9606; CHECK-NEXT: ret607 %v = call <vscale x 1 x i64> @llvm.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b)608 ret <vscale x 1 x i64> %v609}610 611define <vscale x 1 x i64> @usub_nxv1i64_vx(<vscale x 1 x i64> %va, i64 %b) {612; RV32-LABEL: usub_nxv1i64_vx:613; RV32: # %bb.0:614; RV32-NEXT: addi sp, sp, -16615; RV32-NEXT: .cfi_def_cfa_offset 16616; RV32-NEXT: sw a0, 8(sp)617; RV32-NEXT: sw a1, 12(sp)618; RV32-NEXT: addi a0, sp, 8619; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma620; RV32-NEXT: vlse64.v v9, (a0), zero621; RV32-NEXT: vssubu.vv v8, v8, v9622; RV32-NEXT: addi sp, sp, 16623; RV32-NEXT: .cfi_def_cfa_offset 0624; RV32-NEXT: ret625;626; RV64-LABEL: usub_nxv1i64_vx:627; RV64: # %bb.0:628; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma629; RV64-NEXT: vssubu.vx v8, v8, a0630; RV64-NEXT: ret631 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0632 %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer633 %v = call <vscale x 1 x i64> @llvm.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb)634 ret <vscale x 1 x i64> %v635}636 637define <vscale x 1 x i64> @usub_nxv1i64_vi(<vscale x 1 x i64> %va) {638; CHECK-LABEL: usub_nxv1i64_vi:639; CHECK: # %bb.0:640; CHECK-NEXT: li a0, 2641; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma642; CHECK-NEXT: vssubu.vx v8, v8, a0643; CHECK-NEXT: ret644 %v = call <vscale x 1 x i64> @llvm.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 2))645 ret <vscale x 1 x i64> %v646}647 648define <vscale x 2 x i64> @usub_nxv2i64_vv(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b) {649; CHECK-LABEL: usub_nxv2i64_vv:650; CHECK: # %bb.0:651; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma652; CHECK-NEXT: vssubu.vv v8, v8, v10653; CHECK-NEXT: ret654 %v = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b)655 ret <vscale x 2 x i64> %v656}657 658define <vscale x 2 x i64> @usub_nxv2i64_vx(<vscale x 2 x i64> %va, i64 %b) {659; RV32-LABEL: usub_nxv2i64_vx:660; RV32: # %bb.0:661; RV32-NEXT: addi sp, sp, -16662; RV32-NEXT: .cfi_def_cfa_offset 16663; RV32-NEXT: sw a0, 8(sp)664; RV32-NEXT: sw a1, 12(sp)665; RV32-NEXT: addi a0, sp, 8666; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma667; RV32-NEXT: vlse64.v v10, (a0), zero668; RV32-NEXT: vssubu.vv v8, v8, v10669; RV32-NEXT: addi sp, sp, 16670; RV32-NEXT: .cfi_def_cfa_offset 0671; RV32-NEXT: ret672;673; RV64-LABEL: usub_nxv2i64_vx:674; RV64: # %bb.0:675; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma676; RV64-NEXT: vssubu.vx v8, v8, a0677; RV64-NEXT: ret678 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0679 %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer680 %v = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb)681 ret <vscale x 2 x i64> %v682}683 684define <vscale x 2 x i64> @usub_nxv2i64_vi(<vscale x 2 x i64> %va) {685; CHECK-LABEL: usub_nxv2i64_vi:686; CHECK: # %bb.0:687; CHECK-NEXT: li a0, 2688; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma689; CHECK-NEXT: vssubu.vx v8, v8, a0690; CHECK-NEXT: ret691 %v = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 2))692 ret <vscale x 2 x i64> %v693}694 695define <vscale x 4 x i64> @usub_nxv4i64_vv(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b) {696; CHECK-LABEL: usub_nxv4i64_vv:697; CHECK: # %bb.0:698; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma699; CHECK-NEXT: vssubu.vv v8, v8, v12700; CHECK-NEXT: ret701 %v = call <vscale x 4 x i64> @llvm.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b)702 ret <vscale x 4 x i64> %v703}704 705define <vscale x 4 x i64> @usub_nxv4i64_vx(<vscale x 4 x i64> %va, i64 %b) {706; RV32-LABEL: usub_nxv4i64_vx:707; RV32: # %bb.0:708; RV32-NEXT: addi sp, sp, -16709; RV32-NEXT: .cfi_def_cfa_offset 16710; RV32-NEXT: sw a0, 8(sp)711; RV32-NEXT: sw a1, 12(sp)712; RV32-NEXT: addi a0, sp, 8713; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma714; RV32-NEXT: vlse64.v v12, (a0), zero715; RV32-NEXT: vssubu.vv v8, v8, v12716; RV32-NEXT: addi sp, sp, 16717; RV32-NEXT: .cfi_def_cfa_offset 0718; RV32-NEXT: ret719;720; RV64-LABEL: usub_nxv4i64_vx:721; RV64: # %bb.0:722; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma723; RV64-NEXT: vssubu.vx v8, v8, a0724; RV64-NEXT: ret725 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0726 %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer727 %v = call <vscale x 4 x i64> @llvm.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb)728 ret <vscale x 4 x i64> %v729}730 731define <vscale x 4 x i64> @usub_nxv4i64_vi(<vscale x 4 x i64> %va) {732; CHECK-LABEL: usub_nxv4i64_vi:733; CHECK: # %bb.0:734; CHECK-NEXT: li a0, 2735; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma736; CHECK-NEXT: vssubu.vx v8, v8, a0737; CHECK-NEXT: ret738 %v = call <vscale x 4 x i64> @llvm.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 2))739 ret <vscale x 4 x i64> %v740}741 742define <vscale x 8 x i64> @usub_nxv8i64_vv(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b) {743; CHECK-LABEL: usub_nxv8i64_vv:744; CHECK: # %bb.0:745; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma746; CHECK-NEXT: vssubu.vv v8, v8, v16747; CHECK-NEXT: ret748 %v = call <vscale x 8 x i64> @llvm.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b)749 ret <vscale x 8 x i64> %v750}751 752define <vscale x 8 x i64> @usub_nxv8i64_vx(<vscale x 8 x i64> %va, i64 %b) {753; RV32-LABEL: usub_nxv8i64_vx:754; RV32: # %bb.0:755; RV32-NEXT: addi sp, sp, -16756; RV32-NEXT: .cfi_def_cfa_offset 16757; RV32-NEXT: sw a0, 8(sp)758; RV32-NEXT: sw a1, 12(sp)759; RV32-NEXT: addi a0, sp, 8760; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma761; RV32-NEXT: vlse64.v v16, (a0), zero762; RV32-NEXT: vssubu.vv v8, v8, v16763; RV32-NEXT: addi sp, sp, 16764; RV32-NEXT: .cfi_def_cfa_offset 0765; RV32-NEXT: ret766;767; RV64-LABEL: usub_nxv8i64_vx:768; RV64: # %bb.0:769; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma770; RV64-NEXT: vssubu.vx v8, v8, a0771; RV64-NEXT: ret772 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0773 %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer774 %v = call <vscale x 8 x i64> @llvm.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb)775 ret <vscale x 8 x i64> %v776}777 778define <vscale x 8 x i64> @usub_nxv8i64_vi(<vscale x 8 x i64> %va) {779; CHECK-LABEL: usub_nxv8i64_vi:780; CHECK: # %bb.0:781; CHECK-NEXT: li a0, 2782; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma783; CHECK-NEXT: vssubu.vx v8, v8, a0784; CHECK-NEXT: ret785 %v = call <vscale x 8 x i64> @llvm.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 2))786 ret <vscale x 8 x i64> %v787}788