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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 8 x i7> @vssubu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: vssubu_vx_nxv8i7:9; CHECK:       # %bb.0:10; CHECK-NEXT:    li a2, 12711; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma12; CHECK-NEXT:    vmv.v.x v9, a013; CHECK-NEXT:    vand.vx v8, v8, a214; CHECK-NEXT:    vand.vx v9, v9, a215; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t16; CHECK-NEXT:    ret17  %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 018  %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer19  %v = call <vscale x 8 x i7> @llvm.vp.usub.sat.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)20  ret <vscale x 8 x i7> %v21}22 23define <vscale x 1 x i8> @vssubu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {24; CHECK-LABEL: vssubu_vv_nxv1i8:25; CHECK:       # %bb.0:26; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma27; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t28; CHECK-NEXT:    ret29  %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)30  ret <vscale x 1 x i8> %v31}32 33define <vscale x 1 x i8> @vssubu_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {34; CHECK-LABEL: vssubu_vv_nxv1i8_unmasked:35; CHECK:       # %bb.0:36; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma37; CHECK-NEXT:    vssubu.vv v8, v8, v938; CHECK-NEXT:    ret39  %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)40  ret <vscale x 1 x i8> %v41}42 43define <vscale x 1 x i8> @vssubu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {44; CHECK-LABEL: vssubu_vx_nxv1i8:45; CHECK:       # %bb.0:46; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma47; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t48; CHECK-NEXT:    ret49  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 050  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer51  %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)52  ret <vscale x 1 x i8> %v53}54 55define <vscale x 1 x i8> @vssubu_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {56; CHECK-LABEL: vssubu_vx_nxv1i8_commute:57; CHECK:       # %bb.0:58; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma59; CHECK-NEXT:    vmv.v.x v9, a060; CHECK-NEXT:    vssubu.vv v8, v9, v8, v0.t61; CHECK-NEXT:    ret62  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 063  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer64  %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)65  ret <vscale x 1 x i8> %v66}67 68define <vscale x 1 x i8> @vssubu_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {69; CHECK-LABEL: vssubu_vx_nxv1i8_unmasked:70; CHECK:       # %bb.0:71; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma72; CHECK-NEXT:    vssubu.vx v8, v8, a073; CHECK-NEXT:    ret74  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 075  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer76  %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)77  ret <vscale x 1 x i8> %v78}79 80define <vscale x 1 x i8> @vssubu_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {81; CHECK-LABEL: vssubu_vi_nxv1i8:82; CHECK:       # %bb.0:83; CHECK-NEXT:    li a1, -184; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma85; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t86; CHECK-NEXT:    ret87  %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)88  ret <vscale x 1 x i8> %v89}90 91define <vscale x 1 x i8> @vssubu_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {92; CHECK-LABEL: vssubu_vi_nxv1i8_unmasked:93; CHECK:       # %bb.0:94; CHECK-NEXT:    li a1, -195; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma96; CHECK-NEXT:    vssubu.vx v8, v8, a197; CHECK-NEXT:    ret98  %v = call <vscale x 1 x i8> @llvm.vp.usub.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)99  ret <vscale x 1 x i8> %v100}101 102define <vscale x 2 x i8> @vssubu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {103; CHECK-LABEL: vssubu_vv_nxv2i8:104; CHECK:       # %bb.0:105; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma106; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t107; CHECK-NEXT:    ret108  %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)109  ret <vscale x 2 x i8> %v110}111 112define <vscale x 2 x i8> @vssubu_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {113; CHECK-LABEL: vssubu_vv_nxv2i8_unmasked:114; CHECK:       # %bb.0:115; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma116; CHECK-NEXT:    vssubu.vv v8, v8, v9117; CHECK-NEXT:    ret118  %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)119  ret <vscale x 2 x i8> %v120}121 122define <vscale x 2 x i8> @vssubu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {123; CHECK-LABEL: vssubu_vx_nxv2i8:124; CHECK:       # %bb.0:125; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma126; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t127; CHECK-NEXT:    ret128  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0129  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer130  %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)131  ret <vscale x 2 x i8> %v132}133 134define <vscale x 2 x i8> @vssubu_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {135; CHECK-LABEL: vssubu_vx_nxv2i8_unmasked:136; CHECK:       # %bb.0:137; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma138; CHECK-NEXT:    vssubu.vx v8, v8, a0139; CHECK-NEXT:    ret140  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0141  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer142  %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)143  ret <vscale x 2 x i8> %v144}145 146define <vscale x 2 x i8> @vssubu_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {147; CHECK-LABEL: vssubu_vi_nxv2i8:148; CHECK:       # %bb.0:149; CHECK-NEXT:    li a1, -1150; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma151; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t152; CHECK-NEXT:    ret153  %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)154  ret <vscale x 2 x i8> %v155}156 157define <vscale x 2 x i8> @vssubu_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {158; CHECK-LABEL: vssubu_vi_nxv2i8_unmasked:159; CHECK:       # %bb.0:160; CHECK-NEXT:    li a1, -1161; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma162; CHECK-NEXT:    vssubu.vx v8, v8, a1163; CHECK-NEXT:    ret164  %v = call <vscale x 2 x i8> @llvm.vp.usub.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)165  ret <vscale x 2 x i8> %v166}167 168define <vscale x 3 x i8> @vssubu_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {169; CHECK-LABEL: vssubu_vv_nxv3i8:170; CHECK:       # %bb.0:171; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma172; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t173; CHECK-NEXT:    ret174  %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)175  ret <vscale x 3 x i8> %v176}177 178define <vscale x 3 x i8> @vssubu_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {179; CHECK-LABEL: vssubu_vv_nxv3i8_unmasked:180; CHECK:       # %bb.0:181; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma182; CHECK-NEXT:    vssubu.vv v8, v8, v9183; CHECK-NEXT:    ret184  %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)185  ret <vscale x 3 x i8> %v186}187 188define <vscale x 3 x i8> @vssubu_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {189; CHECK-LABEL: vssubu_vx_nxv3i8:190; CHECK:       # %bb.0:191; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma192; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t193; CHECK-NEXT:    ret194  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0195  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer196  %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl)197  ret <vscale x 3 x i8> %v198}199 200define <vscale x 3 x i8> @vssubu_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {201; CHECK-LABEL: vssubu_vx_nxv3i8_unmasked:202; CHECK:       # %bb.0:203; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma204; CHECK-NEXT:    vssubu.vx v8, v8, a0205; CHECK-NEXT:    ret206  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0207  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer208  %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl)209  ret <vscale x 3 x i8> %v210}211 212define <vscale x 3 x i8> @vssubu_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {213; CHECK-LABEL: vssubu_vi_nxv3i8:214; CHECK:       # %bb.0:215; CHECK-NEXT:    li a1, -1216; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma217; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t218; CHECK-NEXT:    ret219  %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)220  ret <vscale x 3 x i8> %v221}222 223define <vscale x 3 x i8> @vssubu_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {224; CHECK-LABEL: vssubu_vi_nxv3i8_unmasked:225; CHECK:       # %bb.0:226; CHECK-NEXT:    li a1, -1227; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma228; CHECK-NEXT:    vssubu.vx v8, v8, a1229; CHECK-NEXT:    ret230  %v = call <vscale x 3 x i8> @llvm.vp.usub.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)231  ret <vscale x 3 x i8> %v232}233 234define <vscale x 4 x i8> @vssubu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {235; CHECK-LABEL: vssubu_vv_nxv4i8:236; CHECK:       # %bb.0:237; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma238; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t239; CHECK-NEXT:    ret240  %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)241  ret <vscale x 4 x i8> %v242}243 244define <vscale x 4 x i8> @vssubu_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {245; CHECK-LABEL: vssubu_vv_nxv4i8_unmasked:246; CHECK:       # %bb.0:247; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma248; CHECK-NEXT:    vssubu.vv v8, v8, v9249; CHECK-NEXT:    ret250  %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)251  ret <vscale x 4 x i8> %v252}253 254define <vscale x 4 x i8> @vssubu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {255; CHECK-LABEL: vssubu_vx_nxv4i8:256; CHECK:       # %bb.0:257; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma258; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t259; CHECK-NEXT:    ret260  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0261  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer262  %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)263  ret <vscale x 4 x i8> %v264}265 266define <vscale x 4 x i8> @vssubu_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {267; CHECK-LABEL: vssubu_vx_nxv4i8_unmasked:268; CHECK:       # %bb.0:269; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma270; CHECK-NEXT:    vssubu.vx v8, v8, a0271; CHECK-NEXT:    ret272  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0273  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer274  %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)275  ret <vscale x 4 x i8> %v276}277 278define <vscale x 4 x i8> @vssubu_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {279; CHECK-LABEL: vssubu_vi_nxv4i8:280; CHECK:       # %bb.0:281; CHECK-NEXT:    li a1, -1282; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma283; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t284; CHECK-NEXT:    ret285  %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)286  ret <vscale x 4 x i8> %v287}288 289define <vscale x 4 x i8> @vssubu_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {290; CHECK-LABEL: vssubu_vi_nxv4i8_unmasked:291; CHECK:       # %bb.0:292; CHECK-NEXT:    li a1, -1293; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma294; CHECK-NEXT:    vssubu.vx v8, v8, a1295; CHECK-NEXT:    ret296  %v = call <vscale x 4 x i8> @llvm.vp.usub.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)297  ret <vscale x 4 x i8> %v298}299 300define <vscale x 8 x i8> @vssubu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {301; CHECK-LABEL: vssubu_vv_nxv8i8:302; CHECK:       # %bb.0:303; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma304; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t305; CHECK-NEXT:    ret306  %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)307  ret <vscale x 8 x i8> %v308}309 310define <vscale x 8 x i8> @vssubu_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {311; CHECK-LABEL: vssubu_vv_nxv8i8_unmasked:312; CHECK:       # %bb.0:313; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma314; CHECK-NEXT:    vssubu.vv v8, v8, v9315; CHECK-NEXT:    ret316  %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)317  ret <vscale x 8 x i8> %v318}319 320define <vscale x 8 x i8> @vssubu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {321; CHECK-LABEL: vssubu_vx_nxv8i8:322; CHECK:       # %bb.0:323; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma324; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t325; CHECK-NEXT:    ret326  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0327  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer328  %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)329  ret <vscale x 8 x i8> %v330}331 332define <vscale x 8 x i8> @vssubu_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {333; CHECK-LABEL: vssubu_vx_nxv8i8_unmasked:334; CHECK:       # %bb.0:335; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma336; CHECK-NEXT:    vssubu.vx v8, v8, a0337; CHECK-NEXT:    ret338  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0339  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer340  %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)341  ret <vscale x 8 x i8> %v342}343 344define <vscale x 8 x i8> @vssubu_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {345; CHECK-LABEL: vssubu_vi_nxv8i8:346; CHECK:       # %bb.0:347; CHECK-NEXT:    li a1, -1348; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma349; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t350; CHECK-NEXT:    ret351  %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)352  ret <vscale x 8 x i8> %v353}354 355define <vscale x 8 x i8> @vssubu_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {356; CHECK-LABEL: vssubu_vi_nxv8i8_unmasked:357; CHECK:       # %bb.0:358; CHECK-NEXT:    li a1, -1359; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma360; CHECK-NEXT:    vssubu.vx v8, v8, a1361; CHECK-NEXT:    ret362  %v = call <vscale x 8 x i8> @llvm.vp.usub.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)363  ret <vscale x 8 x i8> %v364}365 366define <vscale x 16 x i8> @vssubu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {367; CHECK-LABEL: vssubu_vv_nxv16i8:368; CHECK:       # %bb.0:369; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma370; CHECK-NEXT:    vssubu.vv v8, v8, v10, v0.t371; CHECK-NEXT:    ret372  %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)373  ret <vscale x 16 x i8> %v374}375 376define <vscale x 16 x i8> @vssubu_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {377; CHECK-LABEL: vssubu_vv_nxv16i8_unmasked:378; CHECK:       # %bb.0:379; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma380; CHECK-NEXT:    vssubu.vv v8, v8, v10381; CHECK-NEXT:    ret382  %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)383  ret <vscale x 16 x i8> %v384}385 386define <vscale x 16 x i8> @vssubu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {387; CHECK-LABEL: vssubu_vx_nxv16i8:388; CHECK:       # %bb.0:389; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma390; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t391; CHECK-NEXT:    ret392  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0393  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer394  %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)395  ret <vscale x 16 x i8> %v396}397 398define <vscale x 16 x i8> @vssubu_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {399; CHECK-LABEL: vssubu_vx_nxv16i8_unmasked:400; CHECK:       # %bb.0:401; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma402; CHECK-NEXT:    vssubu.vx v8, v8, a0403; CHECK-NEXT:    ret404  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0405  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer406  %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)407  ret <vscale x 16 x i8> %v408}409 410define <vscale x 16 x i8> @vssubu_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {411; CHECK-LABEL: vssubu_vi_nxv16i8:412; CHECK:       # %bb.0:413; CHECK-NEXT:    li a1, -1414; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma415; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t416; CHECK-NEXT:    ret417  %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)418  ret <vscale x 16 x i8> %v419}420 421define <vscale x 16 x i8> @vssubu_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {422; CHECK-LABEL: vssubu_vi_nxv16i8_unmasked:423; CHECK:       # %bb.0:424; CHECK-NEXT:    li a1, -1425; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma426; CHECK-NEXT:    vssubu.vx v8, v8, a1427; CHECK-NEXT:    ret428  %v = call <vscale x 16 x i8> @llvm.vp.usub.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)429  ret <vscale x 16 x i8> %v430}431 432define <vscale x 32 x i8> @vssubu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {433; CHECK-LABEL: vssubu_vv_nxv32i8:434; CHECK:       # %bb.0:435; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma436; CHECK-NEXT:    vssubu.vv v8, v8, v12, v0.t437; CHECK-NEXT:    ret438  %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)439  ret <vscale x 32 x i8> %v440}441 442define <vscale x 32 x i8> @vssubu_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {443; CHECK-LABEL: vssubu_vv_nxv32i8_unmasked:444; CHECK:       # %bb.0:445; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma446; CHECK-NEXT:    vssubu.vv v8, v8, v12447; CHECK-NEXT:    ret448  %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)449  ret <vscale x 32 x i8> %v450}451 452define <vscale x 32 x i8> @vssubu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {453; CHECK-LABEL: vssubu_vx_nxv32i8:454; CHECK:       # %bb.0:455; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma456; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t457; CHECK-NEXT:    ret458  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0459  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer460  %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)461  ret <vscale x 32 x i8> %v462}463 464define <vscale x 32 x i8> @vssubu_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {465; CHECK-LABEL: vssubu_vx_nxv32i8_unmasked:466; CHECK:       # %bb.0:467; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma468; CHECK-NEXT:    vssubu.vx v8, v8, a0469; CHECK-NEXT:    ret470  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0471  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer472  %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)473  ret <vscale x 32 x i8> %v474}475 476define <vscale x 32 x i8> @vssubu_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {477; CHECK-LABEL: vssubu_vi_nxv32i8:478; CHECK:       # %bb.0:479; CHECK-NEXT:    li a1, -1480; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma481; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t482; CHECK-NEXT:    ret483  %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)484  ret <vscale x 32 x i8> %v485}486 487define <vscale x 32 x i8> @vssubu_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {488; CHECK-LABEL: vssubu_vi_nxv32i8_unmasked:489; CHECK:       # %bb.0:490; CHECK-NEXT:    li a1, -1491; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma492; CHECK-NEXT:    vssubu.vx v8, v8, a1493; CHECK-NEXT:    ret494  %v = call <vscale x 32 x i8> @llvm.vp.usub.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)495  ret <vscale x 32 x i8> %v496}497 498define <vscale x 64 x i8> @vssubu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {499; CHECK-LABEL: vssubu_vv_nxv64i8:500; CHECK:       # %bb.0:501; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma502; CHECK-NEXT:    vssubu.vv v8, v8, v16, v0.t503; CHECK-NEXT:    ret504  %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)505  ret <vscale x 64 x i8> %v506}507 508define <vscale x 64 x i8> @vssubu_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {509; CHECK-LABEL: vssubu_vv_nxv64i8_unmasked:510; CHECK:       # %bb.0:511; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma512; CHECK-NEXT:    vssubu.vv v8, v8, v16513; CHECK-NEXT:    ret514  %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)515  ret <vscale x 64 x i8> %v516}517 518define <vscale x 64 x i8> @vssubu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {519; CHECK-LABEL: vssubu_vx_nxv64i8:520; CHECK:       # %bb.0:521; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma522; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t523; CHECK-NEXT:    ret524  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0525  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer526  %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)527  ret <vscale x 64 x i8> %v528}529 530define <vscale x 64 x i8> @vssubu_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {531; CHECK-LABEL: vssubu_vx_nxv64i8_unmasked:532; CHECK:       # %bb.0:533; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma534; CHECK-NEXT:    vssubu.vx v8, v8, a0535; CHECK-NEXT:    ret536  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0537  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer538  %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)539  ret <vscale x 64 x i8> %v540}541 542define <vscale x 64 x i8> @vssubu_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {543; CHECK-LABEL: vssubu_vi_nxv64i8:544; CHECK:       # %bb.0:545; CHECK-NEXT:    li a1, -1546; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma547; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t548; CHECK-NEXT:    ret549  %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)550  ret <vscale x 64 x i8> %v551}552 553define <vscale x 64 x i8> @vssubu_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {554; CHECK-LABEL: vssubu_vi_nxv64i8_unmasked:555; CHECK:       # %bb.0:556; CHECK-NEXT:    li a1, -1557; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma558; CHECK-NEXT:    vssubu.vx v8, v8, a1559; CHECK-NEXT:    ret560  %v = call <vscale x 64 x i8> @llvm.vp.usub.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)561  ret <vscale x 64 x i8> %v562}563 564; Test that split-legalization works when the mask itself needs splitting.565 566define <vscale x 128 x i8> @vssubu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {567; CHECK-LABEL: vssubu_vi_nxv128i8:568; CHECK:       # %bb.0:569; CHECK-NEXT:    vsetvli a2, zero, e8, m8, ta, ma570; CHECK-NEXT:    vmv1r.v v24, v0571; CHECK-NEXT:    vlm.v v0, (a0)572; CHECK-NEXT:    csrr a0, vlenb573; CHECK-NEXT:    slli a0, a0, 3574; CHECK-NEXT:    sub a2, a1, a0575; CHECK-NEXT:    sltu a3, a1, a2576; CHECK-NEXT:    addi a3, a3, -1577; CHECK-NEXT:    and a3, a3, a2578; CHECK-NEXT:    li a2, -1579; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma580; CHECK-NEXT:    vssubu.vx v16, v16, a2, v0.t581; CHECK-NEXT:    bltu a1, a0, .LBB50_2582; CHECK-NEXT:  # %bb.1:583; CHECK-NEXT:    mv a1, a0584; CHECK-NEXT:  .LBB50_2:585; CHECK-NEXT:    vmv1r.v v0, v24586; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma587; CHECK-NEXT:    vssubu.vx v8, v8, a2, v0.t588; CHECK-NEXT:    ret589  %v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)590  ret <vscale x 128 x i8> %v591}592 593define <vscale x 128 x i8> @vssubu_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {594; CHECK-LABEL: vssubu_vi_nxv128i8_unmasked:595; CHECK:       # %bb.0:596; CHECK-NEXT:    csrr a1, vlenb597; CHECK-NEXT:    slli a1, a1, 3598; CHECK-NEXT:    sub a2, a0, a1599; CHECK-NEXT:    sltu a3, a0, a2600; CHECK-NEXT:    addi a3, a3, -1601; CHECK-NEXT:    and a3, a3, a2602; CHECK-NEXT:    li a2, -1603; CHECK-NEXT:    vsetvli zero, a3, e8, m8, ta, ma604; CHECK-NEXT:    vssubu.vx v16, v16, a2605; CHECK-NEXT:    bltu a0, a1, .LBB51_2606; CHECK-NEXT:  # %bb.1:607; CHECK-NEXT:    mv a0, a1608; CHECK-NEXT:  .LBB51_2:609; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma610; CHECK-NEXT:    vssubu.vx v8, v8, a2611; CHECK-NEXT:    ret612  %v = call <vscale x 128 x i8> @llvm.vp.usub.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)613  ret <vscale x 128 x i8> %v614}615 616define <vscale x 1 x i16> @vssubu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {617; CHECK-LABEL: vssubu_vv_nxv1i16:618; CHECK:       # %bb.0:619; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma620; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t621; CHECK-NEXT:    ret622  %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)623  ret <vscale x 1 x i16> %v624}625 626define <vscale x 1 x i16> @vssubu_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {627; CHECK-LABEL: vssubu_vv_nxv1i16_unmasked:628; CHECK:       # %bb.0:629; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma630; CHECK-NEXT:    vssubu.vv v8, v8, v9631; CHECK-NEXT:    ret632  %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)633  ret <vscale x 1 x i16> %v634}635 636define <vscale x 1 x i16> @vssubu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {637; CHECK-LABEL: vssubu_vx_nxv1i16:638; CHECK:       # %bb.0:639; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma640; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t641; CHECK-NEXT:    ret642  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0643  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer644  %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)645  ret <vscale x 1 x i16> %v646}647 648define <vscale x 1 x i16> @vssubu_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {649; CHECK-LABEL: vssubu_vx_nxv1i16_unmasked:650; CHECK:       # %bb.0:651; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma652; CHECK-NEXT:    vssubu.vx v8, v8, a0653; CHECK-NEXT:    ret654  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0655  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer656  %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)657  ret <vscale x 1 x i16> %v658}659 660define <vscale x 1 x i16> @vssubu_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {661; CHECK-LABEL: vssubu_vi_nxv1i16:662; CHECK:       # %bb.0:663; CHECK-NEXT:    li a1, -1664; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma665; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t666; CHECK-NEXT:    ret667  %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)668  ret <vscale x 1 x i16> %v669}670 671define <vscale x 1 x i16> @vssubu_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {672; CHECK-LABEL: vssubu_vi_nxv1i16_unmasked:673; CHECK:       # %bb.0:674; CHECK-NEXT:    li a1, -1675; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma676; CHECK-NEXT:    vssubu.vx v8, v8, a1677; CHECK-NEXT:    ret678  %v = call <vscale x 1 x i16> @llvm.vp.usub.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)679  ret <vscale x 1 x i16> %v680}681 682define <vscale x 2 x i16> @vssubu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {683; CHECK-LABEL: vssubu_vv_nxv2i16:684; CHECK:       # %bb.0:685; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma686; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t687; CHECK-NEXT:    ret688  %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)689  ret <vscale x 2 x i16> %v690}691 692define <vscale x 2 x i16> @vssubu_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {693; CHECK-LABEL: vssubu_vv_nxv2i16_unmasked:694; CHECK:       # %bb.0:695; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma696; CHECK-NEXT:    vssubu.vv v8, v8, v9697; CHECK-NEXT:    ret698  %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)699  ret <vscale x 2 x i16> %v700}701 702define <vscale x 2 x i16> @vssubu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {703; CHECK-LABEL: vssubu_vx_nxv2i16:704; CHECK:       # %bb.0:705; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma706; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t707; CHECK-NEXT:    ret708  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0709  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer710  %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)711  ret <vscale x 2 x i16> %v712}713 714define <vscale x 2 x i16> @vssubu_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {715; CHECK-LABEL: vssubu_vx_nxv2i16_unmasked:716; CHECK:       # %bb.0:717; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma718; CHECK-NEXT:    vssubu.vx v8, v8, a0719; CHECK-NEXT:    ret720  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0721  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer722  %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)723  ret <vscale x 2 x i16> %v724}725 726define <vscale x 2 x i16> @vssubu_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {727; CHECK-LABEL: vssubu_vi_nxv2i16:728; CHECK:       # %bb.0:729; CHECK-NEXT:    li a1, -1730; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma731; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t732; CHECK-NEXT:    ret733  %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)734  ret <vscale x 2 x i16> %v735}736 737define <vscale x 2 x i16> @vssubu_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {738; CHECK-LABEL: vssubu_vi_nxv2i16_unmasked:739; CHECK:       # %bb.0:740; CHECK-NEXT:    li a1, -1741; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma742; CHECK-NEXT:    vssubu.vx v8, v8, a1743; CHECK-NEXT:    ret744  %v = call <vscale x 2 x i16> @llvm.vp.usub.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)745  ret <vscale x 2 x i16> %v746}747 748define <vscale x 4 x i16> @vssubu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {749; CHECK-LABEL: vssubu_vv_nxv4i16:750; CHECK:       # %bb.0:751; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma752; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t753; CHECK-NEXT:    ret754  %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)755  ret <vscale x 4 x i16> %v756}757 758define <vscale x 4 x i16> @vssubu_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {759; CHECK-LABEL: vssubu_vv_nxv4i16_unmasked:760; CHECK:       # %bb.0:761; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma762; CHECK-NEXT:    vssubu.vv v8, v8, v9763; CHECK-NEXT:    ret764  %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)765  ret <vscale x 4 x i16> %v766}767 768define <vscale x 4 x i16> @vssubu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {769; CHECK-LABEL: vssubu_vx_nxv4i16:770; CHECK:       # %bb.0:771; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma772; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t773; CHECK-NEXT:    ret774  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0775  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer776  %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)777  ret <vscale x 4 x i16> %v778}779 780define <vscale x 4 x i16> @vssubu_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {781; CHECK-LABEL: vssubu_vx_nxv4i16_unmasked:782; CHECK:       # %bb.0:783; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma784; CHECK-NEXT:    vssubu.vx v8, v8, a0785; CHECK-NEXT:    ret786  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0787  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer788  %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)789  ret <vscale x 4 x i16> %v790}791 792define <vscale x 4 x i16> @vssubu_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {793; CHECK-LABEL: vssubu_vi_nxv4i16:794; CHECK:       # %bb.0:795; CHECK-NEXT:    li a1, -1796; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma797; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t798; CHECK-NEXT:    ret799  %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)800  ret <vscale x 4 x i16> %v801}802 803define <vscale x 4 x i16> @vssubu_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {804; CHECK-LABEL: vssubu_vi_nxv4i16_unmasked:805; CHECK:       # %bb.0:806; CHECK-NEXT:    li a1, -1807; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma808; CHECK-NEXT:    vssubu.vx v8, v8, a1809; CHECK-NEXT:    ret810  %v = call <vscale x 4 x i16> @llvm.vp.usub.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)811  ret <vscale x 4 x i16> %v812}813 814define <vscale x 8 x i16> @vssubu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {815; CHECK-LABEL: vssubu_vv_nxv8i16:816; CHECK:       # %bb.0:817; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma818; CHECK-NEXT:    vssubu.vv v8, v8, v10, v0.t819; CHECK-NEXT:    ret820  %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)821  ret <vscale x 8 x i16> %v822}823 824define <vscale x 8 x i16> @vssubu_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {825; CHECK-LABEL: vssubu_vv_nxv8i16_unmasked:826; CHECK:       # %bb.0:827; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma828; CHECK-NEXT:    vssubu.vv v8, v8, v10829; CHECK-NEXT:    ret830  %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)831  ret <vscale x 8 x i16> %v832}833 834define <vscale x 8 x i16> @vssubu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {835; CHECK-LABEL: vssubu_vx_nxv8i16:836; CHECK:       # %bb.0:837; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma838; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t839; CHECK-NEXT:    ret840  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0841  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer842  %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)843  ret <vscale x 8 x i16> %v844}845 846define <vscale x 8 x i16> @vssubu_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {847; CHECK-LABEL: vssubu_vx_nxv8i16_unmasked:848; CHECK:       # %bb.0:849; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma850; CHECK-NEXT:    vssubu.vx v8, v8, a0851; CHECK-NEXT:    ret852  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0853  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer854  %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)855  ret <vscale x 8 x i16> %v856}857 858define <vscale x 8 x i16> @vssubu_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {859; CHECK-LABEL: vssubu_vi_nxv8i16:860; CHECK:       # %bb.0:861; CHECK-NEXT:    li a1, -1862; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma863; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t864; CHECK-NEXT:    ret865  %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)866  ret <vscale x 8 x i16> %v867}868 869define <vscale x 8 x i16> @vssubu_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {870; CHECK-LABEL: vssubu_vi_nxv8i16_unmasked:871; CHECK:       # %bb.0:872; CHECK-NEXT:    li a1, -1873; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma874; CHECK-NEXT:    vssubu.vx v8, v8, a1875; CHECK-NEXT:    ret876  %v = call <vscale x 8 x i16> @llvm.vp.usub.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)877  ret <vscale x 8 x i16> %v878}879 880define <vscale x 16 x i16> @vssubu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {881; CHECK-LABEL: vssubu_vv_nxv16i16:882; CHECK:       # %bb.0:883; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma884; CHECK-NEXT:    vssubu.vv v8, v8, v12, v0.t885; CHECK-NEXT:    ret886  %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)887  ret <vscale x 16 x i16> %v888}889 890define <vscale x 16 x i16> @vssubu_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {891; CHECK-LABEL: vssubu_vv_nxv16i16_unmasked:892; CHECK:       # %bb.0:893; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma894; CHECK-NEXT:    vssubu.vv v8, v8, v12895; CHECK-NEXT:    ret896  %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)897  ret <vscale x 16 x i16> %v898}899 900define <vscale x 16 x i16> @vssubu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {901; CHECK-LABEL: vssubu_vx_nxv16i16:902; CHECK:       # %bb.0:903; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma904; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t905; CHECK-NEXT:    ret906  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0907  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer908  %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)909  ret <vscale x 16 x i16> %v910}911 912define <vscale x 16 x i16> @vssubu_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {913; CHECK-LABEL: vssubu_vx_nxv16i16_unmasked:914; CHECK:       # %bb.0:915; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma916; CHECK-NEXT:    vssubu.vx v8, v8, a0917; CHECK-NEXT:    ret918  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0919  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer920  %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)921  ret <vscale x 16 x i16> %v922}923 924define <vscale x 16 x i16> @vssubu_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {925; CHECK-LABEL: vssubu_vi_nxv16i16:926; CHECK:       # %bb.0:927; CHECK-NEXT:    li a1, -1928; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma929; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t930; CHECK-NEXT:    ret931  %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)932  ret <vscale x 16 x i16> %v933}934 935define <vscale x 16 x i16> @vssubu_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {936; CHECK-LABEL: vssubu_vi_nxv16i16_unmasked:937; CHECK:       # %bb.0:938; CHECK-NEXT:    li a1, -1939; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma940; CHECK-NEXT:    vssubu.vx v8, v8, a1941; CHECK-NEXT:    ret942  %v = call <vscale x 16 x i16> @llvm.vp.usub.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)943  ret <vscale x 16 x i16> %v944}945 946define <vscale x 32 x i16> @vssubu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {947; CHECK-LABEL: vssubu_vv_nxv32i16:948; CHECK:       # %bb.0:949; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma950; CHECK-NEXT:    vssubu.vv v8, v8, v16, v0.t951; CHECK-NEXT:    ret952  %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)953  ret <vscale x 32 x i16> %v954}955 956define <vscale x 32 x i16> @vssubu_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {957; CHECK-LABEL: vssubu_vv_nxv32i16_unmasked:958; CHECK:       # %bb.0:959; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma960; CHECK-NEXT:    vssubu.vv v8, v8, v16961; CHECK-NEXT:    ret962  %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)963  ret <vscale x 32 x i16> %v964}965 966define <vscale x 32 x i16> @vssubu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {967; CHECK-LABEL: vssubu_vx_nxv32i16:968; CHECK:       # %bb.0:969; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma970; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t971; CHECK-NEXT:    ret972  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0973  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer974  %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)975  ret <vscale x 32 x i16> %v976}977 978define <vscale x 32 x i16> @vssubu_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {979; CHECK-LABEL: vssubu_vx_nxv32i16_unmasked:980; CHECK:       # %bb.0:981; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma982; CHECK-NEXT:    vssubu.vx v8, v8, a0983; CHECK-NEXT:    ret984  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0985  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer986  %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)987  ret <vscale x 32 x i16> %v988}989 990define <vscale x 32 x i16> @vssubu_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {991; CHECK-LABEL: vssubu_vi_nxv32i16:992; CHECK:       # %bb.0:993; CHECK-NEXT:    li a1, -1994; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma995; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t996; CHECK-NEXT:    ret997  %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)998  ret <vscale x 32 x i16> %v999}1000 1001define <vscale x 32 x i16> @vssubu_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {1002; CHECK-LABEL: vssubu_vi_nxv32i16_unmasked:1003; CHECK:       # %bb.0:1004; CHECK-NEXT:    li a1, -11005; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1006; CHECK-NEXT:    vssubu.vx v8, v8, a11007; CHECK-NEXT:    ret1008  %v = call <vscale x 32 x i16> @llvm.vp.usub.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1009  ret <vscale x 32 x i16> %v1010}1011 1012define <vscale x 1 x i32> @vssubu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1013; CHECK-LABEL: vssubu_vv_nxv1i32:1014; CHECK:       # %bb.0:1015; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1016; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t1017; CHECK-NEXT:    ret1018  %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)1019  ret <vscale x 1 x i32> %v1020}1021 1022define <vscale x 1 x i32> @vssubu_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {1023; CHECK-LABEL: vssubu_vv_nxv1i32_unmasked:1024; CHECK:       # %bb.0:1025; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1026; CHECK-NEXT:    vssubu.vv v8, v8, v91027; CHECK-NEXT:    ret1028  %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1029  ret <vscale x 1 x i32> %v1030}1031 1032define <vscale x 1 x i32> @vssubu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1033; CHECK-LABEL: vssubu_vx_nxv1i32:1034; CHECK:       # %bb.0:1035; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1036; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t1037; CHECK-NEXT:    ret1038  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01039  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1040  %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)1041  ret <vscale x 1 x i32> %v1042}1043 1044define <vscale x 1 x i32> @vssubu_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {1045; CHECK-LABEL: vssubu_vx_nxv1i32_unmasked:1046; CHECK:       # %bb.0:1047; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1048; CHECK-NEXT:    vssubu.vx v8, v8, a01049; CHECK-NEXT:    ret1050  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01051  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1052  %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1053  ret <vscale x 1 x i32> %v1054}1055 1056define <vscale x 1 x i32> @vssubu_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1057; CHECK-LABEL: vssubu_vi_nxv1i32:1058; CHECK:       # %bb.0:1059; CHECK-NEXT:    li a1, -11060; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1061; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1062; CHECK-NEXT:    ret1063  %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)1064  ret <vscale x 1 x i32> %v1065}1066 1067define <vscale x 1 x i32> @vssubu_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {1068; CHECK-LABEL: vssubu_vi_nxv1i32_unmasked:1069; CHECK:       # %bb.0:1070; CHECK-NEXT:    li a1, -11071; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1072; CHECK-NEXT:    vssubu.vx v8, v8, a11073; CHECK-NEXT:    ret1074  %v = call <vscale x 1 x i32> @llvm.vp.usub.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1075  ret <vscale x 1 x i32> %v1076}1077 1078define <vscale x 2 x i32> @vssubu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1079; CHECK-LABEL: vssubu_vv_nxv2i32:1080; CHECK:       # %bb.0:1081; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1082; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t1083; CHECK-NEXT:    ret1084  %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)1085  ret <vscale x 2 x i32> %v1086}1087 1088define <vscale x 2 x i32> @vssubu_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {1089; CHECK-LABEL: vssubu_vv_nxv2i32_unmasked:1090; CHECK:       # %bb.0:1091; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1092; CHECK-NEXT:    vssubu.vv v8, v8, v91093; CHECK-NEXT:    ret1094  %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1095  ret <vscale x 2 x i32> %v1096}1097 1098define <vscale x 2 x i32> @vssubu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1099; CHECK-LABEL: vssubu_vx_nxv2i32:1100; CHECK:       # %bb.0:1101; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1102; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t1103; CHECK-NEXT:    ret1104  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01105  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1106  %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)1107  ret <vscale x 2 x i32> %v1108}1109 1110define <vscale x 2 x i32> @vssubu_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {1111; CHECK-LABEL: vssubu_vx_nxv2i32_unmasked:1112; CHECK:       # %bb.0:1113; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1114; CHECK-NEXT:    vssubu.vx v8, v8, a01115; CHECK-NEXT:    ret1116  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01117  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1118  %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1119  ret <vscale x 2 x i32> %v1120}1121 1122define <vscale x 2 x i32> @vssubu_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1123; CHECK-LABEL: vssubu_vi_nxv2i32:1124; CHECK:       # %bb.0:1125; CHECK-NEXT:    li a1, -11126; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1127; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1128; CHECK-NEXT:    ret1129  %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)1130  ret <vscale x 2 x i32> %v1131}1132 1133define <vscale x 2 x i32> @vssubu_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {1134; CHECK-LABEL: vssubu_vi_nxv2i32_unmasked:1135; CHECK:       # %bb.0:1136; CHECK-NEXT:    li a1, -11137; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1138; CHECK-NEXT:    vssubu.vx v8, v8, a11139; CHECK-NEXT:    ret1140  %v = call <vscale x 2 x i32> @llvm.vp.usub.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1141  ret <vscale x 2 x i32> %v1142}1143 1144define <vscale x 4 x i32> @vssubu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1145; CHECK-LABEL: vssubu_vv_nxv4i32:1146; CHECK:       # %bb.0:1147; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1148; CHECK-NEXT:    vssubu.vv v8, v8, v10, v0.t1149; CHECK-NEXT:    ret1150  %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)1151  ret <vscale x 4 x i32> %v1152}1153 1154define <vscale x 4 x i32> @vssubu_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {1155; CHECK-LABEL: vssubu_vv_nxv4i32_unmasked:1156; CHECK:       # %bb.0:1157; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1158; CHECK-NEXT:    vssubu.vv v8, v8, v101159; CHECK-NEXT:    ret1160  %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1161  ret <vscale x 4 x i32> %v1162}1163 1164define <vscale x 4 x i32> @vssubu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1165; CHECK-LABEL: vssubu_vx_nxv4i32:1166; CHECK:       # %bb.0:1167; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1168; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t1169; CHECK-NEXT:    ret1170  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01171  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1172  %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)1173  ret <vscale x 4 x i32> %v1174}1175 1176define <vscale x 4 x i32> @vssubu_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {1177; CHECK-LABEL: vssubu_vx_nxv4i32_unmasked:1178; CHECK:       # %bb.0:1179; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1180; CHECK-NEXT:    vssubu.vx v8, v8, a01181; CHECK-NEXT:    ret1182  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01183  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1184  %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1185  ret <vscale x 4 x i32> %v1186}1187 1188define <vscale x 4 x i32> @vssubu_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1189; CHECK-LABEL: vssubu_vi_nxv4i32:1190; CHECK:       # %bb.0:1191; CHECK-NEXT:    li a1, -11192; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1193; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1194; CHECK-NEXT:    ret1195  %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)1196  ret <vscale x 4 x i32> %v1197}1198 1199define <vscale x 4 x i32> @vssubu_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1200; CHECK-LABEL: vssubu_vi_nxv4i32_unmasked:1201; CHECK:       # %bb.0:1202; CHECK-NEXT:    li a1, -11203; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1204; CHECK-NEXT:    vssubu.vx v8, v8, a11205; CHECK-NEXT:    ret1206  %v = call <vscale x 4 x i32> @llvm.vp.usub.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1207  ret <vscale x 4 x i32> %v1208}1209 1210define <vscale x 8 x i32> @vssubu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1211; CHECK-LABEL: vssubu_vv_nxv8i32:1212; CHECK:       # %bb.0:1213; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1214; CHECK-NEXT:    vssubu.vv v8, v8, v12, v0.t1215; CHECK-NEXT:    ret1216  %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)1217  ret <vscale x 8 x i32> %v1218}1219 1220define <vscale x 8 x i32> @vssubu_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {1221; CHECK-LABEL: vssubu_vv_nxv8i32_unmasked:1222; CHECK:       # %bb.0:1223; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1224; CHECK-NEXT:    vssubu.vv v8, v8, v121225; CHECK-NEXT:    ret1226  %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1227  ret <vscale x 8 x i32> %v1228}1229 1230define <vscale x 8 x i32> @vssubu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1231; CHECK-LABEL: vssubu_vx_nxv8i32:1232; CHECK:       # %bb.0:1233; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1234; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t1235; CHECK-NEXT:    ret1236  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01237  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1238  %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)1239  ret <vscale x 8 x i32> %v1240}1241 1242define <vscale x 8 x i32> @vssubu_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {1243; CHECK-LABEL: vssubu_vx_nxv8i32_unmasked:1244; CHECK:       # %bb.0:1245; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1246; CHECK-NEXT:    vssubu.vx v8, v8, a01247; CHECK-NEXT:    ret1248  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01249  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1250  %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1251  ret <vscale x 8 x i32> %v1252}1253 1254define <vscale x 8 x i32> @vssubu_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1255; CHECK-LABEL: vssubu_vi_nxv8i32:1256; CHECK:       # %bb.0:1257; CHECK-NEXT:    li a1, -11258; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1259; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1260; CHECK-NEXT:    ret1261  %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)1262  ret <vscale x 8 x i32> %v1263}1264 1265define <vscale x 8 x i32> @vssubu_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1266; CHECK-LABEL: vssubu_vi_nxv8i32_unmasked:1267; CHECK:       # %bb.0:1268; CHECK-NEXT:    li a1, -11269; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1270; CHECK-NEXT:    vssubu.vx v8, v8, a11271; CHECK-NEXT:    ret1272  %v = call <vscale x 8 x i32> @llvm.vp.usub.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1273  ret <vscale x 8 x i32> %v1274}1275 1276define <vscale x 16 x i32> @vssubu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1277; CHECK-LABEL: vssubu_vv_nxv16i32:1278; CHECK:       # %bb.0:1279; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1280; CHECK-NEXT:    vssubu.vv v8, v8, v16, v0.t1281; CHECK-NEXT:    ret1282  %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)1283  ret <vscale x 16 x i32> %v1284}1285 1286define <vscale x 16 x i32> @vssubu_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {1287; CHECK-LABEL: vssubu_vv_nxv16i32_unmasked:1288; CHECK:       # %bb.0:1289; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1290; CHECK-NEXT:    vssubu.vv v8, v8, v161291; CHECK-NEXT:    ret1292  %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1293  ret <vscale x 16 x i32> %v1294}1295 1296define <vscale x 16 x i32> @vssubu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1297; CHECK-LABEL: vssubu_vx_nxv16i32:1298; CHECK:       # %bb.0:1299; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1300; CHECK-NEXT:    vssubu.vx v8, v8, a0, v0.t1301; CHECK-NEXT:    ret1302  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01303  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1304  %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)1305  ret <vscale x 16 x i32> %v1306}1307 1308define <vscale x 16 x i32> @vssubu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {1309; CHECK-LABEL: vssubu_vx_nxv16i32_unmasked:1310; CHECK:       # %bb.0:1311; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1312; CHECK-NEXT:    vssubu.vx v8, v8, a01313; CHECK-NEXT:    ret1314  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01315  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1316  %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1317  ret <vscale x 16 x i32> %v1318}1319 1320define <vscale x 16 x i32> @vssubu_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1321; CHECK-LABEL: vssubu_vi_nxv16i32:1322; CHECK:       # %bb.0:1323; CHECK-NEXT:    li a1, -11324; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1325; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1326; CHECK-NEXT:    ret1327  %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)1328  ret <vscale x 16 x i32> %v1329}1330 1331define <vscale x 16 x i32> @vssubu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1332; CHECK-LABEL: vssubu_vi_nxv16i32_unmasked:1333; CHECK:       # %bb.0:1334; CHECK-NEXT:    li a1, -11335; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1336; CHECK-NEXT:    vssubu.vx v8, v8, a11337; CHECK-NEXT:    ret1338  %v = call <vscale x 16 x i32> @llvm.vp.usub.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)1339  ret <vscale x 16 x i32> %v1340}1341 1342; Test that split-legalization works then the mask needs manual splitting.1343 1344define <vscale x 32 x i32> @vssubu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {1345; CHECK-LABEL: vssubu_vi_nxv32i32:1346; CHECK:       # %bb.0:1347; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma1348; CHECK-NEXT:    vmv1r.v v24, v01349; CHECK-NEXT:    csrr a1, vlenb1350; CHECK-NEXT:    srli a2, a1, 21351; CHECK-NEXT:    slli a1, a1, 11352; CHECK-NEXT:    vslidedown.vx v0, v0, a21353; CHECK-NEXT:    sub a2, a0, a11354; CHECK-NEXT:    sltu a3, a0, a21355; CHECK-NEXT:    addi a3, a3, -11356; CHECK-NEXT:    and a3, a3, a21357; CHECK-NEXT:    li a2, -11358; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma1359; CHECK-NEXT:    vssubu.vx v16, v16, a2, v0.t1360; CHECK-NEXT:    bltu a0, a1, .LBB118_21361; CHECK-NEXT:  # %bb.1:1362; CHECK-NEXT:    mv a0, a11363; CHECK-NEXT:  .LBB118_2:1364; CHECK-NEXT:    vmv1r.v v0, v241365; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1366; CHECK-NEXT:    vssubu.vx v8, v8, a2, v0.t1367; CHECK-NEXT:    ret1368  %v = call <vscale x 32 x i32> @llvm.vp.usub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)1369  ret <vscale x 32 x i32> %v1370}1371 1372define <vscale x 32 x i32> @vssubu_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {1373; CHECK-LABEL: vssubu_vi_nxv32i32_unmasked:1374; CHECK:       # %bb.0:1375; CHECK-NEXT:    csrr a1, vlenb1376; CHECK-NEXT:    slli a1, a1, 11377; CHECK-NEXT:    sub a2, a0, a11378; CHECK-NEXT:    sltu a3, a0, a21379; CHECK-NEXT:    addi a3, a3, -11380; CHECK-NEXT:    and a3, a3, a21381; CHECK-NEXT:    li a2, -11382; CHECK-NEXT:    vsetvli zero, a3, e32, m8, ta, ma1383; CHECK-NEXT:    vssubu.vx v16, v16, a21384; CHECK-NEXT:    bltu a0, a1, .LBB119_21385; CHECK-NEXT:  # %bb.1:1386; CHECK-NEXT:    mv a0, a11387; CHECK-NEXT:  .LBB119_2:1388; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1389; CHECK-NEXT:    vssubu.vx v8, v8, a21390; CHECK-NEXT:    ret1391  %v = call <vscale x 32 x i32> @llvm.vp.usub.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1392  ret <vscale x 32 x i32> %v1393}1394 1395define <vscale x 1 x i64> @vssubu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1396; CHECK-LABEL: vssubu_vv_nxv1i64:1397; CHECK:       # %bb.0:1398; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1399; CHECK-NEXT:    vssubu.vv v8, v8, v9, v0.t1400; CHECK-NEXT:    ret1401  %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)1402  ret <vscale x 1 x i64> %v1403}1404 1405define <vscale x 1 x i64> @vssubu_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {1406; CHECK-LABEL: vssubu_vv_nxv1i64_unmasked:1407; CHECK:       # %bb.0:1408; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1409; CHECK-NEXT:    vssubu.vv v8, v8, v91410; CHECK-NEXT:    ret1411  %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1412  ret <vscale x 1 x i64> %v1413}1414 1415define <vscale x 1 x i64> @vssubu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1416; RV32-LABEL: vssubu_vx_nxv1i64:1417; RV32:       # %bb.0:1418; RV32-NEXT:    addi sp, sp, -161419; RV32-NEXT:    .cfi_def_cfa_offset 161420; RV32-NEXT:    sw a0, 8(sp)1421; RV32-NEXT:    sw a1, 12(sp)1422; RV32-NEXT:    addi a0, sp, 81423; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1424; RV32-NEXT:    vlse64.v v9, (a0), zero1425; RV32-NEXT:    vssubu.vv v8, v8, v9, v0.t1426; RV32-NEXT:    addi sp, sp, 161427; RV32-NEXT:    .cfi_def_cfa_offset 01428; RV32-NEXT:    ret1429;1430; RV64-LABEL: vssubu_vx_nxv1i64:1431; RV64:       # %bb.0:1432; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1433; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t1434; RV64-NEXT:    ret1435  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01436  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1437  %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)1438  ret <vscale x 1 x i64> %v1439}1440 1441define <vscale x 1 x i64> @vssubu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {1442; RV32-LABEL: vssubu_vx_nxv1i64_unmasked:1443; RV32:       # %bb.0:1444; RV32-NEXT:    addi sp, sp, -161445; RV32-NEXT:    .cfi_def_cfa_offset 161446; RV32-NEXT:    sw a0, 8(sp)1447; RV32-NEXT:    sw a1, 12(sp)1448; RV32-NEXT:    addi a0, sp, 81449; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1450; RV32-NEXT:    vlse64.v v9, (a0), zero1451; RV32-NEXT:    vssubu.vv v8, v8, v91452; RV32-NEXT:    addi sp, sp, 161453; RV32-NEXT:    .cfi_def_cfa_offset 01454; RV32-NEXT:    ret1455;1456; RV64-LABEL: vssubu_vx_nxv1i64_unmasked:1457; RV64:       # %bb.0:1458; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1459; RV64-NEXT:    vssubu.vx v8, v8, a01460; RV64-NEXT:    ret1461  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01462  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1463  %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1464  ret <vscale x 1 x i64> %v1465}1466 1467define <vscale x 1 x i64> @vssubu_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1468; CHECK-LABEL: vssubu_vi_nxv1i64:1469; CHECK:       # %bb.0:1470; CHECK-NEXT:    li a1, -11471; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1472; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1473; CHECK-NEXT:    ret1474  %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)1475  ret <vscale x 1 x i64> %v1476}1477 1478define <vscale x 1 x i64> @vssubu_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1479; CHECK-LABEL: vssubu_vi_nxv1i64_unmasked:1480; CHECK:       # %bb.0:1481; CHECK-NEXT:    li a1, -11482; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1483; CHECK-NEXT:    vssubu.vx v8, v8, a11484; CHECK-NEXT:    ret1485  %v = call <vscale x 1 x i64> @llvm.vp.usub.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1486  ret <vscale x 1 x i64> %v1487}1488 1489define <vscale x 2 x i64> @vssubu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1490; CHECK-LABEL: vssubu_vv_nxv2i64:1491; CHECK:       # %bb.0:1492; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1493; CHECK-NEXT:    vssubu.vv v8, v8, v10, v0.t1494; CHECK-NEXT:    ret1495  %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)1496  ret <vscale x 2 x i64> %v1497}1498 1499define <vscale x 2 x i64> @vssubu_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {1500; CHECK-LABEL: vssubu_vv_nxv2i64_unmasked:1501; CHECK:       # %bb.0:1502; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1503; CHECK-NEXT:    vssubu.vv v8, v8, v101504; CHECK-NEXT:    ret1505  %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1506  ret <vscale x 2 x i64> %v1507}1508 1509define <vscale x 2 x i64> @vssubu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1510; RV32-LABEL: vssubu_vx_nxv2i64:1511; RV32:       # %bb.0:1512; RV32-NEXT:    addi sp, sp, -161513; RV32-NEXT:    .cfi_def_cfa_offset 161514; RV32-NEXT:    sw a0, 8(sp)1515; RV32-NEXT:    sw a1, 12(sp)1516; RV32-NEXT:    addi a0, sp, 81517; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1518; RV32-NEXT:    vlse64.v v10, (a0), zero1519; RV32-NEXT:    vssubu.vv v8, v8, v10, v0.t1520; RV32-NEXT:    addi sp, sp, 161521; RV32-NEXT:    .cfi_def_cfa_offset 01522; RV32-NEXT:    ret1523;1524; RV64-LABEL: vssubu_vx_nxv2i64:1525; RV64:       # %bb.0:1526; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1527; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t1528; RV64-NEXT:    ret1529  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01530  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1531  %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)1532  ret <vscale x 2 x i64> %v1533}1534 1535define <vscale x 2 x i64> @vssubu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {1536; RV32-LABEL: vssubu_vx_nxv2i64_unmasked:1537; RV32:       # %bb.0:1538; RV32-NEXT:    addi sp, sp, -161539; RV32-NEXT:    .cfi_def_cfa_offset 161540; RV32-NEXT:    sw a0, 8(sp)1541; RV32-NEXT:    sw a1, 12(sp)1542; RV32-NEXT:    addi a0, sp, 81543; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1544; RV32-NEXT:    vlse64.v v10, (a0), zero1545; RV32-NEXT:    vssubu.vv v8, v8, v101546; RV32-NEXT:    addi sp, sp, 161547; RV32-NEXT:    .cfi_def_cfa_offset 01548; RV32-NEXT:    ret1549;1550; RV64-LABEL: vssubu_vx_nxv2i64_unmasked:1551; RV64:       # %bb.0:1552; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1553; RV64-NEXT:    vssubu.vx v8, v8, a01554; RV64-NEXT:    ret1555  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01556  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1557  %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1558  ret <vscale x 2 x i64> %v1559}1560 1561define <vscale x 2 x i64> @vssubu_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1562; CHECK-LABEL: vssubu_vi_nxv2i64:1563; CHECK:       # %bb.0:1564; CHECK-NEXT:    li a1, -11565; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1566; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1567; CHECK-NEXT:    ret1568  %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)1569  ret <vscale x 2 x i64> %v1570}1571 1572define <vscale x 2 x i64> @vssubu_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1573; CHECK-LABEL: vssubu_vi_nxv2i64_unmasked:1574; CHECK:       # %bb.0:1575; CHECK-NEXT:    li a1, -11576; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1577; CHECK-NEXT:    vssubu.vx v8, v8, a11578; CHECK-NEXT:    ret1579  %v = call <vscale x 2 x i64> @llvm.vp.usub.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1580  ret <vscale x 2 x i64> %v1581}1582 1583define <vscale x 4 x i64> @vssubu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1584; CHECK-LABEL: vssubu_vv_nxv4i64:1585; CHECK:       # %bb.0:1586; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1587; CHECK-NEXT:    vssubu.vv v8, v8, v12, v0.t1588; CHECK-NEXT:    ret1589  %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)1590  ret <vscale x 4 x i64> %v1591}1592 1593define <vscale x 4 x i64> @vssubu_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {1594; CHECK-LABEL: vssubu_vv_nxv4i64_unmasked:1595; CHECK:       # %bb.0:1596; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1597; CHECK-NEXT:    vssubu.vv v8, v8, v121598; CHECK-NEXT:    ret1599  %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1600  ret <vscale x 4 x i64> %v1601}1602 1603define <vscale x 4 x i64> @vssubu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1604; RV32-LABEL: vssubu_vx_nxv4i64:1605; RV32:       # %bb.0:1606; RV32-NEXT:    addi sp, sp, -161607; RV32-NEXT:    .cfi_def_cfa_offset 161608; RV32-NEXT:    sw a0, 8(sp)1609; RV32-NEXT:    sw a1, 12(sp)1610; RV32-NEXT:    addi a0, sp, 81611; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1612; RV32-NEXT:    vlse64.v v12, (a0), zero1613; RV32-NEXT:    vssubu.vv v8, v8, v12, v0.t1614; RV32-NEXT:    addi sp, sp, 161615; RV32-NEXT:    .cfi_def_cfa_offset 01616; RV32-NEXT:    ret1617;1618; RV64-LABEL: vssubu_vx_nxv4i64:1619; RV64:       # %bb.0:1620; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1621; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t1622; RV64-NEXT:    ret1623  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01624  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1625  %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)1626  ret <vscale x 4 x i64> %v1627}1628 1629define <vscale x 4 x i64> @vssubu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {1630; RV32-LABEL: vssubu_vx_nxv4i64_unmasked:1631; RV32:       # %bb.0:1632; RV32-NEXT:    addi sp, sp, -161633; RV32-NEXT:    .cfi_def_cfa_offset 161634; RV32-NEXT:    sw a0, 8(sp)1635; RV32-NEXT:    sw a1, 12(sp)1636; RV32-NEXT:    addi a0, sp, 81637; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1638; RV32-NEXT:    vlse64.v v12, (a0), zero1639; RV32-NEXT:    vssubu.vv v8, v8, v121640; RV32-NEXT:    addi sp, sp, 161641; RV32-NEXT:    .cfi_def_cfa_offset 01642; RV32-NEXT:    ret1643;1644; RV64-LABEL: vssubu_vx_nxv4i64_unmasked:1645; RV64:       # %bb.0:1646; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1647; RV64-NEXT:    vssubu.vx v8, v8, a01648; RV64-NEXT:    ret1649  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01650  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1651  %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1652  ret <vscale x 4 x i64> %v1653}1654 1655define <vscale x 4 x i64> @vssubu_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1656; CHECK-LABEL: vssubu_vi_nxv4i64:1657; CHECK:       # %bb.0:1658; CHECK-NEXT:    li a1, -11659; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1660; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1661; CHECK-NEXT:    ret1662  %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)1663  ret <vscale x 4 x i64> %v1664}1665 1666define <vscale x 4 x i64> @vssubu_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1667; CHECK-LABEL: vssubu_vi_nxv4i64_unmasked:1668; CHECK:       # %bb.0:1669; CHECK-NEXT:    li a1, -11670; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1671; CHECK-NEXT:    vssubu.vx v8, v8, a11672; CHECK-NEXT:    ret1673  %v = call <vscale x 4 x i64> @llvm.vp.usub.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1674  ret <vscale x 4 x i64> %v1675}1676 1677define <vscale x 8 x i64> @vssubu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1678; CHECK-LABEL: vssubu_vv_nxv8i64:1679; CHECK:       # %bb.0:1680; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1681; CHECK-NEXT:    vssubu.vv v8, v8, v16, v0.t1682; CHECK-NEXT:    ret1683  %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)1684  ret <vscale x 8 x i64> %v1685}1686 1687define <vscale x 8 x i64> @vssubu_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {1688; CHECK-LABEL: vssubu_vv_nxv8i64_unmasked:1689; CHECK:       # %bb.0:1690; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1691; CHECK-NEXT:    vssubu.vv v8, v8, v161692; CHECK-NEXT:    ret1693  %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1694  ret <vscale x 8 x i64> %v1695}1696 1697define <vscale x 8 x i64> @vssubu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1698; RV32-LABEL: vssubu_vx_nxv8i64:1699; RV32:       # %bb.0:1700; RV32-NEXT:    addi sp, sp, -161701; RV32-NEXT:    .cfi_def_cfa_offset 161702; RV32-NEXT:    sw a0, 8(sp)1703; RV32-NEXT:    sw a1, 12(sp)1704; RV32-NEXT:    addi a0, sp, 81705; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1706; RV32-NEXT:    vlse64.v v16, (a0), zero1707; RV32-NEXT:    vssubu.vv v8, v8, v16, v0.t1708; RV32-NEXT:    addi sp, sp, 161709; RV32-NEXT:    .cfi_def_cfa_offset 01710; RV32-NEXT:    ret1711;1712; RV64-LABEL: vssubu_vx_nxv8i64:1713; RV64:       # %bb.0:1714; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1715; RV64-NEXT:    vssubu.vx v8, v8, a0, v0.t1716; RV64-NEXT:    ret1717  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01718  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1719  %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)1720  ret <vscale x 8 x i64> %v1721}1722 1723define <vscale x 8 x i64> @vssubu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {1724; RV32-LABEL: vssubu_vx_nxv8i64_unmasked:1725; RV32:       # %bb.0:1726; RV32-NEXT:    addi sp, sp, -161727; RV32-NEXT:    .cfi_def_cfa_offset 161728; RV32-NEXT:    sw a0, 8(sp)1729; RV32-NEXT:    sw a1, 12(sp)1730; RV32-NEXT:    addi a0, sp, 81731; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1732; RV32-NEXT:    vlse64.v v16, (a0), zero1733; RV32-NEXT:    vssubu.vv v8, v8, v161734; RV32-NEXT:    addi sp, sp, 161735; RV32-NEXT:    .cfi_def_cfa_offset 01736; RV32-NEXT:    ret1737;1738; RV64-LABEL: vssubu_vx_nxv8i64_unmasked:1739; RV64:       # %bb.0:1740; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1741; RV64-NEXT:    vssubu.vx v8, v8, a01742; RV64-NEXT:    ret1743  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01744  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1745  %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1746  ret <vscale x 8 x i64> %v1747}1748 1749define <vscale x 8 x i64> @vssubu_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1750; CHECK-LABEL: vssubu_vi_nxv8i64:1751; CHECK:       # %bb.0:1752; CHECK-NEXT:    li a1, -11753; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1754; CHECK-NEXT:    vssubu.vx v8, v8, a1, v0.t1755; CHECK-NEXT:    ret1756  %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)1757  ret <vscale x 8 x i64> %v1758}1759 1760define <vscale x 8 x i64> @vssubu_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1761; CHECK-LABEL: vssubu_vi_nxv8i64_unmasked:1762; CHECK:       # %bb.0:1763; CHECK-NEXT:    li a1, -11764; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1765; CHECK-NEXT:    vssubu.vx v8, v8, a11766; CHECK-NEXT:    ret1767  %v = call <vscale x 8 x i64> @llvm.vp.usub.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1768  ret <vscale x 8 x i64> %v1769}1770