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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <vscale x 1 x i8> @vsub_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {6; CHECK-LABEL: vsub_vv_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vsub.vv v8, v8, v910; CHECK-NEXT: ret11 %vc = sub <vscale x 1 x i8> %va, %vb12 ret <vscale x 1 x i8> %vc13}14 15define <vscale x 1 x i8> @vsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {16; CHECK-LABEL: vsub_vx_nxv1i8:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma19; CHECK-NEXT: vsub.vx v8, v8, a020; CHECK-NEXT: ret21 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 022 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer23 %vc = sub <vscale x 1 x i8> %va, %splat24 ret <vscale x 1 x i8> %vc25}26 27define <vscale x 1 x i8> @vsub_vx_nxv1i8_0(<vscale x 1 x i8> %va) {28; CHECK-LABEL: vsub_vx_nxv1i8_0:29; CHECK: # %bb.0:30; CHECK-NEXT: li a0, 1731; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma32; CHECK-NEXT: vsub.vx v8, v8, a033; CHECK-NEXT: ret34 %vc = sub <vscale x 1 x i8> %va, splat (i8 17)35 ret <vscale x 1 x i8> %vc36}37 38; Test constant subs to see if we can optimize them away for scalable vectors.39define <vscale x 1 x i8> @vsub_ii_nxv1i8_1() {40; CHECK-LABEL: vsub_ii_nxv1i8_1:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma43; CHECK-NEXT: vmv.v.i v8, -144; CHECK-NEXT: ret45 %vc = sub <vscale x 1 x i8> splat (i8 2), splat (i8 3)46 ret <vscale x 1 x i8> %vc47}48 49define <vscale x 2 x i8> @vsub_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {50; CHECK-LABEL: vsub_vv_nxv2i8:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma53; CHECK-NEXT: vsub.vv v8, v8, v954; CHECK-NEXT: ret55 %vc = sub <vscale x 2 x i8> %va, %vb56 ret <vscale x 2 x i8> %vc57}58 59define <vscale x 2 x i8> @vsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {60; CHECK-LABEL: vsub_vx_nxv2i8:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma63; CHECK-NEXT: vsub.vx v8, v8, a064; CHECK-NEXT: ret65 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 066 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer67 %vc = sub <vscale x 2 x i8> %va, %splat68 ret <vscale x 2 x i8> %vc69}70 71define <vscale x 2 x i8> @vsub_vx_nxv2i8_0(<vscale x 2 x i8> %va) {72; CHECK-LABEL: vsub_vx_nxv2i8_0:73; CHECK: # %bb.0:74; CHECK-NEXT: li a0, 1775; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma76; CHECK-NEXT: vsub.vx v8, v8, a077; CHECK-NEXT: ret78 %vc = sub <vscale x 2 x i8> %va, splat (i8 17)79 ret <vscale x 2 x i8> %vc80}81 82define <vscale x 4 x i8> @vsub_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {83; CHECK-LABEL: vsub_vv_nxv4i8:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma86; CHECK-NEXT: vsub.vv v8, v8, v987; CHECK-NEXT: ret88 %vc = sub <vscale x 4 x i8> %va, %vb89 ret <vscale x 4 x i8> %vc90}91 92define <vscale x 4 x i8> @vsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {93; CHECK-LABEL: vsub_vx_nxv4i8:94; CHECK: # %bb.0:95; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma96; CHECK-NEXT: vsub.vx v8, v8, a097; CHECK-NEXT: ret98 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 099 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer100 %vc = sub <vscale x 4 x i8> %va, %splat101 ret <vscale x 4 x i8> %vc102}103 104define <vscale x 4 x i8> @vsub_vx_nxv4i8_0(<vscale x 4 x i8> %va) {105; CHECK-LABEL: vsub_vx_nxv4i8_0:106; CHECK: # %bb.0:107; CHECK-NEXT: li a0, 17108; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma109; CHECK-NEXT: vsub.vx v8, v8, a0110; CHECK-NEXT: ret111 %vc = sub <vscale x 4 x i8> %va, splat (i8 17)112 ret <vscale x 4 x i8> %vc113}114 115define <vscale x 8 x i8> @vsub_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {116; CHECK-LABEL: vsub_vv_nxv8i8:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma119; CHECK-NEXT: vsub.vv v8, v8, v9120; CHECK-NEXT: ret121 %vc = sub <vscale x 8 x i8> %va, %vb122 ret <vscale x 8 x i8> %vc123}124 125define <vscale x 8 x i8> @vsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {126; CHECK-LABEL: vsub_vx_nxv8i8:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma129; CHECK-NEXT: vsub.vx v8, v8, a0130; CHECK-NEXT: ret131 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0132 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer133 %vc = sub <vscale x 8 x i8> %va, %splat134 ret <vscale x 8 x i8> %vc135}136 137define <vscale x 8 x i8> @vsub_vx_nxv8i8_0(<vscale x 8 x i8> %va) {138; CHECK-LABEL: vsub_vx_nxv8i8_0:139; CHECK: # %bb.0:140; CHECK-NEXT: li a0, 17141; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma142; CHECK-NEXT: vsub.vx v8, v8, a0143; CHECK-NEXT: ret144 %vc = sub <vscale x 8 x i8> %va, splat (i8 17)145 ret <vscale x 8 x i8> %vc146}147 148define <vscale x 16 x i8> @vsub_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {149; CHECK-LABEL: vsub_vv_nxv16i8:150; CHECK: # %bb.0:151; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma152; CHECK-NEXT: vsub.vv v8, v8, v10153; CHECK-NEXT: ret154 %vc = sub <vscale x 16 x i8> %va, %vb155 ret <vscale x 16 x i8> %vc156}157 158define <vscale x 16 x i8> @vsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {159; CHECK-LABEL: vsub_vx_nxv16i8:160; CHECK: # %bb.0:161; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma162; CHECK-NEXT: vsub.vx v8, v8, a0163; CHECK-NEXT: ret164 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0165 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer166 %vc = sub <vscale x 16 x i8> %va, %splat167 ret <vscale x 16 x i8> %vc168}169 170define <vscale x 16 x i8> @vsub_vx_nxv16i8_0(<vscale x 16 x i8> %va) {171; CHECK-LABEL: vsub_vx_nxv16i8_0:172; CHECK: # %bb.0:173; CHECK-NEXT: li a0, 17174; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma175; CHECK-NEXT: vsub.vx v8, v8, a0176; CHECK-NEXT: ret177 %vc = sub <vscale x 16 x i8> %va, splat (i8 17)178 ret <vscale x 16 x i8> %vc179}180 181define <vscale x 32 x i8> @vsub_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {182; CHECK-LABEL: vsub_vv_nxv32i8:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma185; CHECK-NEXT: vsub.vv v8, v8, v12186; CHECK-NEXT: ret187 %vc = sub <vscale x 32 x i8> %va, %vb188 ret <vscale x 32 x i8> %vc189}190 191define <vscale x 32 x i8> @vsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {192; CHECK-LABEL: vsub_vx_nxv32i8:193; CHECK: # %bb.0:194; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma195; CHECK-NEXT: vsub.vx v8, v8, a0196; CHECK-NEXT: ret197 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0198 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer199 %vc = sub <vscale x 32 x i8> %va, %splat200 ret <vscale x 32 x i8> %vc201}202 203define <vscale x 32 x i8> @vsub_vx_nxv32i8_0(<vscale x 32 x i8> %va) {204; CHECK-LABEL: vsub_vx_nxv32i8_0:205; CHECK: # %bb.0:206; CHECK-NEXT: li a0, 17207; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma208; CHECK-NEXT: vsub.vx v8, v8, a0209; CHECK-NEXT: ret210 %vc = sub <vscale x 32 x i8> %va, splat (i8 17)211 ret <vscale x 32 x i8> %vc212}213 214define <vscale x 64 x i8> @vsub_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {215; CHECK-LABEL: vsub_vv_nxv64i8:216; CHECK: # %bb.0:217; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma218; CHECK-NEXT: vsub.vv v8, v8, v16219; CHECK-NEXT: ret220 %vc = sub <vscale x 64 x i8> %va, %vb221 ret <vscale x 64 x i8> %vc222}223 224define <vscale x 64 x i8> @vsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {225; CHECK-LABEL: vsub_vx_nxv64i8:226; CHECK: # %bb.0:227; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma228; CHECK-NEXT: vsub.vx v8, v8, a0229; CHECK-NEXT: ret230 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0231 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer232 %vc = sub <vscale x 64 x i8> %va, %splat233 ret <vscale x 64 x i8> %vc234}235 236define <vscale x 64 x i8> @vsub_vx_nxv64i8_0(<vscale x 64 x i8> %va) {237; CHECK-LABEL: vsub_vx_nxv64i8_0:238; CHECK: # %bb.0:239; CHECK-NEXT: li a0, 17240; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma241; CHECK-NEXT: vsub.vx v8, v8, a0242; CHECK-NEXT: ret243 %vc = sub <vscale x 64 x i8> %va, splat (i8 17)244 ret <vscale x 64 x i8> %vc245}246 247define <vscale x 1 x i16> @vsub_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {248; CHECK-LABEL: vsub_vv_nxv1i16:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma251; CHECK-NEXT: vsub.vv v8, v8, v9252; CHECK-NEXT: ret253 %vc = sub <vscale x 1 x i16> %va, %vb254 ret <vscale x 1 x i16> %vc255}256 257define <vscale x 1 x i16> @vsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {258; CHECK-LABEL: vsub_vx_nxv1i16:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma261; CHECK-NEXT: vsub.vx v8, v8, a0262; CHECK-NEXT: ret263 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0264 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer265 %vc = sub <vscale x 1 x i16> %va, %splat266 ret <vscale x 1 x i16> %vc267}268 269define <vscale x 1 x i16> @vsub_vx_nxv1i16_0(<vscale x 1 x i16> %va) {270; CHECK-LABEL: vsub_vx_nxv1i16_0:271; CHECK: # %bb.0:272; CHECK-NEXT: li a0, 17273; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma274; CHECK-NEXT: vsub.vx v8, v8, a0275; CHECK-NEXT: ret276 %vc = sub <vscale x 1 x i16> %va, splat (i16 17)277 ret <vscale x 1 x i16> %vc278}279 280define <vscale x 2 x i16> @vsub_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {281; CHECK-LABEL: vsub_vv_nxv2i16:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma284; CHECK-NEXT: vsub.vv v8, v8, v9285; CHECK-NEXT: ret286 %vc = sub <vscale x 2 x i16> %va, %vb287 ret <vscale x 2 x i16> %vc288}289 290define <vscale x 2 x i16> @vsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {291; CHECK-LABEL: vsub_vx_nxv2i16:292; CHECK: # %bb.0:293; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma294; CHECK-NEXT: vsub.vx v8, v8, a0295; CHECK-NEXT: ret296 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0297 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer298 %vc = sub <vscale x 2 x i16> %va, %splat299 ret <vscale x 2 x i16> %vc300}301 302define <vscale x 2 x i16> @vsub_vx_nxv2i16_0(<vscale x 2 x i16> %va) {303; CHECK-LABEL: vsub_vx_nxv2i16_0:304; CHECK: # %bb.0:305; CHECK-NEXT: li a0, 17306; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma307; CHECK-NEXT: vsub.vx v8, v8, a0308; CHECK-NEXT: ret309 %vc = sub <vscale x 2 x i16> %va, splat (i16 17)310 ret <vscale x 2 x i16> %vc311}312 313define <vscale x 4 x i16> @vsub_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {314; CHECK-LABEL: vsub_vv_nxv4i16:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma317; CHECK-NEXT: vsub.vv v8, v8, v9318; CHECK-NEXT: ret319 %vc = sub <vscale x 4 x i16> %va, %vb320 ret <vscale x 4 x i16> %vc321}322 323define <vscale x 4 x i16> @vsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {324; CHECK-LABEL: vsub_vx_nxv4i16:325; CHECK: # %bb.0:326; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma327; CHECK-NEXT: vsub.vx v8, v8, a0328; CHECK-NEXT: ret329 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0330 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer331 %vc = sub <vscale x 4 x i16> %va, %splat332 ret <vscale x 4 x i16> %vc333}334 335define <vscale x 4 x i16> @vsub_vx_nxv4i16_0(<vscale x 4 x i16> %va) {336; CHECK-LABEL: vsub_vx_nxv4i16_0:337; CHECK: # %bb.0:338; CHECK-NEXT: li a0, 17339; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma340; CHECK-NEXT: vsub.vx v8, v8, a0341; CHECK-NEXT: ret342 %vc = sub <vscale x 4 x i16> %va, splat (i16 17)343 ret <vscale x 4 x i16> %vc344}345 346define <vscale x 8 x i16> @vsub_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {347; CHECK-LABEL: vsub_vv_nxv8i16:348; CHECK: # %bb.0:349; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma350; CHECK-NEXT: vsub.vv v8, v8, v10351; CHECK-NEXT: ret352 %vc = sub <vscale x 8 x i16> %va, %vb353 ret <vscale x 8 x i16> %vc354}355 356define <vscale x 8 x i16> @vsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {357; CHECK-LABEL: vsub_vx_nxv8i16:358; CHECK: # %bb.0:359; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma360; CHECK-NEXT: vsub.vx v8, v8, a0361; CHECK-NEXT: ret362 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0363 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer364 %vc = sub <vscale x 8 x i16> %va, %splat365 ret <vscale x 8 x i16> %vc366}367 368define <vscale x 8 x i16> @vsub_vx_nxv8i16_0(<vscale x 8 x i16> %va) {369; CHECK-LABEL: vsub_vx_nxv8i16_0:370; CHECK: # %bb.0:371; CHECK-NEXT: li a0, 17372; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma373; CHECK-NEXT: vsub.vx v8, v8, a0374; CHECK-NEXT: ret375 %vc = sub <vscale x 8 x i16> %va, splat (i16 17)376 ret <vscale x 8 x i16> %vc377}378 379define <vscale x 16 x i16> @vsub_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {380; CHECK-LABEL: vsub_vv_nxv16i16:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma383; CHECK-NEXT: vsub.vv v8, v8, v12384; CHECK-NEXT: ret385 %vc = sub <vscale x 16 x i16> %va, %vb386 ret <vscale x 16 x i16> %vc387}388 389define <vscale x 16 x i16> @vsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {390; CHECK-LABEL: vsub_vx_nxv16i16:391; CHECK: # %bb.0:392; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma393; CHECK-NEXT: vsub.vx v8, v8, a0394; CHECK-NEXT: ret395 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0396 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer397 %vc = sub <vscale x 16 x i16> %va, %splat398 ret <vscale x 16 x i16> %vc399}400 401define <vscale x 16 x i16> @vsub_vx_nxv16i16_0(<vscale x 16 x i16> %va) {402; CHECK-LABEL: vsub_vx_nxv16i16_0:403; CHECK: # %bb.0:404; CHECK-NEXT: li a0, 17405; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma406; CHECK-NEXT: vsub.vx v8, v8, a0407; CHECK-NEXT: ret408 %vc = sub <vscale x 16 x i16> %va, splat (i16 17)409 ret <vscale x 16 x i16> %vc410}411 412define <vscale x 32 x i16> @vsub_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {413; CHECK-LABEL: vsub_vv_nxv32i16:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma416; CHECK-NEXT: vsub.vv v8, v8, v16417; CHECK-NEXT: ret418 %vc = sub <vscale x 32 x i16> %va, %vb419 ret <vscale x 32 x i16> %vc420}421 422define <vscale x 32 x i16> @vsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {423; CHECK-LABEL: vsub_vx_nxv32i16:424; CHECK: # %bb.0:425; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma426; CHECK-NEXT: vsub.vx v8, v8, a0427; CHECK-NEXT: ret428 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0429 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer430 %vc = sub <vscale x 32 x i16> %va, %splat431 ret <vscale x 32 x i16> %vc432}433 434define <vscale x 32 x i16> @vsub_vx_nxv32i16_0(<vscale x 32 x i16> %va) {435; CHECK-LABEL: vsub_vx_nxv32i16_0:436; CHECK: # %bb.0:437; CHECK-NEXT: li a0, 17438; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma439; CHECK-NEXT: vsub.vx v8, v8, a0440; CHECK-NEXT: ret441 %vc = sub <vscale x 32 x i16> %va, splat (i16 17)442 ret <vscale x 32 x i16> %vc443}444 445define <vscale x 1 x i32> @vsub_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {446; CHECK-LABEL: vsub_vv_nxv1i32:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma449; CHECK-NEXT: vsub.vv v8, v8, v9450; CHECK-NEXT: ret451 %vc = sub <vscale x 1 x i32> %va, %vb452 ret <vscale x 1 x i32> %vc453}454 455define <vscale x 1 x i32> @vsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {456; CHECK-LABEL: vsub_vx_nxv1i32:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma459; CHECK-NEXT: vsub.vx v8, v8, a0460; CHECK-NEXT: ret461 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0462 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer463 %vc = sub <vscale x 1 x i32> %va, %splat464 ret <vscale x 1 x i32> %vc465}466 467define <vscale x 1 x i32> @vsub_vx_nxv1i32_0(<vscale x 1 x i32> %va) {468; CHECK-LABEL: vsub_vx_nxv1i32_0:469; CHECK: # %bb.0:470; CHECK-NEXT: li a0, 17471; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma472; CHECK-NEXT: vsub.vx v8, v8, a0473; CHECK-NEXT: ret474 %vc = sub <vscale x 1 x i32> %va, splat (i32 17)475 ret <vscale x 1 x i32> %vc476}477 478define <vscale x 2 x i32> @vsub_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {479; CHECK-LABEL: vsub_vv_nxv2i32:480; CHECK: # %bb.0:481; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma482; CHECK-NEXT: vsub.vv v8, v8, v9483; CHECK-NEXT: ret484 %vc = sub <vscale x 2 x i32> %va, %vb485 ret <vscale x 2 x i32> %vc486}487 488define <vscale x 2 x i32> @vsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {489; CHECK-LABEL: vsub_vx_nxv2i32:490; CHECK: # %bb.0:491; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma492; CHECK-NEXT: vsub.vx v8, v8, a0493; CHECK-NEXT: ret494 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0495 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer496 %vc = sub <vscale x 2 x i32> %va, %splat497 ret <vscale x 2 x i32> %vc498}499 500define <vscale x 2 x i32> @vsub_vx_nxv2i32_0(<vscale x 2 x i32> %va) {501; CHECK-LABEL: vsub_vx_nxv2i32_0:502; CHECK: # %bb.0:503; CHECK-NEXT: li a0, 17504; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma505; CHECK-NEXT: vsub.vx v8, v8, a0506; CHECK-NEXT: ret507 %vc = sub <vscale x 2 x i32> %va, splat (i32 17)508 ret <vscale x 2 x i32> %vc509}510 511define <vscale x 4 x i32> @vsub_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {512; CHECK-LABEL: vsub_vv_nxv4i32:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma515; CHECK-NEXT: vsub.vv v8, v8, v10516; CHECK-NEXT: ret517 %vc = sub <vscale x 4 x i32> %va, %vb518 ret <vscale x 4 x i32> %vc519}520 521define <vscale x 4 x i32> @vsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {522; CHECK-LABEL: vsub_vx_nxv4i32:523; CHECK: # %bb.0:524; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma525; CHECK-NEXT: vsub.vx v8, v8, a0526; CHECK-NEXT: ret527 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0528 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer529 %vc = sub <vscale x 4 x i32> %va, %splat530 ret <vscale x 4 x i32> %vc531}532 533define <vscale x 4 x i32> @vsub_vx_nxv4i32_0(<vscale x 4 x i32> %va) {534; CHECK-LABEL: vsub_vx_nxv4i32_0:535; CHECK: # %bb.0:536; CHECK-NEXT: li a0, 17537; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma538; CHECK-NEXT: vsub.vx v8, v8, a0539; CHECK-NEXT: ret540 %vc = sub <vscale x 4 x i32> %va, splat (i32 17)541 ret <vscale x 4 x i32> %vc542}543 544define <vscale x 8 x i32> @vsub_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {545; CHECK-LABEL: vsub_vv_nxv8i32:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma548; CHECK-NEXT: vsub.vv v8, v8, v12549; CHECK-NEXT: ret550 %vc = sub <vscale x 8 x i32> %va, %vb551 ret <vscale x 8 x i32> %vc552}553 554define <vscale x 8 x i32> @vsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {555; CHECK-LABEL: vsub_vx_nxv8i32:556; CHECK: # %bb.0:557; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma558; CHECK-NEXT: vsub.vx v8, v8, a0559; CHECK-NEXT: ret560 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0561 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer562 %vc = sub <vscale x 8 x i32> %va, %splat563 ret <vscale x 8 x i32> %vc564}565 566define <vscale x 8 x i32> @vsub_vx_nxv8i32_0(<vscale x 8 x i32> %va) {567; CHECK-LABEL: vsub_vx_nxv8i32_0:568; CHECK: # %bb.0:569; CHECK-NEXT: li a0, 17570; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma571; CHECK-NEXT: vsub.vx v8, v8, a0572; CHECK-NEXT: ret573 %vc = sub <vscale x 8 x i32> %va, splat (i32 17)574 ret <vscale x 8 x i32> %vc575}576 577define <vscale x 16 x i32> @vsub_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {578; CHECK-LABEL: vsub_vv_nxv16i32:579; CHECK: # %bb.0:580; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma581; CHECK-NEXT: vsub.vv v8, v8, v16582; CHECK-NEXT: ret583 %vc = sub <vscale x 16 x i32> %va, %vb584 ret <vscale x 16 x i32> %vc585}586 587define <vscale x 16 x i32> @vsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {588; CHECK-LABEL: vsub_vx_nxv16i32:589; CHECK: # %bb.0:590; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma591; CHECK-NEXT: vsub.vx v8, v8, a0592; CHECK-NEXT: ret593 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0594 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer595 %vc = sub <vscale x 16 x i32> %va, %splat596 ret <vscale x 16 x i32> %vc597}598 599define <vscale x 16 x i32> @vsub_vx_nxv16i32_0(<vscale x 16 x i32> %va) {600; CHECK-LABEL: vsub_vx_nxv16i32_0:601; CHECK: # %bb.0:602; CHECK-NEXT: li a0, 17603; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma604; CHECK-NEXT: vsub.vx v8, v8, a0605; CHECK-NEXT: ret606 %vc = sub <vscale x 16 x i32> %va, splat (i32 17)607 ret <vscale x 16 x i32> %vc608}609 610define <vscale x 1 x i64> @vsub_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {611; CHECK-LABEL: vsub_vv_nxv1i64:612; CHECK: # %bb.0:613; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma614; CHECK-NEXT: vsub.vv v8, v8, v9615; CHECK-NEXT: ret616 %vc = sub <vscale x 1 x i64> %va, %vb617 ret <vscale x 1 x i64> %vc618}619 620define <vscale x 1 x i64> @vsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {621; RV32-LABEL: vsub_vx_nxv1i64:622; RV32: # %bb.0:623; RV32-NEXT: addi sp, sp, -16624; RV32-NEXT: .cfi_def_cfa_offset 16625; RV32-NEXT: sw a0, 8(sp)626; RV32-NEXT: sw a1, 12(sp)627; RV32-NEXT: addi a0, sp, 8628; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma629; RV32-NEXT: vlse64.v v9, (a0), zero630; RV32-NEXT: vsub.vv v8, v8, v9631; RV32-NEXT: addi sp, sp, 16632; RV32-NEXT: .cfi_def_cfa_offset 0633; RV32-NEXT: ret634;635; RV64-LABEL: vsub_vx_nxv1i64:636; RV64: # %bb.0:637; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma638; RV64-NEXT: vsub.vx v8, v8, a0639; RV64-NEXT: ret640 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0641 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer642 %vc = sub <vscale x 1 x i64> %va, %splat643 ret <vscale x 1 x i64> %vc644}645 646define <vscale x 1 x i64> @vsub_vx_nxv1i64_0(<vscale x 1 x i64> %va) {647; CHECK-LABEL: vsub_vx_nxv1i64_0:648; CHECK: # %bb.0:649; CHECK-NEXT: li a0, 17650; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma651; CHECK-NEXT: vsub.vx v8, v8, a0652; CHECK-NEXT: ret653 %vc = sub <vscale x 1 x i64> %va, splat (i64 17)654 ret <vscale x 1 x i64> %vc655}656 657define <vscale x 2 x i64> @vsub_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {658; CHECK-LABEL: vsub_vv_nxv2i64:659; CHECK: # %bb.0:660; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma661; CHECK-NEXT: vsub.vv v8, v8, v10662; CHECK-NEXT: ret663 %vc = sub <vscale x 2 x i64> %va, %vb664 ret <vscale x 2 x i64> %vc665}666 667define <vscale x 2 x i64> @vsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {668; RV32-LABEL: vsub_vx_nxv2i64:669; RV32: # %bb.0:670; RV32-NEXT: addi sp, sp, -16671; RV32-NEXT: .cfi_def_cfa_offset 16672; RV32-NEXT: sw a0, 8(sp)673; RV32-NEXT: sw a1, 12(sp)674; RV32-NEXT: addi a0, sp, 8675; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma676; RV32-NEXT: vlse64.v v10, (a0), zero677; RV32-NEXT: vsub.vv v8, v8, v10678; RV32-NEXT: addi sp, sp, 16679; RV32-NEXT: .cfi_def_cfa_offset 0680; RV32-NEXT: ret681;682; RV64-LABEL: vsub_vx_nxv2i64:683; RV64: # %bb.0:684; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma685; RV64-NEXT: vsub.vx v8, v8, a0686; RV64-NEXT: ret687 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0688 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer689 %vc = sub <vscale x 2 x i64> %va, %splat690 ret <vscale x 2 x i64> %vc691}692 693define <vscale x 2 x i64> @vsub_vx_nxv2i64_0(<vscale x 2 x i64> %va) {694; CHECK-LABEL: vsub_vx_nxv2i64_0:695; CHECK: # %bb.0:696; CHECK-NEXT: li a0, 17697; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma698; CHECK-NEXT: vsub.vx v8, v8, a0699; CHECK-NEXT: ret700 %vc = sub <vscale x 2 x i64> %va, splat (i64 17)701 ret <vscale x 2 x i64> %vc702}703 704define <vscale x 4 x i64> @vsub_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {705; CHECK-LABEL: vsub_vv_nxv4i64:706; CHECK: # %bb.0:707; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma708; CHECK-NEXT: vsub.vv v8, v8, v12709; CHECK-NEXT: ret710 %vc = sub <vscale x 4 x i64> %va, %vb711 ret <vscale x 4 x i64> %vc712}713 714define <vscale x 4 x i64> @vsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {715; RV32-LABEL: vsub_vx_nxv4i64:716; RV32: # %bb.0:717; RV32-NEXT: addi sp, sp, -16718; RV32-NEXT: .cfi_def_cfa_offset 16719; RV32-NEXT: sw a0, 8(sp)720; RV32-NEXT: sw a1, 12(sp)721; RV32-NEXT: addi a0, sp, 8722; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma723; RV32-NEXT: vlse64.v v12, (a0), zero724; RV32-NEXT: vsub.vv v8, v8, v12725; RV32-NEXT: addi sp, sp, 16726; RV32-NEXT: .cfi_def_cfa_offset 0727; RV32-NEXT: ret728;729; RV64-LABEL: vsub_vx_nxv4i64:730; RV64: # %bb.0:731; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma732; RV64-NEXT: vsub.vx v8, v8, a0733; RV64-NEXT: ret734 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0735 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer736 %vc = sub <vscale x 4 x i64> %va, %splat737 ret <vscale x 4 x i64> %vc738}739 740define <vscale x 4 x i64> @vsub_vx_nxv4i64_0(<vscale x 4 x i64> %va) {741; CHECK-LABEL: vsub_vx_nxv4i64_0:742; CHECK: # %bb.0:743; CHECK-NEXT: li a0, 17744; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma745; CHECK-NEXT: vsub.vx v8, v8, a0746; CHECK-NEXT: ret747 %vc = sub <vscale x 4 x i64> %va, splat (i64 17)748 ret <vscale x 4 x i64> %vc749}750 751define <vscale x 8 x i64> @vsub_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {752; CHECK-LABEL: vsub_vv_nxv8i64:753; CHECK: # %bb.0:754; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma755; CHECK-NEXT: vsub.vv v8, v8, v16756; CHECK-NEXT: ret757 %vc = sub <vscale x 8 x i64> %va, %vb758 ret <vscale x 8 x i64> %vc759}760 761define <vscale x 8 x i64> @vsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {762; RV32-LABEL: vsub_vx_nxv8i64:763; RV32: # %bb.0:764; RV32-NEXT: addi sp, sp, -16765; RV32-NEXT: .cfi_def_cfa_offset 16766; RV32-NEXT: sw a0, 8(sp)767; RV32-NEXT: sw a1, 12(sp)768; RV32-NEXT: addi a0, sp, 8769; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma770; RV32-NEXT: vlse64.v v16, (a0), zero771; RV32-NEXT: vsub.vv v8, v8, v16772; RV32-NEXT: addi sp, sp, 16773; RV32-NEXT: .cfi_def_cfa_offset 0774; RV32-NEXT: ret775;776; RV64-LABEL: vsub_vx_nxv8i64:777; RV64: # %bb.0:778; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma779; RV64-NEXT: vsub.vx v8, v8, a0780; RV64-NEXT: ret781 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0782 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer783 %vc = sub <vscale x 8 x i64> %va, %splat784 ret <vscale x 8 x i64> %vc785}786 787define <vscale x 8 x i64> @vsub_vx_nxv8i64_0(<vscale x 8 x i64> %va) {788; CHECK-LABEL: vsub_vx_nxv8i64_0:789; CHECK: # %bb.0:790; CHECK-NEXT: li a0, 17791; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma792; CHECK-NEXT: vsub.vx v8, v8, a0793; CHECK-NEXT: ret794 %vc = sub <vscale x 8 x i64> %va, splat (i64 17)795 ret <vscale x 8 x i64> %vc796}797 798define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {799; RV32-LABEL: vsub_xx_nxv8i64:800; RV32: # %bb.0:801; RV32-NEXT: addi sp, sp, -16802; RV32-NEXT: sub a4, a0, a2803; RV32-NEXT: sltu a0, a0, a2804; RV32-NEXT: sub a1, a1, a3805; RV32-NEXT: sub a1, a1, a0806; RV32-NEXT: sw a4, 8(sp)807; RV32-NEXT: sw a1, 12(sp)808; RV32-NEXT: addi a0, sp, 8809; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma810; RV32-NEXT: vlse64.v v8, (a0), zero811; RV32-NEXT: addi sp, sp, 16812; RV32-NEXT: ret813;814; RV64-LABEL: vsub_xx_nxv8i64:815; RV64: # %bb.0:816; RV64-NEXT: sub a0, a0, a1817; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma818; RV64-NEXT: vmv.v.x v8, a0819; RV64-NEXT: ret820 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0821 %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer822 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0823 %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer824 %v = sub <vscale x 8 x i64> %splat1, %splat2825 ret <vscale x 8 x i64> %v826}827 828define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {829; CHECK-LABEL: vsub_vv_mask_nxv8i32:830; CHECK: # %bb.0:831; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu832; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t833; CHECK-NEXT: ret834 835 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer836 %vc = sub <vscale x 8 x i32> %va, %vs837 ret <vscale x 8 x i32> %vc838}839 840define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {841; CHECK-LABEL: vsub_vx_mask_nxv8i32:842; CHECK: # %bb.0:843; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu844; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t845; CHECK-NEXT: ret846 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0847 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer848 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer849 %vc = sub <vscale x 8 x i32> %va, %vs850 ret <vscale x 8 x i32> %vc851}852 853define <vscale x 8 x i32> @vsub_vi_nxv8i32_one(<vscale x 8 x i32> %va) {854; CHECK-LABEL: vsub_vi_nxv8i32_one:855; CHECK: # %bb.0:856; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma857; CHECK-NEXT: vadd.vi v8, v8, -1858; CHECK-NEXT: ret859 %vc = sub <vscale x 8 x i32> %va, splat (i32 1)860 ret <vscale x 8 x i32> %vc861}862 863define <vscale x 8 x i32> @vsub_vi_nxv8i32_minusone(<vscale x 8 x i32> %va) {864; CHECK-LABEL: vsub_vi_nxv8i32_minusone:865; CHECK: # %bb.0:866; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma867; CHECK-NEXT: vadd.vi v8, v8, 1868; CHECK-NEXT: ret869 %vc = sub <vscale x 8 x i32> %va, splat (i32 -1)870 ret <vscale x 8 x i32> %vc871}872 873define <vscale x 8 x i32> @vsub_vi_nxv8i32_15(<vscale x 8 x i32> %va) {874; CHECK-LABEL: vsub_vi_nxv8i32_15:875; CHECK: # %bb.0:876; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma877; CHECK-NEXT: vadd.vi v8, v8, -15878; CHECK-NEXT: ret879 %vc = sub <vscale x 8 x i32> %va, splat (i32 15)880 ret <vscale x 8 x i32> %vc881}882 883define <vscale x 8 x i32> @vsub_vi_nxv8i32_16(<vscale x 8 x i32> %va) {884; CHECK-LABEL: vsub_vi_nxv8i32_16:885; CHECK: # %bb.0:886; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma887; CHECK-NEXT: vadd.vi v8, v8, -16888; CHECK-NEXT: ret889 %vc = sub <vscale x 8 x i32> %va, splat (i32 16)890 ret <vscale x 8 x i32> %vc891}892 893define <vscale x 8 x i32> @vsub_vi_nxv8i32_minus15(<vscale x 8 x i32> %va) {894; CHECK-LABEL: vsub_vi_nxv8i32_minus15:895; CHECK: # %bb.0:896; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma897; CHECK-NEXT: vadd.vi v8, v8, 15898; CHECK-NEXT: ret899 %vc = sub <vscale x 8 x i32> %va, splat (i32 -15)900 ret <vscale x 8 x i32> %vc901}902 903define <vscale x 8 x i32> @vsub_vi_nxv8i32_minus16(<vscale x 8 x i32> %va) {904; CHECK-LABEL: vsub_vi_nxv8i32_minus16:905; CHECK: # %bb.0:906; CHECK-NEXT: li a0, -16907; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma908; CHECK-NEXT: vsub.vx v8, v8, a0909; CHECK-NEXT: ret910 %vc = sub <vscale x 8 x i32> %va, splat (i32 -16)911 ret <vscale x 8 x i32> %vc912}913 914define <vscale x 8 x i32> @vsub_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {915; CHECK-LABEL: vsub_vi_mask_nxv8i32:916; CHECK: # %bb.0:917; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu918; CHECK-NEXT: vadd.vi v8, v8, -7, v0.t919; CHECK-NEXT: ret920 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> zeroinitializer921 %vc = sub <vscale x 8 x i32> %va, %vs922 ret <vscale x 8 x i32> %vc923}924 925; Make sure we are able to split a type that isn't an MVT even if the scalar926; element type isn't legal on RV32. This used to crash.927define <vscale x 64 x i64> @vsub_vv_nxv64i64(<vscale x 64 x i64> %va, <vscale x 64 x i64> %vb) {928; RV32-LABEL: vsub_vv_nxv64i64:929; RV32: # %bb.0:930; RV32-NEXT: addi sp, sp, -80931; RV32-NEXT: .cfi_def_cfa_offset 80932; RV32-NEXT: sw ra, 76(sp) # 4-byte Folded Spill933; RV32-NEXT: sw s0, 72(sp) # 4-byte Folded Spill934; RV32-NEXT: sw s1, 68(sp) # 4-byte Folded Spill935; RV32-NEXT: sw s2, 64(sp) # 4-byte Folded Spill936; RV32-NEXT: sw s3, 60(sp) # 4-byte Folded Spill937; RV32-NEXT: sw s4, 56(sp) # 4-byte Folded Spill938; RV32-NEXT: sw s5, 52(sp) # 4-byte Folded Spill939; RV32-NEXT: sw s6, 48(sp) # 4-byte Folded Spill940; RV32-NEXT: sw s7, 44(sp) # 4-byte Folded Spill941; RV32-NEXT: sw s8, 40(sp) # 4-byte Folded Spill942; RV32-NEXT: sw s9, 36(sp) # 4-byte Folded Spill943; RV32-NEXT: .cfi_offset ra, -4944; RV32-NEXT: .cfi_offset s0, -8945; RV32-NEXT: .cfi_offset s1, -12946; RV32-NEXT: .cfi_offset s2, -16947; RV32-NEXT: .cfi_offset s3, -20948; RV32-NEXT: .cfi_offset s4, -24949; RV32-NEXT: .cfi_offset s5, -28950; RV32-NEXT: .cfi_offset s6, -32951; RV32-NEXT: .cfi_offset s7, -36952; RV32-NEXT: .cfi_offset s8, -40953; RV32-NEXT: .cfi_offset s9, -44954; RV32-NEXT: csrr a2, vlenb955; RV32-NEXT: slli a2, a2, 3956; RV32-NEXT: mv a3, a2957; RV32-NEXT: slli a2, a2, 1958; RV32-NEXT: add a3, a3, a2959; RV32-NEXT: slli a2, a2, 2960; RV32-NEXT: add a2, a2, a3961; RV32-NEXT: sub sp, sp, a2962; RV32-NEXT: .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0xd0, 0x00, 0x22, 0x11, 0xd8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 80 + 88 * vlenb963; RV32-NEXT: mv s2, a7964; RV32-NEXT: mv s3, a1965; RV32-NEXT: csrr a1, vlenb966; RV32-NEXT: slli a1, a1, 6967; RV32-NEXT: add a1, sp, a1968; RV32-NEXT: addi a1, a1, 32969; RV32-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill970; RV32-NEXT: csrr a1, vlenb971; RV32-NEXT: slli a1, a1, 4972; RV32-NEXT: mv a2, a1973; RV32-NEXT: slli a1, a1, 2974; RV32-NEXT: add a1, a1, a2975; RV32-NEXT: add a1, sp, a1976; RV32-NEXT: addi a1, a1, 32977; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill978; RV32-NEXT: csrr s6, vlenb979; RV32-NEXT: slli s7, s6, 4980; RV32-NEXT: slli s8, s6, 3981; RV32-NEXT: add a1, a7, s7982; RV32-NEXT: vl8re64.v v8, (a1)983; RV32-NEXT: csrr a1, vlenb984; RV32-NEXT: slli a1, a1, 3985; RV32-NEXT: mv a2, a1986; RV32-NEXT: slli a1, a1, 3987; RV32-NEXT: add a1, a1, a2988; RV32-NEXT: add a1, sp, a1989; RV32-NEXT: addi a1, a1, 32990; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill991; RV32-NEXT: add a1, a7, s8992; RV32-NEXT: vl8re64.v v8, (a1)993; RV32-NEXT: csrr a1, vlenb994; RV32-NEXT: slli a1, a1, 4995; RV32-NEXT: mv a2, a1996; RV32-NEXT: slli a1, a1, 1997; RV32-NEXT: add a1, a1, a2998; RV32-NEXT: add a1, sp, a1999; RV32-NEXT: addi a1, a1, 321000; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1001; RV32-NEXT: mv s0, a01002; RV32-NEXT: li a1, 561003; RV32-NEXT: mv a0, s61004; RV32-NEXT: call __mulsi31005; RV32-NEXT: mv s1, a01006; RV32-NEXT: add a0, s2, a01007; RV32-NEXT: vl8re64.v v8, (a0)1008; RV32-NEXT: csrr a0, vlenb1009; RV32-NEXT: slli a0, a0, 51010; RV32-NEXT: add a0, sp, a01011; RV32-NEXT: addi a0, a0, 321012; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1013; RV32-NEXT: li a1, 401014; RV32-NEXT: mv a0, s61015; RV32-NEXT: call __mulsi31016; RV32-NEXT: mv s4, a01017; RV32-NEXT: add a0, s3, a01018; RV32-NEXT: vl8re64.v v8, (a0)1019; RV32-NEXT: csrr a0, vlenb1020; RV32-NEXT: slli a0, a0, 31021; RV32-NEXT: mv a1, a01022; RV32-NEXT: slli a0, a0, 11023; RV32-NEXT: add a0, a0, a11024; RV32-NEXT: add a0, sp, a01025; RV32-NEXT: addi a0, a0, 321026; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1027; RV32-NEXT: li a1, 481028; RV32-NEXT: mv a0, s61029; RV32-NEXT: call __mulsi31030; RV32-NEXT: mv s5, a01031; RV32-NEXT: add a0, s2, a01032; RV32-NEXT: slli s9, s6, 51033; RV32-NEXT: vl8re64.v v8, (a0)1034; RV32-NEXT: csrr a0, vlenb1035; RV32-NEXT: slli a0, a0, 31036; RV32-NEXT: mv a1, a01037; RV32-NEXT: slli a0, a0, 21038; RV32-NEXT: add a0, a0, a11039; RV32-NEXT: add a0, sp, a01040; RV32-NEXT: addi a0, a0, 321041; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1042; RV32-NEXT: add a0, s3, s91043; RV32-NEXT: vl8re64.v v8, (a0)1044; RV32-NEXT: csrr a0, vlenb1045; RV32-NEXT: slli a0, a0, 41046; RV32-NEXT: add a0, sp, a01047; RV32-NEXT: addi a0, a0, 321048; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1049; RV32-NEXT: add a0, s2, s41050; RV32-NEXT: vl8re64.v v8, (a0)1051; RV32-NEXT: csrr a0, vlenb1052; RV32-NEXT: slli a0, a0, 31053; RV32-NEXT: mv a1, a01054; RV32-NEXT: slli a0, a0, 11055; RV32-NEXT: add a1, a1, a01056; RV32-NEXT: slli a0, a0, 11057; RV32-NEXT: add a0, a0, a11058; RV32-NEXT: add a0, sp, a01059; RV32-NEXT: addi a0, a0, 321060; RV32-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1061; RV32-NEXT: li a1, 241062; RV32-NEXT: mv a0, s61063; RV32-NEXT: call __mulsi31064; RV32-NEXT: csrr a1, vlenb1065; RV32-NEXT: slli a1, a1, 31066; RV32-NEXT: mv a2, a11067; RV32-NEXT: slli a1, a1, 21068; RV32-NEXT: add a1, a1, a21069; RV32-NEXT: add a1, sp, a11070; RV32-NEXT: addi a1, a1, 321071; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1072; RV32-NEXT: csrr a1, vlenb1073; RV32-NEXT: slli a1, a1, 41074; RV32-NEXT: add a1, sp, a11075; RV32-NEXT: addi a1, a1, 321076; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1077; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1078; RV32-NEXT: vsub.vv v8, v16, v81079; RV32-NEXT: csrr a1, vlenb1080; RV32-NEXT: slli a1, a1, 31081; RV32-NEXT: mv a2, a11082; RV32-NEXT: slli a1, a1, 21083; RV32-NEXT: add a1, a1, a21084; RV32-NEXT: add a1, sp, a11085; RV32-NEXT: addi a1, a1, 321086; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1087; RV32-NEXT: csrr a1, vlenb1088; RV32-NEXT: slli a1, a1, 51089; RV32-NEXT: add a1, sp, a11090; RV32-NEXT: addi a1, a1, 321091; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1092; RV32-NEXT: csrr a1, vlenb1093; RV32-NEXT: slli a1, a1, 31094; RV32-NEXT: mv a2, a11095; RV32-NEXT: slli a1, a1, 11096; RV32-NEXT: add a1, a1, a21097; RV32-NEXT: add a1, sp, a11098; RV32-NEXT: addi a1, a1, 321099; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1100; RV32-NEXT: vsub.vv v8, v16, v81101; RV32-NEXT: csrr a1, vlenb1102; RV32-NEXT: slli a1, a1, 51103; RV32-NEXT: add a1, sp, a11104; RV32-NEXT: addi a1, a1, 321105; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1106; RV32-NEXT: csrr a1, vlenb1107; RV32-NEXT: slli a1, a1, 61108; RV32-NEXT: add a1, sp, a11109; RV32-NEXT: addi a1, a1, 321110; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1111; RV32-NEXT: csrr a1, vlenb1112; RV32-NEXT: slli a1, a1, 41113; RV32-NEXT: mv a2, a11114; RV32-NEXT: slli a1, a1, 11115; RV32-NEXT: add a1, a1, a21116; RV32-NEXT: add a1, sp, a11117; RV32-NEXT: addi a1, a1, 321118; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1119; RV32-NEXT: vsub.vv v8, v8, v161120; RV32-NEXT: csrr a1, vlenb1121; RV32-NEXT: slli a1, a1, 61122; RV32-NEXT: add a1, sp, a11123; RV32-NEXT: addi a1, a1, 321124; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1125; RV32-NEXT: vl8re64.v v8, (s3)1126; RV32-NEXT: csrr a1, vlenb1127; RV32-NEXT: slli a1, a1, 31128; RV32-NEXT: mv a2, a11129; RV32-NEXT: slli a1, a1, 31130; RV32-NEXT: add a1, a1, a21131; RV32-NEXT: add a1, sp, a11132; RV32-NEXT: addi a1, a1, 321133; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1134; RV32-NEXT: vsub.vv v8, v8, v161135; RV32-NEXT: csrr a1, vlenb1136; RV32-NEXT: slli a1, a1, 31137; RV32-NEXT: mv a2, a11138; RV32-NEXT: slli a1, a1, 31139; RV32-NEXT: add a1, a1, a21140; RV32-NEXT: add a1, sp, a11141; RV32-NEXT: addi a1, a1, 321142; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1143; RV32-NEXT: add a1, s3, a01144; RV32-NEXT: add a2, s2, s91145; RV32-NEXT: add a3, s3, s71146; RV32-NEXT: add a4, s2, a01147; RV32-NEXT: add s3, s3, s81148; RV32-NEXT: vl8re64.v v8, (s2)1149; RV32-NEXT: csrr a5, vlenb1150; RV32-NEXT: slli a5, a5, 31151; RV32-NEXT: mv a6, a51152; RV32-NEXT: slli a5, a5, 11153; RV32-NEXT: add a5, a5, a61154; RV32-NEXT: add a5, sp, a51155; RV32-NEXT: addi a5, a5, 321156; RV32-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill1157; RV32-NEXT: vl8re64.v v8, (a2)1158; RV32-NEXT: csrr a2, vlenb1159; RV32-NEXT: slli a2, a2, 41160; RV32-NEXT: mv a5, a21161; RV32-NEXT: slli a2, a2, 11162; RV32-NEXT: add a2, a2, a51163; RV32-NEXT: add a2, sp, a21164; RV32-NEXT: addi a2, a2, 321165; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1166; RV32-NEXT: vl8re64.v v8, (a4)1167; RV32-NEXT: csrr a2, vlenb1168; RV32-NEXT: slli a2, a2, 41169; RV32-NEXT: add a2, sp, a21170; RV32-NEXT: addi a2, a2, 321171; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1172; RV32-NEXT: vl8re64.v v8, (s3)1173; RV32-NEXT: csrr a2, vlenb1174; RV32-NEXT: slli a2, a2, 31175; RV32-NEXT: add a2, sp, a21176; RV32-NEXT: addi a2, a2, 321177; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1178; RV32-NEXT: vl8re64.v v8, (a3)1179; RV32-NEXT: addi a2, sp, 321180; RV32-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1181; RV32-NEXT: vl8re64.v v24, (a1)1182; RV32-NEXT: csrr a1, vlenb1183; RV32-NEXT: slli a1, a1, 41184; RV32-NEXT: mv a2, a11185; RV32-NEXT: slli a1, a1, 21186; RV32-NEXT: add a1, a1, a21187; RV32-NEXT: add a1, sp, a11188; RV32-NEXT: addi a1, a1, 321189; RV32-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload1190; RV32-NEXT: csrr a1, vlenb1191; RV32-NEXT: slli a1, a1, 31192; RV32-NEXT: mv a2, a11193; RV32-NEXT: slli a1, a1, 11194; RV32-NEXT: add a1, a1, a21195; RV32-NEXT: add a1, sp, a11196; RV32-NEXT: addi a1, a1, 321197; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1198; RV32-NEXT: vsub.vv v0, v0, v81199; RV32-NEXT: csrr a1, vlenb1200; RV32-NEXT: slli a1, a1, 41201; RV32-NEXT: add a1, sp, a11202; RV32-NEXT: addi a1, a1, 321203; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1204; RV32-NEXT: csrr a1, vlenb1205; RV32-NEXT: slli a1, a1, 31206; RV32-NEXT: add a1, sp, a11207; RV32-NEXT: addi a1, a1, 321208; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1209; RV32-NEXT: vsub.vv v8, v16, v81210; RV32-NEXT: csrr a1, vlenb1211; RV32-NEXT: slli a1, a1, 41212; RV32-NEXT: mv a2, a11213; RV32-NEXT: slli a1, a1, 21214; RV32-NEXT: add a1, a1, a21215; RV32-NEXT: add a1, sp, a11216; RV32-NEXT: addi a1, a1, 321217; RV32-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1218; RV32-NEXT: csrr a1, vlenb1219; RV32-NEXT: slli a1, a1, 41220; RV32-NEXT: mv a2, a11221; RV32-NEXT: slli a1, a1, 11222; RV32-NEXT: add a1, a1, a21223; RV32-NEXT: add a1, sp, a11224; RV32-NEXT: addi a1, a1, 321225; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1226; RV32-NEXT: addi a1, sp, 321227; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1228; RV32-NEXT: vsub.vv v8, v16, v81229; RV32-NEXT: csrr a1, vlenb1230; RV32-NEXT: slli a1, a1, 31231; RV32-NEXT: mv a2, a11232; RV32-NEXT: slli a1, a1, 11233; RV32-NEXT: add a2, a2, a11234; RV32-NEXT: slli a1, a1, 11235; RV32-NEXT: add a1, a1, a21236; RV32-NEXT: add a1, sp, a11237; RV32-NEXT: addi a1, a1, 321238; RV32-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1239; RV32-NEXT: vsub.vv v16, v24, v161240; RV32-NEXT: vs8r.v v0, (s0)1241; RV32-NEXT: add s1, s0, s11242; RV32-NEXT: csrr a1, vlenb1243; RV32-NEXT: slli a1, a1, 51244; RV32-NEXT: add a1, sp, a11245; RV32-NEXT: addi a1, a1, 321246; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload1247; RV32-NEXT: vs8r.v v24, (s1)1248; RV32-NEXT: add s5, s0, s51249; RV32-NEXT: csrr a1, vlenb1250; RV32-NEXT: slli a1, a1, 31251; RV32-NEXT: mv a2, a11252; RV32-NEXT: slli a1, a1, 21253; RV32-NEXT: add a1, a1, a21254; RV32-NEXT: add a1, sp, a11255; RV32-NEXT: addi a1, a1, 321256; RV32-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload1257; RV32-NEXT: vs8r.v v24, (s5)1258; RV32-NEXT: add s4, s0, s41259; RV32-NEXT: vs8r.v v16, (s4)1260; RV32-NEXT: add s9, s0, s91261; RV32-NEXT: add a0, s0, a01262; RV32-NEXT: add s7, s0, s71263; RV32-NEXT: add s0, s0, s81264; RV32-NEXT: vs8r.v v8, (s9)1265; RV32-NEXT: csrr a1, vlenb1266; RV32-NEXT: slli a1, a1, 41267; RV32-NEXT: mv a2, a11268; RV32-NEXT: slli a1, a1, 21269; RV32-NEXT: add a1, a1, a21270; RV32-NEXT: add a1, sp, a11271; RV32-NEXT: addi a1, a1, 321272; RV32-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1273; RV32-NEXT: vs8r.v v8, (a0)1274; RV32-NEXT: csrr a0, vlenb1275; RV32-NEXT: slli a0, a0, 31276; RV32-NEXT: mv a1, a01277; RV32-NEXT: slli a0, a0, 31278; RV32-NEXT: add a0, a0, a11279; RV32-NEXT: add a0, sp, a01280; RV32-NEXT: addi a0, a0, 321281; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1282; RV32-NEXT: vs8r.v v8, (s7)1283; RV32-NEXT: csrr a0, vlenb1284; RV32-NEXT: slli a0, a0, 61285; RV32-NEXT: add a0, sp, a01286; RV32-NEXT: addi a0, a0, 321287; RV32-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1288; RV32-NEXT: vs8r.v v8, (s0)1289; RV32-NEXT: csrr a0, vlenb1290; RV32-NEXT: slli a0, a0, 31291; RV32-NEXT: mv a1, a01292; RV32-NEXT: slli a0, a0, 11293; RV32-NEXT: add a1, a1, a01294; RV32-NEXT: slli a0, a0, 21295; RV32-NEXT: add a0, a0, a11296; RV32-NEXT: add sp, sp, a01297; RV32-NEXT: .cfi_def_cfa sp, 801298; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload1299; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload1300; RV32-NEXT: lw s1, 68(sp) # 4-byte Folded Reload1301; RV32-NEXT: lw s2, 64(sp) # 4-byte Folded Reload1302; RV32-NEXT: lw s3, 60(sp) # 4-byte Folded Reload1303; RV32-NEXT: lw s4, 56(sp) # 4-byte Folded Reload1304; RV32-NEXT: lw s5, 52(sp) # 4-byte Folded Reload1305; RV32-NEXT: lw s6, 48(sp) # 4-byte Folded Reload1306; RV32-NEXT: lw s7, 44(sp) # 4-byte Folded Reload1307; RV32-NEXT: lw s8, 40(sp) # 4-byte Folded Reload1308; RV32-NEXT: lw s9, 36(sp) # 4-byte Folded Reload1309; RV32-NEXT: .cfi_restore ra1310; RV32-NEXT: .cfi_restore s01311; RV32-NEXT: .cfi_restore s11312; RV32-NEXT: .cfi_restore s21313; RV32-NEXT: .cfi_restore s31314; RV32-NEXT: .cfi_restore s41315; RV32-NEXT: .cfi_restore s51316; RV32-NEXT: .cfi_restore s61317; RV32-NEXT: .cfi_restore s71318; RV32-NEXT: .cfi_restore s81319; RV32-NEXT: .cfi_restore s91320; RV32-NEXT: addi sp, sp, 801321; RV32-NEXT: .cfi_def_cfa_offset 01322; RV32-NEXT: ret1323;1324; RV64-LABEL: vsub_vv_nxv64i64:1325; RV64: # %bb.0:1326; RV64-NEXT: addi sp, sp, -1281327; RV64-NEXT: .cfi_def_cfa_offset 1281328; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill1329; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill1330; RV64-NEXT: sd s1, 104(sp) # 8-byte Folded Spill1331; RV64-NEXT: sd s2, 96(sp) # 8-byte Folded Spill1332; RV64-NEXT: sd s3, 88(sp) # 8-byte Folded Spill1333; RV64-NEXT: sd s4, 80(sp) # 8-byte Folded Spill1334; RV64-NEXT: sd s5, 72(sp) # 8-byte Folded Spill1335; RV64-NEXT: sd s6, 64(sp) # 8-byte Folded Spill1336; RV64-NEXT: sd s7, 56(sp) # 8-byte Folded Spill1337; RV64-NEXT: sd s8, 48(sp) # 8-byte Folded Spill1338; RV64-NEXT: sd s9, 40(sp) # 8-byte Folded Spill1339; RV64-NEXT: .cfi_offset ra, -81340; RV64-NEXT: .cfi_offset s0, -161341; RV64-NEXT: .cfi_offset s1, -241342; RV64-NEXT: .cfi_offset s2, -321343; RV64-NEXT: .cfi_offset s3, -401344; RV64-NEXT: .cfi_offset s4, -481345; RV64-NEXT: .cfi_offset s5, -561346; RV64-NEXT: .cfi_offset s6, -641347; RV64-NEXT: .cfi_offset s7, -721348; RV64-NEXT: .cfi_offset s8, -801349; RV64-NEXT: .cfi_offset s9, -881350; RV64-NEXT: csrr a2, vlenb1351; RV64-NEXT: slli a2, a2, 31352; RV64-NEXT: mv a3, a21353; RV64-NEXT: slli a2, a2, 11354; RV64-NEXT: add a3, a3, a21355; RV64-NEXT: slli a2, a2, 21356; RV64-NEXT: add a2, a2, a31357; RV64-NEXT: sub sp, sp, a21358; RV64-NEXT: .cfi_escape 0x0f, 0x0f, 0x72, 0x00, 0x11, 0x80, 0x01, 0x22, 0x11, 0xd8, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 128 + 88 * vlenb1359; RV64-NEXT: mv s2, a71360; RV64-NEXT: mv s3, a11361; RV64-NEXT: csrr a1, vlenb1362; RV64-NEXT: slli a1, a1, 61363; RV64-NEXT: add a1, sp, a11364; RV64-NEXT: addi a1, a1, 321365; RV64-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill1366; RV64-NEXT: csrr a1, vlenb1367; RV64-NEXT: slli a1, a1, 41368; RV64-NEXT: mv a2, a11369; RV64-NEXT: slli a1, a1, 21370; RV64-NEXT: add a1, a1, a21371; RV64-NEXT: add a1, sp, a11372; RV64-NEXT: addi a1, a1, 321373; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1374; RV64-NEXT: csrr s6, vlenb1375; RV64-NEXT: slli s7, s6, 41376; RV64-NEXT: slli s8, s6, 31377; RV64-NEXT: add a1, a7, s71378; RV64-NEXT: vl8re64.v v8, (a1)1379; RV64-NEXT: csrr a1, vlenb1380; RV64-NEXT: slli a1, a1, 31381; RV64-NEXT: mv a2, a11382; RV64-NEXT: slli a1, a1, 31383; RV64-NEXT: add a1, a1, a21384; RV64-NEXT: add a1, sp, a11385; RV64-NEXT: addi a1, a1, 321386; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1387; RV64-NEXT: add a1, a7, s81388; RV64-NEXT: vl8re64.v v8, (a1)1389; RV64-NEXT: csrr a1, vlenb1390; RV64-NEXT: slli a1, a1, 41391; RV64-NEXT: mv a2, a11392; RV64-NEXT: slli a1, a1, 11393; RV64-NEXT: add a1, a1, a21394; RV64-NEXT: add a1, sp, a11395; RV64-NEXT: addi a1, a1, 321396; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1397; RV64-NEXT: mv s0, a01398; RV64-NEXT: li a1, 561399; RV64-NEXT: mv a0, s61400; RV64-NEXT: call __muldi31401; RV64-NEXT: mv s1, a01402; RV64-NEXT: add a0, s2, a01403; RV64-NEXT: vl8re64.v v8, (a0)1404; RV64-NEXT: csrr a0, vlenb1405; RV64-NEXT: slli a0, a0, 51406; RV64-NEXT: add a0, sp, a01407; RV64-NEXT: addi a0, a0, 321408; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1409; RV64-NEXT: li a1, 401410; RV64-NEXT: mv a0, s61411; RV64-NEXT: call __muldi31412; RV64-NEXT: mv s4, a01413; RV64-NEXT: add a0, s3, a01414; RV64-NEXT: vl8re64.v v8, (a0)1415; RV64-NEXT: csrr a0, vlenb1416; RV64-NEXT: slli a0, a0, 31417; RV64-NEXT: mv a1, a01418; RV64-NEXT: slli a0, a0, 11419; RV64-NEXT: add a0, a0, a11420; RV64-NEXT: add a0, sp, a01421; RV64-NEXT: addi a0, a0, 321422; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1423; RV64-NEXT: li a1, 481424; RV64-NEXT: mv a0, s61425; RV64-NEXT: call __muldi31426; RV64-NEXT: mv s5, a01427; RV64-NEXT: add a0, s2, a01428; RV64-NEXT: slli s9, s6, 51429; RV64-NEXT: vl8re64.v v8, (a0)1430; RV64-NEXT: csrr a0, vlenb1431; RV64-NEXT: slli a0, a0, 31432; RV64-NEXT: mv a1, a01433; RV64-NEXT: slli a0, a0, 21434; RV64-NEXT: add a0, a0, a11435; RV64-NEXT: add a0, sp, a01436; RV64-NEXT: addi a0, a0, 321437; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1438; RV64-NEXT: add a0, s3, s91439; RV64-NEXT: vl8re64.v v8, (a0)1440; RV64-NEXT: csrr a0, vlenb1441; RV64-NEXT: slli a0, a0, 41442; RV64-NEXT: add a0, sp, a01443; RV64-NEXT: addi a0, a0, 321444; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1445; RV64-NEXT: add a0, s2, s41446; RV64-NEXT: vl8re64.v v8, (a0)1447; RV64-NEXT: csrr a0, vlenb1448; RV64-NEXT: slli a0, a0, 31449; RV64-NEXT: mv a1, a01450; RV64-NEXT: slli a0, a0, 11451; RV64-NEXT: add a1, a1, a01452; RV64-NEXT: slli a0, a0, 11453; RV64-NEXT: add a0, a0, a11454; RV64-NEXT: add a0, sp, a01455; RV64-NEXT: addi a0, a0, 321456; RV64-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill1457; RV64-NEXT: li a1, 241458; RV64-NEXT: mv a0, s61459; RV64-NEXT: call __muldi31460; RV64-NEXT: csrr a1, vlenb1461; RV64-NEXT: slli a1, a1, 31462; RV64-NEXT: mv a2, a11463; RV64-NEXT: slli a1, a1, 21464; RV64-NEXT: add a1, a1, a21465; RV64-NEXT: add a1, sp, a11466; RV64-NEXT: addi a1, a1, 321467; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1468; RV64-NEXT: csrr a1, vlenb1469; RV64-NEXT: slli a1, a1, 41470; RV64-NEXT: add a1, sp, a11471; RV64-NEXT: addi a1, a1, 321472; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1473; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1474; RV64-NEXT: vsub.vv v8, v16, v81475; RV64-NEXT: csrr a1, vlenb1476; RV64-NEXT: slli a1, a1, 31477; RV64-NEXT: mv a2, a11478; RV64-NEXT: slli a1, a1, 21479; RV64-NEXT: add a1, a1, a21480; RV64-NEXT: add a1, sp, a11481; RV64-NEXT: addi a1, a1, 321482; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1483; RV64-NEXT: csrr a1, vlenb1484; RV64-NEXT: slli a1, a1, 51485; RV64-NEXT: add a1, sp, a11486; RV64-NEXT: addi a1, a1, 321487; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1488; RV64-NEXT: csrr a1, vlenb1489; RV64-NEXT: slli a1, a1, 31490; RV64-NEXT: mv a2, a11491; RV64-NEXT: slli a1, a1, 11492; RV64-NEXT: add a1, a1, a21493; RV64-NEXT: add a1, sp, a11494; RV64-NEXT: addi a1, a1, 321495; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1496; RV64-NEXT: vsub.vv v8, v16, v81497; RV64-NEXT: csrr a1, vlenb1498; RV64-NEXT: slli a1, a1, 51499; RV64-NEXT: add a1, sp, a11500; RV64-NEXT: addi a1, a1, 321501; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1502; RV64-NEXT: csrr a1, vlenb1503; RV64-NEXT: slli a1, a1, 61504; RV64-NEXT: add a1, sp, a11505; RV64-NEXT: addi a1, a1, 321506; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1507; RV64-NEXT: csrr a1, vlenb1508; RV64-NEXT: slli a1, a1, 41509; RV64-NEXT: mv a2, a11510; RV64-NEXT: slli a1, a1, 11511; RV64-NEXT: add a1, a1, a21512; RV64-NEXT: add a1, sp, a11513; RV64-NEXT: addi a1, a1, 321514; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1515; RV64-NEXT: vsub.vv v8, v8, v161516; RV64-NEXT: csrr a1, vlenb1517; RV64-NEXT: slli a1, a1, 61518; RV64-NEXT: add a1, sp, a11519; RV64-NEXT: addi a1, a1, 321520; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1521; RV64-NEXT: vl8re64.v v8, (s3)1522; RV64-NEXT: csrr a1, vlenb1523; RV64-NEXT: slli a1, a1, 31524; RV64-NEXT: mv a2, a11525; RV64-NEXT: slli a1, a1, 31526; RV64-NEXT: add a1, a1, a21527; RV64-NEXT: add a1, sp, a11528; RV64-NEXT: addi a1, a1, 321529; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1530; RV64-NEXT: vsub.vv v8, v8, v161531; RV64-NEXT: csrr a1, vlenb1532; RV64-NEXT: slli a1, a1, 31533; RV64-NEXT: mv a2, a11534; RV64-NEXT: slli a1, a1, 31535; RV64-NEXT: add a1, a1, a21536; RV64-NEXT: add a1, sp, a11537; RV64-NEXT: addi a1, a1, 321538; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1539; RV64-NEXT: add a1, s3, a01540; RV64-NEXT: add a2, s2, s91541; RV64-NEXT: add a3, s3, s71542; RV64-NEXT: add a4, s2, a01543; RV64-NEXT: add s3, s3, s81544; RV64-NEXT: vl8re64.v v8, (s2)1545; RV64-NEXT: csrr a5, vlenb1546; RV64-NEXT: slli a5, a5, 31547; RV64-NEXT: mv a6, a51548; RV64-NEXT: slli a5, a5, 11549; RV64-NEXT: add a5, a5, a61550; RV64-NEXT: add a5, sp, a51551; RV64-NEXT: addi a5, a5, 321552; RV64-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill1553; RV64-NEXT: vl8re64.v v8, (a2)1554; RV64-NEXT: csrr a2, vlenb1555; RV64-NEXT: slli a2, a2, 41556; RV64-NEXT: mv a5, a21557; RV64-NEXT: slli a2, a2, 11558; RV64-NEXT: add a2, a2, a51559; RV64-NEXT: add a2, sp, a21560; RV64-NEXT: addi a2, a2, 321561; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1562; RV64-NEXT: vl8re64.v v8, (a4)1563; RV64-NEXT: csrr a2, vlenb1564; RV64-NEXT: slli a2, a2, 41565; RV64-NEXT: add a2, sp, a21566; RV64-NEXT: addi a2, a2, 321567; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1568; RV64-NEXT: vl8re64.v v8, (s3)1569; RV64-NEXT: csrr a2, vlenb1570; RV64-NEXT: slli a2, a2, 31571; RV64-NEXT: add a2, sp, a21572; RV64-NEXT: addi a2, a2, 321573; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1574; RV64-NEXT: vl8re64.v v8, (a3)1575; RV64-NEXT: addi a2, sp, 321576; RV64-NEXT: vs8r.v v8, (a2) # vscale x 64-byte Folded Spill1577; RV64-NEXT: vl8re64.v v24, (a1)1578; RV64-NEXT: csrr a1, vlenb1579; RV64-NEXT: slli a1, a1, 41580; RV64-NEXT: mv a2, a11581; RV64-NEXT: slli a1, a1, 21582; RV64-NEXT: add a1, a1, a21583; RV64-NEXT: add a1, sp, a11584; RV64-NEXT: addi a1, a1, 321585; RV64-NEXT: vl8r.v v0, (a1) # vscale x 64-byte Folded Reload1586; RV64-NEXT: csrr a1, vlenb1587; RV64-NEXT: slli a1, a1, 31588; RV64-NEXT: mv a2, a11589; RV64-NEXT: slli a1, a1, 11590; RV64-NEXT: add a1, a1, a21591; RV64-NEXT: add a1, sp, a11592; RV64-NEXT: addi a1, a1, 321593; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1594; RV64-NEXT: vsub.vv v0, v0, v81595; RV64-NEXT: csrr a1, vlenb1596; RV64-NEXT: slli a1, a1, 41597; RV64-NEXT: add a1, sp, a11598; RV64-NEXT: addi a1, a1, 321599; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1600; RV64-NEXT: csrr a1, vlenb1601; RV64-NEXT: slli a1, a1, 31602; RV64-NEXT: add a1, sp, a11603; RV64-NEXT: addi a1, a1, 321604; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1605; RV64-NEXT: vsub.vv v8, v16, v81606; RV64-NEXT: csrr a1, vlenb1607; RV64-NEXT: slli a1, a1, 41608; RV64-NEXT: mv a2, a11609; RV64-NEXT: slli a1, a1, 21610; RV64-NEXT: add a1, a1, a21611; RV64-NEXT: add a1, sp, a11612; RV64-NEXT: addi a1, a1, 321613; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill1614; RV64-NEXT: csrr a1, vlenb1615; RV64-NEXT: slli a1, a1, 41616; RV64-NEXT: mv a2, a11617; RV64-NEXT: slli a1, a1, 11618; RV64-NEXT: add a1, a1, a21619; RV64-NEXT: add a1, sp, a11620; RV64-NEXT: addi a1, a1, 321621; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1622; RV64-NEXT: addi a1, sp, 321623; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1624; RV64-NEXT: vsub.vv v8, v16, v81625; RV64-NEXT: csrr a1, vlenb1626; RV64-NEXT: slli a1, a1, 31627; RV64-NEXT: mv a2, a11628; RV64-NEXT: slli a1, a1, 11629; RV64-NEXT: add a2, a2, a11630; RV64-NEXT: slli a1, a1, 11631; RV64-NEXT: add a1, a1, a21632; RV64-NEXT: add a1, sp, a11633; RV64-NEXT: addi a1, a1, 321634; RV64-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload1635; RV64-NEXT: vsub.vv v16, v24, v161636; RV64-NEXT: vs8r.v v0, (s0)1637; RV64-NEXT: add s1, s0, s11638; RV64-NEXT: csrr a1, vlenb1639; RV64-NEXT: slli a1, a1, 51640; RV64-NEXT: add a1, sp, a11641; RV64-NEXT: addi a1, a1, 321642; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload1643; RV64-NEXT: vs8r.v v24, (s1)1644; RV64-NEXT: add s5, s0, s51645; RV64-NEXT: csrr a1, vlenb1646; RV64-NEXT: slli a1, a1, 31647; RV64-NEXT: mv a2, a11648; RV64-NEXT: slli a1, a1, 21649; RV64-NEXT: add a1, a1, a21650; RV64-NEXT: add a1, sp, a11651; RV64-NEXT: addi a1, a1, 321652; RV64-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload1653; RV64-NEXT: vs8r.v v24, (s5)1654; RV64-NEXT: add s4, s0, s41655; RV64-NEXT: vs8r.v v16, (s4)1656; RV64-NEXT: add s9, s0, s91657; RV64-NEXT: add a0, s0, a01658; RV64-NEXT: add s7, s0, s71659; RV64-NEXT: add s0, s0, s81660; RV64-NEXT: vs8r.v v8, (s9)1661; RV64-NEXT: csrr a1, vlenb1662; RV64-NEXT: slli a1, a1, 41663; RV64-NEXT: mv a2, a11664; RV64-NEXT: slli a1, a1, 21665; RV64-NEXT: add a1, a1, a21666; RV64-NEXT: add a1, sp, a11667; RV64-NEXT: addi a1, a1, 321668; RV64-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload1669; RV64-NEXT: vs8r.v v8, (a0)1670; RV64-NEXT: csrr a0, vlenb1671; RV64-NEXT: slli a0, a0, 31672; RV64-NEXT: mv a1, a01673; RV64-NEXT: slli a0, a0, 31674; RV64-NEXT: add a0, a0, a11675; RV64-NEXT: add a0, sp, a01676; RV64-NEXT: addi a0, a0, 321677; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1678; RV64-NEXT: vs8r.v v8, (s7)1679; RV64-NEXT: csrr a0, vlenb1680; RV64-NEXT: slli a0, a0, 61681; RV64-NEXT: add a0, sp, a01682; RV64-NEXT: addi a0, a0, 321683; RV64-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload1684; RV64-NEXT: vs8r.v v8, (s0)1685; RV64-NEXT: csrr a0, vlenb1686; RV64-NEXT: slli a0, a0, 31687; RV64-NEXT: mv a1, a01688; RV64-NEXT: slli a0, a0, 11689; RV64-NEXT: add a1, a1, a01690; RV64-NEXT: slli a0, a0, 21691; RV64-NEXT: add a0, a0, a11692; RV64-NEXT: add sp, sp, a01693; RV64-NEXT: .cfi_def_cfa sp, 1281694; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload1695; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload1696; RV64-NEXT: ld s1, 104(sp) # 8-byte Folded Reload1697; RV64-NEXT: ld s2, 96(sp) # 8-byte Folded Reload1698; RV64-NEXT: ld s3, 88(sp) # 8-byte Folded Reload1699; RV64-NEXT: ld s4, 80(sp) # 8-byte Folded Reload1700; RV64-NEXT: ld s5, 72(sp) # 8-byte Folded Reload1701; RV64-NEXT: ld s6, 64(sp) # 8-byte Folded Reload1702; RV64-NEXT: ld s7, 56(sp) # 8-byte Folded Reload1703; RV64-NEXT: ld s8, 48(sp) # 8-byte Folded Reload1704; RV64-NEXT: ld s9, 40(sp) # 8-byte Folded Reload1705; RV64-NEXT: .cfi_restore ra1706; RV64-NEXT: .cfi_restore s01707; RV64-NEXT: .cfi_restore s11708; RV64-NEXT: .cfi_restore s21709; RV64-NEXT: .cfi_restore s31710; RV64-NEXT: .cfi_restore s41711; RV64-NEXT: .cfi_restore s51712; RV64-NEXT: .cfi_restore s61713; RV64-NEXT: .cfi_restore s71714; RV64-NEXT: .cfi_restore s81715; RV64-NEXT: .cfi_restore s91716; RV64-NEXT: addi sp, sp, 1281717; RV64-NEXT: .cfi_def_cfa_offset 01718; RV64-NEXT: ret1719 %vc = sub <vscale x 64 x i64> %va, %vb1720 ret <vscale x 64 x i64> %vc1721}1722