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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vsub_vv_nxv1i8_nxv1i8_nxv1i8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    vsub.vv v8, v8, v912; CHECK-NEXT:    ret13entry:14  %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.nxv1i8(15    <vscale x 1 x i8> poison,16    <vscale x 1 x i8> %0,17    <vscale x 1 x i8> %1,18    iXLen %2)19 20  ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i8_nxv1i8_nxv1i8:25; CHECK:       # %bb.0: # %entry26; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu27; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t28; CHECK-NEXT:    ret29entry:30  %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.nxv1i8(31    <vscale x 1 x i8> %0,32    <vscale x 1 x i8> %1,33    <vscale x 1 x i8> %2,34    <vscale x 1 x i1> %3,35    iXLen %4, iXLen 1)36 37  ret <vscale x 1 x i8> %a38}39 40define <vscale x 2 x i8> @intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vsub_vv_nxv2i8_nxv2i8_nxv2i8:42; CHECK:       # %bb.0: # %entry43; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma44; CHECK-NEXT:    vsub.vv v8, v8, v945; CHECK-NEXT:    ret46entry:47  %a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.nxv2i8(48    <vscale x 2 x i8> poison,49    <vscale x 2 x i8> %0,50    <vscale x 2 x i8> %1,51    iXLen %2)52 53  ret <vscale x 2 x i8> %a54}55 56define <vscale x 2 x i8> @intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i8_nxv2i8_nxv2i8:58; CHECK:       # %bb.0: # %entry59; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu60; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t61; CHECK-NEXT:    ret62entry:63  %a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.nxv2i8(64    <vscale x 2 x i8> %0,65    <vscale x 2 x i8> %1,66    <vscale x 2 x i8> %2,67    <vscale x 2 x i1> %3,68    iXLen %4, iXLen 1)69 70  ret <vscale x 2 x i8> %a71}72 73define <vscale x 4 x i8> @intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vsub_vv_nxv4i8_nxv4i8_nxv4i8:75; CHECK:       # %bb.0: # %entry76; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma77; CHECK-NEXT:    vsub.vv v8, v8, v978; CHECK-NEXT:    ret79entry:80  %a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.nxv4i8(81    <vscale x 4 x i8> poison,82    <vscale x 4 x i8> %0,83    <vscale x 4 x i8> %1,84    iXLen %2)85 86  ret <vscale x 4 x i8> %a87}88 89define <vscale x 4 x i8> @intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i8_nxv4i8_nxv4i8:91; CHECK:       # %bb.0: # %entry92; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu93; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t94; CHECK-NEXT:    ret95entry:96  %a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.nxv4i8(97    <vscale x 4 x i8> %0,98    <vscale x 4 x i8> %1,99    <vscale x 4 x i8> %2,100    <vscale x 4 x i1> %3,101    iXLen %4, iXLen 1)102 103  ret <vscale x 4 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vsub_vv_nxv8i8_nxv8i8_nxv8i8:108; CHECK:       # %bb.0: # %entry109; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma110; CHECK-NEXT:    vsub.vv v8, v8, v9111; CHECK-NEXT:    ret112entry:113  %a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.nxv8i8(114    <vscale x 8 x i8> poison,115    <vscale x 8 x i8> %0,116    <vscale x 8 x i8> %1,117    iXLen %2)118 119  ret <vscale x 8 x i8> %a120}121 122define <vscale x 8 x i8> @intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i8_nxv8i8_nxv8i8:124; CHECK:       # %bb.0: # %entry125; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu126; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t127; CHECK-NEXT:    ret128entry:129  %a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.nxv8i8(130    <vscale x 8 x i8> %0,131    <vscale x 8 x i8> %1,132    <vscale x 8 x i8> %2,133    <vscale x 8 x i1> %3,134    iXLen %4, iXLen 1)135 136  ret <vscale x 8 x i8> %a137}138 139define <vscale x 16 x i8> @intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vsub_vv_nxv16i8_nxv16i8_nxv16i8:141; CHECK:       # %bb.0: # %entry142; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma143; CHECK-NEXT:    vsub.vv v8, v8, v10144; CHECK-NEXT:    ret145entry:146  %a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.nxv16i8(147    <vscale x 16 x i8> poison,148    <vscale x 16 x i8> %0,149    <vscale x 16 x i8> %1,150    iXLen %2)151 152  ret <vscale x 16 x i8> %a153}154 155define <vscale x 16 x i8> @intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i8_nxv16i8_nxv16i8:157; CHECK:       # %bb.0: # %entry158; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu159; CHECK-NEXT:    vsub.vv v8, v10, v12, v0.t160; CHECK-NEXT:    ret161entry:162  %a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.nxv16i8(163    <vscale x 16 x i8> %0,164    <vscale x 16 x i8> %1,165    <vscale x 16 x i8> %2,166    <vscale x 16 x i1> %3,167    iXLen %4, iXLen 1)168 169  ret <vscale x 16 x i8> %a170}171 172define <vscale x 32 x i8> @intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vsub_vv_nxv32i8_nxv32i8_nxv32i8:174; CHECK:       # %bb.0: # %entry175; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma176; CHECK-NEXT:    vsub.vv v8, v8, v12177; CHECK-NEXT:    ret178entry:179  %a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.nxv32i8(180    <vscale x 32 x i8> poison,181    <vscale x 32 x i8> %0,182    <vscale x 32 x i8> %1,183    iXLen %2)184 185  ret <vscale x 32 x i8> %a186}187 188define <vscale x 32 x i8> @intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i8_nxv32i8_nxv32i8:190; CHECK:       # %bb.0: # %entry191; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu192; CHECK-NEXT:    vsub.vv v8, v12, v16, v0.t193; CHECK-NEXT:    ret194entry:195  %a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.nxv32i8(196    <vscale x 32 x i8> %0,197    <vscale x 32 x i8> %1,198    <vscale x 32 x i8> %2,199    <vscale x 32 x i1> %3,200    iXLen %4, iXLen 1)201 202  ret <vscale x 32 x i8> %a203}204 205define <vscale x 64 x i8> @intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {206; CHECK-LABEL: intrinsic_vsub_vv_nxv64i8_nxv64i8_nxv64i8:207; CHECK:       # %bb.0: # %entry208; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma209; CHECK-NEXT:    vsub.vv v8, v8, v16210; CHECK-NEXT:    ret211entry:212  %a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.nxv64i8(213    <vscale x 64 x i8> poison,214    <vscale x 64 x i8> %0,215    <vscale x 64 x i8> %1,216    iXLen %2)217 218  ret <vscale x 64 x i8> %a219}220 221define <vscale x 64 x i8> @intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv64i8_nxv64i8_nxv64i8:223; CHECK:       # %bb.0: # %entry224; CHECK-NEXT:    vl8r.v v24, (a0)225; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu226; CHECK-NEXT:    vsub.vv v8, v16, v24, v0.t227; CHECK-NEXT:    ret228entry:229  %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.nxv64i8(230    <vscale x 64 x i8> %0,231    <vscale x 64 x i8> %1,232    <vscale x 64 x i8> %2,233    <vscale x 64 x i1> %3,234    iXLen %4, iXLen 1)235 236  ret <vscale x 64 x i8> %a237}238 239define <vscale x 1 x i16> @intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {240; CHECK-LABEL: intrinsic_vsub_vv_nxv1i16_nxv1i16_nxv1i16:241; CHECK:       # %bb.0: # %entry242; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma243; CHECK-NEXT:    vsub.vv v8, v8, v9244; CHECK-NEXT:    ret245entry:246  %a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.nxv1i16(247    <vscale x 1 x i16> poison,248    <vscale x 1 x i16> %0,249    <vscale x 1 x i16> %1,250    iXLen %2)251 252  ret <vscale x 1 x i16> %a253}254 255define <vscale x 1 x i16> @intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {256; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i16_nxv1i16_nxv1i16:257; CHECK:       # %bb.0: # %entry258; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu259; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t260; CHECK-NEXT:    ret261entry:262  %a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.nxv1i16(263    <vscale x 1 x i16> %0,264    <vscale x 1 x i16> %1,265    <vscale x 1 x i16> %2,266    <vscale x 1 x i1> %3,267    iXLen %4, iXLen 1)268 269  ret <vscale x 1 x i16> %a270}271 272define <vscale x 2 x i16> @intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {273; CHECK-LABEL: intrinsic_vsub_vv_nxv2i16_nxv2i16_nxv2i16:274; CHECK:       # %bb.0: # %entry275; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma276; CHECK-NEXT:    vsub.vv v8, v8, v9277; CHECK-NEXT:    ret278entry:279  %a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.nxv2i16(280    <vscale x 2 x i16> poison,281    <vscale x 2 x i16> %0,282    <vscale x 2 x i16> %1,283    iXLen %2)284 285  ret <vscale x 2 x i16> %a286}287 288define <vscale x 2 x i16> @intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {289; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i16_nxv2i16_nxv2i16:290; CHECK:       # %bb.0: # %entry291; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu292; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t293; CHECK-NEXT:    ret294entry:295  %a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.nxv2i16(296    <vscale x 2 x i16> %0,297    <vscale x 2 x i16> %1,298    <vscale x 2 x i16> %2,299    <vscale x 2 x i1> %3,300    iXLen %4, iXLen 1)301 302  ret <vscale x 2 x i16> %a303}304 305define <vscale x 4 x i16> @intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {306; CHECK-LABEL: intrinsic_vsub_vv_nxv4i16_nxv4i16_nxv4i16:307; CHECK:       # %bb.0: # %entry308; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma309; CHECK-NEXT:    vsub.vv v8, v8, v9310; CHECK-NEXT:    ret311entry:312  %a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.nxv4i16(313    <vscale x 4 x i16> poison,314    <vscale x 4 x i16> %0,315    <vscale x 4 x i16> %1,316    iXLen %2)317 318  ret <vscale x 4 x i16> %a319}320 321define <vscale x 4 x i16> @intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i16_nxv4i16_nxv4i16:323; CHECK:       # %bb.0: # %entry324; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu325; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t326; CHECK-NEXT:    ret327entry:328  %a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.nxv4i16(329    <vscale x 4 x i16> %0,330    <vscale x 4 x i16> %1,331    <vscale x 4 x i16> %2,332    <vscale x 4 x i1> %3,333    iXLen %4, iXLen 1)334 335  ret <vscale x 4 x i16> %a336}337 338define <vscale x 8 x i16> @intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {339; CHECK-LABEL: intrinsic_vsub_vv_nxv8i16_nxv8i16_nxv8i16:340; CHECK:       # %bb.0: # %entry341; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma342; CHECK-NEXT:    vsub.vv v8, v8, v10343; CHECK-NEXT:    ret344entry:345  %a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.nxv8i16(346    <vscale x 8 x i16> poison,347    <vscale x 8 x i16> %0,348    <vscale x 8 x i16> %1,349    iXLen %2)350 351  ret <vscale x 8 x i16> %a352}353 354define <vscale x 8 x i16> @intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {355; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i16_nxv8i16_nxv8i16:356; CHECK:       # %bb.0: # %entry357; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu358; CHECK-NEXT:    vsub.vv v8, v10, v12, v0.t359; CHECK-NEXT:    ret360entry:361  %a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.nxv8i16(362    <vscale x 8 x i16> %0,363    <vscale x 8 x i16> %1,364    <vscale x 8 x i16> %2,365    <vscale x 8 x i1> %3,366    iXLen %4, iXLen 1)367 368  ret <vscale x 8 x i16> %a369}370 371define <vscale x 16 x i16> @intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {372; CHECK-LABEL: intrinsic_vsub_vv_nxv16i16_nxv16i16_nxv16i16:373; CHECK:       # %bb.0: # %entry374; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma375; CHECK-NEXT:    vsub.vv v8, v8, v12376; CHECK-NEXT:    ret377entry:378  %a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.nxv16i16(379    <vscale x 16 x i16> poison,380    <vscale x 16 x i16> %0,381    <vscale x 16 x i16> %1,382    iXLen %2)383 384  ret <vscale x 16 x i16> %a385}386 387define <vscale x 16 x i16> @intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {388; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i16_nxv16i16_nxv16i16:389; CHECK:       # %bb.0: # %entry390; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu391; CHECK-NEXT:    vsub.vv v8, v12, v16, v0.t392; CHECK-NEXT:    ret393entry:394  %a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.nxv16i16(395    <vscale x 16 x i16> %0,396    <vscale x 16 x i16> %1,397    <vscale x 16 x i16> %2,398    <vscale x 16 x i1> %3,399    iXLen %4, iXLen 1)400 401  ret <vscale x 16 x i16> %a402}403 404define <vscale x 32 x i16> @intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {405; CHECK-LABEL: intrinsic_vsub_vv_nxv32i16_nxv32i16_nxv32i16:406; CHECK:       # %bb.0: # %entry407; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma408; CHECK-NEXT:    vsub.vv v8, v8, v16409; CHECK-NEXT:    ret410entry:411  %a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.nxv32i16(412    <vscale x 32 x i16> poison,413    <vscale x 32 x i16> %0,414    <vscale x 32 x i16> %1,415    iXLen %2)416 417  ret <vscale x 32 x i16> %a418}419 420define <vscale x 32 x i16> @intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {421; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv32i16_nxv32i16_nxv32i16:422; CHECK:       # %bb.0: # %entry423; CHECK-NEXT:    vl8re16.v v24, (a0)424; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu425; CHECK-NEXT:    vsub.vv v8, v16, v24, v0.t426; CHECK-NEXT:    ret427entry:428  %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.nxv32i16(429    <vscale x 32 x i16> %0,430    <vscale x 32 x i16> %1,431    <vscale x 32 x i16> %2,432    <vscale x 32 x i1> %3,433    iXLen %4, iXLen 1)434 435  ret <vscale x 32 x i16> %a436}437 438define <vscale x 1 x i32> @intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {439; CHECK-LABEL: intrinsic_vsub_vv_nxv1i32_nxv1i32_nxv1i32:440; CHECK:       # %bb.0: # %entry441; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma442; CHECK-NEXT:    vsub.vv v8, v8, v9443; CHECK-NEXT:    ret444entry:445  %a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.nxv1i32(446    <vscale x 1 x i32> poison,447    <vscale x 1 x i32> %0,448    <vscale x 1 x i32> %1,449    iXLen %2)450 451  ret <vscale x 1 x i32> %a452}453 454define <vscale x 1 x i32> @intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {455; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i32_nxv1i32_nxv1i32:456; CHECK:       # %bb.0: # %entry457; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu458; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t459; CHECK-NEXT:    ret460entry:461  %a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.nxv1i32(462    <vscale x 1 x i32> %0,463    <vscale x 1 x i32> %1,464    <vscale x 1 x i32> %2,465    <vscale x 1 x i1> %3,466    iXLen %4, iXLen 1)467 468  ret <vscale x 1 x i32> %a469}470 471define <vscale x 2 x i32> @intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {472; CHECK-LABEL: intrinsic_vsub_vv_nxv2i32_nxv2i32_nxv2i32:473; CHECK:       # %bb.0: # %entry474; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma475; CHECK-NEXT:    vsub.vv v8, v8, v9476; CHECK-NEXT:    ret477entry:478  %a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.nxv2i32(479    <vscale x 2 x i32> poison,480    <vscale x 2 x i32> %0,481    <vscale x 2 x i32> %1,482    iXLen %2)483 484  ret <vscale x 2 x i32> %a485}486 487define <vscale x 2 x i32> @intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {488; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i32_nxv2i32_nxv2i32:489; CHECK:       # %bb.0: # %entry490; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu491; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t492; CHECK-NEXT:    ret493entry:494  %a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.nxv2i32(495    <vscale x 2 x i32> %0,496    <vscale x 2 x i32> %1,497    <vscale x 2 x i32> %2,498    <vscale x 2 x i1> %3,499    iXLen %4, iXLen 1)500 501  ret <vscale x 2 x i32> %a502}503 504define <vscale x 4 x i32> @intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {505; CHECK-LABEL: intrinsic_vsub_vv_nxv4i32_nxv4i32_nxv4i32:506; CHECK:       # %bb.0: # %entry507; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma508; CHECK-NEXT:    vsub.vv v8, v8, v10509; CHECK-NEXT:    ret510entry:511  %a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.nxv4i32(512    <vscale x 4 x i32> poison,513    <vscale x 4 x i32> %0,514    <vscale x 4 x i32> %1,515    iXLen %2)516 517  ret <vscale x 4 x i32> %a518}519 520define <vscale x 4 x i32> @intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {521; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i32_nxv4i32_nxv4i32:522; CHECK:       # %bb.0: # %entry523; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu524; CHECK-NEXT:    vsub.vv v8, v10, v12, v0.t525; CHECK-NEXT:    ret526entry:527  %a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.nxv4i32(528    <vscale x 4 x i32> %0,529    <vscale x 4 x i32> %1,530    <vscale x 4 x i32> %2,531    <vscale x 4 x i1> %3,532    iXLen %4, iXLen 1)533 534  ret <vscale x 4 x i32> %a535}536 537define <vscale x 8 x i32> @intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {538; CHECK-LABEL: intrinsic_vsub_vv_nxv8i32_nxv8i32_nxv8i32:539; CHECK:       # %bb.0: # %entry540; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma541; CHECK-NEXT:    vsub.vv v8, v8, v12542; CHECK-NEXT:    ret543entry:544  %a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.nxv8i32(545    <vscale x 8 x i32> poison,546    <vscale x 8 x i32> %0,547    <vscale x 8 x i32> %1,548    iXLen %2)549 550  ret <vscale x 8 x i32> %a551}552 553define <vscale x 8 x i32> @intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {554; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i32_nxv8i32_nxv8i32:555; CHECK:       # %bb.0: # %entry556; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu557; CHECK-NEXT:    vsub.vv v8, v12, v16, v0.t558; CHECK-NEXT:    ret559entry:560  %a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.nxv8i32(561    <vscale x 8 x i32> %0,562    <vscale x 8 x i32> %1,563    <vscale x 8 x i32> %2,564    <vscale x 8 x i1> %3,565    iXLen %4, iXLen 1)566 567  ret <vscale x 8 x i32> %a568}569 570define <vscale x 16 x i32> @intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {571; CHECK-LABEL: intrinsic_vsub_vv_nxv16i32_nxv16i32_nxv16i32:572; CHECK:       # %bb.0: # %entry573; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma574; CHECK-NEXT:    vsub.vv v8, v8, v16575; CHECK-NEXT:    ret576entry:577  %a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.nxv16i32(578    <vscale x 16 x i32> poison,579    <vscale x 16 x i32> %0,580    <vscale x 16 x i32> %1,581    iXLen %2)582 583  ret <vscale x 16 x i32> %a584}585 586define <vscale x 16 x i32> @intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {587; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv16i32_nxv16i32_nxv16i32:588; CHECK:       # %bb.0: # %entry589; CHECK-NEXT:    vl8re32.v v24, (a0)590; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu591; CHECK-NEXT:    vsub.vv v8, v16, v24, v0.t592; CHECK-NEXT:    ret593entry:594  %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.nxv16i32(595    <vscale x 16 x i32> %0,596    <vscale x 16 x i32> %1,597    <vscale x 16 x i32> %2,598    <vscale x 16 x i1> %3,599    iXLen %4, iXLen 1)600 601  ret <vscale x 16 x i32> %a602}603 604define <vscale x 1 x i64> @intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {605; CHECK-LABEL: intrinsic_vsub_vv_nxv1i64_nxv1i64_nxv1i64:606; CHECK:       # %bb.0: # %entry607; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma608; CHECK-NEXT:    vsub.vv v8, v8, v9609; CHECK-NEXT:    ret610entry:611  %a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64(612    <vscale x 1 x i64> poison,613    <vscale x 1 x i64> %0,614    <vscale x 1 x i64> %1,615    iXLen %2)616 617  ret <vscale x 1 x i64> %a618}619 620define <vscale x 1 x i64> @intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {621; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv1i64_nxv1i64_nxv1i64:622; CHECK:       # %bb.0: # %entry623; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu624; CHECK-NEXT:    vsub.vv v8, v9, v10, v0.t625; CHECK-NEXT:    ret626entry:627  %a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.nxv1i64(628    <vscale x 1 x i64> %0,629    <vscale x 1 x i64> %1,630    <vscale x 1 x i64> %2,631    <vscale x 1 x i1> %3,632    iXLen %4, iXLen 1)633 634  ret <vscale x 1 x i64> %a635}636 637define <vscale x 2 x i64> @intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {638; CHECK-LABEL: intrinsic_vsub_vv_nxv2i64_nxv2i64_nxv2i64:639; CHECK:       # %bb.0: # %entry640; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma641; CHECK-NEXT:    vsub.vv v8, v8, v10642; CHECK-NEXT:    ret643entry:644  %a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.nxv2i64(645    <vscale x 2 x i64> poison,646    <vscale x 2 x i64> %0,647    <vscale x 2 x i64> %1,648    iXLen %2)649 650  ret <vscale x 2 x i64> %a651}652 653define <vscale x 2 x i64> @intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {654; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv2i64_nxv2i64_nxv2i64:655; CHECK:       # %bb.0: # %entry656; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu657; CHECK-NEXT:    vsub.vv v8, v10, v12, v0.t658; CHECK-NEXT:    ret659entry:660  %a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.nxv2i64(661    <vscale x 2 x i64> %0,662    <vscale x 2 x i64> %1,663    <vscale x 2 x i64> %2,664    <vscale x 2 x i1> %3,665    iXLen %4, iXLen 1)666 667  ret <vscale x 2 x i64> %a668}669 670define <vscale x 4 x i64> @intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vsub_vv_nxv4i64_nxv4i64_nxv4i64:672; CHECK:       # %bb.0: # %entry673; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma674; CHECK-NEXT:    vsub.vv v8, v8, v12675; CHECK-NEXT:    ret676entry:677  %a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.nxv4i64(678    <vscale x 4 x i64> poison,679    <vscale x 4 x i64> %0,680    <vscale x 4 x i64> %1,681    iXLen %2)682 683  ret <vscale x 4 x i64> %a684}685 686define <vscale x 4 x i64> @intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {687; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv4i64_nxv4i64_nxv4i64:688; CHECK:       # %bb.0: # %entry689; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu690; CHECK-NEXT:    vsub.vv v8, v12, v16, v0.t691; CHECK-NEXT:    ret692entry:693  %a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.nxv4i64(694    <vscale x 4 x i64> %0,695    <vscale x 4 x i64> %1,696    <vscale x 4 x i64> %2,697    <vscale x 4 x i1> %3,698    iXLen %4, iXLen 1)699 700  ret <vscale x 4 x i64> %a701}702 703define <vscale x 8 x i64> @intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {704; CHECK-LABEL: intrinsic_vsub_vv_nxv8i64_nxv8i64_nxv8i64:705; CHECK:       # %bb.0: # %entry706; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma707; CHECK-NEXT:    vsub.vv v8, v8, v16708; CHECK-NEXT:    ret709entry:710  %a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.nxv8i64(711    <vscale x 8 x i64> poison,712    <vscale x 8 x i64> %0,713    <vscale x 8 x i64> %1,714    iXLen %2)715 716  ret <vscale x 8 x i64> %a717}718 719define <vscale x 8 x i64> @intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {720; CHECK-LABEL: intrinsic_vsub_mask_vv_nxv8i64_nxv8i64_nxv8i64:721; CHECK:       # %bb.0: # %entry722; CHECK-NEXT:    vl8re64.v v24, (a0)723; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu724; CHECK-NEXT:    vsub.vv v8, v16, v24, v0.t725; CHECK-NEXT:    ret726entry:727  %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.nxv8i64(728    <vscale x 8 x i64> %0,729    <vscale x 8 x i64> %1,730    <vscale x 8 x i64> %2,731    <vscale x 8 x i1> %3,732    iXLen %4, iXLen 1)733 734  ret <vscale x 8 x i64> %a735}736 737define <vscale x 1 x i8> @intrinsic_vsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {738; CHECK-LABEL: intrinsic_vsub_vx_nxv1i8_nxv1i8_i8:739; CHECK:       # %bb.0: # %entry740; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma741; CHECK-NEXT:    vsub.vx v8, v8, a0742; CHECK-NEXT:    ret743entry:744  %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(745    <vscale x 1 x i8> poison,746    <vscale x 1 x i8> %0,747    i8 %1,748    iXLen %2)749 750  ret <vscale x 1 x i8> %a751}752 753define <vscale x 1 x i8> @intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {754; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i8_nxv1i8_i8:755; CHECK:       # %bb.0: # %entry756; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu757; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t758; CHECK-NEXT:    ret759entry:760  %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(761    <vscale x 1 x i8> %0,762    <vscale x 1 x i8> %1,763    i8 %2,764    <vscale x 1 x i1> %3,765    iXLen %4, iXLen 1)766 767  ret <vscale x 1 x i8> %a768}769 770define <vscale x 2 x i8> @intrinsic_vsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {771; CHECK-LABEL: intrinsic_vsub_vx_nxv2i8_nxv2i8_i8:772; CHECK:       # %bb.0: # %entry773; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma774; CHECK-NEXT:    vsub.vx v8, v8, a0775; CHECK-NEXT:    ret776entry:777  %a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(778    <vscale x 2 x i8> poison,779    <vscale x 2 x i8> %0,780    i8 %1,781    iXLen %2)782 783  ret <vscale x 2 x i8> %a784}785 786define <vscale x 2 x i8> @intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {787; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i8_nxv2i8_i8:788; CHECK:       # %bb.0: # %entry789; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu790; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t791; CHECK-NEXT:    ret792entry:793  %a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(794    <vscale x 2 x i8> %0,795    <vscale x 2 x i8> %1,796    i8 %2,797    <vscale x 2 x i1> %3,798    iXLen %4, iXLen 1)799 800  ret <vscale x 2 x i8> %a801}802 803define <vscale x 4 x i8> @intrinsic_vsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {804; CHECK-LABEL: intrinsic_vsub_vx_nxv4i8_nxv4i8_i8:805; CHECK:       # %bb.0: # %entry806; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma807; CHECK-NEXT:    vsub.vx v8, v8, a0808; CHECK-NEXT:    ret809entry:810  %a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(811    <vscale x 4 x i8> poison,812    <vscale x 4 x i8> %0,813    i8 %1,814    iXLen %2)815 816  ret <vscale x 4 x i8> %a817}818 819define <vscale x 4 x i8> @intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {820; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i8_nxv4i8_i8:821; CHECK:       # %bb.0: # %entry822; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu823; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t824; CHECK-NEXT:    ret825entry:826  %a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(827    <vscale x 4 x i8> %0,828    <vscale x 4 x i8> %1,829    i8 %2,830    <vscale x 4 x i1> %3,831    iXLen %4, iXLen 1)832 833  ret <vscale x 4 x i8> %a834}835 836define <vscale x 8 x i8> @intrinsic_vsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {837; CHECK-LABEL: intrinsic_vsub_vx_nxv8i8_nxv8i8_i8:838; CHECK:       # %bb.0: # %entry839; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma840; CHECK-NEXT:    vsub.vx v8, v8, a0841; CHECK-NEXT:    ret842entry:843  %a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(844    <vscale x 8 x i8> poison,845    <vscale x 8 x i8> %0,846    i8 %1,847    iXLen %2)848 849  ret <vscale x 8 x i8> %a850}851 852define <vscale x 8 x i8> @intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {853; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i8_nxv8i8_i8:854; CHECK:       # %bb.0: # %entry855; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu856; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t857; CHECK-NEXT:    ret858entry:859  %a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(860    <vscale x 8 x i8> %0,861    <vscale x 8 x i8> %1,862    i8 %2,863    <vscale x 8 x i1> %3,864    iXLen %4, iXLen 1)865 866  ret <vscale x 8 x i8> %a867}868 869define <vscale x 16 x i8> @intrinsic_vsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {870; CHECK-LABEL: intrinsic_vsub_vx_nxv16i8_nxv16i8_i8:871; CHECK:       # %bb.0: # %entry872; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma873; CHECK-NEXT:    vsub.vx v8, v8, a0874; CHECK-NEXT:    ret875entry:876  %a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(877    <vscale x 16 x i8> poison,878    <vscale x 16 x i8> %0,879    i8 %1,880    iXLen %2)881 882  ret <vscale x 16 x i8> %a883}884 885define <vscale x 16 x i8> @intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {886; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i8_nxv16i8_i8:887; CHECK:       # %bb.0: # %entry888; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu889; CHECK-NEXT:    vsub.vx v8, v10, a0, v0.t890; CHECK-NEXT:    ret891entry:892  %a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(893    <vscale x 16 x i8> %0,894    <vscale x 16 x i8> %1,895    i8 %2,896    <vscale x 16 x i1> %3,897    iXLen %4, iXLen 1)898 899  ret <vscale x 16 x i8> %a900}901 902define <vscale x 32 x i8> @intrinsic_vsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {903; CHECK-LABEL: intrinsic_vsub_vx_nxv32i8_nxv32i8_i8:904; CHECK:       # %bb.0: # %entry905; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma906; CHECK-NEXT:    vsub.vx v8, v8, a0907; CHECK-NEXT:    ret908entry:909  %a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(910    <vscale x 32 x i8> poison,911    <vscale x 32 x i8> %0,912    i8 %1,913    iXLen %2)914 915  ret <vscale x 32 x i8> %a916}917 918define <vscale x 32 x i8> @intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {919; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i8_nxv32i8_i8:920; CHECK:       # %bb.0: # %entry921; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu922; CHECK-NEXT:    vsub.vx v8, v12, a0, v0.t923; CHECK-NEXT:    ret924entry:925  %a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(926    <vscale x 32 x i8> %0,927    <vscale x 32 x i8> %1,928    i8 %2,929    <vscale x 32 x i1> %3,930    iXLen %4, iXLen 1)931 932  ret <vscale x 32 x i8> %a933}934 935define <vscale x 64 x i8> @intrinsic_vsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {936; CHECK-LABEL: intrinsic_vsub_vx_nxv64i8_nxv64i8_i8:937; CHECK:       # %bb.0: # %entry938; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma939; CHECK-NEXT:    vsub.vx v8, v8, a0940; CHECK-NEXT:    ret941entry:942  %a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(943    <vscale x 64 x i8> poison,944    <vscale x 64 x i8> %0,945    i8 %1,946    iXLen %2)947 948  ret <vscale x 64 x i8> %a949}950 951define <vscale x 64 x i8> @intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {952; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv64i8_nxv64i8_i8:953; CHECK:       # %bb.0: # %entry954; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu955; CHECK-NEXT:    vsub.vx v8, v16, a0, v0.t956; CHECK-NEXT:    ret957entry:958  %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(959    <vscale x 64 x i8> %0,960    <vscale x 64 x i8> %1,961    i8 %2,962    <vscale x 64 x i1> %3,963    iXLen %4, iXLen 1)964 965  ret <vscale x 64 x i8> %a966}967 968define <vscale x 1 x i16> @intrinsic_vsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {969; CHECK-LABEL: intrinsic_vsub_vx_nxv1i16_nxv1i16_i16:970; CHECK:       # %bb.0: # %entry971; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma972; CHECK-NEXT:    vsub.vx v8, v8, a0973; CHECK-NEXT:    ret974entry:975  %a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(976    <vscale x 1 x i16> poison,977    <vscale x 1 x i16> %0,978    i16 %1,979    iXLen %2)980 981  ret <vscale x 1 x i16> %a982}983 984define <vscale x 1 x i16> @intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {985; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i16_nxv1i16_i16:986; CHECK:       # %bb.0: # %entry987; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu988; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t989; CHECK-NEXT:    ret990entry:991  %a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(992    <vscale x 1 x i16> %0,993    <vscale x 1 x i16> %1,994    i16 %2,995    <vscale x 1 x i1> %3,996    iXLen %4, iXLen 1)997 998  ret <vscale x 1 x i16> %a999}1000 1001define <vscale x 2 x i16> @intrinsic_vsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {1002; CHECK-LABEL: intrinsic_vsub_vx_nxv2i16_nxv2i16_i16:1003; CHECK:       # %bb.0: # %entry1004; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1005; CHECK-NEXT:    vsub.vx v8, v8, a01006; CHECK-NEXT:    ret1007entry:1008  %a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(1009    <vscale x 2 x i16> poison,1010    <vscale x 2 x i16> %0,1011    i16 %1,1012    iXLen %2)1013 1014  ret <vscale x 2 x i16> %a1015}1016 1017define <vscale x 2 x i16> @intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1018; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i16_nxv2i16_i16:1019; CHECK:       # %bb.0: # %entry1020; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1021; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t1022; CHECK-NEXT:    ret1023entry:1024  %a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(1025    <vscale x 2 x i16> %0,1026    <vscale x 2 x i16> %1,1027    i16 %2,1028    <vscale x 2 x i1> %3,1029    iXLen %4, iXLen 1)1030 1031  ret <vscale x 2 x i16> %a1032}1033 1034define <vscale x 4 x i16> @intrinsic_vsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {1035; CHECK-LABEL: intrinsic_vsub_vx_nxv4i16_nxv4i16_i16:1036; CHECK:       # %bb.0: # %entry1037; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1038; CHECK-NEXT:    vsub.vx v8, v8, a01039; CHECK-NEXT:    ret1040entry:1041  %a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(1042    <vscale x 4 x i16> poison,1043    <vscale x 4 x i16> %0,1044    i16 %1,1045    iXLen %2)1046 1047  ret <vscale x 4 x i16> %a1048}1049 1050define <vscale x 4 x i16> @intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1051; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i16_nxv4i16_i16:1052; CHECK:       # %bb.0: # %entry1053; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1054; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t1055; CHECK-NEXT:    ret1056entry:1057  %a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(1058    <vscale x 4 x i16> %0,1059    <vscale x 4 x i16> %1,1060    i16 %2,1061    <vscale x 4 x i1> %3,1062    iXLen %4, iXLen 1)1063 1064  ret <vscale x 4 x i16> %a1065}1066 1067define <vscale x 8 x i16> @intrinsic_vsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1068; CHECK-LABEL: intrinsic_vsub_vx_nxv8i16_nxv8i16_i16:1069; CHECK:       # %bb.0: # %entry1070; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1071; CHECK-NEXT:    vsub.vx v8, v8, a01072; CHECK-NEXT:    ret1073entry:1074  %a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(1075    <vscale x 8 x i16> poison,1076    <vscale x 8 x i16> %0,1077    i16 %1,1078    iXLen %2)1079 1080  ret <vscale x 8 x i16> %a1081}1082 1083define <vscale x 8 x i16> @intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1084; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i16_nxv8i16_i16:1085; CHECK:       # %bb.0: # %entry1086; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1087; CHECK-NEXT:    vsub.vx v8, v10, a0, v0.t1088; CHECK-NEXT:    ret1089entry:1090  %a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(1091    <vscale x 8 x i16> %0,1092    <vscale x 8 x i16> %1,1093    i16 %2,1094    <vscale x 8 x i1> %3,1095    iXLen %4, iXLen 1)1096 1097  ret <vscale x 8 x i16> %a1098}1099 1100define <vscale x 16 x i16> @intrinsic_vsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1101; CHECK-LABEL: intrinsic_vsub_vx_nxv16i16_nxv16i16_i16:1102; CHECK:       # %bb.0: # %entry1103; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1104; CHECK-NEXT:    vsub.vx v8, v8, a01105; CHECK-NEXT:    ret1106entry:1107  %a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(1108    <vscale x 16 x i16> poison,1109    <vscale x 16 x i16> %0,1110    i16 %1,1111    iXLen %2)1112 1113  ret <vscale x 16 x i16> %a1114}1115 1116define <vscale x 16 x i16> @intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1117; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i16_nxv16i16_i16:1118; CHECK:       # %bb.0: # %entry1119; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1120; CHECK-NEXT:    vsub.vx v8, v12, a0, v0.t1121; CHECK-NEXT:    ret1122entry:1123  %a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(1124    <vscale x 16 x i16> %0,1125    <vscale x 16 x i16> %1,1126    i16 %2,1127    <vscale x 16 x i1> %3,1128    iXLen %4, iXLen 1)1129 1130  ret <vscale x 16 x i16> %a1131}1132 1133define <vscale x 32 x i16> @intrinsic_vsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {1134; CHECK-LABEL: intrinsic_vsub_vx_nxv32i16_nxv32i16_i16:1135; CHECK:       # %bb.0: # %entry1136; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1137; CHECK-NEXT:    vsub.vx v8, v8, a01138; CHECK-NEXT:    ret1139entry:1140  %a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(1141    <vscale x 32 x i16> poison,1142    <vscale x 32 x i16> %0,1143    i16 %1,1144    iXLen %2)1145 1146  ret <vscale x 32 x i16> %a1147}1148 1149define <vscale x 32 x i16> @intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1150; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv32i16_nxv32i16_i16:1151; CHECK:       # %bb.0: # %entry1152; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu1153; CHECK-NEXT:    vsub.vx v8, v16, a0, v0.t1154; CHECK-NEXT:    ret1155entry:1156  %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(1157    <vscale x 32 x i16> %0,1158    <vscale x 32 x i16> %1,1159    i16 %2,1160    <vscale x 32 x i1> %3,1161    iXLen %4, iXLen 1)1162 1163  ret <vscale x 32 x i16> %a1164}1165 1166define <vscale x 1 x i32> @intrinsic_vsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1167; CHECK-LABEL: intrinsic_vsub_vx_nxv1i32_nxv1i32_i32:1168; CHECK:       # %bb.0: # %entry1169; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1170; CHECK-NEXT:    vsub.vx v8, v8, a01171; CHECK-NEXT:    ret1172entry:1173  %a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(1174    <vscale x 1 x i32> poison,1175    <vscale x 1 x i32> %0,1176    i32 %1,1177    iXLen %2)1178 1179  ret <vscale x 1 x i32> %a1180}1181 1182define <vscale x 1 x i32> @intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1183; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv1i32_nxv1i32_i32:1184; CHECK:       # %bb.0: # %entry1185; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1186; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t1187; CHECK-NEXT:    ret1188entry:1189  %a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(1190    <vscale x 1 x i32> %0,1191    <vscale x 1 x i32> %1,1192    i32 %2,1193    <vscale x 1 x i1> %3,1194    iXLen %4, iXLen 1)1195 1196  ret <vscale x 1 x i32> %a1197}1198 1199define <vscale x 2 x i32> @intrinsic_vsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1200; CHECK-LABEL: intrinsic_vsub_vx_nxv2i32_nxv2i32_i32:1201; CHECK:       # %bb.0: # %entry1202; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1203; CHECK-NEXT:    vsub.vx v8, v8, a01204; CHECK-NEXT:    ret1205entry:1206  %a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(1207    <vscale x 2 x i32> poison,1208    <vscale x 2 x i32> %0,1209    i32 %1,1210    iXLen %2)1211 1212  ret <vscale x 2 x i32> %a1213}1214 1215define <vscale x 2 x i32> @intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1216; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv2i32_nxv2i32_i32:1217; CHECK:       # %bb.0: # %entry1218; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1219; CHECK-NEXT:    vsub.vx v8, v9, a0, v0.t1220; CHECK-NEXT:    ret1221entry:1222  %a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(1223    <vscale x 2 x i32> %0,1224    <vscale x 2 x i32> %1,1225    i32 %2,1226    <vscale x 2 x i1> %3,1227    iXLen %4, iXLen 1)1228 1229  ret <vscale x 2 x i32> %a1230}1231 1232define <vscale x 4 x i32> @intrinsic_vsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1233; CHECK-LABEL: intrinsic_vsub_vx_nxv4i32_nxv4i32_i32:1234; CHECK:       # %bb.0: # %entry1235; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1236; CHECK-NEXT:    vsub.vx v8, v8, a01237; CHECK-NEXT:    ret1238entry:1239  %a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(1240    <vscale x 4 x i32> poison,1241    <vscale x 4 x i32> %0,1242    i32 %1,1243    iXLen %2)1244 1245  ret <vscale x 4 x i32> %a1246}1247 1248define <vscale x 4 x i32> @intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1249; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv4i32_nxv4i32_i32:1250; CHECK:       # %bb.0: # %entry1251; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1252; CHECK-NEXT:    vsub.vx v8, v10, a0, v0.t1253; CHECK-NEXT:    ret1254entry:1255  %a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(1256    <vscale x 4 x i32> %0,1257    <vscale x 4 x i32> %1,1258    i32 %2,1259    <vscale x 4 x i1> %3,1260    iXLen %4, iXLen 1)1261 1262  ret <vscale x 4 x i32> %a1263}1264 1265define <vscale x 8 x i32> @intrinsic_vsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1266; CHECK-LABEL: intrinsic_vsub_vx_nxv8i32_nxv8i32_i32:1267; CHECK:       # %bb.0: # %entry1268; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1269; CHECK-NEXT:    vsub.vx v8, v8, a01270; CHECK-NEXT:    ret1271entry:1272  %a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(1273    <vscale x 8 x i32> poison,1274    <vscale x 8 x i32> %0,1275    i32 %1,1276    iXLen %2)1277 1278  ret <vscale x 8 x i32> %a1279}1280 1281define <vscale x 8 x i32> @intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1282; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv8i32_nxv8i32_i32:1283; CHECK:       # %bb.0: # %entry1284; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1285; CHECK-NEXT:    vsub.vx v8, v12, a0, v0.t1286; CHECK-NEXT:    ret1287entry:1288  %a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(1289    <vscale x 8 x i32> %0,1290    <vscale x 8 x i32> %1,1291    i32 %2,1292    <vscale x 8 x i1> %3,1293    iXLen %4, iXLen 1)1294 1295  ret <vscale x 8 x i32> %a1296}1297 1298define <vscale x 16 x i32> @intrinsic_vsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {1299; CHECK-LABEL: intrinsic_vsub_vx_nxv16i32_nxv16i32_i32:1300; CHECK:       # %bb.0: # %entry1301; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1302; CHECK-NEXT:    vsub.vx v8, v8, a01303; CHECK-NEXT:    ret1304entry:1305  %a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(1306    <vscale x 16 x i32> poison,1307    <vscale x 16 x i32> %0,1308    i32 %1,1309    iXLen %2)1310 1311  ret <vscale x 16 x i32> %a1312}1313 1314define <vscale x 16 x i32> @intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1315; CHECK-LABEL: intrinsic_vsub_mask_vx_nxv16i32_nxv16i32_i32:1316; CHECK:       # %bb.0: # %entry1317; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1318; CHECK-NEXT:    vsub.vx v8, v16, a0, v0.t1319; CHECK-NEXT:    ret1320entry:1321  %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(1322    <vscale x 16 x i32> %0,1323    <vscale x 16 x i32> %1,1324    i32 %2,1325    <vscale x 16 x i1> %3,1326    iXLen %4, iXLen 1)1327 1328  ret <vscale x 16 x i32> %a1329}1330 1331define <vscale x 1 x i64> @intrinsic_vsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1332; RV32-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:1333; RV32:       # %bb.0: # %entry1334; RV32-NEXT:    addi sp, sp, -161335; RV32-NEXT:    sw a0, 8(sp)1336; RV32-NEXT:    sw a1, 12(sp)1337; RV32-NEXT:    addi a0, sp, 81338; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1339; RV32-NEXT:    vlse64.v v9, (a0), zero1340; RV32-NEXT:    vsub.vv v8, v8, v91341; RV32-NEXT:    addi sp, sp, 161342; RV32-NEXT:    ret1343;1344; RV64-LABEL: intrinsic_vsub_vx_nxv1i64_nxv1i64_i64:1345; RV64:       # %bb.0: # %entry1346; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1347; RV64-NEXT:    vsub.vx v8, v8, a01348; RV64-NEXT:    ret1349entry:1350  %a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(1351    <vscale x 1 x i64> poison,1352    <vscale x 1 x i64> %0,1353    i64 %1,1354    iXLen %2)1355 1356  ret <vscale x 1 x i64> %a1357}1358 1359define <vscale x 1 x i64> @intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1360; RV32-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:1361; RV32:       # %bb.0: # %entry1362; RV32-NEXT:    addi sp, sp, -161363; RV32-NEXT:    sw a0, 8(sp)1364; RV32-NEXT:    sw a1, 12(sp)1365; RV32-NEXT:    addi a0, sp, 81366; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, mu1367; RV32-NEXT:    vlse64.v v10, (a0), zero1368; RV32-NEXT:    vsub.vv v8, v9, v10, v0.t1369; RV32-NEXT:    addi sp, sp, 161370; RV32-NEXT:    ret1371;1372; RV64-LABEL: intrinsic_vsub_mask_vx_nxv1i64_nxv1i64_i64:1373; RV64:       # %bb.0: # %entry1374; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1375; RV64-NEXT:    vsub.vx v8, v9, a0, v0.t1376; RV64-NEXT:    ret1377entry:1378  %a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(1379    <vscale x 1 x i64> %0,1380    <vscale x 1 x i64> %1,1381    i64 %2,1382    <vscale x 1 x i1> %3,1383    iXLen %4, iXLen 1)1384 1385  ret <vscale x 1 x i64> %a1386}1387 1388define <vscale x 2 x i64> @intrinsic_vsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1389; RV32-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:1390; RV32:       # %bb.0: # %entry1391; RV32-NEXT:    addi sp, sp, -161392; RV32-NEXT:    sw a0, 8(sp)1393; RV32-NEXT:    sw a1, 12(sp)1394; RV32-NEXT:    addi a0, sp, 81395; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1396; RV32-NEXT:    vlse64.v v10, (a0), zero1397; RV32-NEXT:    vsub.vv v8, v8, v101398; RV32-NEXT:    addi sp, sp, 161399; RV32-NEXT:    ret1400;1401; RV64-LABEL: intrinsic_vsub_vx_nxv2i64_nxv2i64_i64:1402; RV64:       # %bb.0: # %entry1403; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1404; RV64-NEXT:    vsub.vx v8, v8, a01405; RV64-NEXT:    ret1406entry:1407  %a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(1408    <vscale x 2 x i64> poison,1409    <vscale x 2 x i64> %0,1410    i64 %1,1411    iXLen %2)1412 1413  ret <vscale x 2 x i64> %a1414}1415 1416define <vscale x 2 x i64> @intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1417; RV32-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:1418; RV32:       # %bb.0: # %entry1419; RV32-NEXT:    addi sp, sp, -161420; RV32-NEXT:    sw a0, 8(sp)1421; RV32-NEXT:    sw a1, 12(sp)1422; RV32-NEXT:    addi a0, sp, 81423; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, mu1424; RV32-NEXT:    vlse64.v v12, (a0), zero1425; RV32-NEXT:    vsub.vv v8, v10, v12, v0.t1426; RV32-NEXT:    addi sp, sp, 161427; RV32-NEXT:    ret1428;1429; RV64-LABEL: intrinsic_vsub_mask_vx_nxv2i64_nxv2i64_i64:1430; RV64:       # %bb.0: # %entry1431; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1432; RV64-NEXT:    vsub.vx v8, v10, a0, v0.t1433; RV64-NEXT:    ret1434entry:1435  %a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(1436    <vscale x 2 x i64> %0,1437    <vscale x 2 x i64> %1,1438    i64 %2,1439    <vscale x 2 x i1> %3,1440    iXLen %4, iXLen 1)1441 1442  ret <vscale x 2 x i64> %a1443}1444 1445define <vscale x 4 x i64> @intrinsic_vsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1446; RV32-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:1447; RV32:       # %bb.0: # %entry1448; RV32-NEXT:    addi sp, sp, -161449; RV32-NEXT:    sw a0, 8(sp)1450; RV32-NEXT:    sw a1, 12(sp)1451; RV32-NEXT:    addi a0, sp, 81452; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1453; RV32-NEXT:    vlse64.v v12, (a0), zero1454; RV32-NEXT:    vsub.vv v8, v8, v121455; RV32-NEXT:    addi sp, sp, 161456; RV32-NEXT:    ret1457;1458; RV64-LABEL: intrinsic_vsub_vx_nxv4i64_nxv4i64_i64:1459; RV64:       # %bb.0: # %entry1460; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1461; RV64-NEXT:    vsub.vx v8, v8, a01462; RV64-NEXT:    ret1463entry:1464  %a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(1465    <vscale x 4 x i64> poison,1466    <vscale x 4 x i64> %0,1467    i64 %1,1468    iXLen %2)1469 1470  ret <vscale x 4 x i64> %a1471}1472 1473define <vscale x 4 x i64> @intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1474; RV32-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:1475; RV32:       # %bb.0: # %entry1476; RV32-NEXT:    addi sp, sp, -161477; RV32-NEXT:    sw a0, 8(sp)1478; RV32-NEXT:    sw a1, 12(sp)1479; RV32-NEXT:    addi a0, sp, 81480; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, mu1481; RV32-NEXT:    vlse64.v v16, (a0), zero1482; RV32-NEXT:    vsub.vv v8, v12, v16, v0.t1483; RV32-NEXT:    addi sp, sp, 161484; RV32-NEXT:    ret1485;1486; RV64-LABEL: intrinsic_vsub_mask_vx_nxv4i64_nxv4i64_i64:1487; RV64:       # %bb.0: # %entry1488; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1489; RV64-NEXT:    vsub.vx v8, v12, a0, v0.t1490; RV64-NEXT:    ret1491entry:1492  %a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(1493    <vscale x 4 x i64> %0,1494    <vscale x 4 x i64> %1,1495    i64 %2,1496    <vscale x 4 x i1> %3,1497    iXLen %4, iXLen 1)1498 1499  ret <vscale x 4 x i64> %a1500}1501 1502define <vscale x 8 x i64> @intrinsic_vsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {1503; RV32-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:1504; RV32:       # %bb.0: # %entry1505; RV32-NEXT:    addi sp, sp, -161506; RV32-NEXT:    sw a0, 8(sp)1507; RV32-NEXT:    sw a1, 12(sp)1508; RV32-NEXT:    addi a0, sp, 81509; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1510; RV32-NEXT:    vlse64.v v16, (a0), zero1511; RV32-NEXT:    vsub.vv v8, v8, v161512; RV32-NEXT:    addi sp, sp, 161513; RV32-NEXT:    ret1514;1515; RV64-LABEL: intrinsic_vsub_vx_nxv8i64_nxv8i64_i64:1516; RV64:       # %bb.0: # %entry1517; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1518; RV64-NEXT:    vsub.vx v8, v8, a01519; RV64-NEXT:    ret1520entry:1521  %a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(1522    <vscale x 8 x i64> poison,1523    <vscale x 8 x i64> %0,1524    i64 %1,1525    iXLen %2)1526 1527  ret <vscale x 8 x i64> %a1528}1529 1530define <vscale x 8 x i64> @intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1531; RV32-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:1532; RV32:       # %bb.0: # %entry1533; RV32-NEXT:    addi sp, sp, -161534; RV32-NEXT:    sw a0, 8(sp)1535; RV32-NEXT:    sw a1, 12(sp)1536; RV32-NEXT:    addi a0, sp, 81537; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, mu1538; RV32-NEXT:    vlse64.v v24, (a0), zero1539; RV32-NEXT:    vsub.vv v8, v16, v24, v0.t1540; RV32-NEXT:    addi sp, sp, 161541; RV32-NEXT:    ret1542;1543; RV64-LABEL: intrinsic_vsub_mask_vx_nxv8i64_nxv8i64_i64:1544; RV64:       # %bb.0: # %entry1545; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1546; RV64-NEXT:    vsub.vx v8, v16, a0, v0.t1547; RV64-NEXT:    ret1548entry:1549  %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(1550    <vscale x 8 x i64> %0,1551    <vscale x 8 x i64> %1,1552    i64 %2,1553    <vscale x 8 x i1> %3,1554    iXLen %4, iXLen 1)1555 1556  ret <vscale x 8 x i64> %a1557}1558 1559define <vscale x 1 x i8> @intrinsic_vsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {1560; CHECK-LABEL: intrinsic_vsub_vi_nxv1i8_nxv1i8_i8:1561; CHECK:       # %bb.0: # %entry1562; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1563; CHECK-NEXT:    vadd.vi v8, v8, -91564; CHECK-NEXT:    ret1565entry:1566  %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(1567    <vscale x 1 x i8> poison,1568    <vscale x 1 x i8> %0,1569    i8 9,1570    iXLen %1)1571 1572  ret <vscale x 1 x i8> %a1573}1574 1575define <vscale x 1 x i8> @intrinsic_vsub_vi_tu_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {1576; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv1i8_nxv1i8_i8:1577; CHECK:       # %bb.0: # %entry1578; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma1579; CHECK-NEXT:    vadd.vi v8, v9, -91580; CHECK-NEXT:    ret1581entry:1582  %a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(1583    <vscale x 1 x i8> %0,1584    <vscale x 1 x i8> %1,1585    i8 9,1586    iXLen %2)1587 1588  ret <vscale x 1 x i8> %a1589}1590 1591define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1592; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8:1593; CHECK:       # %bb.0: # %entry1594; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu1595; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t1596; CHECK-NEXT:    ret1597entry:1598  %a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(1599    <vscale x 1 x i8> %0,1600    <vscale x 1 x i8> %1,1601    i8 -9,1602    <vscale x 1 x i1> %2,1603    iXLen %3, iXLen 1)1604 1605  ret <vscale x 1 x i8> %a1606}1607 1608define <vscale x 2 x i8> @intrinsic_vsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {1609; CHECK-LABEL: intrinsic_vsub_vi_nxv2i8_nxv2i8_i8:1610; CHECK:       # %bb.0: # %entry1611; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1612; CHECK-NEXT:    vadd.vi v8, v8, -91613; CHECK-NEXT:    ret1614entry:1615  %a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(1616    <vscale x 2 x i8> poison,1617    <vscale x 2 x i8> %0,1618    i8 9,1619    iXLen %1)1620 1621  ret <vscale x 2 x i8> %a1622}1623 1624define <vscale x 2 x i8> @intrinsic_vsub_vi_tu_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {1625; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv2i8_nxv2i8_i8:1626; CHECK:       # %bb.0: # %entry1627; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma1628; CHECK-NEXT:    vadd.vi v8, v9, -91629; CHECK-NEXT:    ret1630entry:1631  %a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(1632    <vscale x 2 x i8> %0,1633    <vscale x 2 x i8> %1,1634    i8 9,1635    iXLen %2)1636 1637  ret <vscale x 2 x i8> %a1638}1639 1640define <vscale x 2 x i8> @intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1641; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8:1642; CHECK:       # %bb.0: # %entry1643; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu1644; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t1645; CHECK-NEXT:    ret1646entry:1647  %a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(1648    <vscale x 2 x i8> %0,1649    <vscale x 2 x i8> %1,1650    i8 -9,1651    <vscale x 2 x i1> %2,1652    iXLen %3, iXLen 1)1653 1654  ret <vscale x 2 x i8> %a1655}1656 1657define <vscale x 4 x i8> @intrinsic_vsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {1658; CHECK-LABEL: intrinsic_vsub_vi_nxv4i8_nxv4i8_i8:1659; CHECK:       # %bb.0: # %entry1660; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1661; CHECK-NEXT:    vadd.vi v8, v8, -91662; CHECK-NEXT:    ret1663entry:1664  %a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(1665    <vscale x 4 x i8> poison,1666    <vscale x 4 x i8> %0,1667    i8 9,1668    iXLen %1)1669 1670  ret <vscale x 4 x i8> %a1671}1672 1673define <vscale x 4 x i8> @intrinsic_vsub_vi_tu_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {1674; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv4i8_nxv4i8_i8:1675; CHECK:       # %bb.0: # %entry1676; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma1677; CHECK-NEXT:    vadd.vi v8, v9, -91678; CHECK-NEXT:    ret1679entry:1680  %a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(1681    <vscale x 4 x i8> %0,1682    <vscale x 4 x i8> %1,1683    i8 9,1684    iXLen %2)1685 1686  ret <vscale x 4 x i8> %a1687}1688 1689define <vscale x 4 x i8> @intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1690; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8:1691; CHECK:       # %bb.0: # %entry1692; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu1693; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t1694; CHECK-NEXT:    ret1695entry:1696  %a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(1697    <vscale x 4 x i8> %0,1698    <vscale x 4 x i8> %1,1699    i8 -9,1700    <vscale x 4 x i1> %2,1701    iXLen %3, iXLen 1)1702 1703  ret <vscale x 4 x i8> %a1704}1705 1706define <vscale x 8 x i8> @intrinsic_vsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {1707; CHECK-LABEL: intrinsic_vsub_vi_nxv8i8_nxv8i8_i8:1708; CHECK:       # %bb.0: # %entry1709; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1710; CHECK-NEXT:    vadd.vi v8, v8, -91711; CHECK-NEXT:    ret1712entry:1713  %a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(1714    <vscale x 8 x i8> poison,1715    <vscale x 8 x i8> %0,1716    i8 9,1717    iXLen %1)1718 1719  ret <vscale x 8 x i8> %a1720}1721 1722define <vscale x 8 x i8> @intrinsic_vsub_vi_tu_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {1723; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv8i8_nxv8i8_i8:1724; CHECK:       # %bb.0: # %entry1725; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma1726; CHECK-NEXT:    vadd.vi v8, v9, -91727; CHECK-NEXT:    ret1728entry:1729  %a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(1730    <vscale x 8 x i8> %0,1731    <vscale x 8 x i8> %1,1732    i8 9,1733    iXLen %2)1734 1735  ret <vscale x 8 x i8> %a1736}1737 1738define <vscale x 8 x i8> @intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1739; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8:1740; CHECK:       # %bb.0: # %entry1741; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu1742; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t1743; CHECK-NEXT:    ret1744entry:1745  %a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(1746    <vscale x 8 x i8> %0,1747    <vscale x 8 x i8> %1,1748    i8 -9,1749    <vscale x 8 x i1> %2,1750    iXLen %3, iXLen 1)1751 1752  ret <vscale x 8 x i8> %a1753}1754 1755define <vscale x 16 x i8> @intrinsic_vsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {1756; CHECK-LABEL: intrinsic_vsub_vi_nxv16i8_nxv16i8_i8:1757; CHECK:       # %bb.0: # %entry1758; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1759; CHECK-NEXT:    vadd.vi v8, v8, -91760; CHECK-NEXT:    ret1761entry:1762  %a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(1763    <vscale x 16 x i8> poison,1764    <vscale x 16 x i8> %0,1765    i8 9,1766    iXLen %1)1767 1768  ret <vscale x 16 x i8> %a1769}1770 1771define <vscale x 16 x i8> @intrinsic_vsub_vi_tu_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {1772; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv16i8_nxv16i8_i8:1773; CHECK:       # %bb.0: # %entry1774; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma1775; CHECK-NEXT:    vadd.vi v8, v10, -91776; CHECK-NEXT:    ret1777entry:1778  %a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(1779    <vscale x 16 x i8> %0,1780    <vscale x 16 x i8> %1,1781    i8 9,1782    iXLen %2)1783 1784  ret <vscale x 16 x i8> %a1785}1786 1787define <vscale x 16 x i8> @intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1788; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8:1789; CHECK:       # %bb.0: # %entry1790; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu1791; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t1792; CHECK-NEXT:    ret1793entry:1794  %a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(1795    <vscale x 16 x i8> %0,1796    <vscale x 16 x i8> %1,1797    i8 -9,1798    <vscale x 16 x i1> %2,1799    iXLen %3, iXLen 1)1800 1801  ret <vscale x 16 x i8> %a1802}1803 1804define <vscale x 32 x i8> @intrinsic_vsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {1805; CHECK-LABEL: intrinsic_vsub_vi_nxv32i8_nxv32i8_i8:1806; CHECK:       # %bb.0: # %entry1807; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1808; CHECK-NEXT:    vadd.vi v8, v8, -91809; CHECK-NEXT:    ret1810entry:1811  %a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(1812    <vscale x 32 x i8> poison,1813    <vscale x 32 x i8> %0,1814    i8 9,1815    iXLen %1)1816 1817  ret <vscale x 32 x i8> %a1818}1819 1820define <vscale x 32 x i8> @intrinsic_vsub_vi_tu_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {1821; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv32i8_nxv32i8_i8:1822; CHECK:       # %bb.0: # %entry1823; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma1824; CHECK-NEXT:    vadd.vi v8, v12, -91825; CHECK-NEXT:    ret1826entry:1827  %a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(1828    <vscale x 32 x i8> %0,1829    <vscale x 32 x i8> %1,1830    i8 9,1831    iXLen %2)1832 1833  ret <vscale x 32 x i8> %a1834}1835 1836define <vscale x 32 x i8> @intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1837; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8:1838; CHECK:       # %bb.0: # %entry1839; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu1840; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t1841; CHECK-NEXT:    ret1842entry:1843  %a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(1844    <vscale x 32 x i8> %0,1845    <vscale x 32 x i8> %1,1846    i8 -9,1847    <vscale x 32 x i1> %2,1848    iXLen %3, iXLen 1)1849 1850  ret <vscale x 32 x i8> %a1851}1852 1853define <vscale x 64 x i8> @intrinsic_vsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {1854; CHECK-LABEL: intrinsic_vsub_vi_nxv64i8_nxv64i8_i8:1855; CHECK:       # %bb.0: # %entry1856; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma1857; CHECK-NEXT:    vadd.vi v8, v8, 91858; CHECK-NEXT:    ret1859entry:1860  %a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(1861    <vscale x 64 x i8> poison,1862    <vscale x 64 x i8> %0,1863    i8 -9,1864    iXLen %1)1865 1866  ret <vscale x 64 x i8> %a1867}1868 1869define <vscale x 64 x i8> @intrinsic_vsub_vi_tu_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {1870; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv64i8_nxv64i8_i8:1871; CHECK:       # %bb.0: # %entry1872; CHECK-NEXT:    vsetvli zero, a0, e8, m8, tu, ma1873; CHECK-NEXT:    vadd.vi v8, v16, -91874; CHECK-NEXT:    ret1875entry:1876  %a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(1877    <vscale x 64 x i8> %0,1878    <vscale x 64 x i8> %1,1879    i8 9,1880    iXLen %2)1881 1882  ret <vscale x 64 x i8> %a1883}1884 1885define <vscale x 64 x i8> @intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {1886; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8:1887; CHECK:       # %bb.0: # %entry1888; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, mu1889; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t1890; CHECK-NEXT:    ret1891entry:1892  %a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(1893    <vscale x 64 x i8> %0,1894    <vscale x 64 x i8> %1,1895    i8 -9,1896    <vscale x 64 x i1> %2,1897    iXLen %3, iXLen 1)1898 1899  ret <vscale x 64 x i8> %a1900}1901 1902define <vscale x 1 x i16> @intrinsic_vsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {1903; CHECK-LABEL: intrinsic_vsub_vi_nxv1i16_nxv1i16_i16:1904; CHECK:       # %bb.0: # %entry1905; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1906; CHECK-NEXT:    vadd.vi v8, v8, -91907; CHECK-NEXT:    ret1908entry:1909  %a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(1910    <vscale x 1 x i16> poison,1911    <vscale x 1 x i16> %0,1912    i16 9,1913    iXLen %1)1914 1915  ret <vscale x 1 x i16> %a1916}1917 1918define <vscale x 1 x i16> @intrinsic_vsub_vi_tu_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1919; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv1i16_nxv1i16_i16:1920; CHECK:       # %bb.0: # %entry1921; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma1922; CHECK-NEXT:    vadd.vi v8, v9, -91923; CHECK-NEXT:    ret1924entry:1925  %a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(1926    <vscale x 1 x i16> %0,1927    <vscale x 1 x i16> %1,1928    i16 9,1929    iXLen %2)1930 1931  ret <vscale x 1 x i16> %a1932}1933 1934define <vscale x 1 x i16> @intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1935; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16:1936; CHECK:       # %bb.0: # %entry1937; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu1938; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t1939; CHECK-NEXT:    ret1940entry:1941  %a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(1942    <vscale x 1 x i16> %0,1943    <vscale x 1 x i16> %1,1944    i16 -9,1945    <vscale x 1 x i1> %2,1946    iXLen %3, iXLen 1)1947 1948  ret <vscale x 1 x i16> %a1949}1950 1951define <vscale x 2 x i16> @intrinsic_vsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {1952; CHECK-LABEL: intrinsic_vsub_vi_nxv2i16_nxv2i16_i16:1953; CHECK:       # %bb.0: # %entry1954; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1955; CHECK-NEXT:    vadd.vi v8, v8, -91956; CHECK-NEXT:    ret1957entry:1958  %a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(1959    <vscale x 2 x i16> poison,1960    <vscale x 2 x i16> %0,1961    i16 9,1962    iXLen %1)1963 1964  ret <vscale x 2 x i16> %a1965}1966 1967define <vscale x 2 x i16> @intrinsic_vsub_vi_tu_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1968; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv2i16_nxv2i16_i16:1969; CHECK:       # %bb.0: # %entry1970; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma1971; CHECK-NEXT:    vadd.vi v8, v9, -91972; CHECK-NEXT:    ret1973entry:1974  %a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(1975    <vscale x 2 x i16> %0,1976    <vscale x 2 x i16> %1,1977    i16 9,1978    iXLen %2)1979 1980  ret <vscale x 2 x i16> %a1981}1982 1983define <vscale x 2 x i16> @intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1984; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16:1985; CHECK:       # %bb.0: # %entry1986; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu1987; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t1988; CHECK-NEXT:    ret1989entry:1990  %a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(1991    <vscale x 2 x i16> %0,1992    <vscale x 2 x i16> %1,1993    i16 -9,1994    <vscale x 2 x i1> %2,1995    iXLen %3, iXLen 1)1996 1997  ret <vscale x 2 x i16> %a1998}1999 2000define <vscale x 4 x i16> @intrinsic_vsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {2001; CHECK-LABEL: intrinsic_vsub_vi_nxv4i16_nxv4i16_i16:2002; CHECK:       # %bb.0: # %entry2003; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2004; CHECK-NEXT:    vadd.vi v8, v8, -92005; CHECK-NEXT:    ret2006entry:2007  %a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(2008    <vscale x 4 x i16> poison,2009    <vscale x 4 x i16> %0,2010    i16 9,2011    iXLen %1)2012 2013  ret <vscale x 4 x i16> %a2014}2015 2016define <vscale x 4 x i16> @intrinsic_vsub_vi_tu_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2017; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv4i16_nxv4i16_i16:2018; CHECK:       # %bb.0: # %entry2019; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma2020; CHECK-NEXT:    vadd.vi v8, v9, -92021; CHECK-NEXT:    ret2022entry:2023  %a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(2024    <vscale x 4 x i16> %0,2025    <vscale x 4 x i16> %1,2026    i16 9,2027    iXLen %2)2028 2029  ret <vscale x 4 x i16> %a2030}2031 2032define <vscale x 4 x i16> @intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2033; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16:2034; CHECK:       # %bb.0: # %entry2035; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu2036; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t2037; CHECK-NEXT:    ret2038entry:2039  %a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(2040    <vscale x 4 x i16> %0,2041    <vscale x 4 x i16> %1,2042    i16 -9,2043    <vscale x 4 x i1> %2,2044    iXLen %3, iXLen 1)2045 2046  ret <vscale x 4 x i16> %a2047}2048 2049define <vscale x 8 x i16> @intrinsic_vsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {2050; CHECK-LABEL: intrinsic_vsub_vi_nxv8i16_nxv8i16_i16:2051; CHECK:       # %bb.0: # %entry2052; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2053; CHECK-NEXT:    vadd.vi v8, v8, -92054; CHECK-NEXT:    ret2055entry:2056  %a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(2057    <vscale x 8 x i16> poison,2058    <vscale x 8 x i16> %0,2059    i16 9,2060    iXLen %1)2061 2062  ret <vscale x 8 x i16> %a2063}2064 2065define <vscale x 8 x i16> @intrinsic_vsub_vi_tu_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2066; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv8i16_nxv8i16_i16:2067; CHECK:       # %bb.0: # %entry2068; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma2069; CHECK-NEXT:    vadd.vi v8, v10, -92070; CHECK-NEXT:    ret2071entry:2072  %a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(2073    <vscale x 8 x i16> %0,2074    <vscale x 8 x i16> %1,2075    i16 9,2076    iXLen %2)2077 2078  ret <vscale x 8 x i16> %a2079}2080 2081define <vscale x 8 x i16> @intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2082; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16:2083; CHECK:       # %bb.0: # %entry2084; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu2085; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t2086; CHECK-NEXT:    ret2087entry:2088  %a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(2089    <vscale x 8 x i16> %0,2090    <vscale x 8 x i16> %1,2091    i16 -9,2092    <vscale x 8 x i1> %2,2093    iXLen %3, iXLen 1)2094 2095  ret <vscale x 8 x i16> %a2096}2097 2098define <vscale x 16 x i16> @intrinsic_vsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {2099; CHECK-LABEL: intrinsic_vsub_vi_nxv16i16_nxv16i16_i16:2100; CHECK:       # %bb.0: # %entry2101; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2102; CHECK-NEXT:    vadd.vi v8, v8, -92103; CHECK-NEXT:    ret2104entry:2105  %a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(2106    <vscale x 16 x i16> poison,2107    <vscale x 16 x i16> %0,2108    i16 9,2109    iXLen %1)2110 2111  ret <vscale x 16 x i16> %a2112}2113 2114define <vscale x 16 x i16> @intrinsic_vsub_vi_tu_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {2115; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv16i16_nxv16i16_i16:2116; CHECK:       # %bb.0: # %entry2117; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma2118; CHECK-NEXT:    vadd.vi v8, v12, -92119; CHECK-NEXT:    ret2120entry:2121  %a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(2122    <vscale x 16 x i16> %0,2123    <vscale x 16 x i16> %1,2124    i16 9,2125    iXLen %2)2126 2127  ret <vscale x 16 x i16> %a2128}2129 2130define <vscale x 16 x i16> @intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {2131; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16:2132; CHECK:       # %bb.0: # %entry2133; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu2134; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t2135; CHECK-NEXT:    ret2136entry:2137  %a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(2138    <vscale x 16 x i16> %0,2139    <vscale x 16 x i16> %1,2140    i16 -9,2141    <vscale x 16 x i1> %2,2142    iXLen %3, iXLen 1)2143 2144  ret <vscale x 16 x i16> %a2145}2146 2147define <vscale x 32 x i16> @intrinsic_vsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {2148; CHECK-LABEL: intrinsic_vsub_vi_nxv32i16_nxv32i16_i16:2149; CHECK:       # %bb.0: # %entry2150; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2151; CHECK-NEXT:    vadd.vi v8, v8, -92152; CHECK-NEXT:    ret2153entry:2154  %a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(2155    <vscale x 32 x i16> poison,2156    <vscale x 32 x i16> %0,2157    i16 9,2158    iXLen %1)2159 2160  ret <vscale x 32 x i16> %a2161}2162 2163define <vscale x 32 x i16> @intrinsic_vsub_vi_tu_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {2164; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv32i16_nxv32i16_i16:2165; CHECK:       # %bb.0: # %entry2166; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, ma2167; CHECK-NEXT:    vadd.vi v8, v16, -92168; CHECK-NEXT:    ret2169entry:2170  %a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(2171    <vscale x 32 x i16> %0,2172    <vscale x 32 x i16> %1,2173    i16 9,2174    iXLen %2)2175 2176  ret <vscale x 32 x i16> %a2177}2178 2179define <vscale x 32 x i16> @intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {2180; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16:2181; CHECK:       # %bb.0: # %entry2182; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu2183; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t2184; CHECK-NEXT:    ret2185entry:2186  %a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(2187    <vscale x 32 x i16> %0,2188    <vscale x 32 x i16> %1,2189    i16 -9,2190    <vscale x 32 x i1> %2,2191    iXLen %3, iXLen 1)2192 2193  ret <vscale x 32 x i16> %a2194}2195 2196define <vscale x 1 x i32> @intrinsic_vsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {2197; CHECK-LABEL: intrinsic_vsub_vi_nxv1i32_nxv1i32_i32:2198; CHECK:       # %bb.0: # %entry2199; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2200; CHECK-NEXT:    vadd.vi v8, v8, -92201; CHECK-NEXT:    ret2202entry:2203  %a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(2204    <vscale x 1 x i32> poison,2205    <vscale x 1 x i32> %0,2206    i32 9,2207    iXLen %1)2208 2209  ret <vscale x 1 x i32> %a2210}2211 2212define <vscale x 1 x i32> @intrinsic_vsub_vi_tu_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {2213; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv1i32_nxv1i32_i32:2214; CHECK:       # %bb.0: # %entry2215; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma2216; CHECK-NEXT:    vadd.vi v8, v9, -92217; CHECK-NEXT:    ret2218entry:2219  %a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(2220    <vscale x 1 x i32> %0,2221    <vscale x 1 x i32> %1,2222    i32 9,2223    iXLen %2)2224 2225  ret <vscale x 1 x i32> %a2226}2227 2228define <vscale x 1 x i32> @intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2229; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32:2230; CHECK:       # %bb.0: # %entry2231; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu2232; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t2233; CHECK-NEXT:    ret2234entry:2235  %a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(2236    <vscale x 1 x i32> %0,2237    <vscale x 1 x i32> %1,2238    i32 -9,2239    <vscale x 1 x i1> %2,2240    iXLen %3, iXLen 1)2241 2242  ret <vscale x 1 x i32> %a2243}2244 2245define <vscale x 2 x i32> @intrinsic_vsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {2246; CHECK-LABEL: intrinsic_vsub_vi_nxv2i32_nxv2i32_i32:2247; CHECK:       # %bb.0: # %entry2248; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2249; CHECK-NEXT:    vadd.vi v8, v8, -92250; CHECK-NEXT:    ret2251entry:2252  %a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(2253    <vscale x 2 x i32> poison,2254    <vscale x 2 x i32> %0,2255    i32 9,2256    iXLen %1)2257 2258  ret <vscale x 2 x i32> %a2259}2260 2261define <vscale x 2 x i32> @intrinsic_vsub_vi_tu_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {2262; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv2i32_nxv2i32_i32:2263; CHECK:       # %bb.0: # %entry2264; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma2265; CHECK-NEXT:    vadd.vi v8, v9, -92266; CHECK-NEXT:    ret2267entry:2268  %a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(2269    <vscale x 2 x i32> %0,2270    <vscale x 2 x i32> %1,2271    i32 9,2272    iXLen %2)2273 2274  ret <vscale x 2 x i32> %a2275}2276 2277define <vscale x 2 x i32> @intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2278; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32:2279; CHECK:       # %bb.0: # %entry2280; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu2281; CHECK-NEXT:    vadd.vi v8, v9, 9, v0.t2282; CHECK-NEXT:    ret2283entry:2284  %a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(2285    <vscale x 2 x i32> %0,2286    <vscale x 2 x i32> %1,2287    i32 -9,2288    <vscale x 2 x i1> %2,2289    iXLen %3, iXLen 1)2290 2291  ret <vscale x 2 x i32> %a2292}2293 2294define <vscale x 4 x i32> @intrinsic_vsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {2295; CHECK-LABEL: intrinsic_vsub_vi_nxv4i32_nxv4i32_i32:2296; CHECK:       # %bb.0: # %entry2297; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2298; CHECK-NEXT:    vadd.vi v8, v8, -92299; CHECK-NEXT:    ret2300entry:2301  %a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(2302    <vscale x 4 x i32> poison,2303    <vscale x 4 x i32> %0,2304    i32 9,2305    iXLen %1)2306 2307  ret <vscale x 4 x i32> %a2308}2309 2310define <vscale x 4 x i32> @intrinsic_vsub_vi_tu_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {2311; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv4i32_nxv4i32_i32:2312; CHECK:       # %bb.0: # %entry2313; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma2314; CHECK-NEXT:    vadd.vi v8, v10, -92315; CHECK-NEXT:    ret2316entry:2317  %a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(2318    <vscale x 4 x i32> %0,2319    <vscale x 4 x i32> %1,2320    i32 9,2321    iXLen %2)2322 2323  ret <vscale x 4 x i32> %a2324}2325 2326define <vscale x 4 x i32> @intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2327; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32:2328; CHECK:       # %bb.0: # %entry2329; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu2330; CHECK-NEXT:    vadd.vi v8, v10, 9, v0.t2331; CHECK-NEXT:    ret2332entry:2333  %a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(2334    <vscale x 4 x i32> %0,2335    <vscale x 4 x i32> %1,2336    i32 -9,2337    <vscale x 4 x i1> %2,2338    iXLen %3, iXLen 1)2339 2340  ret <vscale x 4 x i32> %a2341}2342 2343define <vscale x 8 x i32> @intrinsic_vsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {2344; CHECK-LABEL: intrinsic_vsub_vi_nxv8i32_nxv8i32_i32:2345; CHECK:       # %bb.0: # %entry2346; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2347; CHECK-NEXT:    vadd.vi v8, v8, -92348; CHECK-NEXT:    ret2349entry:2350  %a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(2351    <vscale x 8 x i32> poison,2352    <vscale x 8 x i32> %0,2353    i32 9,2354    iXLen %1)2355 2356  ret <vscale x 8 x i32> %a2357}2358 2359define <vscale x 8 x i32> @intrinsic_vsub_vi_tu_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {2360; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv8i32_nxv8i32_i32:2361; CHECK:       # %bb.0: # %entry2362; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma2363; CHECK-NEXT:    vadd.vi v8, v12, -92364; CHECK-NEXT:    ret2365entry:2366  %a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(2367    <vscale x 8 x i32> %0,2368    <vscale x 8 x i32> %1,2369    i32 9,2370    iXLen %2)2371 2372  ret <vscale x 8 x i32> %a2373}2374 2375define <vscale x 8 x i32> @intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2376; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32:2377; CHECK:       # %bb.0: # %entry2378; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu2379; CHECK-NEXT:    vadd.vi v8, v12, 9, v0.t2380; CHECK-NEXT:    ret2381entry:2382  %a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(2383    <vscale x 8 x i32> %0,2384    <vscale x 8 x i32> %1,2385    i32 -9,2386    <vscale x 8 x i1> %2,2387    iXLen %3, iXLen 1)2388 2389  ret <vscale x 8 x i32> %a2390}2391 2392define <vscale x 16 x i32> @intrinsic_vsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {2393; CHECK-LABEL: intrinsic_vsub_vi_nxv16i32_nxv16i32_i32:2394; CHECK:       # %bb.0: # %entry2395; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2396; CHECK-NEXT:    vadd.vi v8, v8, -92397; CHECK-NEXT:    ret2398entry:2399  %a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(2400    <vscale x 16 x i32> poison,2401    <vscale x 16 x i32> %0,2402    i32 9,2403    iXLen %1)2404 2405  ret <vscale x 16 x i32> %a2406}2407 2408define <vscale x 16 x i32> @intrinsic_vsub_vi_tu_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {2409; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv16i32_nxv16i32_i32:2410; CHECK:       # %bb.0: # %entry2411; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma2412; CHECK-NEXT:    vadd.vi v8, v16, -92413; CHECK-NEXT:    ret2414entry:2415  %a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(2416    <vscale x 16 x i32> %0,2417    <vscale x 16 x i32> %1,2418    i32 9,2419    iXLen %2)2420 2421  ret <vscale x 16 x i32> %a2422}2423 2424define <vscale x 16 x i32> @intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {2425; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32:2426; CHECK:       # %bb.0: # %entry2427; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu2428; CHECK-NEXT:    vadd.vi v8, v16, 9, v0.t2429; CHECK-NEXT:    ret2430entry:2431  %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(2432    <vscale x 16 x i32> %0,2433    <vscale x 16 x i32> %1,2434    i32 -9,2435    <vscale x 16 x i1> %2,2436    iXLen %3, iXLen 1)2437 2438  ret <vscale x 16 x i32> %a2439}2440 2441define <vscale x 1 x i64> @intrinsic_vsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {2442; CHECK-LABEL: intrinsic_vsub_vi_nxv1i64_nxv1i64_i64:2443; CHECK:       # %bb.0: # %entry2444; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2445; CHECK-NEXT:    vadd.vi v8, v8, -92446; CHECK-NEXT:    ret2447entry:2448  %a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(2449    <vscale x 1 x i64> poison,2450    <vscale x 1 x i64> %0,2451    i64 9,2452    iXLen %1)2453 2454  ret <vscale x 1 x i64> %a2455}2456 2457define <vscale x 1 x i64> @intrinsic_vsub_vi_tu_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {2458; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv1i64_nxv1i64_i64:2459; CHECK:       # %bb.0: # %entry2460; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma2461; CHECK-NEXT:    vadd.vi v8, v9, -92462; CHECK-NEXT:    ret2463entry:2464  %a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(2465    <vscale x 1 x i64> %0,2466    <vscale x 1 x i64> %1,2467    i64 9,2468    iXLen %2)2469 2470  ret <vscale x 1 x i64> %a2471}2472 2473define <vscale x 1 x i64> @intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2474; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64:2475; CHECK:       # %bb.0: # %entry2476; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu2477; CHECK-NEXT:    vadd.vi v8, v9, -9, v0.t2478; CHECK-NEXT:    ret2479entry:2480  %a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(2481    <vscale x 1 x i64> %0,2482    <vscale x 1 x i64> %1,2483    i64 9,2484    <vscale x 1 x i1> %2,2485    iXLen %3, iXLen 1)2486 2487  ret <vscale x 1 x i64> %a2488}2489 2490define <vscale x 2 x i64> @intrinsic_vsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {2491; CHECK-LABEL: intrinsic_vsub_vi_nxv2i64_nxv2i64_i64:2492; CHECK:       # %bb.0: # %entry2493; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2494; CHECK-NEXT:    vadd.vi v8, v8, -92495; CHECK-NEXT:    ret2496entry:2497  %a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(2498    <vscale x 2 x i64> poison,2499    <vscale x 2 x i64> %0,2500    i64 9,2501    iXLen %1)2502 2503  ret <vscale x 2 x i64> %a2504}2505 2506define <vscale x 2 x i64> @intrinsic_vsub_vi_tu_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {2507; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv2i64_nxv2i64_i64:2508; CHECK:       # %bb.0: # %entry2509; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma2510; CHECK-NEXT:    vadd.vi v8, v10, -92511; CHECK-NEXT:    ret2512entry:2513  %a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(2514    <vscale x 2 x i64> %0,2515    <vscale x 2 x i64> %1,2516    i64 9,2517    iXLen %2)2518 2519  ret <vscale x 2 x i64> %a2520}2521 2522define <vscale x 2 x i64> @intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2523; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64:2524; CHECK:       # %bb.0: # %entry2525; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu2526; CHECK-NEXT:    vadd.vi v8, v10, -9, v0.t2527; CHECK-NEXT:    ret2528entry:2529  %a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(2530    <vscale x 2 x i64> %0,2531    <vscale x 2 x i64> %1,2532    i64 9,2533    <vscale x 2 x i1> %2,2534    iXLen %3, iXLen 1)2535 2536  ret <vscale x 2 x i64> %a2537}2538 2539define <vscale x 4 x i64> @intrinsic_vsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {2540; CHECK-LABEL: intrinsic_vsub_vi_nxv4i64_nxv4i64_i64:2541; CHECK:       # %bb.0: # %entry2542; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2543; CHECK-NEXT:    vadd.vi v8, v8, -92544; CHECK-NEXT:    ret2545entry:2546  %a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(2547    <vscale x 4 x i64> poison,2548    <vscale x 4 x i64> %0,2549    i64 9,2550    iXLen %1)2551 2552  ret <vscale x 4 x i64> %a2553}2554 2555define <vscale x 4 x i64> @intrinsic_vsub_vi_tu_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {2556; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv4i64_nxv4i64_i64:2557; CHECK:       # %bb.0: # %entry2558; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma2559; CHECK-NEXT:    vadd.vi v8, v12, -92560; CHECK-NEXT:    ret2561entry:2562  %a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(2563    <vscale x 4 x i64> %0,2564    <vscale x 4 x i64> %1,2565    i64 9,2566    iXLen %2)2567 2568  ret <vscale x 4 x i64> %a2569}2570 2571define <vscale x 4 x i64> @intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2572; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64:2573; CHECK:       # %bb.0: # %entry2574; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu2575; CHECK-NEXT:    vadd.vi v8, v12, -9, v0.t2576; CHECK-NEXT:    ret2577entry:2578  %a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(2579    <vscale x 4 x i64> %0,2580    <vscale x 4 x i64> %1,2581    i64 9,2582    <vscale x 4 x i1> %2,2583    iXLen %3, iXLen 1)2584 2585  ret <vscale x 4 x i64> %a2586}2587 2588define <vscale x 8 x i64> @intrinsic_vsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {2589; CHECK-LABEL: intrinsic_vsub_vi_nxv8i64_nxv8i64_i64:2590; CHECK:       # %bb.0: # %entry2591; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2592; CHECK-NEXT:    vadd.vi v8, v8, -92593; CHECK-NEXT:    ret2594entry:2595  %a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(2596    <vscale x 8 x i64> poison,2597    <vscale x 8 x i64> %0,2598    i64 9,2599    iXLen %1)2600 2601  ret <vscale x 8 x i64> %a2602}2603 2604define <vscale x 8 x i64> @intrinsic_vsub_vi_tu_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {2605; CHECK-LABEL: intrinsic_vsub_vi_tu_nxv8i64_nxv8i64_i64:2606; CHECK:       # %bb.0: # %entry2607; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, ma2608; CHECK-NEXT:    vadd.vi v8, v16, -92609; CHECK-NEXT:    ret2610entry:2611  %a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(2612    <vscale x 8 x i64> %0,2613    <vscale x 8 x i64> %1,2614    i64 9,2615    iXLen %2)2616 2617  ret <vscale x 8 x i64> %a2618}2619 2620define <vscale x 8 x i64> @intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2621; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64:2622; CHECK:       # %bb.0: # %entry2623; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu2624; CHECK-NEXT:    vadd.vi v8, v16, -9, v0.t2625; CHECK-NEXT:    ret2626entry:2627  %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(2628    <vscale x 8 x i64> %0,2629    <vscale x 8 x i64> %1,2630    i64 9,2631    <vscale x 8 x i1> %2,2632    iXLen %3, iXLen 1)2633 2634  ret <vscale x 8 x i64> %a2635}2636