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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define void @intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vsuxei32.v v8, (a0), v912; CHECK-NEXT: ret13entry:14 call void @llvm.riscv.vsuxei.nxv1i8.nxv1i32(15 <vscale x 1 x i8> %0,16 ptr %1,17 <vscale x 1 x i32> %2,18 iXLen %3)19 20 ret void21}22 23define void @intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i32:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma27; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t28; CHECK-NEXT: ret29entry:30 call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i32(31 <vscale x 1 x i8> %0,32 ptr %1,33 <vscale x 1 x i32> %2,34 <vscale x 1 x i1> %3,35 iXLen %4)36 37 ret void38}39 40define void @intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {41; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i32:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma44; CHECK-NEXT: vsuxei32.v v8, (a0), v945; CHECK-NEXT: ret46entry:47 call void @llvm.riscv.vsuxei.nxv2i8.nxv2i32(48 <vscale x 2 x i8> %0,49 ptr %1,50 <vscale x 2 x i32> %2,51 iXLen %3)52 53 ret void54}55 56define void @intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i32:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma60; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t61; CHECK-NEXT: ret62entry:63 call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i32(64 <vscale x 2 x i8> %0,65 ptr %1,66 <vscale x 2 x i32> %2,67 <vscale x 2 x i1> %3,68 iXLen %4)69 70 ret void71}72 73define void @intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {74; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i32:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma77; CHECK-NEXT: vsuxei32.v v8, (a0), v1078; CHECK-NEXT: ret79entry:80 call void @llvm.riscv.vsuxei.nxv4i8.nxv4i32(81 <vscale x 4 x i8> %0,82 ptr %1,83 <vscale x 4 x i32> %2,84 iXLen %3)85 86 ret void87}88 89define void @intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i32:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma93; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t94; CHECK-NEXT: ret95entry:96 call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i32(97 <vscale x 4 x i8> %0,98 ptr %1,99 <vscale x 4 x i32> %2,100 <vscale x 4 x i1> %3,101 iXLen %4)102 103 ret void104}105 106define void @intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {107; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i32:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma110; CHECK-NEXT: vsuxei32.v v8, (a0), v12111; CHECK-NEXT: ret112entry:113 call void @llvm.riscv.vsuxei.nxv8i8.nxv8i32(114 <vscale x 8 x i8> %0,115 ptr %1,116 <vscale x 8 x i32> %2,117 iXLen %3)118 119 ret void120}121 122define void @intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i32:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma126; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t127; CHECK-NEXT: ret128entry:129 call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i32(130 <vscale x 8 x i8> %0,131 ptr %1,132 <vscale x 8 x i32> %2,133 <vscale x 8 x i1> %3,134 iXLen %4)135 136 ret void137}138 139define void @intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {140; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i32:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma143; CHECK-NEXT: vsuxei32.v v8, (a0), v16144; CHECK-NEXT: ret145entry:146 call void @llvm.riscv.vsuxei.nxv16i8.nxv16i32(147 <vscale x 16 x i8> %0,148 ptr %1,149 <vscale x 16 x i32> %2,150 iXLen %3)151 152 ret void153}154 155define void @intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i32:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma159; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t160; CHECK-NEXT: ret161entry:162 call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i32(163 <vscale x 16 x i8> %0,164 ptr %1,165 <vscale x 16 x i32> %2,166 <vscale x 16 x i1> %3,167 iXLen %4)168 169 ret void170}171 172define void @intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {173; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i32:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma176; CHECK-NEXT: vsuxei32.v v8, (a0), v9177; CHECK-NEXT: ret178entry:179 call void @llvm.riscv.vsuxei.nxv1i16.nxv1i32(180 <vscale x 1 x i16> %0,181 ptr %1,182 <vscale x 1 x i32> %2,183 iXLen %3)184 185 ret void186}187 188define void @intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i32:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma192; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t193; CHECK-NEXT: ret194entry:195 call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i32(196 <vscale x 1 x i16> %0,197 ptr %1,198 <vscale x 1 x i32> %2,199 <vscale x 1 x i1> %3,200 iXLen %4)201 202 ret void203}204 205define void @intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i32:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma209; CHECK-NEXT: vsuxei32.v v8, (a0), v9210; CHECK-NEXT: ret211entry:212 call void @llvm.riscv.vsuxei.nxv2i16.nxv2i32(213 <vscale x 2 x i16> %0,214 ptr %1,215 <vscale x 2 x i32> %2,216 iXLen %3)217 218 ret void219}220 221define void @intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i32:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma225; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t226; CHECK-NEXT: ret227entry:228 call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i32(229 <vscale x 2 x i16> %0,230 ptr %1,231 <vscale x 2 x i32> %2,232 <vscale x 2 x i1> %3,233 iXLen %4)234 235 ret void236}237 238define void @intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {239; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i32:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma242; CHECK-NEXT: vsuxei32.v v8, (a0), v10243; CHECK-NEXT: ret244entry:245 call void @llvm.riscv.vsuxei.nxv4i16.nxv4i32(246 <vscale x 4 x i16> %0,247 ptr %1,248 <vscale x 4 x i32> %2,249 iXLen %3)250 251 ret void252}253 254define void @intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i32:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma258; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t259; CHECK-NEXT: ret260entry:261 call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i32(262 <vscale x 4 x i16> %0,263 ptr %1,264 <vscale x 4 x i32> %2,265 <vscale x 4 x i1> %3,266 iXLen %4)267 268 ret void269}270 271define void @intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {272; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i32:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma275; CHECK-NEXT: vsuxei32.v v8, (a0), v12276; CHECK-NEXT: ret277entry:278 call void @llvm.riscv.vsuxei.nxv8i16.nxv8i32(279 <vscale x 8 x i16> %0,280 ptr %1,281 <vscale x 8 x i32> %2,282 iXLen %3)283 284 ret void285}286 287define void @intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i32:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma291; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t292; CHECK-NEXT: ret293entry:294 call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i32(295 <vscale x 8 x i16> %0,296 ptr %1,297 <vscale x 8 x i32> %2,298 <vscale x 8 x i1> %3,299 iXLen %4)300 301 ret void302}303 304define void @intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {305; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i32:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma308; CHECK-NEXT: vsuxei32.v v8, (a0), v16309; CHECK-NEXT: ret310entry:311 call void @llvm.riscv.vsuxei.nxv16i16.nxv16i32(312 <vscale x 16 x i16> %0,313 ptr %1,314 <vscale x 16 x i32> %2,315 iXLen %3)316 317 ret void318}319 320define void @intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i32:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma324; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t325; CHECK-NEXT: ret326entry:327 call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i32(328 <vscale x 16 x i16> %0,329 ptr %1,330 <vscale x 16 x i32> %2,331 <vscale x 16 x i1> %3,332 iXLen %4)333 334 ret void335}336 337define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {338; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i32:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma341; CHECK-NEXT: vsuxei32.v v8, (a0), v9342; CHECK-NEXT: ret343entry:344 call void @llvm.riscv.vsuxei.nxv1i32.nxv1i32(345 <vscale x 1 x i32> %0,346 ptr %1,347 <vscale x 1 x i32> %2,348 iXLen %3)349 350 ret void351}352 353define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i32:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma357; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t358; CHECK-NEXT: ret359entry:360 call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i32(361 <vscale x 1 x i32> %0,362 ptr %1,363 <vscale x 1 x i32> %2,364 <vscale x 1 x i1> %3,365 iXLen %4)366 367 ret void368}369 370define void @intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {371; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i32:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma374; CHECK-NEXT: vsuxei32.v v8, (a0), v9375; CHECK-NEXT: ret376entry:377 call void @llvm.riscv.vsuxei.nxv2i32.nxv2i32(378 <vscale x 2 x i32> %0,379 ptr %1,380 <vscale x 2 x i32> %2,381 iXLen %3)382 383 ret void384}385 386define void @intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i32:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma390; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t391; CHECK-NEXT: ret392entry:393 call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i32(394 <vscale x 2 x i32> %0,395 ptr %1,396 <vscale x 2 x i32> %2,397 <vscale x 2 x i1> %3,398 iXLen %4)399 400 ret void401}402 403define void @intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {404; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i32:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma407; CHECK-NEXT: vsuxei32.v v8, (a0), v10408; CHECK-NEXT: ret409entry:410 call void @llvm.riscv.vsuxei.nxv4i32.nxv4i32(411 <vscale x 4 x i32> %0,412 ptr %1,413 <vscale x 4 x i32> %2,414 iXLen %3)415 416 ret void417}418 419define void @intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i32:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma423; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t424; CHECK-NEXT: ret425entry:426 call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i32(427 <vscale x 4 x i32> %0,428 ptr %1,429 <vscale x 4 x i32> %2,430 <vscale x 4 x i1> %3,431 iXLen %4)432 433 ret void434}435 436define void @intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {437; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma440; CHECK-NEXT: vsuxei32.v v8, (a0), v12441; CHECK-NEXT: ret442entry:443 call void @llvm.riscv.vsuxei.nxv8i32.nxv8i32(444 <vscale x 8 x i32> %0,445 ptr %1,446 <vscale x 8 x i32> %2,447 iXLen %3)448 449 ret void450}451 452define void @intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i32:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma456; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t457; CHECK-NEXT: ret458entry:459 call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i32(460 <vscale x 8 x i32> %0,461 ptr %1,462 <vscale x 8 x i32> %2,463 <vscale x 8 x i1> %3,464 iXLen %4)465 466 ret void467}468 469define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {470; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma473; CHECK-NEXT: vsuxei32.v v8, (a0), v16474; CHECK-NEXT: ret475entry:476 call void @llvm.riscv.vsuxei.nxv16i32.nxv16i32(477 <vscale x 16 x i32> %0,478 ptr %1,479 <vscale x 16 x i32> %2,480 iXLen %3)481 482 ret void483}484 485define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma489; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t490; CHECK-NEXT: ret491entry:492 call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i32(493 <vscale x 16 x i32> %0,494 ptr %1,495 <vscale x 16 x i32> %2,496 <vscale x 16 x i1> %3,497 iXLen %4)498 499 ret void500}501 502define void @intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {503; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i32:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma506; CHECK-NEXT: vsuxei32.v v8, (a0), v9507; CHECK-NEXT: ret508entry:509 call void @llvm.riscv.vsuxei.nxv1i64.nxv1i32(510 <vscale x 1 x i64> %0,511 ptr %1,512 <vscale x 1 x i32> %2,513 iXLen %3)514 515 ret void516}517 518define void @intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {519; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i32:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma522; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t523; CHECK-NEXT: ret524entry:525 call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i32(526 <vscale x 1 x i64> %0,527 ptr %1,528 <vscale x 1 x i32> %2,529 <vscale x 1 x i1> %3,530 iXLen %4)531 532 ret void533}534 535define void @intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {536; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i32:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma539; CHECK-NEXT: vsuxei32.v v8, (a0), v10540; CHECK-NEXT: ret541entry:542 call void @llvm.riscv.vsuxei.nxv2i64.nxv2i32(543 <vscale x 2 x i64> %0,544 ptr %1,545 <vscale x 2 x i32> %2,546 iXLen %3)547 548 ret void549}550 551define void @intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma555; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t556; CHECK-NEXT: ret557entry:558 call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i32(559 <vscale x 2 x i64> %0,560 ptr %1,561 <vscale x 2 x i32> %2,562 <vscale x 2 x i1> %3,563 iXLen %4)564 565 ret void566}567 568define void @intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {569; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i32:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma572; CHECK-NEXT: vsuxei32.v v8, (a0), v12573; CHECK-NEXT: ret574entry:575 call void @llvm.riscv.vsuxei.nxv4i64.nxv4i32(576 <vscale x 4 x i64> %0,577 ptr %1,578 <vscale x 4 x i32> %2,579 iXLen %3)580 581 ret void582}583 584define void @intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {585; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i32:586; CHECK: # %bb.0: # %entry587; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma588; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t589; CHECK-NEXT: ret590entry:591 call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i32(592 <vscale x 4 x i64> %0,593 ptr %1,594 <vscale x 4 x i32> %2,595 <vscale x 4 x i1> %3,596 iXLen %4)597 598 ret void599}600 601define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {602; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i32:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma605; CHECK-NEXT: vsuxei32.v v8, (a0), v16606; CHECK-NEXT: ret607entry:608 call void @llvm.riscv.vsuxei.nxv8i64.nxv8i32(609 <vscale x 8 x i64> %0,610 ptr %1,611 <vscale x 8 x i32> %2,612 iXLen %3)613 614 ret void615}616 617define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {618; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i32:619; CHECK: # %bb.0: # %entry620; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma621; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t622; CHECK-NEXT: ret623entry:624 call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i32(625 <vscale x 8 x i64> %0,626 ptr %1,627 <vscale x 8 x i32> %2,628 <vscale x 8 x i1> %3,629 iXLen %4)630 631 ret void632}633 634define void @intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {635; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i32:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma638; CHECK-NEXT: vsuxei32.v v8, (a0), v9639; CHECK-NEXT: ret640entry:641 call void @llvm.riscv.vsuxei.nxv1f16.nxv1i32(642 <vscale x 1 x half> %0,643 ptr %1,644 <vscale x 1 x i32> %2,645 iXLen %3)646 647 ret void648}649 650define void @intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {651; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i32:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma654; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t655; CHECK-NEXT: ret656entry:657 call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i32(658 <vscale x 1 x half> %0,659 ptr %1,660 <vscale x 1 x i32> %2,661 <vscale x 1 x i1> %3,662 iXLen %4)663 664 ret void665}666 667define void @intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {668; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i32:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma671; CHECK-NEXT: vsuxei32.v v8, (a0), v9672; CHECK-NEXT: ret673entry:674 call void @llvm.riscv.vsuxei.nxv2f16.nxv2i32(675 <vscale x 2 x half> %0,676 ptr %1,677 <vscale x 2 x i32> %2,678 iXLen %3)679 680 ret void681}682 683define void @intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {684; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i32:685; CHECK: # %bb.0: # %entry686; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma687; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t688; CHECK-NEXT: ret689entry:690 call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i32(691 <vscale x 2 x half> %0,692 ptr %1,693 <vscale x 2 x i32> %2,694 <vscale x 2 x i1> %3,695 iXLen %4)696 697 ret void698}699 700define void @intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {701; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i32:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma704; CHECK-NEXT: vsuxei32.v v8, (a0), v10705; CHECK-NEXT: ret706entry:707 call void @llvm.riscv.vsuxei.nxv4f16.nxv4i32(708 <vscale x 4 x half> %0,709 ptr %1,710 <vscale x 4 x i32> %2,711 iXLen %3)712 713 ret void714}715 716define void @intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {717; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i32:718; CHECK: # %bb.0: # %entry719; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma720; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t721; CHECK-NEXT: ret722entry:723 call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i32(724 <vscale x 4 x half> %0,725 ptr %1,726 <vscale x 4 x i32> %2,727 <vscale x 4 x i1> %3,728 iXLen %4)729 730 ret void731}732 733define void @intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {734; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i32:735; CHECK: # %bb.0: # %entry736; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma737; CHECK-NEXT: vsuxei32.v v8, (a0), v12738; CHECK-NEXT: ret739entry:740 call void @llvm.riscv.vsuxei.nxv8f16.nxv8i32(741 <vscale x 8 x half> %0,742 ptr %1,743 <vscale x 8 x i32> %2,744 iXLen %3)745 746 ret void747}748 749define void @intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {750; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i32:751; CHECK: # %bb.0: # %entry752; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma753; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t754; CHECK-NEXT: ret755entry:756 call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i32(757 <vscale x 8 x half> %0,758 ptr %1,759 <vscale x 8 x i32> %2,760 <vscale x 8 x i1> %3,761 iXLen %4)762 763 ret void764}765 766define void @intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {767; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i32:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma770; CHECK-NEXT: vsuxei32.v v8, (a0), v16771; CHECK-NEXT: ret772entry:773 call void @llvm.riscv.vsuxei.nxv16f16.nxv16i32(774 <vscale x 16 x half> %0,775 ptr %1,776 <vscale x 16 x i32> %2,777 iXLen %3)778 779 ret void780}781 782define void @intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {783; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i32:784; CHECK: # %bb.0: # %entry785; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma786; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t787; CHECK-NEXT: ret788entry:789 call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i32(790 <vscale x 16 x half> %0,791 ptr %1,792 <vscale x 16 x i32> %2,793 <vscale x 16 x i1> %3,794 iXLen %4)795 796 ret void797}798 799define void @intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {800; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i32:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma803; CHECK-NEXT: vsuxei32.v v8, (a0), v9804; CHECK-NEXT: ret805entry:806 call void @llvm.riscv.vsuxei.nxv1f32.nxv1i32(807 <vscale x 1 x float> %0,808 ptr %1,809 <vscale x 1 x i32> %2,810 iXLen %3)811 812 ret void813}814 815define void @intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {816; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i32:817; CHECK: # %bb.0: # %entry818; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma819; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t820; CHECK-NEXT: ret821entry:822 call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i32(823 <vscale x 1 x float> %0,824 ptr %1,825 <vscale x 1 x i32> %2,826 <vscale x 1 x i1> %3,827 iXLen %4)828 829 ret void830}831 832define void @intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {833; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i32:834; CHECK: # %bb.0: # %entry835; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma836; CHECK-NEXT: vsuxei32.v v8, (a0), v9837; CHECK-NEXT: ret838entry:839 call void @llvm.riscv.vsuxei.nxv2f32.nxv2i32(840 <vscale x 2 x float> %0,841 ptr %1,842 <vscale x 2 x i32> %2,843 iXLen %3)844 845 ret void846}847 848define void @intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {849; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i32:850; CHECK: # %bb.0: # %entry851; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma852; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t853; CHECK-NEXT: ret854entry:855 call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i32(856 <vscale x 2 x float> %0,857 ptr %1,858 <vscale x 2 x i32> %2,859 <vscale x 2 x i1> %3,860 iXLen %4)861 862 ret void863}864 865define void @intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {866; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i32:867; CHECK: # %bb.0: # %entry868; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma869; CHECK-NEXT: vsuxei32.v v8, (a0), v10870; CHECK-NEXT: ret871entry:872 call void @llvm.riscv.vsuxei.nxv4f32.nxv4i32(873 <vscale x 4 x float> %0,874 ptr %1,875 <vscale x 4 x i32> %2,876 iXLen %3)877 878 ret void879}880 881define void @intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {882; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i32:883; CHECK: # %bb.0: # %entry884; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma885; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t886; CHECK-NEXT: ret887entry:888 call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i32(889 <vscale x 4 x float> %0,890 ptr %1,891 <vscale x 4 x i32> %2,892 <vscale x 4 x i1> %3,893 iXLen %4)894 895 ret void896}897 898define void @intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {899; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i32:900; CHECK: # %bb.0: # %entry901; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma902; CHECK-NEXT: vsuxei32.v v8, (a0), v12903; CHECK-NEXT: ret904entry:905 call void @llvm.riscv.vsuxei.nxv8f32.nxv8i32(906 <vscale x 8 x float> %0,907 ptr %1,908 <vscale x 8 x i32> %2,909 iXLen %3)910 911 ret void912}913 914define void @intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {915; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i32:916; CHECK: # %bb.0: # %entry917; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma918; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t919; CHECK-NEXT: ret920entry:921 call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i32(922 <vscale x 8 x float> %0,923 ptr %1,924 <vscale x 8 x i32> %2,925 <vscale x 8 x i1> %3,926 iXLen %4)927 928 ret void929}930 931define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {932; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i32:933; CHECK: # %bb.0: # %entry934; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma935; CHECK-NEXT: vsuxei32.v v8, (a0), v16936; CHECK-NEXT: ret937entry:938 call void @llvm.riscv.vsuxei.nxv16f32.nxv16i32(939 <vscale x 16 x float> %0,940 ptr %1,941 <vscale x 16 x i32> %2,942 iXLen %3)943 944 ret void945}946 947define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {948; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i32:949; CHECK: # %bb.0: # %entry950; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma951; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t952; CHECK-NEXT: ret953entry:954 call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i32(955 <vscale x 16 x float> %0,956 ptr %1,957 <vscale x 16 x i32> %2,958 <vscale x 16 x i1> %3,959 iXLen %4)960 961 ret void962}963 964define void @intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {965; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i32:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma968; CHECK-NEXT: vsuxei32.v v8, (a0), v9969; CHECK-NEXT: ret970entry:971 call void @llvm.riscv.vsuxei.nxv1f64.nxv1i32(972 <vscale x 1 x double> %0,973 ptr %1,974 <vscale x 1 x i32> %2,975 iXLen %3)976 977 ret void978}979 980define void @intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {981; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i32:982; CHECK: # %bb.0: # %entry983; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma984; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t985; CHECK-NEXT: ret986entry:987 call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i32(988 <vscale x 1 x double> %0,989 ptr %1,990 <vscale x 1 x i32> %2,991 <vscale x 1 x i1> %3,992 iXLen %4)993 994 ret void995}996 997define void @intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {998; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i32:999; CHECK: # %bb.0: # %entry1000; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma1001; CHECK-NEXT: vsuxei32.v v8, (a0), v101002; CHECK-NEXT: ret1003entry:1004 call void @llvm.riscv.vsuxei.nxv2f64.nxv2i32(1005 <vscale x 2 x double> %0,1006 ptr %1,1007 <vscale x 2 x i32> %2,1008 iXLen %3)1009 1010 ret void1011}1012 1013define void @intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1014; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i32:1015; CHECK: # %bb.0: # %entry1016; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma1017; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t1018; CHECK-NEXT: ret1019entry:1020 call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i32(1021 <vscale x 2 x double> %0,1022 ptr %1,1023 <vscale x 2 x i32> %2,1024 <vscale x 2 x i1> %3,1025 iXLen %4)1026 1027 ret void1028}1029 1030define void @intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {1031; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i32:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1034; CHECK-NEXT: vsuxei32.v v8, (a0), v121035; CHECK-NEXT: ret1036entry:1037 call void @llvm.riscv.vsuxei.nxv4f64.nxv4i32(1038 <vscale x 4 x double> %0,1039 ptr %1,1040 <vscale x 4 x i32> %2,1041 iXLen %3)1042 1043 ret void1044}1045 1046define void @intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1047; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i32:1048; CHECK: # %bb.0: # %entry1049; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1050; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t1051; CHECK-NEXT: ret1052entry:1053 call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i32(1054 <vscale x 4 x double> %0,1055 ptr %1,1056 <vscale x 4 x i32> %2,1057 <vscale x 4 x i1> %3,1058 iXLen %4)1059 1060 ret void1061}1062 1063define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {1064; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i32:1065; CHECK: # %bb.0: # %entry1066; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1067; CHECK-NEXT: vsuxei32.v v8, (a0), v161068; CHECK-NEXT: ret1069entry:1070 call void @llvm.riscv.vsuxei.nxv8f64.nxv8i32(1071 <vscale x 8 x double> %0,1072 ptr %1,1073 <vscale x 8 x i32> %2,1074 iXLen %3)1075 1076 ret void1077}1078 1079define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1080; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i32:1081; CHECK: # %bb.0: # %entry1082; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1083; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t1084; CHECK-NEXT: ret1085entry:1086 call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i32(1087 <vscale x 8 x double> %0,1088 ptr %1,1089 <vscale x 8 x i32> %2,1090 <vscale x 8 x i1> %3,1091 iXLen %4)1092 1093 ret void1094}1095 1096define void @intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {1097; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i16:1098; CHECK: # %bb.0: # %entry1099; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1100; CHECK-NEXT: vsuxei16.v v8, (a0), v91101; CHECK-NEXT: ret1102entry:1103 call void @llvm.riscv.vsuxei.nxv1i8.nxv1i16(1104 <vscale x 1 x i8> %0,1105 ptr %1,1106 <vscale x 1 x i16> %2,1107 iXLen %3)1108 1109 ret void1110}1111 1112define void @intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1113; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i16:1114; CHECK: # %bb.0: # %entry1115; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1116; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1117; CHECK-NEXT: ret1118entry:1119 call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i16(1120 <vscale x 1 x i8> %0,1121 ptr %1,1122 <vscale x 1 x i16> %2,1123 <vscale x 1 x i1> %3,1124 iXLen %4)1125 1126 ret void1127}1128 1129define void @intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {1130; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i16:1131; CHECK: # %bb.0: # %entry1132; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1133; CHECK-NEXT: vsuxei16.v v8, (a0), v91134; CHECK-NEXT: ret1135entry:1136 call void @llvm.riscv.vsuxei.nxv2i8.nxv2i16(1137 <vscale x 2 x i8> %0,1138 ptr %1,1139 <vscale x 2 x i16> %2,1140 iXLen %3)1141 1142 ret void1143}1144 1145define void @intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1146; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i16:1147; CHECK: # %bb.0: # %entry1148; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1149; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1150; CHECK-NEXT: ret1151entry:1152 call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i16(1153 <vscale x 2 x i8> %0,1154 ptr %1,1155 <vscale x 2 x i16> %2,1156 <vscale x 2 x i1> %3,1157 iXLen %4)1158 1159 ret void1160}1161 1162define void @intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {1163; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i16:1164; CHECK: # %bb.0: # %entry1165; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1166; CHECK-NEXT: vsuxei16.v v8, (a0), v91167; CHECK-NEXT: ret1168entry:1169 call void @llvm.riscv.vsuxei.nxv4i8.nxv4i16(1170 <vscale x 4 x i8> %0,1171 ptr %1,1172 <vscale x 4 x i16> %2,1173 iXLen %3)1174 1175 ret void1176}1177 1178define void @intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1179; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i16:1180; CHECK: # %bb.0: # %entry1181; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1182; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1183; CHECK-NEXT: ret1184entry:1185 call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i16(1186 <vscale x 4 x i8> %0,1187 ptr %1,1188 <vscale x 4 x i16> %2,1189 <vscale x 4 x i1> %3,1190 iXLen %4)1191 1192 ret void1193}1194 1195define void @intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {1196; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i16:1197; CHECK: # %bb.0: # %entry1198; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1199; CHECK-NEXT: vsuxei16.v v8, (a0), v101200; CHECK-NEXT: ret1201entry:1202 call void @llvm.riscv.vsuxei.nxv8i8.nxv8i16(1203 <vscale x 8 x i8> %0,1204 ptr %1,1205 <vscale x 8 x i16> %2,1206 iXLen %3)1207 1208 ret void1209}1210 1211define void @intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1212; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i16:1213; CHECK: # %bb.0: # %entry1214; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1215; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t1216; CHECK-NEXT: ret1217entry:1218 call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i16(1219 <vscale x 8 x i8> %0,1220 ptr %1,1221 <vscale x 8 x i16> %2,1222 <vscale x 8 x i1> %3,1223 iXLen %4)1224 1225 ret void1226}1227 1228define void @intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {1229; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i16:1230; CHECK: # %bb.0: # %entry1231; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1232; CHECK-NEXT: vsuxei16.v v8, (a0), v121233; CHECK-NEXT: ret1234entry:1235 call void @llvm.riscv.vsuxei.nxv16i8.nxv16i16(1236 <vscale x 16 x i8> %0,1237 ptr %1,1238 <vscale x 16 x i16> %2,1239 iXLen %3)1240 1241 ret void1242}1243 1244define void @intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1245; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i16:1246; CHECK: # %bb.0: # %entry1247; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1248; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t1249; CHECK-NEXT: ret1250entry:1251 call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i16(1252 <vscale x 16 x i8> %0,1253 ptr %1,1254 <vscale x 16 x i16> %2,1255 <vscale x 16 x i1> %3,1256 iXLen %4)1257 1258 ret void1259}1260 1261define void @intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i16> %2, iXLen %3) nounwind {1262; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i16:1263; CHECK: # %bb.0: # %entry1264; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma1265; CHECK-NEXT: vsuxei16.v v8, (a0), v161266; CHECK-NEXT: ret1267entry:1268 call void @llvm.riscv.vsuxei.nxv32i8.nxv32i16(1269 <vscale x 32 x i8> %0,1270 ptr %1,1271 <vscale x 32 x i16> %2,1272 iXLen %3)1273 1274 ret void1275}1276 1277define void @intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1278; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i16:1279; CHECK: # %bb.0: # %entry1280; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma1281; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t1282; CHECK-NEXT: ret1283entry:1284 call void @llvm.riscv.vsuxei.mask.nxv32i8.nxv32i16(1285 <vscale x 32 x i8> %0,1286 ptr %1,1287 <vscale x 32 x i16> %2,1288 <vscale x 32 x i1> %3,1289 iXLen %4)1290 1291 ret void1292}1293 1294define void @intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {1295; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i16:1296; CHECK: # %bb.0: # %entry1297; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1298; CHECK-NEXT: vsuxei16.v v8, (a0), v91299; CHECK-NEXT: ret1300entry:1301 call void @llvm.riscv.vsuxei.nxv1i16.nxv1i16(1302 <vscale x 1 x i16> %0,1303 ptr %1,1304 <vscale x 1 x i16> %2,1305 iXLen %3)1306 1307 ret void1308}1309 1310define void @intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1311; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i16:1312; CHECK: # %bb.0: # %entry1313; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1314; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1315; CHECK-NEXT: ret1316entry:1317 call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i16(1318 <vscale x 1 x i16> %0,1319 ptr %1,1320 <vscale x 1 x i16> %2,1321 <vscale x 1 x i1> %3,1322 iXLen %4)1323 1324 ret void1325}1326 1327define void @intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {1328; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i16:1329; CHECK: # %bb.0: # %entry1330; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1331; CHECK-NEXT: vsuxei16.v v8, (a0), v91332; CHECK-NEXT: ret1333entry:1334 call void @llvm.riscv.vsuxei.nxv2i16.nxv2i16(1335 <vscale x 2 x i16> %0,1336 ptr %1,1337 <vscale x 2 x i16> %2,1338 iXLen %3)1339 1340 ret void1341}1342 1343define void @intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1344; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i16:1345; CHECK: # %bb.0: # %entry1346; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1347; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1348; CHECK-NEXT: ret1349entry:1350 call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i16(1351 <vscale x 2 x i16> %0,1352 ptr %1,1353 <vscale x 2 x i16> %2,1354 <vscale x 2 x i1> %3,1355 iXLen %4)1356 1357 ret void1358}1359 1360define void @intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {1361; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i16:1362; CHECK: # %bb.0: # %entry1363; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1364; CHECK-NEXT: vsuxei16.v v8, (a0), v91365; CHECK-NEXT: ret1366entry:1367 call void @llvm.riscv.vsuxei.nxv4i16.nxv4i16(1368 <vscale x 4 x i16> %0,1369 ptr %1,1370 <vscale x 4 x i16> %2,1371 iXLen %3)1372 1373 ret void1374}1375 1376define void @intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1377; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i16:1378; CHECK: # %bb.0: # %entry1379; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1380; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1381; CHECK-NEXT: ret1382entry:1383 call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i16(1384 <vscale x 4 x i16> %0,1385 ptr %1,1386 <vscale x 4 x i16> %2,1387 <vscale x 4 x i1> %3,1388 iXLen %4)1389 1390 ret void1391}1392 1393define void @intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {1394; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i16:1395; CHECK: # %bb.0: # %entry1396; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1397; CHECK-NEXT: vsuxei16.v v8, (a0), v101398; CHECK-NEXT: ret1399entry:1400 call void @llvm.riscv.vsuxei.nxv8i16.nxv8i16(1401 <vscale x 8 x i16> %0,1402 ptr %1,1403 <vscale x 8 x i16> %2,1404 iXLen %3)1405 1406 ret void1407}1408 1409define void @intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1410; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i16:1411; CHECK: # %bb.0: # %entry1412; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1413; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t1414; CHECK-NEXT: ret1415entry:1416 call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i16(1417 <vscale x 8 x i16> %0,1418 ptr %1,1419 <vscale x 8 x i16> %2,1420 <vscale x 8 x i1> %3,1421 iXLen %4)1422 1423 ret void1424}1425 1426define void @intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {1427; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i16:1428; CHECK: # %bb.0: # %entry1429; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1430; CHECK-NEXT: vsuxei16.v v8, (a0), v121431; CHECK-NEXT: ret1432entry:1433 call void @llvm.riscv.vsuxei.nxv16i16.nxv16i16(1434 <vscale x 16 x i16> %0,1435 ptr %1,1436 <vscale x 16 x i16> %2,1437 iXLen %3)1438 1439 ret void1440}1441 1442define void @intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1443; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i16:1444; CHECK: # %bb.0: # %entry1445; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1446; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t1447; CHECK-NEXT: ret1448entry:1449 call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i16(1450 <vscale x 16 x i16> %0,1451 ptr %1,1452 <vscale x 16 x i16> %2,1453 <vscale x 16 x i1> %3,1454 iXLen %4)1455 1456 ret void1457}1458 1459define void @intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i16> %2, iXLen %3) nounwind {1460; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i16:1461; CHECK: # %bb.0: # %entry1462; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1463; CHECK-NEXT: vsuxei16.v v8, (a0), v161464; CHECK-NEXT: ret1465entry:1466 call void @llvm.riscv.vsuxei.nxv32i16.nxv32i16(1467 <vscale x 32 x i16> %0,1468 ptr %1,1469 <vscale x 32 x i16> %2,1470 iXLen %3)1471 1472 ret void1473}1474 1475define void @intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1476; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i16:1477; CHECK: # %bb.0: # %entry1478; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1479; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t1480; CHECK-NEXT: ret1481entry:1482 call void @llvm.riscv.vsuxei.mask.nxv32i16.nxv32i16(1483 <vscale x 32 x i16> %0,1484 ptr %1,1485 <vscale x 32 x i16> %2,1486 <vscale x 32 x i1> %3,1487 iXLen %4)1488 1489 ret void1490}1491 1492define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {1493; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16:1494; CHECK: # %bb.0: # %entry1495; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1496; CHECK-NEXT: vsuxei16.v v8, (a0), v91497; CHECK-NEXT: ret1498entry:1499 call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16(1500 <vscale x 1 x i32> %0,1501 ptr %1,1502 <vscale x 1 x i16> %2,1503 iXLen %3)1504 1505 ret void1506}1507 1508define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1509; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16:1510; CHECK: # %bb.0: # %entry1511; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1512; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1513; CHECK-NEXT: ret1514entry:1515 call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16(1516 <vscale x 1 x i32> %0,1517 ptr %1,1518 <vscale x 1 x i16> %2,1519 <vscale x 1 x i1> %3,1520 iXLen %4)1521 1522 ret void1523}1524 1525define void @intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {1526; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i16:1527; CHECK: # %bb.0: # %entry1528; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1529; CHECK-NEXT: vsuxei16.v v8, (a0), v91530; CHECK-NEXT: ret1531entry:1532 call void @llvm.riscv.vsuxei.nxv2i32.nxv2i16(1533 <vscale x 2 x i32> %0,1534 ptr %1,1535 <vscale x 2 x i16> %2,1536 iXLen %3)1537 1538 ret void1539}1540 1541define void @intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1542; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i16:1543; CHECK: # %bb.0: # %entry1544; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1545; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1546; CHECK-NEXT: ret1547entry:1548 call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i16(1549 <vscale x 2 x i32> %0,1550 ptr %1,1551 <vscale x 2 x i16> %2,1552 <vscale x 2 x i1> %3,1553 iXLen %4)1554 1555 ret void1556}1557 1558define void @intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {1559; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i16:1560; CHECK: # %bb.0: # %entry1561; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1562; CHECK-NEXT: vsuxei16.v v8, (a0), v101563; CHECK-NEXT: ret1564entry:1565 call void @llvm.riscv.vsuxei.nxv4i32.nxv4i16(1566 <vscale x 4 x i32> %0,1567 ptr %1,1568 <vscale x 4 x i16> %2,1569 iXLen %3)1570 1571 ret void1572}1573 1574define void @intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1575; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i16:1576; CHECK: # %bb.0: # %entry1577; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1578; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t1579; CHECK-NEXT: ret1580entry:1581 call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i16(1582 <vscale x 4 x i32> %0,1583 ptr %1,1584 <vscale x 4 x i16> %2,1585 <vscale x 4 x i1> %3,1586 iXLen %4)1587 1588 ret void1589}1590 1591define void @intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {1592; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i16:1593; CHECK: # %bb.0: # %entry1594; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1595; CHECK-NEXT: vsuxei16.v v8, (a0), v121596; CHECK-NEXT: ret1597entry:1598 call void @llvm.riscv.vsuxei.nxv8i32.nxv8i16(1599 <vscale x 8 x i32> %0,1600 ptr %1,1601 <vscale x 8 x i16> %2,1602 iXLen %3)1603 1604 ret void1605}1606 1607define void @intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1608; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i16:1609; CHECK: # %bb.0: # %entry1610; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1611; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t1612; CHECK-NEXT: ret1613entry:1614 call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i16(1615 <vscale x 8 x i32> %0,1616 ptr %1,1617 <vscale x 8 x i16> %2,1618 <vscale x 8 x i1> %3,1619 iXLen %4)1620 1621 ret void1622}1623 1624define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {1625; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i16:1626; CHECK: # %bb.0: # %entry1627; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1628; CHECK-NEXT: vsuxei16.v v8, (a0), v161629; CHECK-NEXT: ret1630entry:1631 call void @llvm.riscv.vsuxei.nxv16i32.nxv16i16(1632 <vscale x 16 x i32> %0,1633 ptr %1,1634 <vscale x 16 x i16> %2,1635 iXLen %3)1636 1637 ret void1638}1639 1640define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1641; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i16:1642; CHECK: # %bb.0: # %entry1643; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1644; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t1645; CHECK-NEXT: ret1646entry:1647 call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i16(1648 <vscale x 16 x i32> %0,1649 ptr %1,1650 <vscale x 16 x i16> %2,1651 <vscale x 16 x i1> %3,1652 iXLen %4)1653 1654 ret void1655}1656 1657define void @intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {1658; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i16:1659; CHECK: # %bb.0: # %entry1660; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma1661; CHECK-NEXT: vsuxei16.v v8, (a0), v91662; CHECK-NEXT: ret1663entry:1664 call void @llvm.riscv.vsuxei.nxv1i64.nxv1i16(1665 <vscale x 1 x i64> %0,1666 ptr %1,1667 <vscale x 1 x i16> %2,1668 iXLen %3)1669 1670 ret void1671}1672 1673define void @intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1674; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i16:1675; CHECK: # %bb.0: # %entry1676; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma1677; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1678; CHECK-NEXT: ret1679entry:1680 call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i16(1681 <vscale x 1 x i64> %0,1682 ptr %1,1683 <vscale x 1 x i16> %2,1684 <vscale x 1 x i1> %3,1685 iXLen %4)1686 1687 ret void1688}1689 1690define void @intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {1691; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i16:1692; CHECK: # %bb.0: # %entry1693; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma1694; CHECK-NEXT: vsuxei16.v v8, (a0), v101695; CHECK-NEXT: ret1696entry:1697 call void @llvm.riscv.vsuxei.nxv2i64.nxv2i16(1698 <vscale x 2 x i64> %0,1699 ptr %1,1700 <vscale x 2 x i16> %2,1701 iXLen %3)1702 1703 ret void1704}1705 1706define void @intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1707; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i16:1708; CHECK: # %bb.0: # %entry1709; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma1710; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t1711; CHECK-NEXT: ret1712entry:1713 call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i16(1714 <vscale x 2 x i64> %0,1715 ptr %1,1716 <vscale x 2 x i16> %2,1717 <vscale x 2 x i1> %3,1718 iXLen %4)1719 1720 ret void1721}1722 1723define void @intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {1724; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i16:1725; CHECK: # %bb.0: # %entry1726; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1727; CHECK-NEXT: vsuxei16.v v8, (a0), v121728; CHECK-NEXT: ret1729entry:1730 call void @llvm.riscv.vsuxei.nxv4i64.nxv4i16(1731 <vscale x 4 x i64> %0,1732 ptr %1,1733 <vscale x 4 x i16> %2,1734 iXLen %3)1735 1736 ret void1737}1738 1739define void @intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1740; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i16:1741; CHECK: # %bb.0: # %entry1742; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1743; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t1744; CHECK-NEXT: ret1745entry:1746 call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i16(1747 <vscale x 4 x i64> %0,1748 ptr %1,1749 <vscale x 4 x i16> %2,1750 <vscale x 4 x i1> %3,1751 iXLen %4)1752 1753 ret void1754}1755 1756define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {1757; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i16:1758; CHECK: # %bb.0: # %entry1759; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1760; CHECK-NEXT: vsuxei16.v v8, (a0), v161761; CHECK-NEXT: ret1762entry:1763 call void @llvm.riscv.vsuxei.nxv8i64.nxv8i16(1764 <vscale x 8 x i64> %0,1765 ptr %1,1766 <vscale x 8 x i16> %2,1767 iXLen %3)1768 1769 ret void1770}1771 1772define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1773; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i16:1774; CHECK: # %bb.0: # %entry1775; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1776; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t1777; CHECK-NEXT: ret1778entry:1779 call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i16(1780 <vscale x 8 x i64> %0,1781 ptr %1,1782 <vscale x 8 x i16> %2,1783 <vscale x 8 x i1> %3,1784 iXLen %4)1785 1786 ret void1787}1788 1789define void @intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {1790; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i16:1791; CHECK: # %bb.0: # %entry1792; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1793; CHECK-NEXT: vsuxei16.v v8, (a0), v91794; CHECK-NEXT: ret1795entry:1796 call void @llvm.riscv.vsuxei.nxv1f16.nxv1i16(1797 <vscale x 1 x half> %0,1798 ptr %1,1799 <vscale x 1 x i16> %2,1800 iXLen %3)1801 1802 ret void1803}1804 1805define void @intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1806; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i16:1807; CHECK: # %bb.0: # %entry1808; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1809; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1810; CHECK-NEXT: ret1811entry:1812 call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i16(1813 <vscale x 1 x half> %0,1814 ptr %1,1815 <vscale x 1 x i16> %2,1816 <vscale x 1 x i1> %3,1817 iXLen %4)1818 1819 ret void1820}1821 1822define void @intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {1823; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i16:1824; CHECK: # %bb.0: # %entry1825; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1826; CHECK-NEXT: vsuxei16.v v8, (a0), v91827; CHECK-NEXT: ret1828entry:1829 call void @llvm.riscv.vsuxei.nxv2f16.nxv2i16(1830 <vscale x 2 x half> %0,1831 ptr %1,1832 <vscale x 2 x i16> %2,1833 iXLen %3)1834 1835 ret void1836}1837 1838define void @intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1839; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i16:1840; CHECK: # %bb.0: # %entry1841; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1842; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1843; CHECK-NEXT: ret1844entry:1845 call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i16(1846 <vscale x 2 x half> %0,1847 ptr %1,1848 <vscale x 2 x i16> %2,1849 <vscale x 2 x i1> %3,1850 iXLen %4)1851 1852 ret void1853}1854 1855define void @intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {1856; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i16:1857; CHECK: # %bb.0: # %entry1858; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1859; CHECK-NEXT: vsuxei16.v v8, (a0), v91860; CHECK-NEXT: ret1861entry:1862 call void @llvm.riscv.vsuxei.nxv4f16.nxv4i16(1863 <vscale x 4 x half> %0,1864 ptr %1,1865 <vscale x 4 x i16> %2,1866 iXLen %3)1867 1868 ret void1869}1870 1871define void @intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1872; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i16:1873; CHECK: # %bb.0: # %entry1874; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1875; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t1876; CHECK-NEXT: ret1877entry:1878 call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i16(1879 <vscale x 4 x half> %0,1880 ptr %1,1881 <vscale x 4 x i16> %2,1882 <vscale x 4 x i1> %3,1883 iXLen %4)1884 1885 ret void1886}1887 1888define void @intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {1889; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i16:1890; CHECK: # %bb.0: # %entry1891; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1892; CHECK-NEXT: vsuxei16.v v8, (a0), v101893; CHECK-NEXT: ret1894entry:1895 call void @llvm.riscv.vsuxei.nxv8f16.nxv8i16(1896 <vscale x 8 x half> %0,1897 ptr %1,1898 <vscale x 8 x i16> %2,1899 iXLen %3)1900 1901 ret void1902}1903 1904define void @intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1905; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i16:1906; CHECK: # %bb.0: # %entry1907; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1908; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t1909; CHECK-NEXT: ret1910entry:1911 call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i16(1912 <vscale x 8 x half> %0,1913 ptr %1,1914 <vscale x 8 x i16> %2,1915 <vscale x 8 x i1> %3,1916 iXLen %4)1917 1918 ret void1919}1920 1921define void @intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {1922; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i16:1923; CHECK: # %bb.0: # %entry1924; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1925; CHECK-NEXT: vsuxei16.v v8, (a0), v121926; CHECK-NEXT: ret1927entry:1928 call void @llvm.riscv.vsuxei.nxv16f16.nxv16i16(1929 <vscale x 16 x half> %0,1930 ptr %1,1931 <vscale x 16 x i16> %2,1932 iXLen %3)1933 1934 ret void1935}1936 1937define void @intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1938; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i16:1939; CHECK: # %bb.0: # %entry1940; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1941; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t1942; CHECK-NEXT: ret1943entry:1944 call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i16(1945 <vscale x 16 x half> %0,1946 ptr %1,1947 <vscale x 16 x i16> %2,1948 <vscale x 16 x i1> %3,1949 iXLen %4)1950 1951 ret void1952}1953 1954define void @intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, iXLen %3) nounwind {1955; CHECK-LABEL: intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i16:1956; CHECK: # %bb.0: # %entry1957; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1958; CHECK-NEXT: vsuxei16.v v8, (a0), v161959; CHECK-NEXT: ret1960entry:1961 call void @llvm.riscv.vsuxei.nxv32f16.nxv32i16(1962 <vscale x 32 x half> %0,1963 ptr %1,1964 <vscale x 32 x i16> %2,1965 iXLen %3)1966 1967 ret void1968}1969 1970define void @intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1971; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i16:1972; CHECK: # %bb.0: # %entry1973; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1974; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t1975; CHECK-NEXT: ret1976entry:1977 call void @llvm.riscv.vsuxei.mask.nxv32f16.nxv32i16(1978 <vscale x 32 x half> %0,1979 ptr %1,1980 <vscale x 32 x i16> %2,1981 <vscale x 32 x i1> %3,1982 iXLen %4)1983 1984 ret void1985}1986 1987define void @intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {1988; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i16:1989; CHECK: # %bb.0: # %entry1990; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1991; CHECK-NEXT: vsuxei16.v v8, (a0), v91992; CHECK-NEXT: ret1993entry:1994 call void @llvm.riscv.vsuxei.nxv1f32.nxv1i16(1995 <vscale x 1 x float> %0,1996 ptr %1,1997 <vscale x 1 x i16> %2,1998 iXLen %3)1999 2000 ret void2001}2002 2003define void @intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2004; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i16:2005; CHECK: # %bb.0: # %entry2006; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma2007; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t2008; CHECK-NEXT: ret2009entry:2010 call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i16(2011 <vscale x 1 x float> %0,2012 ptr %1,2013 <vscale x 1 x i16> %2,2014 <vscale x 1 x i1> %3,2015 iXLen %4)2016 2017 ret void2018}2019 2020define void @intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {2021; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i16:2022; CHECK: # %bb.0: # %entry2023; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma2024; CHECK-NEXT: vsuxei16.v v8, (a0), v92025; CHECK-NEXT: ret2026entry:2027 call void @llvm.riscv.vsuxei.nxv2f32.nxv2i16(2028 <vscale x 2 x float> %0,2029 ptr %1,2030 <vscale x 2 x i16> %2,2031 iXLen %3)2032 2033 ret void2034}2035 2036define void @intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2037; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i16:2038; CHECK: # %bb.0: # %entry2039; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma2040; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t2041; CHECK-NEXT: ret2042entry:2043 call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i16(2044 <vscale x 2 x float> %0,2045 ptr %1,2046 <vscale x 2 x i16> %2,2047 <vscale x 2 x i1> %3,2048 iXLen %4)2049 2050 ret void2051}2052 2053define void @intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {2054; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i16:2055; CHECK: # %bb.0: # %entry2056; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma2057; CHECK-NEXT: vsuxei16.v v8, (a0), v102058; CHECK-NEXT: ret2059entry:2060 call void @llvm.riscv.vsuxei.nxv4f32.nxv4i16(2061 <vscale x 4 x float> %0,2062 ptr %1,2063 <vscale x 4 x i16> %2,2064 iXLen %3)2065 2066 ret void2067}2068 2069define void @intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2070; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i16:2071; CHECK: # %bb.0: # %entry2072; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma2073; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t2074; CHECK-NEXT: ret2075entry:2076 call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i16(2077 <vscale x 4 x float> %0,2078 ptr %1,2079 <vscale x 4 x i16> %2,2080 <vscale x 4 x i1> %3,2081 iXLen %4)2082 2083 ret void2084}2085 2086define void @intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {2087; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i16:2088; CHECK: # %bb.0: # %entry2089; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma2090; CHECK-NEXT: vsuxei16.v v8, (a0), v122091; CHECK-NEXT: ret2092entry:2093 call void @llvm.riscv.vsuxei.nxv8f32.nxv8i16(2094 <vscale x 8 x float> %0,2095 ptr %1,2096 <vscale x 8 x i16> %2,2097 iXLen %3)2098 2099 ret void2100}2101 2102define void @intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2103; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i16:2104; CHECK: # %bb.0: # %entry2105; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma2106; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t2107; CHECK-NEXT: ret2108entry:2109 call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i16(2110 <vscale x 8 x float> %0,2111 ptr %1,2112 <vscale x 8 x i16> %2,2113 <vscale x 8 x i1> %3,2114 iXLen %4)2115 2116 ret void2117}2118 2119define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {2120; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i16:2121; CHECK: # %bb.0: # %entry2122; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2123; CHECK-NEXT: vsuxei16.v v8, (a0), v162124; CHECK-NEXT: ret2125entry:2126 call void @llvm.riscv.vsuxei.nxv16f32.nxv16i16(2127 <vscale x 16 x float> %0,2128 ptr %1,2129 <vscale x 16 x i16> %2,2130 iXLen %3)2131 2132 ret void2133}2134 2135define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2136; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i16:2137; CHECK: # %bb.0: # %entry2138; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2139; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t2140; CHECK-NEXT: ret2141entry:2142 call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i16(2143 <vscale x 16 x float> %0,2144 ptr %1,2145 <vscale x 16 x i16> %2,2146 <vscale x 16 x i1> %3,2147 iXLen %4)2148 2149 ret void2150}2151 2152define void @intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {2153; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i16:2154; CHECK: # %bb.0: # %entry2155; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma2156; CHECK-NEXT: vsuxei16.v v8, (a0), v92157; CHECK-NEXT: ret2158entry:2159 call void @llvm.riscv.vsuxei.nxv1f64.nxv1i16(2160 <vscale x 1 x double> %0,2161 ptr %1,2162 <vscale x 1 x i16> %2,2163 iXLen %3)2164 2165 ret void2166}2167 2168define void @intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2169; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i16:2170; CHECK: # %bb.0: # %entry2171; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma2172; CHECK-NEXT: vsuxei16.v v8, (a0), v9, v0.t2173; CHECK-NEXT: ret2174entry:2175 call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i16(2176 <vscale x 1 x double> %0,2177 ptr %1,2178 <vscale x 1 x i16> %2,2179 <vscale x 1 x i1> %3,2180 iXLen %4)2181 2182 ret void2183}2184 2185define void @intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {2186; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i16:2187; CHECK: # %bb.0: # %entry2188; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma2189; CHECK-NEXT: vsuxei16.v v8, (a0), v102190; CHECK-NEXT: ret2191entry:2192 call void @llvm.riscv.vsuxei.nxv2f64.nxv2i16(2193 <vscale x 2 x double> %0,2194 ptr %1,2195 <vscale x 2 x i16> %2,2196 iXLen %3)2197 2198 ret void2199}2200 2201define void @intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2202; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i16:2203; CHECK: # %bb.0: # %entry2204; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma2205; CHECK-NEXT: vsuxei16.v v8, (a0), v10, v0.t2206; CHECK-NEXT: ret2207entry:2208 call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i16(2209 <vscale x 2 x double> %0,2210 ptr %1,2211 <vscale x 2 x i16> %2,2212 <vscale x 2 x i1> %3,2213 iXLen %4)2214 2215 ret void2216}2217 2218define void @intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {2219; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i16:2220; CHECK: # %bb.0: # %entry2221; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma2222; CHECK-NEXT: vsuxei16.v v8, (a0), v122223; CHECK-NEXT: ret2224entry:2225 call void @llvm.riscv.vsuxei.nxv4f64.nxv4i16(2226 <vscale x 4 x double> %0,2227 ptr %1,2228 <vscale x 4 x i16> %2,2229 iXLen %3)2230 2231 ret void2232}2233 2234define void @intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2235; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i16:2236; CHECK: # %bb.0: # %entry2237; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma2238; CHECK-NEXT: vsuxei16.v v8, (a0), v12, v0.t2239; CHECK-NEXT: ret2240entry:2241 call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i16(2242 <vscale x 4 x double> %0,2243 ptr %1,2244 <vscale x 4 x i16> %2,2245 <vscale x 4 x i1> %3,2246 iXLen %4)2247 2248 ret void2249}2250 2251define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {2252; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i16:2253; CHECK: # %bb.0: # %entry2254; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma2255; CHECK-NEXT: vsuxei16.v v8, (a0), v162256; CHECK-NEXT: ret2257entry:2258 call void @llvm.riscv.vsuxei.nxv8f64.nxv8i16(2259 <vscale x 8 x double> %0,2260 ptr %1,2261 <vscale x 8 x i16> %2,2262 iXLen %3)2263 2264 ret void2265}2266 2267define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2268; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i16:2269; CHECK: # %bb.0: # %entry2270; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma2271; CHECK-NEXT: vsuxei16.v v8, (a0), v16, v0.t2272; CHECK-NEXT: ret2273entry:2274 call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i16(2275 <vscale x 8 x double> %0,2276 ptr %1,2277 <vscale x 8 x i16> %2,2278 <vscale x 8 x i1> %3,2279 iXLen %4)2280 2281 ret void2282}2283 2284define void @intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {2285; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i8_nxv1i8_nxv1i8:2286; CHECK: # %bb.0: # %entry2287; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2288; CHECK-NEXT: vsuxei8.v v8, (a0), v92289; CHECK-NEXT: ret2290entry:2291 call void @llvm.riscv.vsuxei.nxv1i8.nxv1i8(2292 <vscale x 1 x i8> %0,2293 ptr %1,2294 <vscale x 1 x i8> %2,2295 iXLen %3)2296 2297 ret void2298}2299 2300define void @intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2301; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i8_nxv1i8_nxv1i8:2302; CHECK: # %bb.0: # %entry2303; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2304; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2305; CHECK-NEXT: ret2306entry:2307 call void @llvm.riscv.vsuxei.mask.nxv1i8.nxv1i8(2308 <vscale x 1 x i8> %0,2309 ptr %1,2310 <vscale x 1 x i8> %2,2311 <vscale x 1 x i1> %3,2312 iXLen %4)2313 2314 ret void2315}2316 2317define void @intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {2318; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i8_nxv2i8_nxv2i8:2319; CHECK: # %bb.0: # %entry2320; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2321; CHECK-NEXT: vsuxei8.v v8, (a0), v92322; CHECK-NEXT: ret2323entry:2324 call void @llvm.riscv.vsuxei.nxv2i8.nxv2i8(2325 <vscale x 2 x i8> %0,2326 ptr %1,2327 <vscale x 2 x i8> %2,2328 iXLen %3)2329 2330 ret void2331}2332 2333define void @intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2334; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i8_nxv2i8_nxv2i8:2335; CHECK: # %bb.0: # %entry2336; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2337; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2338; CHECK-NEXT: ret2339entry:2340 call void @llvm.riscv.vsuxei.mask.nxv2i8.nxv2i8(2341 <vscale x 2 x i8> %0,2342 ptr %1,2343 <vscale x 2 x i8> %2,2344 <vscale x 2 x i1> %3,2345 iXLen %4)2346 2347 ret void2348}2349 2350define void @intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {2351; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i8_nxv4i8_nxv4i8:2352; CHECK: # %bb.0: # %entry2353; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2354; CHECK-NEXT: vsuxei8.v v8, (a0), v92355; CHECK-NEXT: ret2356entry:2357 call void @llvm.riscv.vsuxei.nxv4i8.nxv4i8(2358 <vscale x 4 x i8> %0,2359 ptr %1,2360 <vscale x 4 x i8> %2,2361 iXLen %3)2362 2363 ret void2364}2365 2366define void @intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2367; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i8_nxv4i8_nxv4i8:2368; CHECK: # %bb.0: # %entry2369; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2370; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2371; CHECK-NEXT: ret2372entry:2373 call void @llvm.riscv.vsuxei.mask.nxv4i8.nxv4i8(2374 <vscale x 4 x i8> %0,2375 ptr %1,2376 <vscale x 4 x i8> %2,2377 <vscale x 4 x i1> %3,2378 iXLen %4)2379 2380 ret void2381}2382 2383define void @intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {2384; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i8_nxv8i8_nxv8i8:2385; CHECK: # %bb.0: # %entry2386; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2387; CHECK-NEXT: vsuxei8.v v8, (a0), v92388; CHECK-NEXT: ret2389entry:2390 call void @llvm.riscv.vsuxei.nxv8i8.nxv8i8(2391 <vscale x 8 x i8> %0,2392 ptr %1,2393 <vscale x 8 x i8> %2,2394 iXLen %3)2395 2396 ret void2397}2398 2399define void @intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2400; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i8_nxv8i8_nxv8i8:2401; CHECK: # %bb.0: # %entry2402; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2403; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2404; CHECK-NEXT: ret2405entry:2406 call void @llvm.riscv.vsuxei.mask.nxv8i8.nxv8i8(2407 <vscale x 8 x i8> %0,2408 ptr %1,2409 <vscale x 8 x i8> %2,2410 <vscale x 8 x i1> %3,2411 iXLen %4)2412 2413 ret void2414}2415 2416define void @intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {2417; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i8_nxv16i8_nxv16i8:2418; CHECK: # %bb.0: # %entry2419; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma2420; CHECK-NEXT: vsuxei8.v v8, (a0), v102421; CHECK-NEXT: ret2422entry:2423 call void @llvm.riscv.vsuxei.nxv16i8.nxv16i8(2424 <vscale x 16 x i8> %0,2425 ptr %1,2426 <vscale x 16 x i8> %2,2427 iXLen %3)2428 2429 ret void2430}2431 2432define void @intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2433; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i8_nxv16i8_nxv16i8:2434; CHECK: # %bb.0: # %entry2435; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma2436; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t2437; CHECK-NEXT: ret2438entry:2439 call void @llvm.riscv.vsuxei.mask.nxv16i8.nxv16i8(2440 <vscale x 16 x i8> %0,2441 ptr %1,2442 <vscale x 16 x i8> %2,2443 <vscale x 16 x i1> %3,2444 iXLen %4)2445 2446 ret void2447}2448 2449define void @intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {2450; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i8_nxv32i8_nxv32i8:2451; CHECK: # %bb.0: # %entry2452; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma2453; CHECK-NEXT: vsuxei8.v v8, (a0), v122454; CHECK-NEXT: ret2455entry:2456 call void @llvm.riscv.vsuxei.nxv32i8.nxv32i8(2457 <vscale x 32 x i8> %0,2458 ptr %1,2459 <vscale x 32 x i8> %2,2460 iXLen %3)2461 2462 ret void2463}2464 2465define void @intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2466; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i8_nxv32i8_nxv32i8:2467; CHECK: # %bb.0: # %entry2468; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma2469; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t2470; CHECK-NEXT: ret2471entry:2472 call void @llvm.riscv.vsuxei.mask.nxv32i8.nxv32i8(2473 <vscale x 32 x i8> %0,2474 ptr %1,2475 <vscale x 32 x i8> %2,2476 <vscale x 32 x i1> %3,2477 iXLen %4)2478 2479 ret void2480}2481 2482define void @intrinsic_vsuxei_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {2483; CHECK-LABEL: intrinsic_vsuxei_v_nxv64i8_nxv64i8_nxv64i8:2484; CHECK: # %bb.0: # %entry2485; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma2486; CHECK-NEXT: vsuxei8.v v8, (a0), v162487; CHECK-NEXT: ret2488entry:2489 call void @llvm.riscv.vsuxei.nxv64i8.nxv64i8(2490 <vscale x 64 x i8> %0,2491 ptr %1,2492 <vscale x 64 x i8> %2,2493 iXLen %3)2494 2495 ret void2496}2497 2498define void @intrinsic_vsuxei_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {2499; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv64i8_nxv64i8_nxv64i8:2500; CHECK: # %bb.0: # %entry2501; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma2502; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t2503; CHECK-NEXT: ret2504entry:2505 call void @llvm.riscv.vsuxei.mask.nxv64i8.nxv64i8(2506 <vscale x 64 x i8> %0,2507 ptr %1,2508 <vscale x 64 x i8> %2,2509 <vscale x 64 x i1> %3,2510 iXLen %4)2511 2512 ret void2513}2514 2515define void @intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {2516; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i16_nxv1i16_nxv1i8:2517; CHECK: # %bb.0: # %entry2518; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2519; CHECK-NEXT: vsuxei8.v v8, (a0), v92520; CHECK-NEXT: ret2521entry:2522 call void @llvm.riscv.vsuxei.nxv1i16.nxv1i8(2523 <vscale x 1 x i16> %0,2524 ptr %1,2525 <vscale x 1 x i8> %2,2526 iXLen %3)2527 2528 ret void2529}2530 2531define void @intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2532; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i16_nxv1i16_nxv1i8:2533; CHECK: # %bb.0: # %entry2534; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2535; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2536; CHECK-NEXT: ret2537entry:2538 call void @llvm.riscv.vsuxei.mask.nxv1i16.nxv1i8(2539 <vscale x 1 x i16> %0,2540 ptr %1,2541 <vscale x 1 x i8> %2,2542 <vscale x 1 x i1> %3,2543 iXLen %4)2544 2545 ret void2546}2547 2548define void @intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {2549; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i16_nxv2i16_nxv2i8:2550; CHECK: # %bb.0: # %entry2551; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2552; CHECK-NEXT: vsuxei8.v v8, (a0), v92553; CHECK-NEXT: ret2554entry:2555 call void @llvm.riscv.vsuxei.nxv2i16.nxv2i8(2556 <vscale x 2 x i16> %0,2557 ptr %1,2558 <vscale x 2 x i8> %2,2559 iXLen %3)2560 2561 ret void2562}2563 2564define void @intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2565; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i16_nxv2i16_nxv2i8:2566; CHECK: # %bb.0: # %entry2567; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2568; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2569; CHECK-NEXT: ret2570entry:2571 call void @llvm.riscv.vsuxei.mask.nxv2i16.nxv2i8(2572 <vscale x 2 x i16> %0,2573 ptr %1,2574 <vscale x 2 x i8> %2,2575 <vscale x 2 x i1> %3,2576 iXLen %4)2577 2578 ret void2579}2580 2581define void @intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {2582; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i16_nxv4i16_nxv4i8:2583; CHECK: # %bb.0: # %entry2584; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma2585; CHECK-NEXT: vsuxei8.v v8, (a0), v92586; CHECK-NEXT: ret2587entry:2588 call void @llvm.riscv.vsuxei.nxv4i16.nxv4i8(2589 <vscale x 4 x i16> %0,2590 ptr %1,2591 <vscale x 4 x i8> %2,2592 iXLen %3)2593 2594 ret void2595}2596 2597define void @intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2598; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i16_nxv4i16_nxv4i8:2599; CHECK: # %bb.0: # %entry2600; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma2601; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2602; CHECK-NEXT: ret2603entry:2604 call void @llvm.riscv.vsuxei.mask.nxv4i16.nxv4i8(2605 <vscale x 4 x i16> %0,2606 ptr %1,2607 <vscale x 4 x i8> %2,2608 <vscale x 4 x i1> %3,2609 iXLen %4)2610 2611 ret void2612}2613 2614define void @intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {2615; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i16_nxv8i16_nxv8i8:2616; CHECK: # %bb.0: # %entry2617; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma2618; CHECK-NEXT: vsuxei8.v v8, (a0), v102619; CHECK-NEXT: ret2620entry:2621 call void @llvm.riscv.vsuxei.nxv8i16.nxv8i8(2622 <vscale x 8 x i16> %0,2623 ptr %1,2624 <vscale x 8 x i8> %2,2625 iXLen %3)2626 2627 ret void2628}2629 2630define void @intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2631; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i16_nxv8i16_nxv8i8:2632; CHECK: # %bb.0: # %entry2633; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma2634; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t2635; CHECK-NEXT: ret2636entry:2637 call void @llvm.riscv.vsuxei.mask.nxv8i16.nxv8i8(2638 <vscale x 8 x i16> %0,2639 ptr %1,2640 <vscale x 8 x i8> %2,2641 <vscale x 8 x i1> %3,2642 iXLen %4)2643 2644 ret void2645}2646 2647define void @intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {2648; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i16_nxv16i16_nxv16i8:2649; CHECK: # %bb.0: # %entry2650; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma2651; CHECK-NEXT: vsuxei8.v v8, (a0), v122652; CHECK-NEXT: ret2653entry:2654 call void @llvm.riscv.vsuxei.nxv16i16.nxv16i8(2655 <vscale x 16 x i16> %0,2656 ptr %1,2657 <vscale x 16 x i8> %2,2658 iXLen %3)2659 2660 ret void2661}2662 2663define void @intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2664; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i16_nxv16i16_nxv16i8:2665; CHECK: # %bb.0: # %entry2666; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma2667; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t2668; CHECK-NEXT: ret2669entry:2670 call void @llvm.riscv.vsuxei.mask.nxv16i16.nxv16i8(2671 <vscale x 16 x i16> %0,2672 ptr %1,2673 <vscale x 16 x i8> %2,2674 <vscale x 16 x i1> %3,2675 iXLen %4)2676 2677 ret void2678}2679 2680define void @intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {2681; CHECK-LABEL: intrinsic_vsuxei_v_nxv32i16_nxv32i16_nxv32i8:2682; CHECK: # %bb.0: # %entry2683; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2684; CHECK-NEXT: vsuxei8.v v8, (a0), v162685; CHECK-NEXT: ret2686entry:2687 call void @llvm.riscv.vsuxei.nxv32i16.nxv32i8(2688 <vscale x 32 x i16> %0,2689 ptr %1,2690 <vscale x 32 x i8> %2,2691 iXLen %3)2692 2693 ret void2694}2695 2696define void @intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2697; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32i16_nxv32i16_nxv32i8:2698; CHECK: # %bb.0: # %entry2699; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma2700; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t2701; CHECK-NEXT: ret2702entry:2703 call void @llvm.riscv.vsuxei.mask.nxv32i16.nxv32i8(2704 <vscale x 32 x i16> %0,2705 ptr %1,2706 <vscale x 32 x i8> %2,2707 <vscale x 32 x i1> %3,2708 iXLen %4)2709 2710 ret void2711}2712 2713define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {2714; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i8:2715; CHECK: # %bb.0: # %entry2716; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma2717; CHECK-NEXT: vsuxei8.v v8, (a0), v92718; CHECK-NEXT: ret2719entry:2720 call void @llvm.riscv.vsuxei.nxv1i32.nxv1i8(2721 <vscale x 1 x i32> %0,2722 ptr %1,2723 <vscale x 1 x i8> %2,2724 iXLen %3)2725 2726 ret void2727}2728 2729define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2730; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i8:2731; CHECK: # %bb.0: # %entry2732; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma2733; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2734; CHECK-NEXT: ret2735entry:2736 call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i8(2737 <vscale x 1 x i32> %0,2738 ptr %1,2739 <vscale x 1 x i8> %2,2740 <vscale x 1 x i1> %3,2741 iXLen %4)2742 2743 ret void2744}2745 2746define void @intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {2747; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i32_nxv2i32_nxv2i8:2748; CHECK: # %bb.0: # %entry2749; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma2750; CHECK-NEXT: vsuxei8.v v8, (a0), v92751; CHECK-NEXT: ret2752entry:2753 call void @llvm.riscv.vsuxei.nxv2i32.nxv2i8(2754 <vscale x 2 x i32> %0,2755 ptr %1,2756 <vscale x 2 x i8> %2,2757 iXLen %3)2758 2759 ret void2760}2761 2762define void @intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2763; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i32_nxv2i32_nxv2i8:2764; CHECK: # %bb.0: # %entry2765; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma2766; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2767; CHECK-NEXT: ret2768entry:2769 call void @llvm.riscv.vsuxei.mask.nxv2i32.nxv2i8(2770 <vscale x 2 x i32> %0,2771 ptr %1,2772 <vscale x 2 x i8> %2,2773 <vscale x 2 x i1> %3,2774 iXLen %4)2775 2776 ret void2777}2778 2779define void @intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {2780; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i32_nxv4i32_nxv4i8:2781; CHECK: # %bb.0: # %entry2782; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma2783; CHECK-NEXT: vsuxei8.v v8, (a0), v102784; CHECK-NEXT: ret2785entry:2786 call void @llvm.riscv.vsuxei.nxv4i32.nxv4i8(2787 <vscale x 4 x i32> %0,2788 ptr %1,2789 <vscale x 4 x i8> %2,2790 iXLen %3)2791 2792 ret void2793}2794 2795define void @intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2796; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i32_nxv4i32_nxv4i8:2797; CHECK: # %bb.0: # %entry2798; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma2799; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t2800; CHECK-NEXT: ret2801entry:2802 call void @llvm.riscv.vsuxei.mask.nxv4i32.nxv4i8(2803 <vscale x 4 x i32> %0,2804 ptr %1,2805 <vscale x 4 x i8> %2,2806 <vscale x 4 x i1> %3,2807 iXLen %4)2808 2809 ret void2810}2811 2812define void @intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {2813; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i32_nxv8i32_nxv8i8:2814; CHECK: # %bb.0: # %entry2815; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma2816; CHECK-NEXT: vsuxei8.v v8, (a0), v122817; CHECK-NEXT: ret2818entry:2819 call void @llvm.riscv.vsuxei.nxv8i32.nxv8i8(2820 <vscale x 8 x i32> %0,2821 ptr %1,2822 <vscale x 8 x i8> %2,2823 iXLen %3)2824 2825 ret void2826}2827 2828define void @intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2829; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i32_nxv8i32_nxv8i8:2830; CHECK: # %bb.0: # %entry2831; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma2832; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t2833; CHECK-NEXT: ret2834entry:2835 call void @llvm.riscv.vsuxei.mask.nxv8i32.nxv8i8(2836 <vscale x 8 x i32> %0,2837 ptr %1,2838 <vscale x 8 x i8> %2,2839 <vscale x 8 x i1> %3,2840 iXLen %4)2841 2842 ret void2843}2844 2845define void @intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {2846; CHECK-LABEL: intrinsic_vsuxei_v_nxv16i32_nxv16i32_nxv16i8:2847; CHECK: # %bb.0: # %entry2848; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2849; CHECK-NEXT: vsuxei8.v v8, (a0), v162850; CHECK-NEXT: ret2851entry:2852 call void @llvm.riscv.vsuxei.nxv16i32.nxv16i8(2853 <vscale x 16 x i32> %0,2854 ptr %1,2855 <vscale x 16 x i8> %2,2856 iXLen %3)2857 2858 ret void2859}2860 2861define void @intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2862; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16i32_nxv16i32_nxv16i8:2863; CHECK: # %bb.0: # %entry2864; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma2865; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t2866; CHECK-NEXT: ret2867entry:2868 call void @llvm.riscv.vsuxei.mask.nxv16i32.nxv16i8(2869 <vscale x 16 x i32> %0,2870 ptr %1,2871 <vscale x 16 x i8> %2,2872 <vscale x 16 x i1> %3,2873 iXLen %4)2874 2875 ret void2876}2877 2878define void @intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {2879; CHECK-LABEL: intrinsic_vsuxei_v_nxv1i64_nxv1i64_nxv1i8:2880; CHECK: # %bb.0: # %entry2881; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma2882; CHECK-NEXT: vsuxei8.v v8, (a0), v92883; CHECK-NEXT: ret2884entry:2885 call void @llvm.riscv.vsuxei.nxv1i64.nxv1i8(2886 <vscale x 1 x i64> %0,2887 ptr %1,2888 <vscale x 1 x i8> %2,2889 iXLen %3)2890 2891 ret void2892}2893 2894define void @intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2895; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1i64_nxv1i64_nxv1i8:2896; CHECK: # %bb.0: # %entry2897; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma2898; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t2899; CHECK-NEXT: ret2900entry:2901 call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i8(2902 <vscale x 1 x i64> %0,2903 ptr %1,2904 <vscale x 1 x i8> %2,2905 <vscale x 1 x i1> %3,2906 iXLen %4)2907 2908 ret void2909}2910 2911define void @intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {2912; CHECK-LABEL: intrinsic_vsuxei_v_nxv2i64_nxv2i64_nxv2i8:2913; CHECK: # %bb.0: # %entry2914; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma2915; CHECK-NEXT: vsuxei8.v v8, (a0), v102916; CHECK-NEXT: ret2917entry:2918 call void @llvm.riscv.vsuxei.nxv2i64.nxv2i8(2919 <vscale x 2 x i64> %0,2920 ptr %1,2921 <vscale x 2 x i8> %2,2922 iXLen %3)2923 2924 ret void2925}2926 2927define void @intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2928; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2i64_nxv2i64_nxv2i8:2929; CHECK: # %bb.0: # %entry2930; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma2931; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t2932; CHECK-NEXT: ret2933entry:2934 call void @llvm.riscv.vsuxei.mask.nxv2i64.nxv2i8(2935 <vscale x 2 x i64> %0,2936 ptr %1,2937 <vscale x 2 x i8> %2,2938 <vscale x 2 x i1> %3,2939 iXLen %4)2940 2941 ret void2942}2943 2944define void @intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {2945; CHECK-LABEL: intrinsic_vsuxei_v_nxv4i64_nxv4i64_nxv4i8:2946; CHECK: # %bb.0: # %entry2947; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma2948; CHECK-NEXT: vsuxei8.v v8, (a0), v122949; CHECK-NEXT: ret2950entry:2951 call void @llvm.riscv.vsuxei.nxv4i64.nxv4i8(2952 <vscale x 4 x i64> %0,2953 ptr %1,2954 <vscale x 4 x i8> %2,2955 iXLen %3)2956 2957 ret void2958}2959 2960define void @intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2961; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4i64_nxv4i64_nxv4i8:2962; CHECK: # %bb.0: # %entry2963; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma2964; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t2965; CHECK-NEXT: ret2966entry:2967 call void @llvm.riscv.vsuxei.mask.nxv4i64.nxv4i8(2968 <vscale x 4 x i64> %0,2969 ptr %1,2970 <vscale x 4 x i8> %2,2971 <vscale x 4 x i1> %3,2972 iXLen %4)2973 2974 ret void2975}2976 2977define void @intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {2978; CHECK-LABEL: intrinsic_vsuxei_v_nxv8i64_nxv8i64_nxv8i8:2979; CHECK: # %bb.0: # %entry2980; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma2981; CHECK-NEXT: vsuxei8.v v8, (a0), v162982; CHECK-NEXT: ret2983entry:2984 call void @llvm.riscv.vsuxei.nxv8i64.nxv8i8(2985 <vscale x 8 x i64> %0,2986 ptr %1,2987 <vscale x 8 x i8> %2,2988 iXLen %3)2989 2990 ret void2991}2992 2993define void @intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2994; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8i64_nxv8i64_nxv8i8:2995; CHECK: # %bb.0: # %entry2996; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma2997; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t2998; CHECK-NEXT: ret2999entry:3000 call void @llvm.riscv.vsuxei.mask.nxv8i64.nxv8i8(3001 <vscale x 8 x i64> %0,3002 ptr %1,3003 <vscale x 8 x i8> %2,3004 <vscale x 8 x i1> %3,3005 iXLen %4)3006 3007 ret void3008}3009 3010define void @intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {3011; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f16_nxv1f16_nxv1i8:3012; CHECK: # %bb.0: # %entry3013; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3014; CHECK-NEXT: vsuxei8.v v8, (a0), v93015; CHECK-NEXT: ret3016entry:3017 call void @llvm.riscv.vsuxei.nxv1f16.nxv1i8(3018 <vscale x 1 x half> %0,3019 ptr %1,3020 <vscale x 1 x i8> %2,3021 iXLen %3)3022 3023 ret void3024}3025 3026define void @intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3027; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f16_nxv1f16_nxv1i8:3028; CHECK: # %bb.0: # %entry3029; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3030; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t3031; CHECK-NEXT: ret3032entry:3033 call void @llvm.riscv.vsuxei.mask.nxv1f16.nxv1i8(3034 <vscale x 1 x half> %0,3035 ptr %1,3036 <vscale x 1 x i8> %2,3037 <vscale x 1 x i1> %3,3038 iXLen %4)3039 3040 ret void3041}3042 3043define void @intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {3044; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f16_nxv2f16_nxv2i8:3045; CHECK: # %bb.0: # %entry3046; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3047; CHECK-NEXT: vsuxei8.v v8, (a0), v93048; CHECK-NEXT: ret3049entry:3050 call void @llvm.riscv.vsuxei.nxv2f16.nxv2i8(3051 <vscale x 2 x half> %0,3052 ptr %1,3053 <vscale x 2 x i8> %2,3054 iXLen %3)3055 3056 ret void3057}3058 3059define void @intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3060; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f16_nxv2f16_nxv2i8:3061; CHECK: # %bb.0: # %entry3062; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3063; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t3064; CHECK-NEXT: ret3065entry:3066 call void @llvm.riscv.vsuxei.mask.nxv2f16.nxv2i8(3067 <vscale x 2 x half> %0,3068 ptr %1,3069 <vscale x 2 x i8> %2,3070 <vscale x 2 x i1> %3,3071 iXLen %4)3072 3073 ret void3074}3075 3076define void @intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {3077; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f16_nxv4f16_nxv4i8:3078; CHECK: # %bb.0: # %entry3079; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3080; CHECK-NEXT: vsuxei8.v v8, (a0), v93081; CHECK-NEXT: ret3082entry:3083 call void @llvm.riscv.vsuxei.nxv4f16.nxv4i8(3084 <vscale x 4 x half> %0,3085 ptr %1,3086 <vscale x 4 x i8> %2,3087 iXLen %3)3088 3089 ret void3090}3091 3092define void @intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3093; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f16_nxv4f16_nxv4i8:3094; CHECK: # %bb.0: # %entry3095; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3096; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t3097; CHECK-NEXT: ret3098entry:3099 call void @llvm.riscv.vsuxei.mask.nxv4f16.nxv4i8(3100 <vscale x 4 x half> %0,3101 ptr %1,3102 <vscale x 4 x i8> %2,3103 <vscale x 4 x i1> %3,3104 iXLen %4)3105 3106 ret void3107}3108 3109define void @intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {3110; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f16_nxv8f16_nxv8i8:3111; CHECK: # %bb.0: # %entry3112; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3113; CHECK-NEXT: vsuxei8.v v8, (a0), v103114; CHECK-NEXT: ret3115entry:3116 call void @llvm.riscv.vsuxei.nxv8f16.nxv8i8(3117 <vscale x 8 x half> %0,3118 ptr %1,3119 <vscale x 8 x i8> %2,3120 iXLen %3)3121 3122 ret void3123}3124 3125define void @intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3126; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f16_nxv8f16_nxv8i8:3127; CHECK: # %bb.0: # %entry3128; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3129; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t3130; CHECK-NEXT: ret3131entry:3132 call void @llvm.riscv.vsuxei.mask.nxv8f16.nxv8i8(3133 <vscale x 8 x half> %0,3134 ptr %1,3135 <vscale x 8 x i8> %2,3136 <vscale x 8 x i1> %3,3137 iXLen %4)3138 3139 ret void3140}3141 3142define void @intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {3143; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f16_nxv16f16_nxv16i8:3144; CHECK: # %bb.0: # %entry3145; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3146; CHECK-NEXT: vsuxei8.v v8, (a0), v123147; CHECK-NEXT: ret3148entry:3149 call void @llvm.riscv.vsuxei.nxv16f16.nxv16i8(3150 <vscale x 16 x half> %0,3151 ptr %1,3152 <vscale x 16 x i8> %2,3153 iXLen %3)3154 3155 ret void3156}3157 3158define void @intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3159; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f16_nxv16f16_nxv16i8:3160; CHECK: # %bb.0: # %entry3161; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3162; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t3163; CHECK-NEXT: ret3164entry:3165 call void @llvm.riscv.vsuxei.mask.nxv16f16.nxv16i8(3166 <vscale x 16 x half> %0,3167 ptr %1,3168 <vscale x 16 x i8> %2,3169 <vscale x 16 x i1> %3,3170 iXLen %4)3171 3172 ret void3173}3174 3175define void @intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {3176; CHECK-LABEL: intrinsic_vsuxei_v_nxv32f16_nxv32f16_nxv32i8:3177; CHECK: # %bb.0: # %entry3178; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma3179; CHECK-NEXT: vsuxei8.v v8, (a0), v163180; CHECK-NEXT: ret3181entry:3182 call void @llvm.riscv.vsuxei.nxv32f16.nxv32i8(3183 <vscale x 32 x half> %0,3184 ptr %1,3185 <vscale x 32 x i8> %2,3186 iXLen %3)3187 3188 ret void3189}3190 3191define void @intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {3192; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv32f16_nxv32f16_nxv32i8:3193; CHECK: # %bb.0: # %entry3194; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma3195; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t3196; CHECK-NEXT: ret3197entry:3198 call void @llvm.riscv.vsuxei.mask.nxv32f16.nxv32i8(3199 <vscale x 32 x half> %0,3200 ptr %1,3201 <vscale x 32 x i8> %2,3202 <vscale x 32 x i1> %3,3203 iXLen %4)3204 3205 ret void3206}3207 3208define void @intrinsic_vsuxei_v_nxv1bf16_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {3209; CHECK-LABEL: intrinsic_vsuxei_v_nxv1bf16_nxv1bf16_nxv1i32:3210; CHECK: # %bb.0: # %entry3211; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3212; CHECK-NEXT: vsuxei32.v v8, (a0), v93213; CHECK-NEXT: ret3214entry:3215 call void @llvm.riscv.vsuxei.nxv1bf16.nxv1i32(3216 <vscale x 1 x bfloat> %0,3217 ptr %1,3218 <vscale x 1 x i32> %2,3219 iXLen %3)3220 3221 ret void3222}3223 3224define void @intrinsic_vsuxei_mask_v_nxv1bf16_nxv1bf16_nxv1i32(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3225; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1bf16_nxv1bf16_nxv1i32:3226; CHECK: # %bb.0: # %entry3227; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3228; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t3229; CHECK-NEXT: ret3230entry:3231 call void @llvm.riscv.vsuxei.mask.nxv1bf16.nxv1i32(3232 <vscale x 1 x bfloat> %0,3233 ptr %1,3234 <vscale x 1 x i32> %2,3235 <vscale x 1 x i1> %3,3236 iXLen %4)3237 3238 ret void3239}3240 3241define void @intrinsic_vsuxei_v_nxv2bf16_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {3242; CHECK-LABEL: intrinsic_vsuxei_v_nxv2bf16_nxv2bf16_nxv2i32:3243; CHECK: # %bb.0: # %entry3244; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3245; CHECK-NEXT: vsuxei32.v v8, (a0), v93246; CHECK-NEXT: ret3247entry:3248 call void @llvm.riscv.vsuxei.nxv2bf16.nxv2i32(3249 <vscale x 2 x bfloat> %0,3250 ptr %1,3251 <vscale x 2 x i32> %2,3252 iXLen %3)3253 3254 ret void3255}3256 3257define void @intrinsic_vsuxei_mask_v_nxv2bf16_nxv2bf16_nxv2i32(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3258; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2bf16_nxv2bf16_nxv2i32:3259; CHECK: # %bb.0: # %entry3260; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3261; CHECK-NEXT: vsuxei32.v v8, (a0), v9, v0.t3262; CHECK-NEXT: ret3263entry:3264 call void @llvm.riscv.vsuxei.mask.nxv2bf16.nxv2i32(3265 <vscale x 2 x bfloat> %0,3266 ptr %1,3267 <vscale x 2 x i32> %2,3268 <vscale x 2 x i1> %3,3269 iXLen %4)3270 3271 ret void3272}3273 3274define void @intrinsic_vsuxei_v_nxv4bf16_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {3275; CHECK-LABEL: intrinsic_vsuxei_v_nxv4bf16_nxv4bf16_nxv4i32:3276; CHECK: # %bb.0: # %entry3277; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3278; CHECK-NEXT: vsuxei32.v v8, (a0), v103279; CHECK-NEXT: ret3280entry:3281 call void @llvm.riscv.vsuxei.nxv4bf16.nxv4i32(3282 <vscale x 4 x bfloat> %0,3283 ptr %1,3284 <vscale x 4 x i32> %2,3285 iXLen %3)3286 3287 ret void3288}3289 3290define void @intrinsic_vsuxei_mask_v_nxv4bf16_nxv4bf16_nxv4i32(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3291; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4bf16_nxv4bf16_nxv4i32:3292; CHECK: # %bb.0: # %entry3293; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3294; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t3295; CHECK-NEXT: ret3296entry:3297 call void @llvm.riscv.vsuxei.mask.nxv4bf16.nxv4i32(3298 <vscale x 4 x bfloat> %0,3299 ptr %1,3300 <vscale x 4 x i32> %2,3301 <vscale x 4 x i1> %3,3302 iXLen %4)3303 3304 ret void3305}3306 3307define void @intrinsic_vsuxei_v_nxv8bf16_nxv8bf16_nxv8i32(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {3308; CHECK-LABEL: intrinsic_vsuxei_v_nxv8bf16_nxv8bf16_nxv8i32:3309; CHECK: # %bb.0: # %entry3310; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3311; CHECK-NEXT: vsuxei32.v v8, (a0), v123312; CHECK-NEXT: ret3313entry:3314 call void @llvm.riscv.vsuxei.nxv8bf16.nxv8i32(3315 <vscale x 8 x bfloat> %0,3316 ptr %1,3317 <vscale x 8 x i32> %2,3318 iXLen %3)3319 3320 ret void3321}3322 3323define void @intrinsic_vsuxei_mask_v_nxv8bf16_nxv8bf16_nxv8i32(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3324; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8bf16_nxv8bf16_nxv8i32:3325; CHECK: # %bb.0: # %entry3326; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3327; CHECK-NEXT: vsuxei32.v v8, (a0), v12, v0.t3328; CHECK-NEXT: ret3329entry:3330 call void @llvm.riscv.vsuxei.mask.nxv8bf16.nxv8i32(3331 <vscale x 8 x bfloat> %0,3332 ptr %1,3333 <vscale x 8 x i32> %2,3334 <vscale x 8 x i1> %3,3335 iXLen %4)3336 3337 ret void3338}3339 3340define void @intrinsic_vsuxei_v_nxv16bf16_nxv16bf16_nxv16i32(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {3341; CHECK-LABEL: intrinsic_vsuxei_v_nxv16bf16_nxv16bf16_nxv16i32:3342; CHECK: # %bb.0: # %entry3343; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3344; CHECK-NEXT: vsuxei32.v v8, (a0), v163345; CHECK-NEXT: ret3346entry:3347 call void @llvm.riscv.vsuxei.nxv16bf16.nxv16i32(3348 <vscale x 16 x bfloat> %0,3349 ptr %1,3350 <vscale x 16 x i32> %2,3351 iXLen %3)3352 3353 ret void3354}3355 3356define void @intrinsic_vsuxei_mask_v_nxv16bf16_nxv16bf16_nxv16i32(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3357; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16bf16_nxv16bf16_nxv16i32:3358; CHECK: # %bb.0: # %entry3359; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3360; CHECK-NEXT: vsuxei32.v v8, (a0), v16, v0.t3361; CHECK-NEXT: ret3362entry:3363 call void @llvm.riscv.vsuxei.mask.nxv16bf16.nxv16i32(3364 <vscale x 16 x bfloat> %0,3365 ptr %1,3366 <vscale x 16 x i32> %2,3367 <vscale x 16 x i1> %3,3368 iXLen %4)3369 3370 ret void3371}3372 3373define void @intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {3374; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f32_nxv1f32_nxv1i8:3375; CHECK: # %bb.0: # %entry3376; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma3377; CHECK-NEXT: vsuxei8.v v8, (a0), v93378; CHECK-NEXT: ret3379entry:3380 call void @llvm.riscv.vsuxei.nxv1f32.nxv1i8(3381 <vscale x 1 x float> %0,3382 ptr %1,3383 <vscale x 1 x i8> %2,3384 iXLen %3)3385 3386 ret void3387}3388 3389define void @intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3390; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f32_nxv1f32_nxv1i8:3391; CHECK: # %bb.0: # %entry3392; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma3393; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t3394; CHECK-NEXT: ret3395entry:3396 call void @llvm.riscv.vsuxei.mask.nxv1f32.nxv1i8(3397 <vscale x 1 x float> %0,3398 ptr %1,3399 <vscale x 1 x i8> %2,3400 <vscale x 1 x i1> %3,3401 iXLen %4)3402 3403 ret void3404}3405 3406define void @intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {3407; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f32_nxv2f32_nxv2i8:3408; CHECK: # %bb.0: # %entry3409; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma3410; CHECK-NEXT: vsuxei8.v v8, (a0), v93411; CHECK-NEXT: ret3412entry:3413 call void @llvm.riscv.vsuxei.nxv2f32.nxv2i8(3414 <vscale x 2 x float> %0,3415 ptr %1,3416 <vscale x 2 x i8> %2,3417 iXLen %3)3418 3419 ret void3420}3421 3422define void @intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3423; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f32_nxv2f32_nxv2i8:3424; CHECK: # %bb.0: # %entry3425; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma3426; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t3427; CHECK-NEXT: ret3428entry:3429 call void @llvm.riscv.vsuxei.mask.nxv2f32.nxv2i8(3430 <vscale x 2 x float> %0,3431 ptr %1,3432 <vscale x 2 x i8> %2,3433 <vscale x 2 x i1> %3,3434 iXLen %4)3435 3436 ret void3437}3438 3439define void @intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {3440; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f32_nxv4f32_nxv4i8:3441; CHECK: # %bb.0: # %entry3442; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma3443; CHECK-NEXT: vsuxei8.v v8, (a0), v103444; CHECK-NEXT: ret3445entry:3446 call void @llvm.riscv.vsuxei.nxv4f32.nxv4i8(3447 <vscale x 4 x float> %0,3448 ptr %1,3449 <vscale x 4 x i8> %2,3450 iXLen %3)3451 3452 ret void3453}3454 3455define void @intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3456; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f32_nxv4f32_nxv4i8:3457; CHECK: # %bb.0: # %entry3458; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma3459; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t3460; CHECK-NEXT: ret3461entry:3462 call void @llvm.riscv.vsuxei.mask.nxv4f32.nxv4i8(3463 <vscale x 4 x float> %0,3464 ptr %1,3465 <vscale x 4 x i8> %2,3466 <vscale x 4 x i1> %3,3467 iXLen %4)3468 3469 ret void3470}3471 3472define void @intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {3473; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f32_nxv8f32_nxv8i8:3474; CHECK: # %bb.0: # %entry3475; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma3476; CHECK-NEXT: vsuxei8.v v8, (a0), v123477; CHECK-NEXT: ret3478entry:3479 call void @llvm.riscv.vsuxei.nxv8f32.nxv8i8(3480 <vscale x 8 x float> %0,3481 ptr %1,3482 <vscale x 8 x i8> %2,3483 iXLen %3)3484 3485 ret void3486}3487 3488define void @intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3489; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f32_nxv8f32_nxv8i8:3490; CHECK: # %bb.0: # %entry3491; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma3492; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t3493; CHECK-NEXT: ret3494entry:3495 call void @llvm.riscv.vsuxei.mask.nxv8f32.nxv8i8(3496 <vscale x 8 x float> %0,3497 ptr %1,3498 <vscale x 8 x i8> %2,3499 <vscale x 8 x i1> %3,3500 iXLen %4)3501 3502 ret void3503}3504 3505define void @intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {3506; CHECK-LABEL: intrinsic_vsuxei_v_nxv16f32_nxv16f32_nxv16i8:3507; CHECK: # %bb.0: # %entry3508; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma3509; CHECK-NEXT: vsuxei8.v v8, (a0), v163510; CHECK-NEXT: ret3511entry:3512 call void @llvm.riscv.vsuxei.nxv16f32.nxv16i8(3513 <vscale x 16 x float> %0,3514 ptr %1,3515 <vscale x 16 x i8> %2,3516 iXLen %3)3517 3518 ret void3519}3520 3521define void @intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3522; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv16f32_nxv16f32_nxv16i8:3523; CHECK: # %bb.0: # %entry3524; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma3525; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t3526; CHECK-NEXT: ret3527entry:3528 call void @llvm.riscv.vsuxei.mask.nxv16f32.nxv16i8(3529 <vscale x 16 x float> %0,3530 ptr %1,3531 <vscale x 16 x i8> %2,3532 <vscale x 16 x i1> %3,3533 iXLen %4)3534 3535 ret void3536}3537 3538define void @intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {3539; CHECK-LABEL: intrinsic_vsuxei_v_nxv1f64_nxv1f64_nxv1i8:3540; CHECK: # %bb.0: # %entry3541; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma3542; CHECK-NEXT: vsuxei8.v v8, (a0), v93543; CHECK-NEXT: ret3544entry:3545 call void @llvm.riscv.vsuxei.nxv1f64.nxv1i8(3546 <vscale x 1 x double> %0,3547 ptr %1,3548 <vscale x 1 x i8> %2,3549 iXLen %3)3550 3551 ret void3552}3553 3554define void @intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3555; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv1f64_nxv1f64_nxv1i8:3556; CHECK: # %bb.0: # %entry3557; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma3558; CHECK-NEXT: vsuxei8.v v8, (a0), v9, v0.t3559; CHECK-NEXT: ret3560entry:3561 call void @llvm.riscv.vsuxei.mask.nxv1f64.nxv1i8(3562 <vscale x 1 x double> %0,3563 ptr %1,3564 <vscale x 1 x i8> %2,3565 <vscale x 1 x i1> %3,3566 iXLen %4)3567 3568 ret void3569}3570 3571define void @intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {3572; CHECK-LABEL: intrinsic_vsuxei_v_nxv2f64_nxv2f64_nxv2i8:3573; CHECK: # %bb.0: # %entry3574; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma3575; CHECK-NEXT: vsuxei8.v v8, (a0), v103576; CHECK-NEXT: ret3577entry:3578 call void @llvm.riscv.vsuxei.nxv2f64.nxv2i8(3579 <vscale x 2 x double> %0,3580 ptr %1,3581 <vscale x 2 x i8> %2,3582 iXLen %3)3583 3584 ret void3585}3586 3587define void @intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3588; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv2f64_nxv2f64_nxv2i8:3589; CHECK: # %bb.0: # %entry3590; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma3591; CHECK-NEXT: vsuxei8.v v8, (a0), v10, v0.t3592; CHECK-NEXT: ret3593entry:3594 call void @llvm.riscv.vsuxei.mask.nxv2f64.nxv2i8(3595 <vscale x 2 x double> %0,3596 ptr %1,3597 <vscale x 2 x i8> %2,3598 <vscale x 2 x i1> %3,3599 iXLen %4)3600 3601 ret void3602}3603 3604define void @intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {3605; CHECK-LABEL: intrinsic_vsuxei_v_nxv4f64_nxv4f64_nxv4i8:3606; CHECK: # %bb.0: # %entry3607; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma3608; CHECK-NEXT: vsuxei8.v v8, (a0), v123609; CHECK-NEXT: ret3610entry:3611 call void @llvm.riscv.vsuxei.nxv4f64.nxv4i8(3612 <vscale x 4 x double> %0,3613 ptr %1,3614 <vscale x 4 x i8> %2,3615 iXLen %3)3616 3617 ret void3618}3619 3620define void @intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3621; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv4f64_nxv4f64_nxv4i8:3622; CHECK: # %bb.0: # %entry3623; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma3624; CHECK-NEXT: vsuxei8.v v8, (a0), v12, v0.t3625; CHECK-NEXT: ret3626entry:3627 call void @llvm.riscv.vsuxei.mask.nxv4f64.nxv4i8(3628 <vscale x 4 x double> %0,3629 ptr %1,3630 <vscale x 4 x i8> %2,3631 <vscale x 4 x i1> %3,3632 iXLen %4)3633 3634 ret void3635}3636 3637define void @intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {3638; CHECK-LABEL: intrinsic_vsuxei_v_nxv8f64_nxv8f64_nxv8i8:3639; CHECK: # %bb.0: # %entry3640; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma3641; CHECK-NEXT: vsuxei8.v v8, (a0), v163642; CHECK-NEXT: ret3643entry:3644 call void @llvm.riscv.vsuxei.nxv8f64.nxv8i8(3645 <vscale x 8 x double> %0,3646 ptr %1,3647 <vscale x 8 x i8> %2,3648 iXLen %3)3649 3650 ret void3651}3652 3653define void @intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3654; CHECK-LABEL: intrinsic_vsuxei_mask_v_nxv8f64_nxv8f64_nxv8i8:3655; CHECK: # %bb.0: # %entry3656; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma3657; CHECK-NEXT: vsuxei8.v v8, (a0), v16, v0.t3658; CHECK-NEXT: ret3659entry:3660 call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i8(3661 <vscale x 8 x double> %0,3662 ptr %1,3663 <vscale x 8 x i8> %2,3664 <vscale x 8 x i1> %3,3665 iXLen %4)3666 3667 ret void3668}3669