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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \3; RUN: -verify-machineinstrs < %s | FileCheck %s4 5define void @test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {6; CHECK-LABEL: test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma9; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1010; CHECK-NEXT: ret11entry:12 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 3)13 ret void14}15 16define void @test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {17; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8:18; CHECK: # %bb.0: # %entry19; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma20; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t21; CHECK-NEXT: ret22entry:23 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)24 ret void25}26 27define void @test_vsuxseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {28; CHECK-LABEL: test_vsuxseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i8:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma31; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1032; CHECK-NEXT: ret33entry:34 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 3)35 ret void36}37 38define void @test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {39; CHECK-LABEL: test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma42; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1043; CHECK-NEXT: ret44entry:45 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 3)46 ret void47}48 49define void @test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {50; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i16:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma53; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t54; CHECK-NEXT: ret55entry:56 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)57 ret void58}59 60define void @test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {61; CHECK-LABEL: test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32:62; CHECK: # %bb.0: # %entry63; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma64; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1065; CHECK-NEXT: ret66entry:67 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 3)68 ret void69}70 71define void @test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {72; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma75; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t76; CHECK-NEXT: ret77entry:78 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)79 ret void80}81 82define void @test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {83; CHECK-LABEL: test_vsuxseg2_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i64:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma86; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1087; CHECK-NEXT: ret88entry:89 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 3)90 ret void91}92 93define void @test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {94; CHECK-LABEL: test_vsuxseg2_mask_nxv1i8_triscv.vector.tuple_nxv1i8_2t_nxv1i64:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma97; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t98; CHECK-NEXT: ret99entry:100 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)101 ret void102}103 104define void @test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {105; CHECK-LABEL: test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma108; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10109; CHECK-NEXT: ret110entry:111 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 3)112 ret void113}114 115define void @test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {116; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i8:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma119; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t120; CHECK-NEXT: ret121entry:122 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)123 ret void124}125 126define void @test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {127; CHECK-LABEL: test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma130; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10131; CHECK-NEXT: ret132entry:133 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 3)134 ret void135}136 137define void @test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {138; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i16:139; CHECK: # %bb.0: # %entry140; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma141; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t142; CHECK-NEXT: ret143entry:144 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)145 ret void146}147 148define void @test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {149; CHECK-LABEL: test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32:150; CHECK: # %bb.0: # %entry151; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma152; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10153; CHECK-NEXT: ret154entry:155 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 3)156 ret void157}158 159define void @test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {160; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i32:161; CHECK: # %bb.0: # %entry162; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma163; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t164; CHECK-NEXT: ret165entry:166 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)167 ret void168}169 170define void @test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {171; CHECK-LABEL: test_vsuxseg2_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i64:172; CHECK: # %bb.0: # %entry173; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma174; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10175; CHECK-NEXT: ret176entry:177 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 3)178 ret void179}180 181define void @test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {182; CHECK-LABEL: test_vsuxseg2_mask_nxv2i8_triscv.vector.tuple_nxv2i8_2t_nxv2i64:183; CHECK: # %bb.0: # %entry184; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma185; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t186; CHECK-NEXT: ret187entry:188 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)189 ret void190}191 192define void @test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {193; CHECK-LABEL: test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma196; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10197; CHECK-NEXT: ret198entry:199 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 3)200 ret void201}202 203define void @test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {204; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i8:205; CHECK: # %bb.0: # %entry206; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma207; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t208; CHECK-NEXT: ret209entry:210 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)211 ret void212}213 214define void @test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {215; CHECK-LABEL: test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16:216; CHECK: # %bb.0: # %entry217; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma218; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10219; CHECK-NEXT: ret220entry:221 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 3)222 ret void223}224 225define void @test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {226; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i16:227; CHECK: # %bb.0: # %entry228; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma229; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t230; CHECK-NEXT: ret231entry:232 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)233 ret void234}235 236define void @test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {237; CHECK-LABEL: test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32:238; CHECK: # %bb.0: # %entry239; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma240; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10241; CHECK-NEXT: ret242entry:243 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 3)244 ret void245}246 247define void @test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {248; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i32:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma251; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t252; CHECK-NEXT: ret253entry:254 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)255 ret void256}257 258define void @test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {259; CHECK-LABEL: test_vsuxseg2_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i64:260; CHECK: # %bb.0: # %entry261; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma262; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12263; CHECK-NEXT: ret264entry:265 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 3)266 ret void267}268 269define void @test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {270; CHECK-LABEL: test_vsuxseg2_mask_nxv4i8_triscv.vector.tuple_nxv4i8_2t_nxv4i64:271; CHECK: # %bb.0: # %entry272; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma273; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t274; CHECK-NEXT: ret275entry:276 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)277 ret void278}279 280define void @test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {281; CHECK-LABEL: test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8:282; CHECK: # %bb.0: # %entry283; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma284; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10285; CHECK-NEXT: ret286entry:287 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 3)288 ret void289}290 291define void @test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {292; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i8:293; CHECK: # %bb.0: # %entry294; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma295; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t296; CHECK-NEXT: ret297entry:298 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)299 ret void300}301 302define void @test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {303; CHECK-LABEL: test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16:304; CHECK: # %bb.0: # %entry305; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma306; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10307; CHECK-NEXT: ret308entry:309 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 3)310 ret void311}312 313define void @test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {314; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i16:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma317; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t318; CHECK-NEXT: ret319entry:320 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)321 ret void322}323 324define void @test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {325; CHECK-LABEL: test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32:326; CHECK: # %bb.0: # %entry327; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma328; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12329; CHECK-NEXT: ret330entry:331 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 3)332 ret void333}334 335define void @test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {336; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i32:337; CHECK: # %bb.0: # %entry338; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma339; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t340; CHECK-NEXT: ret341entry:342 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)343 ret void344}345 346define void @test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {347; CHECK-LABEL: test_vsuxseg2_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i64:348; CHECK: # %bb.0: # %entry349; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma350; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16351; CHECK-NEXT: ret352entry:353 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 3)354 ret void355}356 357define void @test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {358; CHECK-LABEL: test_vsuxseg2_mask_nxv8i8_triscv.vector.tuple_nxv8i8_2t_nxv8i64:359; CHECK: # %bb.0: # %entry360; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma361; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t362; CHECK-NEXT: ret363entry:364 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)365 ret void366}367 368define void @test_vsuxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {369; CHECK-LABEL: test_vsuxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8:370; CHECK: # %bb.0: # %entry371; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma372; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12373; CHECK-NEXT: ret374entry:375 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, i64 3)376 ret void377}378 379define void @test_vsuxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {380; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i8:381; CHECK: # %bb.0: # %entry382; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma383; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t384; CHECK-NEXT: ret385entry:386 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)387 ret void388}389 390define void @test_vsuxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {391; CHECK-LABEL: test_vsuxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16:392; CHECK: # %bb.0: # %entry393; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma394; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12395; CHECK-NEXT: ret396entry:397 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, i64 3)398 ret void399}400 401define void @test_vsuxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {402; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i16:403; CHECK: # %bb.0: # %entry404; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma405; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t406; CHECK-NEXT: ret407entry:408 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)409 ret void410}411 412define void @test_vsuxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {413; CHECK-LABEL: test_vsuxseg2_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma416; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16417; CHECK-NEXT: ret418entry:419 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, i64 3)420 ret void421}422 423define void @test_vsuxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {424; CHECK-LABEL: test_vsuxseg2_mask_nxv16i8_triscv.vector.tuple_nxv16i8_2t_nxv16i32:425; CHECK: # %bb.0: # %entry426; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma427; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t428; CHECK-NEXT: ret429entry:430 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)431 ret void432}433 434define void @test_vsuxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, i64 %vl) {435; CHECK-LABEL: test_vsuxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8:436; CHECK: # %bb.0: # %entry437; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma438; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16439; CHECK-NEXT: ret440entry:441 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv32i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, i64 %vl, i64 3)442 ret void443}444 445define void @test_vsuxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, i64 %vl, <vscale x 32 x i1> %mask) {446; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i8:447; CHECK: # %bb.0: # %entry448; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma449; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t450; CHECK-NEXT: ret451entry:452 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv32i8.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl, i64 3)453 ret void454}455 456define void @test_vsuxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, i64 %vl) {457; CHECK-LABEL: test_vsuxseg2_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16:458; CHECK: # %bb.0: # %entry459; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma460; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16461; CHECK-NEXT: ret462entry:463 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv32i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, i64 %vl, i64 3)464 ret void465}466 467define void @test_vsuxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, i64 %vl, <vscale x 32 x i1> %mask) {468; CHECK-LABEL: test_vsuxseg2_mask_nxv32i8_triscv.vector.tuple_nxv32i8_2t_nxv32i16:469; CHECK: # %bb.0: # %entry470; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma471; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t472; CHECK-NEXT: ret473entry:474 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv32i16.nxv32i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl, i64 3)475 ret void476}477 478define void @test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {479; CHECK-LABEL: test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8:480; CHECK: # %bb.0: # %entry481; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma482; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11483; CHECK-NEXT: ret484entry:485 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 3)486 ret void487}488 489define void @test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {490; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8:491; CHECK: # %bb.0: # %entry492; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma493; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t494; CHECK-NEXT: ret495entry:496 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)497 ret void498}499 500define void @test_vsuxseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {501; CHECK-LABEL: test_vsuxseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i8:502; CHECK: # %bb.0: # %entry503; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma504; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11505; CHECK-NEXT: ret506entry:507 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 3)508 ret void509}510 511define void @test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {512; CHECK-LABEL: test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16:513; CHECK: # %bb.0: # %entry514; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma515; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11516; CHECK-NEXT: ret517entry:518 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 3)519 ret void520}521 522define void @test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {523; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i16:524; CHECK: # %bb.0: # %entry525; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma526; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t527; CHECK-NEXT: ret528entry:529 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)530 ret void531}532 533define void @test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {534; CHECK-LABEL: test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32:535; CHECK: # %bb.0: # %entry536; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma537; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11538; CHECK-NEXT: ret539entry:540 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 3)541 ret void542}543 544define void @test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {545; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i32:546; CHECK: # %bb.0: # %entry547; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma548; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t549; CHECK-NEXT: ret550entry:551 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)552 ret void553}554 555define void @test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {556; CHECK-LABEL: test_vsuxseg3_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i64:557; CHECK: # %bb.0: # %entry558; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma559; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11560; CHECK-NEXT: ret561entry:562 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv1i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 3)563 ret void564}565 566define void @test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {567; CHECK-LABEL: test_vsuxseg3_mask_nxv1i8_triscv.vector.tuple_nxv1i8_3t_nxv1i64:568; CHECK: # %bb.0: # %entry569; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma570; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t571; CHECK-NEXT: ret572entry:573 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)574 ret void575}576 577define void @test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {578; CHECK-LABEL: test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8:579; CHECK: # %bb.0: # %entry580; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma581; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11582; CHECK-NEXT: ret583entry:584 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 3)585 ret void586}587 588define void @test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {589; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i8:590; CHECK: # %bb.0: # %entry591; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma592; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t593; CHECK-NEXT: ret594entry:595 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)596 ret void597}598 599define void @test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {600; CHECK-LABEL: test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16:601; CHECK: # %bb.0: # %entry602; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma603; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11604; CHECK-NEXT: ret605entry:606 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 3)607 ret void608}609 610define void @test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {611; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i16:612; CHECK: # %bb.0: # %entry613; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma614; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t615; CHECK-NEXT: ret616entry:617 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)618 ret void619}620 621define void @test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {622; CHECK-LABEL: test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32:623; CHECK: # %bb.0: # %entry624; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma625; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11626; CHECK-NEXT: ret627entry:628 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 3)629 ret void630}631 632define void @test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {633; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i32:634; CHECK: # %bb.0: # %entry635; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma636; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t637; CHECK-NEXT: ret638entry:639 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)640 ret void641}642 643define void @test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {644; CHECK-LABEL: test_vsuxseg3_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i64:645; CHECK: # %bb.0: # %entry646; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma647; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12648; CHECK-NEXT: ret649entry:650 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 3)651 ret void652}653 654define void @test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {655; CHECK-LABEL: test_vsuxseg3_mask_nxv2i8_triscv.vector.tuple_nxv2i8_3t_nxv2i64:656; CHECK: # %bb.0: # %entry657; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma658; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t659; CHECK-NEXT: ret660entry:661 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)662 ret void663}664 665define void @test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {666; CHECK-LABEL: test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8:667; CHECK: # %bb.0: # %entry668; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma669; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11670; CHECK-NEXT: ret671entry:672 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 3)673 ret void674}675 676define void @test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {677; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i8:678; CHECK: # %bb.0: # %entry679; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma680; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t681; CHECK-NEXT: ret682entry:683 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)684 ret void685}686 687define void @test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {688; CHECK-LABEL: test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16:689; CHECK: # %bb.0: # %entry690; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma691; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11692; CHECK-NEXT: ret693entry:694 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 3)695 ret void696}697 698define void @test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {699; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i16:700; CHECK: # %bb.0: # %entry701; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma702; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t703; CHECK-NEXT: ret704entry:705 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)706 ret void707}708 709define void @test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {710; CHECK-LABEL: test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32:711; CHECK: # %bb.0: # %entry712; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma713; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12714; CHECK-NEXT: ret715entry:716 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 3)717 ret void718}719 720define void @test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {721; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i32:722; CHECK: # %bb.0: # %entry723; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma724; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t725; CHECK-NEXT: ret726entry:727 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)728 ret void729}730 731define void @test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {732; CHECK-LABEL: test_vsuxseg3_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i64:733; CHECK: # %bb.0: # %entry734; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma735; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12736; CHECK-NEXT: ret737entry:738 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 3)739 ret void740}741 742define void @test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {743; CHECK-LABEL: test_vsuxseg3_mask_nxv4i8_triscv.vector.tuple_nxv4i8_3t_nxv4i64:744; CHECK: # %bb.0: # %entry745; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma746; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t747; CHECK-NEXT: ret748entry:749 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)750 ret void751}752 753define void @test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {754; CHECK-LABEL: test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8:755; CHECK: # %bb.0: # %entry756; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma757; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11758; CHECK-NEXT: ret759entry:760 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 3)761 ret void762}763 764define void @test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {765; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i8:766; CHECK: # %bb.0: # %entry767; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma768; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t769; CHECK-NEXT: ret770entry:771 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)772 ret void773}774 775define void @test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {776; CHECK-LABEL: test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16:777; CHECK: # %bb.0: # %entry778; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma779; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12780; CHECK-NEXT: ret781entry:782 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 3)783 ret void784}785 786define void @test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {787; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i16:788; CHECK: # %bb.0: # %entry789; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma790; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v12, v0.t791; CHECK-NEXT: ret792entry:793 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)794 ret void795}796 797define void @test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {798; CHECK-LABEL: test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32:799; CHECK: # %bb.0: # %entry800; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma801; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12802; CHECK-NEXT: ret803entry:804 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 3)805 ret void806}807 808define void @test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {809; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i32:810; CHECK: # %bb.0: # %entry811; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma812; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t813; CHECK-NEXT: ret814entry:815 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)816 ret void817}818 819define void @test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {820; CHECK-LABEL: test_vsuxseg3_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i64:821; CHECK: # %bb.0: # %entry822; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma823; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v16824; CHECK-NEXT: ret825entry:826 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 3)827 ret void828}829 830define void @test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {831; CHECK-LABEL: test_vsuxseg3_mask_nxv8i8_triscv.vector.tuple_nxv8i8_3t_nxv8i64:832; CHECK: # %bb.0: # %entry833; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma834; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v16, v0.t835; CHECK-NEXT: ret836entry:837 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)838 ret void839}840 841define void @test_vsuxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {842; CHECK-LABEL: test_vsuxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8:843; CHECK: # %bb.0: # %entry844; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma845; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14846; CHECK-NEXT: ret847entry:848 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, i64 3)849 ret void850}851 852define void @test_vsuxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {853; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i8:854; CHECK: # %bb.0: # %entry855; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma856; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t857; CHECK-NEXT: ret858entry:859 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)860 ret void861}862 863define void @test_vsuxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {864; CHECK-LABEL: test_vsuxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16:865; CHECK: # %bb.0: # %entry866; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma867; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16868; CHECK-NEXT: ret869entry:870 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, i64 3)871 ret void872}873 874define void @test_vsuxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {875; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i16:876; CHECK: # %bb.0: # %entry877; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma878; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v16, v0.t879; CHECK-NEXT: ret880entry:881 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)882 ret void883}884 885define void @test_vsuxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {886; CHECK-LABEL: test_vsuxseg3_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32:887; CHECK: # %bb.0: # %entry888; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma889; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16890; CHECK-NEXT: ret891entry:892 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, i64 3)893 ret void894}895 896define void @test_vsuxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {897; CHECK-LABEL: test_vsuxseg3_mask_nxv16i8_triscv.vector.tuple_nxv16i8_3t_nxv16i32:898; CHECK: # %bb.0: # %entry899; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma900; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t901; CHECK-NEXT: ret902entry:903 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)904 ret void905}906 907define void @test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {908; CHECK-LABEL: test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8:909; CHECK: # %bb.0: # %entry910; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma911; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12912; CHECK-NEXT: ret913entry:914 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 3)915 ret void916}917 918define void @test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {919; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8:920; CHECK: # %bb.0: # %entry921; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma922; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t923; CHECK-NEXT: ret924entry:925 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)926 ret void927}928 929define void @test_vsuxseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {930; CHECK-LABEL: test_vsuxseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i8:931; CHECK: # %bb.0: # %entry932; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma933; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12934; CHECK-NEXT: ret935entry:936 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 3)937 ret void938}939 940define void @test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {941; CHECK-LABEL: test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16:942; CHECK: # %bb.0: # %entry943; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma944; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12945; CHECK-NEXT: ret946entry:947 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 3)948 ret void949}950 951define void @test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {952; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i16:953; CHECK: # %bb.0: # %entry954; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma955; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t956; CHECK-NEXT: ret957entry:958 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)959 ret void960}961 962define void @test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {963; CHECK-LABEL: test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32:964; CHECK: # %bb.0: # %entry965; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma966; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12967; CHECK-NEXT: ret968entry:969 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 3)970 ret void971}972 973define void @test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {974; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i32:975; CHECK: # %bb.0: # %entry976; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma977; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t978; CHECK-NEXT: ret979entry:980 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)981 ret void982}983 984define void @test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {985; CHECK-LABEL: test_vsuxseg4_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i64:986; CHECK: # %bb.0: # %entry987; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma988; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12989; CHECK-NEXT: ret990entry:991 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv1i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 3)992 ret void993}994 995define void @test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {996; CHECK-LABEL: test_vsuxseg4_mask_nxv1i8_triscv.vector.tuple_nxv1i8_4t_nxv1i64:997; CHECK: # %bb.0: # %entry998; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma999; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t1000; CHECK-NEXT: ret1001entry:1002 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1003 ret void1004}1005 1006define void @test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {1007; CHECK-LABEL: test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8:1008; CHECK: # %bb.0: # %entry1009; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1010; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v121011; CHECK-NEXT: ret1012entry:1013 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 3)1014 ret void1015}1016 1017define void @test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {1018; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i8:1019; CHECK: # %bb.0: # %entry1020; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1021; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t1022; CHECK-NEXT: ret1023entry:1024 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1025 ret void1026}1027 1028define void @test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {1029; CHECK-LABEL: test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16:1030; CHECK: # %bb.0: # %entry1031; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1032; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v121033; CHECK-NEXT: ret1034entry:1035 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 3)1036 ret void1037}1038 1039define void @test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {1040; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i16:1041; CHECK: # %bb.0: # %entry1042; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1043; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t1044; CHECK-NEXT: ret1045entry:1046 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1047 ret void1048}1049 1050define void @test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {1051; CHECK-LABEL: test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32:1052; CHECK: # %bb.0: # %entry1053; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1054; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v121055; CHECK-NEXT: ret1056entry:1057 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 3)1058 ret void1059}1060 1061define void @test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {1062; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i32:1063; CHECK: # %bb.0: # %entry1064; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1065; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t1066; CHECK-NEXT: ret1067entry:1068 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1069 ret void1070}1071 1072define void @test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {1073; CHECK-LABEL: test_vsuxseg4_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i64:1074; CHECK: # %bb.0: # %entry1075; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1076; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v121077; CHECK-NEXT: ret1078entry:1079 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 3)1080 ret void1081}1082 1083define void @test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {1084; CHECK-LABEL: test_vsuxseg4_mask_nxv2i8_triscv.vector.tuple_nxv2i8_4t_nxv2i64:1085; CHECK: # %bb.0: # %entry1086; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1087; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t1088; CHECK-NEXT: ret1089entry:1090 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1091 ret void1092}1093 1094define void @test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {1095; CHECK-LABEL: test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8:1096; CHECK: # %bb.0: # %entry1097; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1098; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v121099; CHECK-NEXT: ret1100entry:1101 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 3)1102 ret void1103}1104 1105define void @test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {1106; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i8:1107; CHECK: # %bb.0: # %entry1108; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1109; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t1110; CHECK-NEXT: ret1111entry:1112 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1113 ret void1114}1115 1116define void @test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {1117; CHECK-LABEL: test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16:1118; CHECK: # %bb.0: # %entry1119; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1120; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v121121; CHECK-NEXT: ret1122entry:1123 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 3)1124 ret void1125}1126 1127define void @test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {1128; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i16:1129; CHECK: # %bb.0: # %entry1130; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1131; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t1132; CHECK-NEXT: ret1133entry:1134 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1135 ret void1136}1137 1138define void @test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {1139; CHECK-LABEL: test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32:1140; CHECK: # %bb.0: # %entry1141; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1142; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v121143; CHECK-NEXT: ret1144entry:1145 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 3)1146 ret void1147}1148 1149define void @test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {1150; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i32:1151; CHECK: # %bb.0: # %entry1152; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1153; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t1154; CHECK-NEXT: ret1155entry:1156 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1157 ret void1158}1159 1160define void @test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {1161; CHECK-LABEL: test_vsuxseg4_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i64:1162; CHECK: # %bb.0: # %entry1163; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1164; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v121165; CHECK-NEXT: ret1166entry:1167 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 3)1168 ret void1169}1170 1171define void @test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {1172; CHECK-LABEL: test_vsuxseg4_mask_nxv4i8_triscv.vector.tuple_nxv4i8_4t_nxv4i64:1173; CHECK: # %bb.0: # %entry1174; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1175; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t1176; CHECK-NEXT: ret1177entry:1178 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1179 ret void1180}1181 1182define void @test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {1183; CHECK-LABEL: test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8:1184; CHECK: # %bb.0: # %entry1185; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1186; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v121187; CHECK-NEXT: ret1188entry:1189 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 3)1190 ret void1191}1192 1193define void @test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {1194; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i8:1195; CHECK: # %bb.0: # %entry1196; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1197; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t1198; CHECK-NEXT: ret1199entry:1200 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1201 ret void1202}1203 1204define void @test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {1205; CHECK-LABEL: test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16:1206; CHECK: # %bb.0: # %entry1207; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1208; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v121209; CHECK-NEXT: ret1210entry:1211 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 3)1212 ret void1213}1214 1215define void @test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {1216; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i16:1217; CHECK: # %bb.0: # %entry1218; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1219; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t1220; CHECK-NEXT: ret1221entry:1222 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1223 ret void1224}1225 1226define void @test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {1227; CHECK-LABEL: test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32:1228; CHECK: # %bb.0: # %entry1229; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1230; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v121231; CHECK-NEXT: ret1232entry:1233 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 3)1234 ret void1235}1236 1237define void @test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {1238; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i32:1239; CHECK: # %bb.0: # %entry1240; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1241; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t1242; CHECK-NEXT: ret1243entry:1244 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1245 ret void1246}1247 1248define void @test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {1249; CHECK-LABEL: test_vsuxseg4_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i64:1250; CHECK: # %bb.0: # %entry1251; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1252; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v161253; CHECK-NEXT: ret1254entry:1255 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 3)1256 ret void1257}1258 1259define void @test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {1260; CHECK-LABEL: test_vsuxseg4_mask_nxv8i8_triscv.vector.tuple_nxv8i8_4t_nxv8i64:1261; CHECK: # %bb.0: # %entry1262; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1263; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t1264; CHECK-NEXT: ret1265entry:1266 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1267 ret void1268}1269 1270define void @test_vsuxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {1271; CHECK-LABEL: test_vsuxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8:1272; CHECK: # %bb.0: # %entry1273; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1274; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v161275; CHECK-NEXT: ret1276entry:1277 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, i64 3)1278 ret void1279}1280 1281define void @test_vsuxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {1282; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i8:1283; CHECK: # %bb.0: # %entry1284; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1285; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t1286; CHECK-NEXT: ret1287entry:1288 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)1289 ret void1290}1291 1292define void @test_vsuxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {1293; CHECK-LABEL: test_vsuxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16:1294; CHECK: # %bb.0: # %entry1295; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1296; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v161297; CHECK-NEXT: ret1298entry:1299 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, i64 3)1300 ret void1301}1302 1303define void @test_vsuxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {1304; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i16:1305; CHECK: # %bb.0: # %entry1306; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1307; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t1308; CHECK-NEXT: ret1309entry:1310 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)1311 ret void1312}1313 1314define void @test_vsuxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {1315; CHECK-LABEL: test_vsuxseg4_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32:1316; CHECK: # %bb.0: # %entry1317; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1318; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v161319; CHECK-NEXT: ret1320entry:1321 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, i64 3)1322 ret void1323}1324 1325define void @test_vsuxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {1326; CHECK-LABEL: test_vsuxseg4_mask_nxv16i8_triscv.vector.tuple_nxv16i8_4t_nxv16i32:1327; CHECK: # %bb.0: # %entry1328; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1329; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t1330; CHECK-NEXT: ret1331entry:1332 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 3)1333 ret void1334}1335 1336define void @test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {1337; CHECK-LABEL: test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8:1338; CHECK: # %bb.0: # %entry1339; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1340; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v131341; CHECK-NEXT: ret1342entry:1343 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 3)1344 ret void1345}1346 1347define void @test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {1348; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8:1349; CHECK: # %bb.0: # %entry1350; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1351; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t1352; CHECK-NEXT: ret1353entry:1354 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1355 ret void1356}1357 1358define void @test_vsuxseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {1359; CHECK-LABEL: test_vsuxseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i8:1360; CHECK: # %bb.0: # %entry1361; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1362; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v131363; CHECK-NEXT: ret1364entry:1365 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 3)1366 ret void1367}1368 1369define void @test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {1370; CHECK-LABEL: test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16:1371; CHECK: # %bb.0: # %entry1372; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1373; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v131374; CHECK-NEXT: ret1375entry:1376 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 3)1377 ret void1378}1379 1380define void @test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {1381; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i16:1382; CHECK: # %bb.0: # %entry1383; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1384; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t1385; CHECK-NEXT: ret1386entry:1387 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1388 ret void1389}1390 1391define void @test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {1392; CHECK-LABEL: test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32:1393; CHECK: # %bb.0: # %entry1394; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1395; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v131396; CHECK-NEXT: ret1397entry:1398 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 3)1399 ret void1400}1401 1402define void @test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {1403; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i32:1404; CHECK: # %bb.0: # %entry1405; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1406; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t1407; CHECK-NEXT: ret1408entry:1409 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1410 ret void1411}1412 1413define void @test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {1414; CHECK-LABEL: test_vsuxseg5_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i64:1415; CHECK: # %bb.0: # %entry1416; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1417; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v131418; CHECK-NEXT: ret1419entry:1420 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv1i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 3)1421 ret void1422}1423 1424define void @test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {1425; CHECK-LABEL: test_vsuxseg5_mask_nxv1i8_triscv.vector.tuple_nxv1i8_5t_nxv1i64:1426; CHECK: # %bb.0: # %entry1427; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1428; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t1429; CHECK-NEXT: ret1430entry:1431 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1432 ret void1433}1434 1435define void @test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {1436; CHECK-LABEL: test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8:1437; CHECK: # %bb.0: # %entry1438; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1439; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v131440; CHECK-NEXT: ret1441entry:1442 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 3)1443 ret void1444}1445 1446define void @test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {1447; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i8:1448; CHECK: # %bb.0: # %entry1449; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1450; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t1451; CHECK-NEXT: ret1452entry:1453 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1454 ret void1455}1456 1457define void @test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {1458; CHECK-LABEL: test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16:1459; CHECK: # %bb.0: # %entry1460; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1461; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v131462; CHECK-NEXT: ret1463entry:1464 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 3)1465 ret void1466}1467 1468define void @test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {1469; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i16:1470; CHECK: # %bb.0: # %entry1471; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1472; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t1473; CHECK-NEXT: ret1474entry:1475 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1476 ret void1477}1478 1479define void @test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {1480; CHECK-LABEL: test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32:1481; CHECK: # %bb.0: # %entry1482; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1483; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v131484; CHECK-NEXT: ret1485entry:1486 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 3)1487 ret void1488}1489 1490define void @test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {1491; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i32:1492; CHECK: # %bb.0: # %entry1493; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1494; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t1495; CHECK-NEXT: ret1496entry:1497 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1498 ret void1499}1500 1501define void @test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {1502; CHECK-LABEL: test_vsuxseg5_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i64:1503; CHECK: # %bb.0: # %entry1504; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1505; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v141506; CHECK-NEXT: ret1507entry:1508 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 3)1509 ret void1510}1511 1512define void @test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {1513; CHECK-LABEL: test_vsuxseg5_mask_nxv2i8_triscv.vector.tuple_nxv2i8_5t_nxv2i64:1514; CHECK: # %bb.0: # %entry1515; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1516; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v14, v0.t1517; CHECK-NEXT: ret1518entry:1519 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1520 ret void1521}1522 1523define void @test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {1524; CHECK-LABEL: test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8:1525; CHECK: # %bb.0: # %entry1526; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1527; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v131528; CHECK-NEXT: ret1529entry:1530 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 3)1531 ret void1532}1533 1534define void @test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {1535; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i8:1536; CHECK: # %bb.0: # %entry1537; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1538; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t1539; CHECK-NEXT: ret1540entry:1541 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1542 ret void1543}1544 1545define void @test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {1546; CHECK-LABEL: test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16:1547; CHECK: # %bb.0: # %entry1548; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1549; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v131550; CHECK-NEXT: ret1551entry:1552 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 3)1553 ret void1554}1555 1556define void @test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {1557; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i16:1558; CHECK: # %bb.0: # %entry1559; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1560; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t1561; CHECK-NEXT: ret1562entry:1563 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1564 ret void1565}1566 1567define void @test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {1568; CHECK-LABEL: test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32:1569; CHECK: # %bb.0: # %entry1570; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1571; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v141572; CHECK-NEXT: ret1573entry:1574 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 3)1575 ret void1576}1577 1578define void @test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {1579; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i32:1580; CHECK: # %bb.0: # %entry1581; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1582; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v14, v0.t1583; CHECK-NEXT: ret1584entry:1585 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1586 ret void1587}1588 1589define void @test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {1590; CHECK-LABEL: test_vsuxseg5_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i64:1591; CHECK: # %bb.0: # %entry1592; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1593; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v161594; CHECK-NEXT: ret1595entry:1596 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 3)1597 ret void1598}1599 1600define void @test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {1601; CHECK-LABEL: test_vsuxseg5_mask_nxv4i8_triscv.vector.tuple_nxv4i8_5t_nxv4i64:1602; CHECK: # %bb.0: # %entry1603; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1604; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v16, v0.t1605; CHECK-NEXT: ret1606entry:1607 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1608 ret void1609}1610 1611define void @test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {1612; CHECK-LABEL: test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8:1613; CHECK: # %bb.0: # %entry1614; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1615; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v131616; CHECK-NEXT: ret1617entry:1618 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 3)1619 ret void1620}1621 1622define void @test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {1623; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i8:1624; CHECK: # %bb.0: # %entry1625; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1626; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t1627; CHECK-NEXT: ret1628entry:1629 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1630 ret void1631}1632 1633define void @test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {1634; CHECK-LABEL: test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16:1635; CHECK: # %bb.0: # %entry1636; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1637; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v141638; CHECK-NEXT: ret1639entry:1640 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 3)1641 ret void1642}1643 1644define void @test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {1645; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i16:1646; CHECK: # %bb.0: # %entry1647; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1648; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v14, v0.t1649; CHECK-NEXT: ret1650entry:1651 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1652 ret void1653}1654 1655define void @test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {1656; CHECK-LABEL: test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32:1657; CHECK: # %bb.0: # %entry1658; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1659; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v161660; CHECK-NEXT: ret1661entry:1662 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 3)1663 ret void1664}1665 1666define void @test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {1667; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i32:1668; CHECK: # %bb.0: # %entry1669; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1670; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v16, v0.t1671; CHECK-NEXT: ret1672entry:1673 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1674 ret void1675}1676 1677define void @test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {1678; CHECK-LABEL: test_vsuxseg5_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i64:1679; CHECK: # %bb.0: # %entry1680; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1681; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v161682; CHECK-NEXT: ret1683entry:1684 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 3)1685 ret void1686}1687 1688define void @test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {1689; CHECK-LABEL: test_vsuxseg5_mask_nxv8i8_triscv.vector.tuple_nxv8i8_5t_nxv8i64:1690; CHECK: # %bb.0: # %entry1691; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1692; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v16, v0.t1693; CHECK-NEXT: ret1694entry:1695 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1696 ret void1697}1698 1699define void @test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {1700; CHECK-LABEL: test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8:1701; CHECK: # %bb.0: # %entry1702; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1703; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v141704; CHECK-NEXT: ret1705entry:1706 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 3)1707 ret void1708}1709 1710define void @test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {1711; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8:1712; CHECK: # %bb.0: # %entry1713; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1714; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t1715; CHECK-NEXT: ret1716entry:1717 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1718 ret void1719}1720 1721define void @test_vsuxseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {1722; CHECK-LABEL: test_vsuxseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i8:1723; CHECK: # %bb.0: # %entry1724; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1725; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v141726; CHECK-NEXT: ret1727entry:1728 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 3)1729 ret void1730}1731 1732define void @test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {1733; CHECK-LABEL: test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16:1734; CHECK: # %bb.0: # %entry1735; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1736; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v141737; CHECK-NEXT: ret1738entry:1739 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 3)1740 ret void1741}1742 1743define void @test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {1744; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i16:1745; CHECK: # %bb.0: # %entry1746; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1747; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t1748; CHECK-NEXT: ret1749entry:1750 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1751 ret void1752}1753 1754define void @test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {1755; CHECK-LABEL: test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32:1756; CHECK: # %bb.0: # %entry1757; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1758; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v141759; CHECK-NEXT: ret1760entry:1761 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 3)1762 ret void1763}1764 1765define void @test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {1766; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i32:1767; CHECK: # %bb.0: # %entry1768; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1769; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t1770; CHECK-NEXT: ret1771entry:1772 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1773 ret void1774}1775 1776define void @test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {1777; CHECK-LABEL: test_vsuxseg6_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i64:1778; CHECK: # %bb.0: # %entry1779; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1780; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v141781; CHECK-NEXT: ret1782entry:1783 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv1i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 3)1784 ret void1785}1786 1787define void @test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {1788; CHECK-LABEL: test_vsuxseg6_mask_nxv1i8_triscv.vector.tuple_nxv1i8_6t_nxv1i64:1789; CHECK: # %bb.0: # %entry1790; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1791; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t1792; CHECK-NEXT: ret1793entry:1794 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)1795 ret void1796}1797 1798define void @test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {1799; CHECK-LABEL: test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8:1800; CHECK: # %bb.0: # %entry1801; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1802; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v141803; CHECK-NEXT: ret1804entry:1805 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 3)1806 ret void1807}1808 1809define void @test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {1810; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i8:1811; CHECK: # %bb.0: # %entry1812; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1813; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t1814; CHECK-NEXT: ret1815entry:1816 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1817 ret void1818}1819 1820define void @test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {1821; CHECK-LABEL: test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16:1822; CHECK: # %bb.0: # %entry1823; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1824; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v141825; CHECK-NEXT: ret1826entry:1827 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 3)1828 ret void1829}1830 1831define void @test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {1832; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i16:1833; CHECK: # %bb.0: # %entry1834; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1835; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t1836; CHECK-NEXT: ret1837entry:1838 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1839 ret void1840}1841 1842define void @test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {1843; CHECK-LABEL: test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32:1844; CHECK: # %bb.0: # %entry1845; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1846; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v141847; CHECK-NEXT: ret1848entry:1849 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 3)1850 ret void1851}1852 1853define void @test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {1854; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i32:1855; CHECK: # %bb.0: # %entry1856; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1857; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t1858; CHECK-NEXT: ret1859entry:1860 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1861 ret void1862}1863 1864define void @test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {1865; CHECK-LABEL: test_vsuxseg6_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i64:1866; CHECK: # %bb.0: # %entry1867; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1868; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v141869; CHECK-NEXT: ret1870entry:1871 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 3)1872 ret void1873}1874 1875define void @test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {1876; CHECK-LABEL: test_vsuxseg6_mask_nxv2i8_triscv.vector.tuple_nxv2i8_6t_nxv2i64:1877; CHECK: # %bb.0: # %entry1878; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1879; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t1880; CHECK-NEXT: ret1881entry:1882 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)1883 ret void1884}1885 1886define void @test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {1887; CHECK-LABEL: test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8:1888; CHECK: # %bb.0: # %entry1889; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1890; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v141891; CHECK-NEXT: ret1892entry:1893 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 3)1894 ret void1895}1896 1897define void @test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {1898; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i8:1899; CHECK: # %bb.0: # %entry1900; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1901; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t1902; CHECK-NEXT: ret1903entry:1904 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1905 ret void1906}1907 1908define void @test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {1909; CHECK-LABEL: test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16:1910; CHECK: # %bb.0: # %entry1911; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1912; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v141913; CHECK-NEXT: ret1914entry:1915 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 3)1916 ret void1917}1918 1919define void @test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {1920; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i16:1921; CHECK: # %bb.0: # %entry1922; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1923; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t1924; CHECK-NEXT: ret1925entry:1926 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1927 ret void1928}1929 1930define void @test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {1931; CHECK-LABEL: test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32:1932; CHECK: # %bb.0: # %entry1933; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1934; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v141935; CHECK-NEXT: ret1936entry:1937 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 3)1938 ret void1939}1940 1941define void @test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {1942; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i32:1943; CHECK: # %bb.0: # %entry1944; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1945; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t1946; CHECK-NEXT: ret1947entry:1948 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1949 ret void1950}1951 1952define void @test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {1953; CHECK-LABEL: test_vsuxseg6_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i64:1954; CHECK: # %bb.0: # %entry1955; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1956; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v161957; CHECK-NEXT: ret1958entry:1959 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 3)1960 ret void1961}1962 1963define void @test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {1964; CHECK-LABEL: test_vsuxseg6_mask_nxv4i8_triscv.vector.tuple_nxv4i8_6t_nxv4i64:1965; CHECK: # %bb.0: # %entry1966; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1967; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v16, v0.t1968; CHECK-NEXT: ret1969entry:1970 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)1971 ret void1972}1973 1974define void @test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {1975; CHECK-LABEL: test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8:1976; CHECK: # %bb.0: # %entry1977; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1978; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v141979; CHECK-NEXT: ret1980entry:1981 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 3)1982 ret void1983}1984 1985define void @test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {1986; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i8:1987; CHECK: # %bb.0: # %entry1988; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1989; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t1990; CHECK-NEXT: ret1991entry:1992 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)1993 ret void1994}1995 1996define void @test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {1997; CHECK-LABEL: test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16:1998; CHECK: # %bb.0: # %entry1999; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2000; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v142001; CHECK-NEXT: ret2002entry:2003 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 3)2004 ret void2005}2006 2007define void @test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {2008; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i16:2009; CHECK: # %bb.0: # %entry2010; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2011; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t2012; CHECK-NEXT: ret2013entry:2014 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2015 ret void2016}2017 2018define void @test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {2019; CHECK-LABEL: test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32:2020; CHECK: # %bb.0: # %entry2021; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2022; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v162023; CHECK-NEXT: ret2024entry:2025 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 3)2026 ret void2027}2028 2029define void @test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {2030; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i32:2031; CHECK: # %bb.0: # %entry2032; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2033; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v16, v0.t2034; CHECK-NEXT: ret2035entry:2036 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2037 ret void2038}2039 2040define void @test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {2041; CHECK-LABEL: test_vsuxseg6_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i64:2042; CHECK: # %bb.0: # %entry2043; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2044; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v162045; CHECK-NEXT: ret2046entry:2047 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 3)2048 ret void2049}2050 2051define void @test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {2052; CHECK-LABEL: test_vsuxseg6_mask_nxv8i8_triscv.vector.tuple_nxv8i8_6t_nxv8i64:2053; CHECK: # %bb.0: # %entry2054; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2055; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v16, v0.t2056; CHECK-NEXT: ret2057entry:2058 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2059 ret void2060}2061 2062define void @test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {2063; CHECK-LABEL: test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8:2064; CHECK: # %bb.0: # %entry2065; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2066; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v152067; CHECK-NEXT: ret2068entry:2069 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 3)2070 ret void2071}2072 2073define void @test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {2074; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8:2075; CHECK: # %bb.0: # %entry2076; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2077; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t2078; CHECK-NEXT: ret2079entry:2080 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2081 ret void2082}2083 2084define void @test_vsuxseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {2085; CHECK-LABEL: test_vsuxseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i8:2086; CHECK: # %bb.0: # %entry2087; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2088; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v152089; CHECK-NEXT: ret2090entry:2091 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 3)2092 ret void2093}2094 2095define void @test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {2096; CHECK-LABEL: test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16:2097; CHECK: # %bb.0: # %entry2098; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2099; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v152100; CHECK-NEXT: ret2101entry:2102 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 3)2103 ret void2104}2105 2106define void @test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {2107; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i16:2108; CHECK: # %bb.0: # %entry2109; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2110; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t2111; CHECK-NEXT: ret2112entry:2113 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2114 ret void2115}2116 2117define void @test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {2118; CHECK-LABEL: test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32:2119; CHECK: # %bb.0: # %entry2120; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2121; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v152122; CHECK-NEXT: ret2123entry:2124 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 3)2125 ret void2126}2127 2128define void @test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {2129; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i32:2130; CHECK: # %bb.0: # %entry2131; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2132; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t2133; CHECK-NEXT: ret2134entry:2135 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2136 ret void2137}2138 2139define void @test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {2140; CHECK-LABEL: test_vsuxseg7_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i64:2141; CHECK: # %bb.0: # %entry2142; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2143; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v152144; CHECK-NEXT: ret2145entry:2146 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv1i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 3)2147 ret void2148}2149 2150define void @test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {2151; CHECK-LABEL: test_vsuxseg7_mask_nxv1i8_triscv.vector.tuple_nxv1i8_7t_nxv1i64:2152; CHECK: # %bb.0: # %entry2153; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2154; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t2155; CHECK-NEXT: ret2156entry:2157 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2158 ret void2159}2160 2161define void @test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {2162; CHECK-LABEL: test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8:2163; CHECK: # %bb.0: # %entry2164; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2165; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v152166; CHECK-NEXT: ret2167entry:2168 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 3)2169 ret void2170}2171 2172define void @test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {2173; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i8:2174; CHECK: # %bb.0: # %entry2175; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2176; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t2177; CHECK-NEXT: ret2178entry:2179 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2180 ret void2181}2182 2183define void @test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {2184; CHECK-LABEL: test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16:2185; CHECK: # %bb.0: # %entry2186; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2187; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v152188; CHECK-NEXT: ret2189entry:2190 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 3)2191 ret void2192}2193 2194define void @test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {2195; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i16:2196; CHECK: # %bb.0: # %entry2197; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2198; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t2199; CHECK-NEXT: ret2200entry:2201 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2202 ret void2203}2204 2205define void @test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {2206; CHECK-LABEL: test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32:2207; CHECK: # %bb.0: # %entry2208; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2209; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v152210; CHECK-NEXT: ret2211entry:2212 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 3)2213 ret void2214}2215 2216define void @test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {2217; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i32:2218; CHECK: # %bb.0: # %entry2219; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2220; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t2221; CHECK-NEXT: ret2222entry:2223 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2224 ret void2225}2226 2227define void @test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {2228; CHECK-LABEL: test_vsuxseg7_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i64:2229; CHECK: # %bb.0: # %entry2230; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2231; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v162232; CHECK-NEXT: ret2233entry:2234 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 3)2235 ret void2236}2237 2238define void @test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {2239; CHECK-LABEL: test_vsuxseg7_mask_nxv2i8_triscv.vector.tuple_nxv2i8_7t_nxv2i64:2240; CHECK: # %bb.0: # %entry2241; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2242; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t2243; CHECK-NEXT: ret2244entry:2245 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2246 ret void2247}2248 2249define void @test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {2250; CHECK-LABEL: test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8:2251; CHECK: # %bb.0: # %entry2252; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2253; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v152254; CHECK-NEXT: ret2255entry:2256 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 3)2257 ret void2258}2259 2260define void @test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {2261; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i8:2262; CHECK: # %bb.0: # %entry2263; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2264; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t2265; CHECK-NEXT: ret2266entry:2267 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2268 ret void2269}2270 2271define void @test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {2272; CHECK-LABEL: test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16:2273; CHECK: # %bb.0: # %entry2274; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2275; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v152276; CHECK-NEXT: ret2277entry:2278 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 3)2279 ret void2280}2281 2282define void @test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {2283; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i16:2284; CHECK: # %bb.0: # %entry2285; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2286; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t2287; CHECK-NEXT: ret2288entry:2289 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2290 ret void2291}2292 2293define void @test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {2294; CHECK-LABEL: test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32:2295; CHECK: # %bb.0: # %entry2296; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2297; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v162298; CHECK-NEXT: ret2299entry:2300 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 3)2301 ret void2302}2303 2304define void @test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {2305; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i32:2306; CHECK: # %bb.0: # %entry2307; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2308; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t2309; CHECK-NEXT: ret2310entry:2311 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2312 ret void2313}2314 2315define void @test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {2316; CHECK-LABEL: test_vsuxseg7_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i64:2317; CHECK: # %bb.0: # %entry2318; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2319; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v162320; CHECK-NEXT: ret2321entry:2322 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 3)2323 ret void2324}2325 2326define void @test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {2327; CHECK-LABEL: test_vsuxseg7_mask_nxv4i8_triscv.vector.tuple_nxv4i8_7t_nxv4i64:2328; CHECK: # %bb.0: # %entry2329; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2330; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t2331; CHECK-NEXT: ret2332entry:2333 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2334 ret void2335}2336 2337define void @test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {2338; CHECK-LABEL: test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8:2339; CHECK: # %bb.0: # %entry2340; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2341; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v152342; CHECK-NEXT: ret2343entry:2344 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 3)2345 ret void2346}2347 2348define void @test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {2349; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i8:2350; CHECK: # %bb.0: # %entry2351; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2352; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t2353; CHECK-NEXT: ret2354entry:2355 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2356 ret void2357}2358 2359define void @test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {2360; CHECK-LABEL: test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16:2361; CHECK: # %bb.0: # %entry2362; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2363; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v162364; CHECK-NEXT: ret2365entry:2366 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 3)2367 ret void2368}2369 2370define void @test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {2371; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i16:2372; CHECK: # %bb.0: # %entry2373; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2374; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v16, v0.t2375; CHECK-NEXT: ret2376entry:2377 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2378 ret void2379}2380 2381define void @test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {2382; CHECK-LABEL: test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32:2383; CHECK: # %bb.0: # %entry2384; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2385; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v162386; CHECK-NEXT: ret2387entry:2388 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 3)2389 ret void2390}2391 2392define void @test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {2393; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i32:2394; CHECK: # %bb.0: # %entry2395; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2396; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t2397; CHECK-NEXT: ret2398entry:2399 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2400 ret void2401}2402 2403define void @test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {2404; CHECK-LABEL: test_vsuxseg7_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i64:2405; CHECK: # %bb.0: # %entry2406; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2407; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v162408; CHECK-NEXT: ret2409entry:2410 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 3)2411 ret void2412}2413 2414define void @test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {2415; CHECK-LABEL: test_vsuxseg7_mask_nxv8i8_triscv.vector.tuple_nxv8i8_7t_nxv8i64:2416; CHECK: # %bb.0: # %entry2417; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2418; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t2419; CHECK-NEXT: ret2420entry:2421 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2422 ret void2423}2424 2425define void @test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {2426; CHECK-LABEL: test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8:2427; CHECK: # %bb.0: # %entry2428; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2429; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v162430; CHECK-NEXT: ret2431entry:2432 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 3)2433 ret void2434}2435 2436define void @test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {2437; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8:2438; CHECK: # %bb.0: # %entry2439; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2440; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t2441; CHECK-NEXT: ret2442entry:2443 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2444 ret void2445}2446 2447define void @test_vsuxseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {2448; CHECK-LABEL: test_vsuxseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i8:2449; CHECK: # %bb.0: # %entry2450; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2451; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v162452; CHECK-NEXT: ret2453entry:2454 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 3)2455 ret void2456}2457 2458define void @test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {2459; CHECK-LABEL: test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16:2460; CHECK: # %bb.0: # %entry2461; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2462; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v162463; CHECK-NEXT: ret2464entry:2465 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 3)2466 ret void2467}2468 2469define void @test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {2470; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i16:2471; CHECK: # %bb.0: # %entry2472; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2473; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t2474; CHECK-NEXT: ret2475entry:2476 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2477 ret void2478}2479 2480define void @test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {2481; CHECK-LABEL: test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32:2482; CHECK: # %bb.0: # %entry2483; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2484; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v162485; CHECK-NEXT: ret2486entry:2487 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 3)2488 ret void2489}2490 2491define void @test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {2492; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i32:2493; CHECK: # %bb.0: # %entry2494; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2495; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t2496; CHECK-NEXT: ret2497entry:2498 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2499 ret void2500}2501 2502define void @test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {2503; CHECK-LABEL: test_vsuxseg8_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i64:2504; CHECK: # %bb.0: # %entry2505; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2506; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v162507; CHECK-NEXT: ret2508entry:2509 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv1i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 3)2510 ret void2511}2512 2513define void @test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {2514; CHECK-LABEL: test_vsuxseg8_mask_nxv1i8_triscv.vector.tuple_nxv1i8_8t_nxv1i64:2515; CHECK: # %bb.0: # %entry2516; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma2517; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t2518; CHECK-NEXT: ret2519entry:2520 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 3)2521 ret void2522}2523 2524define void @test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {2525; CHECK-LABEL: test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8:2526; CHECK: # %bb.0: # %entry2527; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2528; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v162529; CHECK-NEXT: ret2530entry:2531 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 3)2532 ret void2533}2534 2535define void @test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {2536; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i8:2537; CHECK: # %bb.0: # %entry2538; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2539; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t2540; CHECK-NEXT: ret2541entry:2542 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2543 ret void2544}2545 2546define void @test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {2547; CHECK-LABEL: test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16:2548; CHECK: # %bb.0: # %entry2549; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2550; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v162551; CHECK-NEXT: ret2552entry:2553 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 3)2554 ret void2555}2556 2557define void @test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {2558; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i16:2559; CHECK: # %bb.0: # %entry2560; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2561; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t2562; CHECK-NEXT: ret2563entry:2564 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2565 ret void2566}2567 2568define void @test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {2569; CHECK-LABEL: test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32:2570; CHECK: # %bb.0: # %entry2571; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2572; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v162573; CHECK-NEXT: ret2574entry:2575 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 3)2576 ret void2577}2578 2579define void @test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {2580; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i32:2581; CHECK: # %bb.0: # %entry2582; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2583; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t2584; CHECK-NEXT: ret2585entry:2586 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2587 ret void2588}2589 2590define void @test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {2591; CHECK-LABEL: test_vsuxseg8_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i64:2592; CHECK: # %bb.0: # %entry2593; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2594; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v162595; CHECK-NEXT: ret2596entry:2597 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 3)2598 ret void2599}2600 2601define void @test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {2602; CHECK-LABEL: test_vsuxseg8_mask_nxv2i8_triscv.vector.tuple_nxv2i8_8t_nxv2i64:2603; CHECK: # %bb.0: # %entry2604; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma2605; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t2606; CHECK-NEXT: ret2607entry:2608 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 3)2609 ret void2610}2611 2612define void @test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {2613; CHECK-LABEL: test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8:2614; CHECK: # %bb.0: # %entry2615; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2616; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v162617; CHECK-NEXT: ret2618entry:2619 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 3)2620 ret void2621}2622 2623define void @test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {2624; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i8:2625; CHECK: # %bb.0: # %entry2626; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2627; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t2628; CHECK-NEXT: ret2629entry:2630 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2631 ret void2632}2633 2634define void @test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {2635; CHECK-LABEL: test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16:2636; CHECK: # %bb.0: # %entry2637; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2638; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v162639; CHECK-NEXT: ret2640entry:2641 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 3)2642 ret void2643}2644 2645define void @test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {2646; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i16:2647; CHECK: # %bb.0: # %entry2648; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2649; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t2650; CHECK-NEXT: ret2651entry:2652 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2653 ret void2654}2655 2656define void @test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {2657; CHECK-LABEL: test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32:2658; CHECK: # %bb.0: # %entry2659; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2660; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v162661; CHECK-NEXT: ret2662entry:2663 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 3)2664 ret void2665}2666 2667define void @test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {2668; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i32:2669; CHECK: # %bb.0: # %entry2670; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2671; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t2672; CHECK-NEXT: ret2673entry:2674 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2675 ret void2676}2677 2678define void @test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {2679; CHECK-LABEL: test_vsuxseg8_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i64:2680; CHECK: # %bb.0: # %entry2681; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2682; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v162683; CHECK-NEXT: ret2684entry:2685 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 3)2686 ret void2687}2688 2689define void @test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {2690; CHECK-LABEL: test_vsuxseg8_mask_nxv4i8_triscv.vector.tuple_nxv4i8_8t_nxv4i64:2691; CHECK: # %bb.0: # %entry2692; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma2693; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t2694; CHECK-NEXT: ret2695entry:2696 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 3)2697 ret void2698}2699 2700define void @test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {2701; CHECK-LABEL: test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8:2702; CHECK: # %bb.0: # %entry2703; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2704; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v162705; CHECK-NEXT: ret2706entry:2707 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 3)2708 ret void2709}2710 2711define void @test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {2712; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i8:2713; CHECK: # %bb.0: # %entry2714; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2715; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t2716; CHECK-NEXT: ret2717entry:2718 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2719 ret void2720}2721 2722define void @test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {2723; CHECK-LABEL: test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16:2724; CHECK: # %bb.0: # %entry2725; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2726; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v162727; CHECK-NEXT: ret2728entry:2729 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 3)2730 ret void2731}2732 2733define void @test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {2734; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i16:2735; CHECK: # %bb.0: # %entry2736; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2737; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t2738; CHECK-NEXT: ret2739entry:2740 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2741 ret void2742}2743 2744define void @test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {2745; CHECK-LABEL: test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32:2746; CHECK: # %bb.0: # %entry2747; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2748; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v162749; CHECK-NEXT: ret2750entry:2751 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 3)2752 ret void2753}2754 2755define void @test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {2756; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i32:2757; CHECK: # %bb.0: # %entry2758; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2759; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t2760; CHECK-NEXT: ret2761entry:2762 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2763 ret void2764}2765 2766define void @test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {2767; CHECK-LABEL: test_vsuxseg8_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i64:2768; CHECK: # %bb.0: # %entry2769; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2770; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v162771; CHECK-NEXT: ret2772entry:2773 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 3)2774 ret void2775}2776 2777define void @test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {2778; CHECK-LABEL: test_vsuxseg8_mask_nxv8i8_triscv.vector.tuple_nxv8i8_8t_nxv8i64:2779; CHECK: # %bb.0: # %entry2780; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma2781; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t2782; CHECK-NEXT: ret2783entry:2784 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 3)2785 ret void2786}2787 2788define void @test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {2789; CHECK-LABEL: test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:2790; CHECK: # %bb.0: # %entry2791; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2792; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v102793; CHECK-NEXT: ret2794entry:2795 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)2796 ret void2797}2798 2799define void @test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {2800; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:2801; CHECK: # %bb.0: # %entry2802; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2803; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t2804; CHECK-NEXT: ret2805entry:2806 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)2807 ret void2808}2809 2810define void @test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {2811; CHECK-LABEL: test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:2812; CHECK: # %bb.0: # %entry2813; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2814; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v102815; CHECK-NEXT: ret2816entry:2817 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)2818 ret void2819}2820 2821define void @test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {2822; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:2823; CHECK: # %bb.0: # %entry2824; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2825; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t2826; CHECK-NEXT: ret2827entry:2828 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)2829 ret void2830}2831 2832define void @test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {2833; CHECK-LABEL: test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:2834; CHECK: # %bb.0: # %entry2835; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2836; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v102837; CHECK-NEXT: ret2838entry:2839 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)2840 ret void2841}2842 2843define void @test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {2844; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:2845; CHECK: # %bb.0: # %entry2846; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2847; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t2848; CHECK-NEXT: ret2849entry:2850 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)2851 ret void2852}2853 2854define void @test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {2855; CHECK-LABEL: test_vsuxseg2_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i64:2856; CHECK: # %bb.0: # %entry2857; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2858; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v102859; CHECK-NEXT: ret2860entry:2861 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)2862 ret void2863}2864 2865define void @test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {2866; CHECK-LABEL: test_vsuxseg2_mask_nxv1i16_triscv.vector.tuple_nxv2i8_2t_nxv1i64:2867; CHECK: # %bb.0: # %entry2868; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma2869; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t2870; CHECK-NEXT: ret2871entry:2872 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)2873 ret void2874}2875 2876define void @test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {2877; CHECK-LABEL: test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:2878; CHECK: # %bb.0: # %entry2879; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2880; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v102881; CHECK-NEXT: ret2882entry:2883 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)2884 ret void2885}2886 2887define void @test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {2888; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:2889; CHECK: # %bb.0: # %entry2890; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2891; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t2892; CHECK-NEXT: ret2893entry:2894 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)2895 ret void2896}2897 2898define void @test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {2899; CHECK-LABEL: test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:2900; CHECK: # %bb.0: # %entry2901; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2902; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v102903; CHECK-NEXT: ret2904entry:2905 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)2906 ret void2907}2908 2909define void @test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {2910; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:2911; CHECK: # %bb.0: # %entry2912; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2913; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t2914; CHECK-NEXT: ret2915entry:2916 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)2917 ret void2918}2919 2920define void @test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {2921; CHECK-LABEL: test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:2922; CHECK: # %bb.0: # %entry2923; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2924; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v102925; CHECK-NEXT: ret2926entry:2927 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)2928 ret void2929}2930 2931define void @test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {2932; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:2933; CHECK: # %bb.0: # %entry2934; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2935; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t2936; CHECK-NEXT: ret2937entry:2938 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)2939 ret void2940}2941 2942define void @test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {2943; CHECK-LABEL: test_vsuxseg2_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i64:2944; CHECK: # %bb.0: # %entry2945; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2946; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v102947; CHECK-NEXT: ret2948entry:2949 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)2950 ret void2951}2952 2953define void @test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {2954; CHECK-LABEL: test_vsuxseg2_mask_nxv2i16_triscv.vector.tuple_nxv4i8_2t_nxv2i64:2955; CHECK: # %bb.0: # %entry2956; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma2957; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t2958; CHECK-NEXT: ret2959entry:2960 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)2961 ret void2962}2963 2964define void @test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {2965; CHECK-LABEL: test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:2966; CHECK: # %bb.0: # %entry2967; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma2968; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v102969; CHECK-NEXT: ret2970entry:2971 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)2972 ret void2973}2974 2975define void @test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {2976; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:2977; CHECK: # %bb.0: # %entry2978; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma2979; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t2980; CHECK-NEXT: ret2981entry:2982 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)2983 ret void2984}2985 2986define void @test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {2987; CHECK-LABEL: test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:2988; CHECK: # %bb.0: # %entry2989; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma2990; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v102991; CHECK-NEXT: ret2992entry:2993 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)2994 ret void2995}2996 2997define void @test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {2998; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:2999; CHECK: # %bb.0: # %entry3000; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3001; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t3002; CHECK-NEXT: ret3003entry:3004 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3005 ret void3006}3007 3008define void @test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {3009; CHECK-LABEL: test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:3010; CHECK: # %bb.0: # %entry3011; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3012; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v103013; CHECK-NEXT: ret3014entry:3015 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)3016 ret void3017}3018 3019define void @test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {3020; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:3021; CHECK: # %bb.0: # %entry3022; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3023; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t3024; CHECK-NEXT: ret3025entry:3026 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3027 ret void3028}3029 3030define void @test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {3031; CHECK-LABEL: test_vsuxseg2_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i64:3032; CHECK: # %bb.0: # %entry3033; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3034; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v123035; CHECK-NEXT: ret3036entry:3037 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)3038 ret void3039}3040 3041define void @test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {3042; CHECK-LABEL: test_vsuxseg2_mask_nxv4i16_triscv.vector.tuple_nxv8i8_2t_nxv4i64:3043; CHECK: # %bb.0: # %entry3044; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3045; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t3046; CHECK-NEXT: ret3047entry:3048 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3049 ret void3050}3051 3052define void @test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {3053; CHECK-LABEL: test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:3054; CHECK: # %bb.0: # %entry3055; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3056; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v123057; CHECK-NEXT: ret3058entry:3059 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)3060 ret void3061}3062 3063define void @test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {3064; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:3065; CHECK: # %bb.0: # %entry3066; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3067; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t3068; CHECK-NEXT: ret3069entry:3070 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3071 ret void3072}3073 3074define void @test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {3075; CHECK-LABEL: test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:3076; CHECK: # %bb.0: # %entry3077; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3078; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v123079; CHECK-NEXT: ret3080entry:3081 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)3082 ret void3083}3084 3085define void @test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {3086; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:3087; CHECK: # %bb.0: # %entry3088; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3089; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t3090; CHECK-NEXT: ret3091entry:3092 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3093 ret void3094}3095 3096define void @test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {3097; CHECK-LABEL: test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:3098; CHECK: # %bb.0: # %entry3099; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3100; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v123101; CHECK-NEXT: ret3102entry:3103 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)3104 ret void3105}3106 3107define void @test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {3108; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:3109; CHECK: # %bb.0: # %entry3110; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3111; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t3112; CHECK-NEXT: ret3113entry:3114 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3115 ret void3116}3117 3118define void @test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {3119; CHECK-LABEL: test_vsuxseg2_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i64:3120; CHECK: # %bb.0: # %entry3121; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3122; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v163123; CHECK-NEXT: ret3124entry:3125 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)3126 ret void3127}3128 3129define void @test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {3130; CHECK-LABEL: test_vsuxseg2_mask_nxv8i16_triscv.vector.tuple_nxv16i8_2t_nxv8i64:3131; CHECK: # %bb.0: # %entry3132; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3133; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t3134; CHECK-NEXT: ret3135entry:3136 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3137 ret void3138}3139 3140define void @test_vsuxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {3141; CHECK-LABEL: test_vsuxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:3142; CHECK: # %bb.0: # %entry3143; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3144; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v163145; CHECK-NEXT: ret3146entry:3147 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, i64 4)3148 ret void3149}3150 3151define void @test_vsuxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {3152; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:3153; CHECK: # %bb.0: # %entry3154; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3155; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t3156; CHECK-NEXT: ret3157entry:3158 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)3159 ret void3160}3161 3162define void @test_vsuxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {3163; CHECK-LABEL: test_vsuxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:3164; CHECK: # %bb.0: # %entry3165; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3166; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v163167; CHECK-NEXT: ret3168entry:3169 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, i64 4)3170 ret void3171}3172 3173define void @test_vsuxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {3174; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:3175; CHECK: # %bb.0: # %entry3176; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3177; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t3178; CHECK-NEXT: ret3179entry:3180 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)3181 ret void3182}3183 3184define void @test_vsuxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {3185; CHECK-LABEL: test_vsuxseg2_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:3186; CHECK: # %bb.0: # %entry3187; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3188; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v163189; CHECK-NEXT: ret3190entry:3191 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, i64 4)3192 ret void3193}3194 3195define void @test_vsuxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {3196; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:3197; CHECK: # %bb.0: # %entry3198; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma3199; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t3200; CHECK-NEXT: ret3201entry:3202 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)3203 ret void3204}3205 3206define void @test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {3207; CHECK-LABEL: test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:3208; CHECK: # %bb.0: # %entry3209; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3210; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v113211; CHECK-NEXT: ret3212entry:3213 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)3214 ret void3215}3216 3217define void @test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {3218; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:3219; CHECK: # %bb.0: # %entry3220; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3221; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t3222; CHECK-NEXT: ret3223entry:3224 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3225 ret void3226}3227 3228define void @test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {3229; CHECK-LABEL: test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:3230; CHECK: # %bb.0: # %entry3231; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3232; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v113233; CHECK-NEXT: ret3234entry:3235 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)3236 ret void3237}3238 3239define void @test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {3240; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:3241; CHECK: # %bb.0: # %entry3242; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3243; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t3244; CHECK-NEXT: ret3245entry:3246 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3247 ret void3248}3249 3250define void @test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {3251; CHECK-LABEL: test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:3252; CHECK: # %bb.0: # %entry3253; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3254; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v113255; CHECK-NEXT: ret3256entry:3257 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)3258 ret void3259}3260 3261define void @test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {3262; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:3263; CHECK: # %bb.0: # %entry3264; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3265; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t3266; CHECK-NEXT: ret3267entry:3268 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3269 ret void3270}3271 3272define void @test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {3273; CHECK-LABEL: test_vsuxseg3_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i64:3274; CHECK: # %bb.0: # %entry3275; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3276; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v113277; CHECK-NEXT: ret3278entry:3279 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)3280 ret void3281}3282 3283define void @test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {3284; CHECK-LABEL: test_vsuxseg3_mask_nxv1i16_triscv.vector.tuple_nxv2i8_3t_nxv1i64:3285; CHECK: # %bb.0: # %entry3286; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3287; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t3288; CHECK-NEXT: ret3289entry:3290 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3291 ret void3292}3293 3294define void @test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {3295; CHECK-LABEL: test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:3296; CHECK: # %bb.0: # %entry3297; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3298; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v113299; CHECK-NEXT: ret3300entry:3301 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)3302 ret void3303}3304 3305define void @test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {3306; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:3307; CHECK: # %bb.0: # %entry3308; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3309; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t3310; CHECK-NEXT: ret3311entry:3312 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3313 ret void3314}3315 3316define void @test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {3317; CHECK-LABEL: test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:3318; CHECK: # %bb.0: # %entry3319; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3320; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v113321; CHECK-NEXT: ret3322entry:3323 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)3324 ret void3325}3326 3327define void @test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {3328; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:3329; CHECK: # %bb.0: # %entry3330; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3331; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t3332; CHECK-NEXT: ret3333entry:3334 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3335 ret void3336}3337 3338define void @test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {3339; CHECK-LABEL: test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:3340; CHECK: # %bb.0: # %entry3341; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3342; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v113343; CHECK-NEXT: ret3344entry:3345 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)3346 ret void3347}3348 3349define void @test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {3350; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:3351; CHECK: # %bb.0: # %entry3352; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3353; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t3354; CHECK-NEXT: ret3355entry:3356 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3357 ret void3358}3359 3360define void @test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {3361; CHECK-LABEL: test_vsuxseg3_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i64:3362; CHECK: # %bb.0: # %entry3363; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3364; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v123365; CHECK-NEXT: ret3366entry:3367 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)3368 ret void3369}3370 3371define void @test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {3372; CHECK-LABEL: test_vsuxseg3_mask_nxv2i16_triscv.vector.tuple_nxv4i8_3t_nxv2i64:3373; CHECK: # %bb.0: # %entry3374; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3375; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t3376; CHECK-NEXT: ret3377entry:3378 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3379 ret void3380}3381 3382define void @test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {3383; CHECK-LABEL: test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:3384; CHECK: # %bb.0: # %entry3385; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3386; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v113387; CHECK-NEXT: ret3388entry:3389 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)3390 ret void3391}3392 3393define void @test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {3394; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:3395; CHECK: # %bb.0: # %entry3396; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3397; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t3398; CHECK-NEXT: ret3399entry:3400 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3401 ret void3402}3403 3404define void @test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {3405; CHECK-LABEL: test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:3406; CHECK: # %bb.0: # %entry3407; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3408; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v113409; CHECK-NEXT: ret3410entry:3411 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)3412 ret void3413}3414 3415define void @test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {3416; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:3417; CHECK: # %bb.0: # %entry3418; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3419; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t3420; CHECK-NEXT: ret3421entry:3422 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3423 ret void3424}3425 3426define void @test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {3427; CHECK-LABEL: test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:3428; CHECK: # %bb.0: # %entry3429; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3430; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v123431; CHECK-NEXT: ret3432entry:3433 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)3434 ret void3435}3436 3437define void @test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {3438; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:3439; CHECK: # %bb.0: # %entry3440; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3441; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t3442; CHECK-NEXT: ret3443entry:3444 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3445 ret void3446}3447 3448define void @test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {3449; CHECK-LABEL: test_vsuxseg3_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i64:3450; CHECK: # %bb.0: # %entry3451; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3452; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v123453; CHECK-NEXT: ret3454entry:3455 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)3456 ret void3457}3458 3459define void @test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {3460; CHECK-LABEL: test_vsuxseg3_mask_nxv4i16_triscv.vector.tuple_nxv8i8_3t_nxv4i64:3461; CHECK: # %bb.0: # %entry3462; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3463; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t3464; CHECK-NEXT: ret3465entry:3466 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3467 ret void3468}3469 3470define void @test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {3471; CHECK-LABEL: test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:3472; CHECK: # %bb.0: # %entry3473; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3474; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v143475; CHECK-NEXT: ret3476entry:3477 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)3478 ret void3479}3480 3481define void @test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {3482; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:3483; CHECK: # %bb.0: # %entry3484; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3485; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t3486; CHECK-NEXT: ret3487entry:3488 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3489 ret void3490}3491 3492define void @test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {3493; CHECK-LABEL: test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:3494; CHECK: # %bb.0: # %entry3495; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3496; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v143497; CHECK-NEXT: ret3498entry:3499 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)3500 ret void3501}3502 3503define void @test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {3504; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:3505; CHECK: # %bb.0: # %entry3506; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3507; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v14, v0.t3508; CHECK-NEXT: ret3509entry:3510 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3511 ret void3512}3513 3514define void @test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {3515; CHECK-LABEL: test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:3516; CHECK: # %bb.0: # %entry3517; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3518; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v163519; CHECK-NEXT: ret3520entry:3521 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)3522 ret void3523}3524 3525define void @test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {3526; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:3527; CHECK: # %bb.0: # %entry3528; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3529; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t3530; CHECK-NEXT: ret3531entry:3532 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3533 ret void3534}3535 3536define void @test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {3537; CHECK-LABEL: test_vsuxseg3_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i64:3538; CHECK: # %bb.0: # %entry3539; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3540; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v163541; CHECK-NEXT: ret3542entry:3543 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)3544 ret void3545}3546 3547define void @test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {3548; CHECK-LABEL: test_vsuxseg3_mask_nxv8i16_triscv.vector.tuple_nxv16i8_3t_nxv8i64:3549; CHECK: # %bb.0: # %entry3550; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3551; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v16, v0.t3552; CHECK-NEXT: ret3553entry:3554 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3555 ret void3556}3557 3558define void @test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {3559; CHECK-LABEL: test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:3560; CHECK: # %bb.0: # %entry3561; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3562; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v123563; CHECK-NEXT: ret3564entry:3565 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)3566 ret void3567}3568 3569define void @test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {3570; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:3571; CHECK: # %bb.0: # %entry3572; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3573; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t3574; CHECK-NEXT: ret3575entry:3576 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3577 ret void3578}3579 3580define void @test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {3581; CHECK-LABEL: test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:3582; CHECK: # %bb.0: # %entry3583; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3584; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v123585; CHECK-NEXT: ret3586entry:3587 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)3588 ret void3589}3590 3591define void @test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {3592; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:3593; CHECK: # %bb.0: # %entry3594; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3595; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t3596; CHECK-NEXT: ret3597entry:3598 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3599 ret void3600}3601 3602define void @test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {3603; CHECK-LABEL: test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:3604; CHECK: # %bb.0: # %entry3605; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3606; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v123607; CHECK-NEXT: ret3608entry:3609 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)3610 ret void3611}3612 3613define void @test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {3614; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:3615; CHECK: # %bb.0: # %entry3616; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3617; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t3618; CHECK-NEXT: ret3619entry:3620 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3621 ret void3622}3623 3624define void @test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {3625; CHECK-LABEL: test_vsuxseg4_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i64:3626; CHECK: # %bb.0: # %entry3627; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3628; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v123629; CHECK-NEXT: ret3630entry:3631 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)3632 ret void3633}3634 3635define void @test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {3636; CHECK-LABEL: test_vsuxseg4_mask_nxv1i16_triscv.vector.tuple_nxv2i8_4t_nxv1i64:3637; CHECK: # %bb.0: # %entry3638; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3639; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t3640; CHECK-NEXT: ret3641entry:3642 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3643 ret void3644}3645 3646define void @test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {3647; CHECK-LABEL: test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:3648; CHECK: # %bb.0: # %entry3649; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3650; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v123651; CHECK-NEXT: ret3652entry:3653 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)3654 ret void3655}3656 3657define void @test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {3658; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:3659; CHECK: # %bb.0: # %entry3660; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3661; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t3662; CHECK-NEXT: ret3663entry:3664 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3665 ret void3666}3667 3668define void @test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {3669; CHECK-LABEL: test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:3670; CHECK: # %bb.0: # %entry3671; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3672; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v123673; CHECK-NEXT: ret3674entry:3675 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)3676 ret void3677}3678 3679define void @test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {3680; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:3681; CHECK: # %bb.0: # %entry3682; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3683; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t3684; CHECK-NEXT: ret3685entry:3686 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3687 ret void3688}3689 3690define void @test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {3691; CHECK-LABEL: test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:3692; CHECK: # %bb.0: # %entry3693; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3694; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v123695; CHECK-NEXT: ret3696entry:3697 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)3698 ret void3699}3700 3701define void @test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {3702; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:3703; CHECK: # %bb.0: # %entry3704; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3705; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t3706; CHECK-NEXT: ret3707entry:3708 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3709 ret void3710}3711 3712define void @test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {3713; CHECK-LABEL: test_vsuxseg4_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i64:3714; CHECK: # %bb.0: # %entry3715; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3716; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v123717; CHECK-NEXT: ret3718entry:3719 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)3720 ret void3721}3722 3723define void @test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {3724; CHECK-LABEL: test_vsuxseg4_mask_nxv2i16_triscv.vector.tuple_nxv4i8_4t_nxv2i64:3725; CHECK: # %bb.0: # %entry3726; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma3727; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t3728; CHECK-NEXT: ret3729entry:3730 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)3731 ret void3732}3733 3734define void @test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {3735; CHECK-LABEL: test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:3736; CHECK: # %bb.0: # %entry3737; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3738; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v123739; CHECK-NEXT: ret3740entry:3741 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)3742 ret void3743}3744 3745define void @test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {3746; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:3747; CHECK: # %bb.0: # %entry3748; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3749; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t3750; CHECK-NEXT: ret3751entry:3752 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3753 ret void3754}3755 3756define void @test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {3757; CHECK-LABEL: test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:3758; CHECK: # %bb.0: # %entry3759; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3760; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v123761; CHECK-NEXT: ret3762entry:3763 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)3764 ret void3765}3766 3767define void @test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {3768; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:3769; CHECK: # %bb.0: # %entry3770; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3771; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t3772; CHECK-NEXT: ret3773entry:3774 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3775 ret void3776}3777 3778define void @test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {3779; CHECK-LABEL: test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:3780; CHECK: # %bb.0: # %entry3781; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3782; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v123783; CHECK-NEXT: ret3784entry:3785 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)3786 ret void3787}3788 3789define void @test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {3790; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:3791; CHECK: # %bb.0: # %entry3792; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3793; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t3794; CHECK-NEXT: ret3795entry:3796 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3797 ret void3798}3799 3800define void @test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {3801; CHECK-LABEL: test_vsuxseg4_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i64:3802; CHECK: # %bb.0: # %entry3803; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3804; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v123805; CHECK-NEXT: ret3806entry:3807 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)3808 ret void3809}3810 3811define void @test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {3812; CHECK-LABEL: test_vsuxseg4_mask_nxv4i16_triscv.vector.tuple_nxv8i8_4t_nxv4i64:3813; CHECK: # %bb.0: # %entry3814; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma3815; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t3816; CHECK-NEXT: ret3817entry:3818 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)3819 ret void3820}3821 3822define void @test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {3823; CHECK-LABEL: test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:3824; CHECK: # %bb.0: # %entry3825; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3826; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v163827; CHECK-NEXT: ret3828entry:3829 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)3830 ret void3831}3832 3833define void @test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {3834; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:3835; CHECK: # %bb.0: # %entry3836; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3837; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t3838; CHECK-NEXT: ret3839entry:3840 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3841 ret void3842}3843 3844define void @test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {3845; CHECK-LABEL: test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:3846; CHECK: # %bb.0: # %entry3847; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3848; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v163849; CHECK-NEXT: ret3850entry:3851 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)3852 ret void3853}3854 3855define void @test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {3856; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:3857; CHECK: # %bb.0: # %entry3858; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3859; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t3860; CHECK-NEXT: ret3861entry:3862 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3863 ret void3864}3865 3866define void @test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {3867; CHECK-LABEL: test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:3868; CHECK: # %bb.0: # %entry3869; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3870; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v163871; CHECK-NEXT: ret3872entry:3873 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)3874 ret void3875}3876 3877define void @test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {3878; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:3879; CHECK: # %bb.0: # %entry3880; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3881; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t3882; CHECK-NEXT: ret3883entry:3884 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3885 ret void3886}3887 3888define void @test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {3889; CHECK-LABEL: test_vsuxseg4_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i64:3890; CHECK: # %bb.0: # %entry3891; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3892; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v163893; CHECK-NEXT: ret3894entry:3895 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)3896 ret void3897}3898 3899define void @test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {3900; CHECK-LABEL: test_vsuxseg4_mask_nxv8i16_triscv.vector.tuple_nxv16i8_4t_nxv8i64:3901; CHECK: # %bb.0: # %entry3902; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma3903; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t3904; CHECK-NEXT: ret3905entry:3906 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)3907 ret void3908}3909 3910define void @test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {3911; CHECK-LABEL: test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:3912; CHECK: # %bb.0: # %entry3913; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3914; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v133915; CHECK-NEXT: ret3916entry:3917 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)3918 ret void3919}3920 3921define void @test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {3922; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:3923; CHECK: # %bb.0: # %entry3924; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3925; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t3926; CHECK-NEXT: ret3927entry:3928 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3929 ret void3930}3931 3932define void @test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {3933; CHECK-LABEL: test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:3934; CHECK: # %bb.0: # %entry3935; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3936; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v133937; CHECK-NEXT: ret3938entry:3939 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)3940 ret void3941}3942 3943define void @test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {3944; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:3945; CHECK: # %bb.0: # %entry3946; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3947; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t3948; CHECK-NEXT: ret3949entry:3950 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3951 ret void3952}3953 3954define void @test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {3955; CHECK-LABEL: test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:3956; CHECK: # %bb.0: # %entry3957; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3958; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v133959; CHECK-NEXT: ret3960entry:3961 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)3962 ret void3963}3964 3965define void @test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {3966; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:3967; CHECK: # %bb.0: # %entry3968; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3969; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t3970; CHECK-NEXT: ret3971entry:3972 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3973 ret void3974}3975 3976define void @test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {3977; CHECK-LABEL: test_vsuxseg5_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i64:3978; CHECK: # %bb.0: # %entry3979; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3980; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v133981; CHECK-NEXT: ret3982entry:3983 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)3984 ret void3985}3986 3987define void @test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {3988; CHECK-LABEL: test_vsuxseg5_mask_nxv1i16_triscv.vector.tuple_nxv2i8_5t_nxv1i64:3989; CHECK: # %bb.0: # %entry3990; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma3991; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t3992; CHECK-NEXT: ret3993entry:3994 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)3995 ret void3996}3997 3998define void @test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {3999; CHECK-LABEL: test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:4000; CHECK: # %bb.0: # %entry4001; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4002; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v134003; CHECK-NEXT: ret4004entry:4005 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)4006 ret void4007}4008 4009define void @test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {4010; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:4011; CHECK: # %bb.0: # %entry4012; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4013; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t4014; CHECK-NEXT: ret4015entry:4016 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4017 ret void4018}4019 4020define void @test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {4021; CHECK-LABEL: test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:4022; CHECK: # %bb.0: # %entry4023; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4024; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v134025; CHECK-NEXT: ret4026entry:4027 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)4028 ret void4029}4030 4031define void @test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {4032; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:4033; CHECK: # %bb.0: # %entry4034; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4035; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t4036; CHECK-NEXT: ret4037entry:4038 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4039 ret void4040}4041 4042define void @test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {4043; CHECK-LABEL: test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:4044; CHECK: # %bb.0: # %entry4045; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4046; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v134047; CHECK-NEXT: ret4048entry:4049 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)4050 ret void4051}4052 4053define void @test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {4054; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:4055; CHECK: # %bb.0: # %entry4056; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4057; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t4058; CHECK-NEXT: ret4059entry:4060 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4061 ret void4062}4063 4064define void @test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {4065; CHECK-LABEL: test_vsuxseg5_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i64:4066; CHECK: # %bb.0: # %entry4067; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4068; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v144069; CHECK-NEXT: ret4070entry:4071 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)4072 ret void4073}4074 4075define void @test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {4076; CHECK-LABEL: test_vsuxseg5_mask_nxv2i16_triscv.vector.tuple_nxv4i8_5t_nxv2i64:4077; CHECK: # %bb.0: # %entry4078; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4079; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v14, v0.t4080; CHECK-NEXT: ret4081entry:4082 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4083 ret void4084}4085 4086define void @test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {4087; CHECK-LABEL: test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:4088; CHECK: # %bb.0: # %entry4089; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4090; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v134091; CHECK-NEXT: ret4092entry:4093 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)4094 ret void4095}4096 4097define void @test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {4098; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:4099; CHECK: # %bb.0: # %entry4100; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4101; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t4102; CHECK-NEXT: ret4103entry:4104 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4105 ret void4106}4107 4108define void @test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {4109; CHECK-LABEL: test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:4110; CHECK: # %bb.0: # %entry4111; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4112; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v134113; CHECK-NEXT: ret4114entry:4115 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)4116 ret void4117}4118 4119define void @test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {4120; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:4121; CHECK: # %bb.0: # %entry4122; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4123; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t4124; CHECK-NEXT: ret4125entry:4126 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4127 ret void4128}4129 4130define void @test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {4131; CHECK-LABEL: test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:4132; CHECK: # %bb.0: # %entry4133; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4134; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v144135; CHECK-NEXT: ret4136entry:4137 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)4138 ret void4139}4140 4141define void @test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {4142; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:4143; CHECK: # %bb.0: # %entry4144; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4145; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v14, v0.t4146; CHECK-NEXT: ret4147entry:4148 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4149 ret void4150}4151 4152define void @test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {4153; CHECK-LABEL: test_vsuxseg5_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i64:4154; CHECK: # %bb.0: # %entry4155; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4156; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v164157; CHECK-NEXT: ret4158entry:4159 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)4160 ret void4161}4162 4163define void @test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {4164; CHECK-LABEL: test_vsuxseg5_mask_nxv4i16_triscv.vector.tuple_nxv8i8_5t_nxv4i64:4165; CHECK: # %bb.0: # %entry4166; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4167; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v16, v0.t4168; CHECK-NEXT: ret4169entry:4170 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4171 ret void4172}4173 4174define void @test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {4175; CHECK-LABEL: test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:4176; CHECK: # %bb.0: # %entry4177; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4178; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v144179; CHECK-NEXT: ret4180entry:4181 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)4182 ret void4183}4184 4185define void @test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {4186; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:4187; CHECK: # %bb.0: # %entry4188; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4189; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t4190; CHECK-NEXT: ret4191entry:4192 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4193 ret void4194}4195 4196define void @test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {4197; CHECK-LABEL: test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:4198; CHECK: # %bb.0: # %entry4199; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4200; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v144201; CHECK-NEXT: ret4202entry:4203 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)4204 ret void4205}4206 4207define void @test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {4208; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:4209; CHECK: # %bb.0: # %entry4210; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4211; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t4212; CHECK-NEXT: ret4213entry:4214 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4215 ret void4216}4217 4218define void @test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {4219; CHECK-LABEL: test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:4220; CHECK: # %bb.0: # %entry4221; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4222; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v144223; CHECK-NEXT: ret4224entry:4225 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)4226 ret void4227}4228 4229define void @test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {4230; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:4231; CHECK: # %bb.0: # %entry4232; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4233; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t4234; CHECK-NEXT: ret4235entry:4236 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4237 ret void4238}4239 4240define void @test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {4241; CHECK-LABEL: test_vsuxseg6_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i64:4242; CHECK: # %bb.0: # %entry4243; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4244; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v144245; CHECK-NEXT: ret4246entry:4247 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)4248 ret void4249}4250 4251define void @test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {4252; CHECK-LABEL: test_vsuxseg6_mask_nxv1i16_triscv.vector.tuple_nxv2i8_6t_nxv1i64:4253; CHECK: # %bb.0: # %entry4254; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4255; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t4256; CHECK-NEXT: ret4257entry:4258 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4259 ret void4260}4261 4262define void @test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {4263; CHECK-LABEL: test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:4264; CHECK: # %bb.0: # %entry4265; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4266; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v144267; CHECK-NEXT: ret4268entry:4269 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)4270 ret void4271}4272 4273define void @test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {4274; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:4275; CHECK: # %bb.0: # %entry4276; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4277; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t4278; CHECK-NEXT: ret4279entry:4280 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4281 ret void4282}4283 4284define void @test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {4285; CHECK-LABEL: test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:4286; CHECK: # %bb.0: # %entry4287; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4288; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v144289; CHECK-NEXT: ret4290entry:4291 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)4292 ret void4293}4294 4295define void @test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {4296; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:4297; CHECK: # %bb.0: # %entry4298; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4299; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t4300; CHECK-NEXT: ret4301entry:4302 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4303 ret void4304}4305 4306define void @test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {4307; CHECK-LABEL: test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:4308; CHECK: # %bb.0: # %entry4309; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4310; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v144311; CHECK-NEXT: ret4312entry:4313 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)4314 ret void4315}4316 4317define void @test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {4318; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:4319; CHECK: # %bb.0: # %entry4320; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4321; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t4322; CHECK-NEXT: ret4323entry:4324 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4325 ret void4326}4327 4328define void @test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {4329; CHECK-LABEL: test_vsuxseg6_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i64:4330; CHECK: # %bb.0: # %entry4331; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4332; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v144333; CHECK-NEXT: ret4334entry:4335 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)4336 ret void4337}4338 4339define void @test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {4340; CHECK-LABEL: test_vsuxseg6_mask_nxv2i16_triscv.vector.tuple_nxv4i8_6t_nxv2i64:4341; CHECK: # %bb.0: # %entry4342; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4343; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t4344; CHECK-NEXT: ret4345entry:4346 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4347 ret void4348}4349 4350define void @test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {4351; CHECK-LABEL: test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:4352; CHECK: # %bb.0: # %entry4353; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4354; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v144355; CHECK-NEXT: ret4356entry:4357 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)4358 ret void4359}4360 4361define void @test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {4362; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:4363; CHECK: # %bb.0: # %entry4364; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4365; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t4366; CHECK-NEXT: ret4367entry:4368 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4369 ret void4370}4371 4372define void @test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {4373; CHECK-LABEL: test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:4374; CHECK: # %bb.0: # %entry4375; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4376; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v144377; CHECK-NEXT: ret4378entry:4379 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)4380 ret void4381}4382 4383define void @test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {4384; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:4385; CHECK: # %bb.0: # %entry4386; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4387; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t4388; CHECK-NEXT: ret4389entry:4390 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4391 ret void4392}4393 4394define void @test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {4395; CHECK-LABEL: test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:4396; CHECK: # %bb.0: # %entry4397; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4398; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v144399; CHECK-NEXT: ret4400entry:4401 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)4402 ret void4403}4404 4405define void @test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {4406; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:4407; CHECK: # %bb.0: # %entry4408; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4409; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t4410; CHECK-NEXT: ret4411entry:4412 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4413 ret void4414}4415 4416define void @test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {4417; CHECK-LABEL: test_vsuxseg6_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i64:4418; CHECK: # %bb.0: # %entry4419; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4420; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v164421; CHECK-NEXT: ret4422entry:4423 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)4424 ret void4425}4426 4427define void @test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {4428; CHECK-LABEL: test_vsuxseg6_mask_nxv4i16_triscv.vector.tuple_nxv8i8_6t_nxv4i64:4429; CHECK: # %bb.0: # %entry4430; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4431; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v16, v0.t4432; CHECK-NEXT: ret4433entry:4434 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4435 ret void4436}4437 4438define void @test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {4439; CHECK-LABEL: test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:4440; CHECK: # %bb.0: # %entry4441; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4442; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v154443; CHECK-NEXT: ret4444entry:4445 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)4446 ret void4447}4448 4449define void @test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {4450; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:4451; CHECK: # %bb.0: # %entry4452; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4453; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t4454; CHECK-NEXT: ret4455entry:4456 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4457 ret void4458}4459 4460define void @test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {4461; CHECK-LABEL: test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:4462; CHECK: # %bb.0: # %entry4463; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4464; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v154465; CHECK-NEXT: ret4466entry:4467 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)4468 ret void4469}4470 4471define void @test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {4472; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:4473; CHECK: # %bb.0: # %entry4474; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4475; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t4476; CHECK-NEXT: ret4477entry:4478 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4479 ret void4480}4481 4482define void @test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {4483; CHECK-LABEL: test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:4484; CHECK: # %bb.0: # %entry4485; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4486; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v154487; CHECK-NEXT: ret4488entry:4489 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)4490 ret void4491}4492 4493define void @test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {4494; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:4495; CHECK: # %bb.0: # %entry4496; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4497; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t4498; CHECK-NEXT: ret4499entry:4500 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4501 ret void4502}4503 4504define void @test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {4505; CHECK-LABEL: test_vsuxseg7_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i64:4506; CHECK: # %bb.0: # %entry4507; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4508; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v154509; CHECK-NEXT: ret4510entry:4511 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)4512 ret void4513}4514 4515define void @test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {4516; CHECK-LABEL: test_vsuxseg7_mask_nxv1i16_triscv.vector.tuple_nxv2i8_7t_nxv1i64:4517; CHECK: # %bb.0: # %entry4518; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4519; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t4520; CHECK-NEXT: ret4521entry:4522 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4523 ret void4524}4525 4526define void @test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {4527; CHECK-LABEL: test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:4528; CHECK: # %bb.0: # %entry4529; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4530; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v154531; CHECK-NEXT: ret4532entry:4533 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)4534 ret void4535}4536 4537define void @test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {4538; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:4539; CHECK: # %bb.0: # %entry4540; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4541; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t4542; CHECK-NEXT: ret4543entry:4544 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4545 ret void4546}4547 4548define void @test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {4549; CHECK-LABEL: test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:4550; CHECK: # %bb.0: # %entry4551; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4552; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v154553; CHECK-NEXT: ret4554entry:4555 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)4556 ret void4557}4558 4559define void @test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {4560; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:4561; CHECK: # %bb.0: # %entry4562; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4563; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t4564; CHECK-NEXT: ret4565entry:4566 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4567 ret void4568}4569 4570define void @test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {4571; CHECK-LABEL: test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:4572; CHECK: # %bb.0: # %entry4573; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4574; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v154575; CHECK-NEXT: ret4576entry:4577 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)4578 ret void4579}4580 4581define void @test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {4582; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:4583; CHECK: # %bb.0: # %entry4584; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4585; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t4586; CHECK-NEXT: ret4587entry:4588 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4589 ret void4590}4591 4592define void @test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {4593; CHECK-LABEL: test_vsuxseg7_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i64:4594; CHECK: # %bb.0: # %entry4595; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4596; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v164597; CHECK-NEXT: ret4598entry:4599 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)4600 ret void4601}4602 4603define void @test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {4604; CHECK-LABEL: test_vsuxseg7_mask_nxv2i16_triscv.vector.tuple_nxv4i8_7t_nxv2i64:4605; CHECK: # %bb.0: # %entry4606; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4607; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t4608; CHECK-NEXT: ret4609entry:4610 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4611 ret void4612}4613 4614define void @test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {4615; CHECK-LABEL: test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:4616; CHECK: # %bb.0: # %entry4617; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4618; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v154619; CHECK-NEXT: ret4620entry:4621 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)4622 ret void4623}4624 4625define void @test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {4626; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:4627; CHECK: # %bb.0: # %entry4628; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4629; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t4630; CHECK-NEXT: ret4631entry:4632 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4633 ret void4634}4635 4636define void @test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {4637; CHECK-LABEL: test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:4638; CHECK: # %bb.0: # %entry4639; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4640; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v154641; CHECK-NEXT: ret4642entry:4643 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)4644 ret void4645}4646 4647define void @test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {4648; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:4649; CHECK: # %bb.0: # %entry4650; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4651; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t4652; CHECK-NEXT: ret4653entry:4654 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4655 ret void4656}4657 4658define void @test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {4659; CHECK-LABEL: test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:4660; CHECK: # %bb.0: # %entry4661; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4662; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v164663; CHECK-NEXT: ret4664entry:4665 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)4666 ret void4667}4668 4669define void @test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {4670; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:4671; CHECK: # %bb.0: # %entry4672; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4673; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t4674; CHECK-NEXT: ret4675entry:4676 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4677 ret void4678}4679 4680define void @test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {4681; CHECK-LABEL: test_vsuxseg7_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i64:4682; CHECK: # %bb.0: # %entry4683; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4684; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v164685; CHECK-NEXT: ret4686entry:4687 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)4688 ret void4689}4690 4691define void @test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {4692; CHECK-LABEL: test_vsuxseg7_mask_nxv4i16_triscv.vector.tuple_nxv8i8_7t_nxv4i64:4693; CHECK: # %bb.0: # %entry4694; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4695; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t4696; CHECK-NEXT: ret4697entry:4698 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4699 ret void4700}4701 4702define void @test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {4703; CHECK-LABEL: test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:4704; CHECK: # %bb.0: # %entry4705; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4706; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v164707; CHECK-NEXT: ret4708entry:4709 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)4710 ret void4711}4712 4713define void @test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {4714; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:4715; CHECK: # %bb.0: # %entry4716; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4717; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t4718; CHECK-NEXT: ret4719entry:4720 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4721 ret void4722}4723 4724define void @test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {4725; CHECK-LABEL: test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:4726; CHECK: # %bb.0: # %entry4727; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4728; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v164729; CHECK-NEXT: ret4730entry:4731 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)4732 ret void4733}4734 4735define void @test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {4736; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:4737; CHECK: # %bb.0: # %entry4738; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4739; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t4740; CHECK-NEXT: ret4741entry:4742 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4743 ret void4744}4745 4746define void @test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {4747; CHECK-LABEL: test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:4748; CHECK: # %bb.0: # %entry4749; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4750; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v164751; CHECK-NEXT: ret4752entry:4753 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)4754 ret void4755}4756 4757define void @test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {4758; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:4759; CHECK: # %bb.0: # %entry4760; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4761; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t4762; CHECK-NEXT: ret4763entry:4764 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4765 ret void4766}4767 4768define void @test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {4769; CHECK-LABEL: test_vsuxseg8_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i64:4770; CHECK: # %bb.0: # %entry4771; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4772; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v164773; CHECK-NEXT: ret4774entry:4775 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)4776 ret void4777}4778 4779define void @test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {4780; CHECK-LABEL: test_vsuxseg8_mask_nxv1i16_triscv.vector.tuple_nxv2i8_8t_nxv1i64:4781; CHECK: # %bb.0: # %entry4782; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma4783; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t4784; CHECK-NEXT: ret4785entry:4786 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)4787 ret void4788}4789 4790define void @test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {4791; CHECK-LABEL: test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:4792; CHECK: # %bb.0: # %entry4793; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4794; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v164795; CHECK-NEXT: ret4796entry:4797 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)4798 ret void4799}4800 4801define void @test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {4802; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:4803; CHECK: # %bb.0: # %entry4804; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4805; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t4806; CHECK-NEXT: ret4807entry:4808 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4809 ret void4810}4811 4812define void @test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {4813; CHECK-LABEL: test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:4814; CHECK: # %bb.0: # %entry4815; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4816; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v164817; CHECK-NEXT: ret4818entry:4819 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)4820 ret void4821}4822 4823define void @test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {4824; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:4825; CHECK: # %bb.0: # %entry4826; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4827; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t4828; CHECK-NEXT: ret4829entry:4830 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4831 ret void4832}4833 4834define void @test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {4835; CHECK-LABEL: test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:4836; CHECK: # %bb.0: # %entry4837; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4838; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v164839; CHECK-NEXT: ret4840entry:4841 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)4842 ret void4843}4844 4845define void @test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {4846; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:4847; CHECK: # %bb.0: # %entry4848; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4849; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t4850; CHECK-NEXT: ret4851entry:4852 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4853 ret void4854}4855 4856define void @test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {4857; CHECK-LABEL: test_vsuxseg8_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i64:4858; CHECK: # %bb.0: # %entry4859; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4860; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v164861; CHECK-NEXT: ret4862entry:4863 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)4864 ret void4865}4866 4867define void @test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {4868; CHECK-LABEL: test_vsuxseg8_mask_nxv2i16_triscv.vector.tuple_nxv4i8_8t_nxv2i64:4869; CHECK: # %bb.0: # %entry4870; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma4871; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t4872; CHECK-NEXT: ret4873entry:4874 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)4875 ret void4876}4877 4878define void @test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {4879; CHECK-LABEL: test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:4880; CHECK: # %bb.0: # %entry4881; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4882; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v164883; CHECK-NEXT: ret4884entry:4885 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)4886 ret void4887}4888 4889define void @test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {4890; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:4891; CHECK: # %bb.0: # %entry4892; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4893; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t4894; CHECK-NEXT: ret4895entry:4896 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4897 ret void4898}4899 4900define void @test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {4901; CHECK-LABEL: test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:4902; CHECK: # %bb.0: # %entry4903; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4904; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v164905; CHECK-NEXT: ret4906entry:4907 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)4908 ret void4909}4910 4911define void @test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {4912; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:4913; CHECK: # %bb.0: # %entry4914; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4915; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t4916; CHECK-NEXT: ret4917entry:4918 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4919 ret void4920}4921 4922define void @test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {4923; CHECK-LABEL: test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:4924; CHECK: # %bb.0: # %entry4925; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4926; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v164927; CHECK-NEXT: ret4928entry:4929 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)4930 ret void4931}4932 4933define void @test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {4934; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:4935; CHECK: # %bb.0: # %entry4936; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4937; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t4938; CHECK-NEXT: ret4939entry:4940 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4941 ret void4942}4943 4944define void @test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {4945; CHECK-LABEL: test_vsuxseg8_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i64:4946; CHECK: # %bb.0: # %entry4947; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4948; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v164949; CHECK-NEXT: ret4950entry:4951 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)4952 ret void4953}4954 4955define void @test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {4956; CHECK-LABEL: test_vsuxseg8_mask_nxv4i16_triscv.vector.tuple_nxv8i8_8t_nxv4i64:4957; CHECK: # %bb.0: # %entry4958; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma4959; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t4960; CHECK-NEXT: ret4961entry:4962 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)4963 ret void4964}4965 4966define void @test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {4967; CHECK-LABEL: test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:4968; CHECK: # %bb.0: # %entry4969; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma4970; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v104971; CHECK-NEXT: ret4972entry:4973 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)4974 ret void4975}4976 4977define void @test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {4978; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:4979; CHECK: # %bb.0: # %entry4980; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma4981; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t4982; CHECK-NEXT: ret4983entry:4984 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4985 ret void4986}4987 4988define void @test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {4989; CHECK-LABEL: test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:4990; CHECK: # %bb.0: # %entry4991; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma4992; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v104993; CHECK-NEXT: ret4994entry:4995 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4996 ret void4997}4998 4999define void @test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {5000; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:5001; CHECK: # %bb.0: # %entry5002; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5003; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t5004; CHECK-NEXT: ret5005entry:5006 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5007 ret void5008}5009 5010define void @test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {5011; CHECK-LABEL: test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:5012; CHECK: # %bb.0: # %entry5013; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5014; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v105015; CHECK-NEXT: ret5016entry:5017 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)5018 ret void5019}5020 5021define void @test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {5022; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:5023; CHECK: # %bb.0: # %entry5024; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5025; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t5026; CHECK-NEXT: ret5027entry:5028 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5029 ret void5030}5031 5032define void @test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {5033; CHECK-LABEL: test_vsuxseg2_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i64:5034; CHECK: # %bb.0: # %entry5035; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5036; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v105037; CHECK-NEXT: ret5038entry:5039 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)5040 ret void5041}5042 5043define void @test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {5044; CHECK-LABEL: test_vsuxseg2_mask_nxv1i32_triscv.vector.tuple_nxv4i8_2t_nxv1i64:5045; CHECK: # %bb.0: # %entry5046; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5047; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t5048; CHECK-NEXT: ret5049entry:5050 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5051 ret void5052}5053 5054define void @test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {5055; CHECK-LABEL: test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:5056; CHECK: # %bb.0: # %entry5057; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5058; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v105059; CHECK-NEXT: ret5060entry:5061 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)5062 ret void5063}5064 5065define void @test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {5066; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:5067; CHECK: # %bb.0: # %entry5068; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5069; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t5070; CHECK-NEXT: ret5071entry:5072 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5073 ret void5074}5075 5076define void @test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {5077; CHECK-LABEL: test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:5078; CHECK: # %bb.0: # %entry5079; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5080; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v105081; CHECK-NEXT: ret5082entry:5083 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)5084 ret void5085}5086 5087define void @test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {5088; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:5089; CHECK: # %bb.0: # %entry5090; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5091; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t5092; CHECK-NEXT: ret5093entry:5094 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5095 ret void5096}5097 5098define void @test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {5099; CHECK-LABEL: test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:5100; CHECK: # %bb.0: # %entry5101; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5102; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v105103; CHECK-NEXT: ret5104entry:5105 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)5106 ret void5107}5108 5109define void @test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {5110; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:5111; CHECK: # %bb.0: # %entry5112; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5113; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t5114; CHECK-NEXT: ret5115entry:5116 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5117 ret void5118}5119 5120define void @test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {5121; CHECK-LABEL: test_vsuxseg2_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i64:5122; CHECK: # %bb.0: # %entry5123; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5124; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v105125; CHECK-NEXT: ret5126entry:5127 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)5128 ret void5129}5130 5131define void @test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {5132; CHECK-LABEL: test_vsuxseg2_mask_nxv2i32_triscv.vector.tuple_nxv8i8_2t_nxv2i64:5133; CHECK: # %bb.0: # %entry5134; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5135; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t5136; CHECK-NEXT: ret5137entry:5138 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5139 ret void5140}5141 5142define void @test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {5143; CHECK-LABEL: test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:5144; CHECK: # %bb.0: # %entry5145; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5146; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v125147; CHECK-NEXT: ret5148entry:5149 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 5)5150 ret void5151}5152 5153define void @test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {5154; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:5155; CHECK: # %bb.0: # %entry5156; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5157; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t5158; CHECK-NEXT: ret5159entry:5160 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5161 ret void5162}5163 5164define void @test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {5165; CHECK-LABEL: test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:5166; CHECK: # %bb.0: # %entry5167; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5168; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v125169; CHECK-NEXT: ret5170entry:5171 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 5)5172 ret void5173}5174 5175define void @test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {5176; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:5177; CHECK: # %bb.0: # %entry5178; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5179; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t5180; CHECK-NEXT: ret5181entry:5182 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5183 ret void5184}5185 5186define void @test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {5187; CHECK-LABEL: test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:5188; CHECK: # %bb.0: # %entry5189; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5190; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v125191; CHECK-NEXT: ret5192entry:5193 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 5)5194 ret void5195}5196 5197define void @test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {5198; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:5199; CHECK: # %bb.0: # %entry5200; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5201; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t5202; CHECK-NEXT: ret5203entry:5204 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5205 ret void5206}5207 5208define void @test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {5209; CHECK-LABEL: test_vsuxseg2_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i64:5210; CHECK: # %bb.0: # %entry5211; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5212; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v125213; CHECK-NEXT: ret5214entry:5215 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 5)5216 ret void5217}5218 5219define void @test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {5220; CHECK-LABEL: test_vsuxseg2_mask_nxv4i32_triscv.vector.tuple_nxv16i8_2t_nxv4i64:5221; CHECK: # %bb.0: # %entry5222; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5223; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t5224; CHECK-NEXT: ret5225entry:5226 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5227 ret void5228}5229 5230define void @test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {5231; CHECK-LABEL: test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:5232; CHECK: # %bb.0: # %entry5233; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5234; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v165235; CHECK-NEXT: ret5236entry:5237 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 5)5238 ret void5239}5240 5241define void @test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {5242; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:5243; CHECK: # %bb.0: # %entry5244; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5245; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t5246; CHECK-NEXT: ret5247entry:5248 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)5249 ret void5250}5251 5252define void @test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {5253; CHECK-LABEL: test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:5254; CHECK: # %bb.0: # %entry5255; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5256; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v165257; CHECK-NEXT: ret5258entry:5259 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 5)5260 ret void5261}5262 5263define void @test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {5264; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:5265; CHECK: # %bb.0: # %entry5266; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5267; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t5268; CHECK-NEXT: ret5269entry:5270 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)5271 ret void5272}5273 5274define void @test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {5275; CHECK-LABEL: test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:5276; CHECK: # %bb.0: # %entry5277; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5278; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v165279; CHECK-NEXT: ret5280entry:5281 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 5)5282 ret void5283}5284 5285define void @test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {5286; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:5287; CHECK: # %bb.0: # %entry5288; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5289; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t5290; CHECK-NEXT: ret5291entry:5292 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)5293 ret void5294}5295 5296define void @test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {5297; CHECK-LABEL: test_vsuxseg2_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i64:5298; CHECK: # %bb.0: # %entry5299; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5300; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v165301; CHECK-NEXT: ret5302entry:5303 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 5)5304 ret void5305}5306 5307define void @test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {5308; CHECK-LABEL: test_vsuxseg2_mask_nxv8i32_triscv.vector.tuple_nxv32i8_2t_nxv8i64:5309; CHECK: # %bb.0: # %entry5310; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma5311; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t5312; CHECK-NEXT: ret5313entry:5314 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)5315 ret void5316}5317 5318define void @test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {5319; CHECK-LABEL: test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:5320; CHECK: # %bb.0: # %entry5321; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5322; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v115323; CHECK-NEXT: ret5324entry:5325 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)5326 ret void5327}5328 5329define void @test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {5330; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:5331; CHECK: # %bb.0: # %entry5332; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5333; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t5334; CHECK-NEXT: ret5335entry:5336 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5337 ret void5338}5339 5340define void @test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {5341; CHECK-LABEL: test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:5342; CHECK: # %bb.0: # %entry5343; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5344; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v115345; CHECK-NEXT: ret5346entry:5347 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)5348 ret void5349}5350 5351define void @test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {5352; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:5353; CHECK: # %bb.0: # %entry5354; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5355; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t5356; CHECK-NEXT: ret5357entry:5358 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5359 ret void5360}5361 5362define void @test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {5363; CHECK-LABEL: test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:5364; CHECK: # %bb.0: # %entry5365; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5366; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v115367; CHECK-NEXT: ret5368entry:5369 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)5370 ret void5371}5372 5373define void @test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {5374; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:5375; CHECK: # %bb.0: # %entry5376; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5377; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t5378; CHECK-NEXT: ret5379entry:5380 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5381 ret void5382}5383 5384define void @test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {5385; CHECK-LABEL: test_vsuxseg3_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i64:5386; CHECK: # %bb.0: # %entry5387; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5388; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v115389; CHECK-NEXT: ret5390entry:5391 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)5392 ret void5393}5394 5395define void @test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {5396; CHECK-LABEL: test_vsuxseg3_mask_nxv1i32_triscv.vector.tuple_nxv4i8_3t_nxv1i64:5397; CHECK: # %bb.0: # %entry5398; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5399; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t5400; CHECK-NEXT: ret5401entry:5402 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5403 ret void5404}5405 5406define void @test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {5407; CHECK-LABEL: test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:5408; CHECK: # %bb.0: # %entry5409; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5410; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v115411; CHECK-NEXT: ret5412entry:5413 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)5414 ret void5415}5416 5417define void @test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {5418; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:5419; CHECK: # %bb.0: # %entry5420; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5421; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t5422; CHECK-NEXT: ret5423entry:5424 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5425 ret void5426}5427 5428define void @test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {5429; CHECK-LABEL: test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:5430; CHECK: # %bb.0: # %entry5431; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5432; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v115433; CHECK-NEXT: ret5434entry:5435 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)5436 ret void5437}5438 5439define void @test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {5440; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:5441; CHECK: # %bb.0: # %entry5442; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5443; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t5444; CHECK-NEXT: ret5445entry:5446 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5447 ret void5448}5449 5450define void @test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {5451; CHECK-LABEL: test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:5452; CHECK: # %bb.0: # %entry5453; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5454; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v115455; CHECK-NEXT: ret5456entry:5457 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)5458 ret void5459}5460 5461define void @test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {5462; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:5463; CHECK: # %bb.0: # %entry5464; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5465; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t5466; CHECK-NEXT: ret5467entry:5468 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5469 ret void5470}5471 5472define void @test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {5473; CHECK-LABEL: test_vsuxseg3_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i64:5474; CHECK: # %bb.0: # %entry5475; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5476; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v125477; CHECK-NEXT: ret5478entry:5479 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)5480 ret void5481}5482 5483define void @test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {5484; CHECK-LABEL: test_vsuxseg3_mask_nxv2i32_triscv.vector.tuple_nxv8i8_3t_nxv2i64:5485; CHECK: # %bb.0: # %entry5486; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5487; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t5488; CHECK-NEXT: ret5489entry:5490 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5491 ret void5492}5493 5494define void @test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {5495; CHECK-LABEL: test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:5496; CHECK: # %bb.0: # %entry5497; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5498; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v145499; CHECK-NEXT: ret5500entry:5501 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 5)5502 ret void5503}5504 5505define void @test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {5506; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:5507; CHECK: # %bb.0: # %entry5508; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5509; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t5510; CHECK-NEXT: ret5511entry:5512 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5513 ret void5514}5515 5516define void @test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {5517; CHECK-LABEL: test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:5518; CHECK: # %bb.0: # %entry5519; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5520; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v145521; CHECK-NEXT: ret5522entry:5523 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 5)5524 ret void5525}5526 5527define void @test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {5528; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:5529; CHECK: # %bb.0: # %entry5530; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5531; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v14, v0.t5532; CHECK-NEXT: ret5533entry:5534 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5535 ret void5536}5537 5538define void @test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {5539; CHECK-LABEL: test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:5540; CHECK: # %bb.0: # %entry5541; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5542; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v145543; CHECK-NEXT: ret5544entry:5545 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 5)5546 ret void5547}5548 5549define void @test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {5550; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:5551; CHECK: # %bb.0: # %entry5552; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5553; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v14, v0.t5554; CHECK-NEXT: ret5555entry:5556 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5557 ret void5558}5559 5560define void @test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {5561; CHECK-LABEL: test_vsuxseg3_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i64:5562; CHECK: # %bb.0: # %entry5563; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5564; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v165565; CHECK-NEXT: ret5566entry:5567 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 5)5568 ret void5569}5570 5571define void @test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {5572; CHECK-LABEL: test_vsuxseg3_mask_nxv4i32_triscv.vector.tuple_nxv16i8_3t_nxv4i64:5573; CHECK: # %bb.0: # %entry5574; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5575; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v16, v0.t5576; CHECK-NEXT: ret5577entry:5578 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5579 ret void5580}5581 5582define void @test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {5583; CHECK-LABEL: test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:5584; CHECK: # %bb.0: # %entry5585; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5586; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v125587; CHECK-NEXT: ret5588entry:5589 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)5590 ret void5591}5592 5593define void @test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {5594; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:5595; CHECK: # %bb.0: # %entry5596; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5597; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t5598; CHECK-NEXT: ret5599entry:5600 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5601 ret void5602}5603 5604define void @test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {5605; CHECK-LABEL: test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:5606; CHECK: # %bb.0: # %entry5607; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5608; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v125609; CHECK-NEXT: ret5610entry:5611 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)5612 ret void5613}5614 5615define void @test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {5616; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:5617; CHECK: # %bb.0: # %entry5618; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5619; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t5620; CHECK-NEXT: ret5621entry:5622 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5623 ret void5624}5625 5626define void @test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {5627; CHECK-LABEL: test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:5628; CHECK: # %bb.0: # %entry5629; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5630; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v125631; CHECK-NEXT: ret5632entry:5633 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)5634 ret void5635}5636 5637define void @test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {5638; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:5639; CHECK: # %bb.0: # %entry5640; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5641; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t5642; CHECK-NEXT: ret5643entry:5644 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5645 ret void5646}5647 5648define void @test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {5649; CHECK-LABEL: test_vsuxseg4_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i64:5650; CHECK: # %bb.0: # %entry5651; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5652; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v125653; CHECK-NEXT: ret5654entry:5655 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)5656 ret void5657}5658 5659define void @test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {5660; CHECK-LABEL: test_vsuxseg4_mask_nxv1i32_triscv.vector.tuple_nxv4i8_4t_nxv1i64:5661; CHECK: # %bb.0: # %entry5662; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5663; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t5664; CHECK-NEXT: ret5665entry:5666 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5667 ret void5668}5669 5670define void @test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {5671; CHECK-LABEL: test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:5672; CHECK: # %bb.0: # %entry5673; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5674; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v125675; CHECK-NEXT: ret5676entry:5677 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)5678 ret void5679}5680 5681define void @test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {5682; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:5683; CHECK: # %bb.0: # %entry5684; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5685; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t5686; CHECK-NEXT: ret5687entry:5688 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5689 ret void5690}5691 5692define void @test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {5693; CHECK-LABEL: test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:5694; CHECK: # %bb.0: # %entry5695; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5696; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v125697; CHECK-NEXT: ret5698entry:5699 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)5700 ret void5701}5702 5703define void @test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {5704; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:5705; CHECK: # %bb.0: # %entry5706; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5707; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t5708; CHECK-NEXT: ret5709entry:5710 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5711 ret void5712}5713 5714define void @test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {5715; CHECK-LABEL: test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:5716; CHECK: # %bb.0: # %entry5717; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5718; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v125719; CHECK-NEXT: ret5720entry:5721 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)5722 ret void5723}5724 5725define void @test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {5726; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:5727; CHECK: # %bb.0: # %entry5728; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5729; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t5730; CHECK-NEXT: ret5731entry:5732 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5733 ret void5734}5735 5736define void @test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {5737; CHECK-LABEL: test_vsuxseg4_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i64:5738; CHECK: # %bb.0: # %entry5739; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5740; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v125741; CHECK-NEXT: ret5742entry:5743 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)5744 ret void5745}5746 5747define void @test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {5748; CHECK-LABEL: test_vsuxseg4_mask_nxv2i32_triscv.vector.tuple_nxv8i8_4t_nxv2i64:5749; CHECK: # %bb.0: # %entry5750; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5751; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t5752; CHECK-NEXT: ret5753entry:5754 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5755 ret void5756}5757 5758define void @test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {5759; CHECK-LABEL: test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:5760; CHECK: # %bb.0: # %entry5761; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5762; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v165763; CHECK-NEXT: ret5764entry:5765 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 5)5766 ret void5767}5768 5769define void @test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {5770; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:5771; CHECK: # %bb.0: # %entry5772; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5773; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t5774; CHECK-NEXT: ret5775entry:5776 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5777 ret void5778}5779 5780define void @test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {5781; CHECK-LABEL: test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:5782; CHECK: # %bb.0: # %entry5783; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5784; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v165785; CHECK-NEXT: ret5786entry:5787 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 5)5788 ret void5789}5790 5791define void @test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {5792; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:5793; CHECK: # %bb.0: # %entry5794; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5795; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t5796; CHECK-NEXT: ret5797entry:5798 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5799 ret void5800}5801 5802define void @test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {5803; CHECK-LABEL: test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:5804; CHECK: # %bb.0: # %entry5805; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5806; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v165807; CHECK-NEXT: ret5808entry:5809 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 5)5810 ret void5811}5812 5813define void @test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {5814; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:5815; CHECK: # %bb.0: # %entry5816; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5817; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t5818; CHECK-NEXT: ret5819entry:5820 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5821 ret void5822}5823 5824define void @test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {5825; CHECK-LABEL: test_vsuxseg4_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i64:5826; CHECK: # %bb.0: # %entry5827; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5828; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v165829; CHECK-NEXT: ret5830entry:5831 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 5)5832 ret void5833}5834 5835define void @test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {5836; CHECK-LABEL: test_vsuxseg4_mask_nxv4i32_triscv.vector.tuple_nxv16i8_4t_nxv4i64:5837; CHECK: # %bb.0: # %entry5838; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma5839; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t5840; CHECK-NEXT: ret5841entry:5842 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)5843 ret void5844}5845 5846define void @test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {5847; CHECK-LABEL: test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:5848; CHECK: # %bb.0: # %entry5849; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5850; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v135851; CHECK-NEXT: ret5852entry:5853 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)5854 ret void5855}5856 5857define void @test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {5858; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:5859; CHECK: # %bb.0: # %entry5860; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5861; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t5862; CHECK-NEXT: ret5863entry:5864 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5865 ret void5866}5867 5868define void @test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {5869; CHECK-LABEL: test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:5870; CHECK: # %bb.0: # %entry5871; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5872; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v135873; CHECK-NEXT: ret5874entry:5875 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)5876 ret void5877}5878 5879define void @test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {5880; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:5881; CHECK: # %bb.0: # %entry5882; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5883; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t5884; CHECK-NEXT: ret5885entry:5886 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5887 ret void5888}5889 5890define void @test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {5891; CHECK-LABEL: test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:5892; CHECK: # %bb.0: # %entry5893; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5894; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v135895; CHECK-NEXT: ret5896entry:5897 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)5898 ret void5899}5900 5901define void @test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {5902; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:5903; CHECK: # %bb.0: # %entry5904; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5905; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t5906; CHECK-NEXT: ret5907entry:5908 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5909 ret void5910}5911 5912define void @test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {5913; CHECK-LABEL: test_vsuxseg5_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i64:5914; CHECK: # %bb.0: # %entry5915; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5916; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v135917; CHECK-NEXT: ret5918entry:5919 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)5920 ret void5921}5922 5923define void @test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {5924; CHECK-LABEL: test_vsuxseg5_mask_nxv1i32_triscv.vector.tuple_nxv4i8_5t_nxv1i64:5925; CHECK: # %bb.0: # %entry5926; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma5927; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t5928; CHECK-NEXT: ret5929entry:5930 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5931 ret void5932}5933 5934define void @test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {5935; CHECK-LABEL: test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:5936; CHECK: # %bb.0: # %entry5937; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5938; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v135939; CHECK-NEXT: ret5940entry:5941 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)5942 ret void5943}5944 5945define void @test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {5946; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:5947; CHECK: # %bb.0: # %entry5948; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5949; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t5950; CHECK-NEXT: ret5951entry:5952 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5953 ret void5954}5955 5956define void @test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {5957; CHECK-LABEL: test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:5958; CHECK: # %bb.0: # %entry5959; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5960; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v135961; CHECK-NEXT: ret5962entry:5963 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)5964 ret void5965}5966 5967define void @test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {5968; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:5969; CHECK: # %bb.0: # %entry5970; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5971; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t5972; CHECK-NEXT: ret5973entry:5974 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5975 ret void5976}5977 5978define void @test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {5979; CHECK-LABEL: test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:5980; CHECK: # %bb.0: # %entry5981; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5982; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v135983; CHECK-NEXT: ret5984entry:5985 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)5986 ret void5987}5988 5989define void @test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {5990; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:5991; CHECK: # %bb.0: # %entry5992; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma5993; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t5994; CHECK-NEXT: ret5995entry:5996 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)5997 ret void5998}5999 6000define void @test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {6001; CHECK-LABEL: test_vsuxseg5_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i64:6002; CHECK: # %bb.0: # %entry6003; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6004; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v146005; CHECK-NEXT: ret6006entry:6007 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)6008 ret void6009}6010 6011define void @test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {6012; CHECK-LABEL: test_vsuxseg5_mask_nxv2i32_triscv.vector.tuple_nxv8i8_5t_nxv2i64:6013; CHECK: # %bb.0: # %entry6014; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6015; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v14, v0.t6016; CHECK-NEXT: ret6017entry:6018 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6019 ret void6020}6021 6022define void @test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {6023; CHECK-LABEL: test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:6024; CHECK: # %bb.0: # %entry6025; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6026; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v146027; CHECK-NEXT: ret6028entry:6029 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)6030 ret void6031}6032 6033define void @test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {6034; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:6035; CHECK: # %bb.0: # %entry6036; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6037; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t6038; CHECK-NEXT: ret6039entry:6040 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6041 ret void6042}6043 6044define void @test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {6045; CHECK-LABEL: test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:6046; CHECK: # %bb.0: # %entry6047; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6048; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v146049; CHECK-NEXT: ret6050entry:6051 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)6052 ret void6053}6054 6055define void @test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {6056; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:6057; CHECK: # %bb.0: # %entry6058; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6059; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t6060; CHECK-NEXT: ret6061entry:6062 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6063 ret void6064}6065 6066define void @test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {6067; CHECK-LABEL: test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:6068; CHECK: # %bb.0: # %entry6069; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6070; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v146071; CHECK-NEXT: ret6072entry:6073 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)6074 ret void6075}6076 6077define void @test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {6078; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:6079; CHECK: # %bb.0: # %entry6080; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6081; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t6082; CHECK-NEXT: ret6083entry:6084 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6085 ret void6086}6087 6088define void @test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {6089; CHECK-LABEL: test_vsuxseg6_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i64:6090; CHECK: # %bb.0: # %entry6091; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6092; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v146093; CHECK-NEXT: ret6094entry:6095 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)6096 ret void6097}6098 6099define void @test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {6100; CHECK-LABEL: test_vsuxseg6_mask_nxv1i32_triscv.vector.tuple_nxv4i8_6t_nxv1i64:6101; CHECK: # %bb.0: # %entry6102; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6103; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t6104; CHECK-NEXT: ret6105entry:6106 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6107 ret void6108}6109 6110define void @test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {6111; CHECK-LABEL: test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:6112; CHECK: # %bb.0: # %entry6113; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6114; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v146115; CHECK-NEXT: ret6116entry:6117 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)6118 ret void6119}6120 6121define void @test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {6122; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:6123; CHECK: # %bb.0: # %entry6124; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6125; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t6126; CHECK-NEXT: ret6127entry:6128 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6129 ret void6130}6131 6132define void @test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {6133; CHECK-LABEL: test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:6134; CHECK: # %bb.0: # %entry6135; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6136; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v146137; CHECK-NEXT: ret6138entry:6139 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)6140 ret void6141}6142 6143define void @test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {6144; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:6145; CHECK: # %bb.0: # %entry6146; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6147; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t6148; CHECK-NEXT: ret6149entry:6150 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6151 ret void6152}6153 6154define void @test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {6155; CHECK-LABEL: test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:6156; CHECK: # %bb.0: # %entry6157; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6158; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v146159; CHECK-NEXT: ret6160entry:6161 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)6162 ret void6163}6164 6165define void @test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {6166; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:6167; CHECK: # %bb.0: # %entry6168; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6169; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t6170; CHECK-NEXT: ret6171entry:6172 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6173 ret void6174}6175 6176define void @test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {6177; CHECK-LABEL: test_vsuxseg6_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i64:6178; CHECK: # %bb.0: # %entry6179; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6180; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v146181; CHECK-NEXT: ret6182entry:6183 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)6184 ret void6185}6186 6187define void @test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {6188; CHECK-LABEL: test_vsuxseg6_mask_nxv2i32_triscv.vector.tuple_nxv8i8_6t_nxv2i64:6189; CHECK: # %bb.0: # %entry6190; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6191; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t6192; CHECK-NEXT: ret6193entry:6194 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6195 ret void6196}6197 6198define void @test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {6199; CHECK-LABEL: test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:6200; CHECK: # %bb.0: # %entry6201; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6202; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v156203; CHECK-NEXT: ret6204entry:6205 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)6206 ret void6207}6208 6209define void @test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {6210; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:6211; CHECK: # %bb.0: # %entry6212; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6213; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t6214; CHECK-NEXT: ret6215entry:6216 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6217 ret void6218}6219 6220define void @test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {6221; CHECK-LABEL: test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:6222; CHECK: # %bb.0: # %entry6223; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6224; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v156225; CHECK-NEXT: ret6226entry:6227 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)6228 ret void6229}6230 6231define void @test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {6232; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:6233; CHECK: # %bb.0: # %entry6234; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6235; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t6236; CHECK-NEXT: ret6237entry:6238 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6239 ret void6240}6241 6242define void @test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {6243; CHECK-LABEL: test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:6244; CHECK: # %bb.0: # %entry6245; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6246; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v156247; CHECK-NEXT: ret6248entry:6249 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)6250 ret void6251}6252 6253define void @test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {6254; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:6255; CHECK: # %bb.0: # %entry6256; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6257; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t6258; CHECK-NEXT: ret6259entry:6260 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6261 ret void6262}6263 6264define void @test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {6265; CHECK-LABEL: test_vsuxseg7_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i64:6266; CHECK: # %bb.0: # %entry6267; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6268; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v156269; CHECK-NEXT: ret6270entry:6271 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)6272 ret void6273}6274 6275define void @test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {6276; CHECK-LABEL: test_vsuxseg7_mask_nxv1i32_triscv.vector.tuple_nxv4i8_7t_nxv1i64:6277; CHECK: # %bb.0: # %entry6278; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6279; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t6280; CHECK-NEXT: ret6281entry:6282 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6283 ret void6284}6285 6286define void @test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {6287; CHECK-LABEL: test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:6288; CHECK: # %bb.0: # %entry6289; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6290; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v156291; CHECK-NEXT: ret6292entry:6293 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)6294 ret void6295}6296 6297define void @test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {6298; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:6299; CHECK: # %bb.0: # %entry6300; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6301; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t6302; CHECK-NEXT: ret6303entry:6304 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6305 ret void6306}6307 6308define void @test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {6309; CHECK-LABEL: test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:6310; CHECK: # %bb.0: # %entry6311; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6312; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v156313; CHECK-NEXT: ret6314entry:6315 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)6316 ret void6317}6318 6319define void @test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {6320; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:6321; CHECK: # %bb.0: # %entry6322; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6323; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t6324; CHECK-NEXT: ret6325entry:6326 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6327 ret void6328}6329 6330define void @test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {6331; CHECK-LABEL: test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:6332; CHECK: # %bb.0: # %entry6333; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6334; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v156335; CHECK-NEXT: ret6336entry:6337 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)6338 ret void6339}6340 6341define void @test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {6342; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:6343; CHECK: # %bb.0: # %entry6344; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6345; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t6346; CHECK-NEXT: ret6347entry:6348 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6349 ret void6350}6351 6352define void @test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {6353; CHECK-LABEL: test_vsuxseg7_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i64:6354; CHECK: # %bb.0: # %entry6355; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6356; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v166357; CHECK-NEXT: ret6358entry:6359 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)6360 ret void6361}6362 6363define void @test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {6364; CHECK-LABEL: test_vsuxseg7_mask_nxv2i32_triscv.vector.tuple_nxv8i8_7t_nxv2i64:6365; CHECK: # %bb.0: # %entry6366; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6367; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t6368; CHECK-NEXT: ret6369entry:6370 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6371 ret void6372}6373 6374define void @test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {6375; CHECK-LABEL: test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:6376; CHECK: # %bb.0: # %entry6377; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6378; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v166379; CHECK-NEXT: ret6380entry:6381 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)6382 ret void6383}6384 6385define void @test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {6386; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:6387; CHECK: # %bb.0: # %entry6388; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6389; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t6390; CHECK-NEXT: ret6391entry:6392 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6393 ret void6394}6395 6396define void @test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {6397; CHECK-LABEL: test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:6398; CHECK: # %bb.0: # %entry6399; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6400; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v166401; CHECK-NEXT: ret6402entry:6403 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)6404 ret void6405}6406 6407define void @test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {6408; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:6409; CHECK: # %bb.0: # %entry6410; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6411; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t6412; CHECK-NEXT: ret6413entry:6414 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6415 ret void6416}6417 6418define void @test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {6419; CHECK-LABEL: test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:6420; CHECK: # %bb.0: # %entry6421; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6422; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v166423; CHECK-NEXT: ret6424entry:6425 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)6426 ret void6427}6428 6429define void @test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {6430; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:6431; CHECK: # %bb.0: # %entry6432; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6433; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t6434; CHECK-NEXT: ret6435entry:6436 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6437 ret void6438}6439 6440define void @test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {6441; CHECK-LABEL: test_vsuxseg8_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i64:6442; CHECK: # %bb.0: # %entry6443; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6444; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v166445; CHECK-NEXT: ret6446entry:6447 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)6448 ret void6449}6450 6451define void @test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {6452; CHECK-LABEL: test_vsuxseg8_mask_nxv1i32_triscv.vector.tuple_nxv4i8_8t_nxv1i64:6453; CHECK: # %bb.0: # %entry6454; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma6455; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t6456; CHECK-NEXT: ret6457entry:6458 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)6459 ret void6460}6461 6462define void @test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {6463; CHECK-LABEL: test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:6464; CHECK: # %bb.0: # %entry6465; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6466; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v166467; CHECK-NEXT: ret6468entry:6469 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)6470 ret void6471}6472 6473define void @test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {6474; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:6475; CHECK: # %bb.0: # %entry6476; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6477; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t6478; CHECK-NEXT: ret6479entry:6480 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6481 ret void6482}6483 6484define void @test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {6485; CHECK-LABEL: test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:6486; CHECK: # %bb.0: # %entry6487; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6488; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v166489; CHECK-NEXT: ret6490entry:6491 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)6492 ret void6493}6494 6495define void @test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {6496; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:6497; CHECK: # %bb.0: # %entry6498; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6499; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t6500; CHECK-NEXT: ret6501entry:6502 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6503 ret void6504}6505 6506define void @test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {6507; CHECK-LABEL: test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:6508; CHECK: # %bb.0: # %entry6509; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6510; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v166511; CHECK-NEXT: ret6512entry:6513 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)6514 ret void6515}6516 6517define void @test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {6518; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:6519; CHECK: # %bb.0: # %entry6520; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6521; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t6522; CHECK-NEXT: ret6523entry:6524 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6525 ret void6526}6527 6528define void @test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {6529; CHECK-LABEL: test_vsuxseg8_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i64:6530; CHECK: # %bb.0: # %entry6531; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6532; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v166533; CHECK-NEXT: ret6534entry:6535 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)6536 ret void6537}6538 6539define void @test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {6540; CHECK-LABEL: test_vsuxseg8_mask_nxv2i32_triscv.vector.tuple_nxv8i8_8t_nxv2i64:6541; CHECK: # %bb.0: # %entry6542; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma6543; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t6544; CHECK-NEXT: ret6545entry:6546 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)6547 ret void6548}6549 6550define void @test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {6551; CHECK-LABEL: test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:6552; CHECK: # %bb.0: # %entry6553; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6554; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v106555; CHECK-NEXT: ret6556entry:6557 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)6558 ret void6559}6560 6561define void @test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {6562; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:6563; CHECK: # %bb.0: # %entry6564; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6565; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t6566; CHECK-NEXT: ret6567entry:6568 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6569 ret void6570}6571 6572define void @test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {6573; CHECK-LABEL: test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:6574; CHECK: # %bb.0: # %entry6575; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6576; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v106577; CHECK-NEXT: ret6578entry:6579 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)6580 ret void6581}6582 6583define void @test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {6584; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:6585; CHECK: # %bb.0: # %entry6586; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6587; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t6588; CHECK-NEXT: ret6589entry:6590 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6591 ret void6592}6593 6594define void @test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {6595; CHECK-LABEL: test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:6596; CHECK: # %bb.0: # %entry6597; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6598; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v106599; CHECK-NEXT: ret6600entry:6601 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)6602 ret void6603}6604 6605define void @test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {6606; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:6607; CHECK: # %bb.0: # %entry6608; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6609; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t6610; CHECK-NEXT: ret6611entry:6612 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6613 ret void6614}6615 6616define void @test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {6617; CHECK-LABEL: test_vsuxseg2_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i64:6618; CHECK: # %bb.0: # %entry6619; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6620; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v106621; CHECK-NEXT: ret6622entry:6623 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)6624 ret void6625}6626 6627define void @test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {6628; CHECK-LABEL: test_vsuxseg2_mask_nxv1i64_triscv.vector.tuple_nxv8i8_2t_nxv1i64:6629; CHECK: # %bb.0: # %entry6630; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6631; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t6632; CHECK-NEXT: ret6633entry:6634 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6635 ret void6636}6637 6638define void @test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {6639; CHECK-LABEL: test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:6640; CHECK: # %bb.0: # %entry6641; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6642; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v126643; CHECK-NEXT: ret6644entry:6645 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 6)6646 ret void6647}6648 6649define void @test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {6650; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:6651; CHECK: # %bb.0: # %entry6652; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6653; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t6654; CHECK-NEXT: ret6655entry:6656 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6657 ret void6658}6659 6660define void @test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {6661; CHECK-LABEL: test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:6662; CHECK: # %bb.0: # %entry6663; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6664; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v126665; CHECK-NEXT: ret6666entry:6667 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 6)6668 ret void6669}6670 6671define void @test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {6672; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:6673; CHECK: # %bb.0: # %entry6674; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6675; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t6676; CHECK-NEXT: ret6677entry:6678 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6679 ret void6680}6681 6682define void @test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {6683; CHECK-LABEL: test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:6684; CHECK: # %bb.0: # %entry6685; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6686; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v126687; CHECK-NEXT: ret6688entry:6689 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 6)6690 ret void6691}6692 6693define void @test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {6694; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:6695; CHECK: # %bb.0: # %entry6696; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6697; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t6698; CHECK-NEXT: ret6699entry:6700 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6701 ret void6702}6703 6704define void @test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {6705; CHECK-LABEL: test_vsuxseg2_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i64:6706; CHECK: # %bb.0: # %entry6707; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6708; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v126709; CHECK-NEXT: ret6710entry:6711 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 6)6712 ret void6713}6714 6715define void @test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {6716; CHECK-LABEL: test_vsuxseg2_mask_nxv2i64_triscv.vector.tuple_nxv16i8_2t_nxv2i64:6717; CHECK: # %bb.0: # %entry6718; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6719; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t6720; CHECK-NEXT: ret6721entry:6722 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6723 ret void6724}6725 6726define void @test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {6727; CHECK-LABEL: test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:6728; CHECK: # %bb.0: # %entry6729; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6730; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v166731; CHECK-NEXT: ret6732entry:6733 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 6)6734 ret void6735}6736 6737define void @test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {6738; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:6739; CHECK: # %bb.0: # %entry6740; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6741; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t6742; CHECK-NEXT: ret6743entry:6744 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)6745 ret void6746}6747 6748define void @test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {6749; CHECK-LABEL: test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:6750; CHECK: # %bb.0: # %entry6751; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6752; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v166753; CHECK-NEXT: ret6754entry:6755 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 6)6756 ret void6757}6758 6759define void @test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {6760; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:6761; CHECK: # %bb.0: # %entry6762; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6763; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t6764; CHECK-NEXT: ret6765entry:6766 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)6767 ret void6768}6769 6770define void @test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {6771; CHECK-LABEL: test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:6772; CHECK: # %bb.0: # %entry6773; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6774; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v166775; CHECK-NEXT: ret6776entry:6777 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 6)6778 ret void6779}6780 6781define void @test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {6782; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:6783; CHECK: # %bb.0: # %entry6784; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6785; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t6786; CHECK-NEXT: ret6787entry:6788 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)6789 ret void6790}6791 6792define void @test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {6793; CHECK-LABEL: test_vsuxseg2_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i64:6794; CHECK: # %bb.0: # %entry6795; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6796; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v166797; CHECK-NEXT: ret6798entry:6799 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 6)6800 ret void6801}6802 6803define void @test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {6804; CHECK-LABEL: test_vsuxseg2_mask_nxv4i64_triscv.vector.tuple_nxv32i8_2t_nxv4i64:6805; CHECK: # %bb.0: # %entry6806; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma6807; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t6808; CHECK-NEXT: ret6809entry:6810 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)6811 ret void6812}6813 6814define void @test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {6815; CHECK-LABEL: test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:6816; CHECK: # %bb.0: # %entry6817; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6818; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v116819; CHECK-NEXT: ret6820entry:6821 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)6822 ret void6823}6824 6825define void @test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {6826; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:6827; CHECK: # %bb.0: # %entry6828; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6829; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t6830; CHECK-NEXT: ret6831entry:6832 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6833 ret void6834}6835 6836define void @test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {6837; CHECK-LABEL: test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:6838; CHECK: # %bb.0: # %entry6839; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6840; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v116841; CHECK-NEXT: ret6842entry:6843 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)6844 ret void6845}6846 6847define void @test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {6848; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:6849; CHECK: # %bb.0: # %entry6850; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6851; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t6852; CHECK-NEXT: ret6853entry:6854 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6855 ret void6856}6857 6858define void @test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {6859; CHECK-LABEL: test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:6860; CHECK: # %bb.0: # %entry6861; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6862; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v116863; CHECK-NEXT: ret6864entry:6865 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)6866 ret void6867}6868 6869define void @test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {6870; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:6871; CHECK: # %bb.0: # %entry6872; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6873; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t6874; CHECK-NEXT: ret6875entry:6876 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6877 ret void6878}6879 6880define void @test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {6881; CHECK-LABEL: test_vsuxseg3_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i64:6882; CHECK: # %bb.0: # %entry6883; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6884; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v116885; CHECK-NEXT: ret6886entry:6887 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)6888 ret void6889}6890 6891define void @test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {6892; CHECK-LABEL: test_vsuxseg3_mask_nxv1i64_triscv.vector.tuple_nxv8i8_3t_nxv1i64:6893; CHECK: # %bb.0: # %entry6894; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6895; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t6896; CHECK-NEXT: ret6897entry:6898 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)6899 ret void6900}6901 6902define void @test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {6903; CHECK-LABEL: test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:6904; CHECK: # %bb.0: # %entry6905; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6906; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v146907; CHECK-NEXT: ret6908entry:6909 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 6)6910 ret void6911}6912 6913define void @test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {6914; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:6915; CHECK: # %bb.0: # %entry6916; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6917; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t6918; CHECK-NEXT: ret6919entry:6920 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6921 ret void6922}6923 6924define void @test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {6925; CHECK-LABEL: test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:6926; CHECK: # %bb.0: # %entry6927; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6928; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v146929; CHECK-NEXT: ret6930entry:6931 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 6)6932 ret void6933}6934 6935define void @test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {6936; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:6937; CHECK: # %bb.0: # %entry6938; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6939; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v14, v0.t6940; CHECK-NEXT: ret6941entry:6942 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6943 ret void6944}6945 6946define void @test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {6947; CHECK-LABEL: test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:6948; CHECK: # %bb.0: # %entry6949; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6950; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v146951; CHECK-NEXT: ret6952entry:6953 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 6)6954 ret void6955}6956 6957define void @test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {6958; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:6959; CHECK: # %bb.0: # %entry6960; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6961; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v14, v0.t6962; CHECK-NEXT: ret6963entry:6964 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6965 ret void6966}6967 6968define void @test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {6969; CHECK-LABEL: test_vsuxseg3_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i64:6970; CHECK: # %bb.0: # %entry6971; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6972; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v146973; CHECK-NEXT: ret6974entry:6975 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 6)6976 ret void6977}6978 6979define void @test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {6980; CHECK-LABEL: test_vsuxseg3_mask_nxv2i64_triscv.vector.tuple_nxv16i8_3t_nxv2i64:6981; CHECK: # %bb.0: # %entry6982; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma6983; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v14, v0.t6984; CHECK-NEXT: ret6985entry:6986 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)6987 ret void6988}6989 6990define void @test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {6991; CHECK-LABEL: test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:6992; CHECK: # %bb.0: # %entry6993; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma6994; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v126995; CHECK-NEXT: ret6996entry:6997 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)6998 ret void6999}7000 7001define void @test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {7002; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:7003; CHECK: # %bb.0: # %entry7004; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7005; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t7006; CHECK-NEXT: ret7007entry:7008 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7009 ret void7010}7011 7012define void @test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {7013; CHECK-LABEL: test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:7014; CHECK: # %bb.0: # %entry7015; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7016; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v127017; CHECK-NEXT: ret7018entry:7019 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)7020 ret void7021}7022 7023define void @test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {7024; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:7025; CHECK: # %bb.0: # %entry7026; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7027; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t7028; CHECK-NEXT: ret7029entry:7030 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7031 ret void7032}7033 7034define void @test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {7035; CHECK-LABEL: test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:7036; CHECK: # %bb.0: # %entry7037; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7038; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v127039; CHECK-NEXT: ret7040entry:7041 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)7042 ret void7043}7044 7045define void @test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {7046; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:7047; CHECK: # %bb.0: # %entry7048; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7049; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t7050; CHECK-NEXT: ret7051entry:7052 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7053 ret void7054}7055 7056define void @test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {7057; CHECK-LABEL: test_vsuxseg4_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i64:7058; CHECK: # %bb.0: # %entry7059; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7060; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v127061; CHECK-NEXT: ret7062entry:7063 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)7064 ret void7065}7066 7067define void @test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {7068; CHECK-LABEL: test_vsuxseg4_mask_nxv1i64_triscv.vector.tuple_nxv8i8_4t_nxv1i64:7069; CHECK: # %bb.0: # %entry7070; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7071; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t7072; CHECK-NEXT: ret7073entry:7074 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7075 ret void7076}7077 7078define void @test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {7079; CHECK-LABEL: test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:7080; CHECK: # %bb.0: # %entry7081; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7082; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v167083; CHECK-NEXT: ret7084entry:7085 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 6)7086 ret void7087}7088 7089define void @test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {7090; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:7091; CHECK: # %bb.0: # %entry7092; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7093; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t7094; CHECK-NEXT: ret7095entry:7096 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)7097 ret void7098}7099 7100define void @test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {7101; CHECK-LABEL: test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:7102; CHECK: # %bb.0: # %entry7103; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7104; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v167105; CHECK-NEXT: ret7106entry:7107 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 6)7108 ret void7109}7110 7111define void @test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {7112; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:7113; CHECK: # %bb.0: # %entry7114; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7115; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t7116; CHECK-NEXT: ret7117entry:7118 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)7119 ret void7120}7121 7122define void @test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {7123; CHECK-LABEL: test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:7124; CHECK: # %bb.0: # %entry7125; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7126; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v167127; CHECK-NEXT: ret7128entry:7129 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 6)7130 ret void7131}7132 7133define void @test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {7134; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:7135; CHECK: # %bb.0: # %entry7136; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7137; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t7138; CHECK-NEXT: ret7139entry:7140 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)7141 ret void7142}7143 7144define void @test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {7145; CHECK-LABEL: test_vsuxseg4_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i64:7146; CHECK: # %bb.0: # %entry7147; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7148; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v167149; CHECK-NEXT: ret7150entry:7151 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 6)7152 ret void7153}7154 7155define void @test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {7156; CHECK-LABEL: test_vsuxseg4_mask_nxv2i64_triscv.vector.tuple_nxv16i8_4t_nxv2i64:7157; CHECK: # %bb.0: # %entry7158; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma7159; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t7160; CHECK-NEXT: ret7161entry:7162 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)7163 ret void7164}7165 7166define void @test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {7167; CHECK-LABEL: test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:7168; CHECK: # %bb.0: # %entry7169; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7170; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v137171; CHECK-NEXT: ret7172entry:7173 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)7174 ret void7175}7176 7177define void @test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {7178; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:7179; CHECK: # %bb.0: # %entry7180; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7181; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t7182; CHECK-NEXT: ret7183entry:7184 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7185 ret void7186}7187 7188define void @test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {7189; CHECK-LABEL: test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:7190; CHECK: # %bb.0: # %entry7191; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7192; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v137193; CHECK-NEXT: ret7194entry:7195 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)7196 ret void7197}7198 7199define void @test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {7200; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:7201; CHECK: # %bb.0: # %entry7202; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7203; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t7204; CHECK-NEXT: ret7205entry:7206 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7207 ret void7208}7209 7210define void @test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {7211; CHECK-LABEL: test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:7212; CHECK: # %bb.0: # %entry7213; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7214; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v137215; CHECK-NEXT: ret7216entry:7217 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)7218 ret void7219}7220 7221define void @test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {7222; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:7223; CHECK: # %bb.0: # %entry7224; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7225; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t7226; CHECK-NEXT: ret7227entry:7228 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7229 ret void7230}7231 7232define void @test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {7233; CHECK-LABEL: test_vsuxseg5_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i64:7234; CHECK: # %bb.0: # %entry7235; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7236; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v137237; CHECK-NEXT: ret7238entry:7239 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)7240 ret void7241}7242 7243define void @test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {7244; CHECK-LABEL: test_vsuxseg5_mask_nxv1i64_triscv.vector.tuple_nxv8i8_5t_nxv1i64:7245; CHECK: # %bb.0: # %entry7246; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7247; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t7248; CHECK-NEXT: ret7249entry:7250 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7251 ret void7252}7253 7254define void @test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {7255; CHECK-LABEL: test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:7256; CHECK: # %bb.0: # %entry7257; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7258; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v147259; CHECK-NEXT: ret7260entry:7261 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)7262 ret void7263}7264 7265define void @test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {7266; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:7267; CHECK: # %bb.0: # %entry7268; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7269; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t7270; CHECK-NEXT: ret7271entry:7272 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7273 ret void7274}7275 7276define void @test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {7277; CHECK-LABEL: test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:7278; CHECK: # %bb.0: # %entry7279; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7280; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v147281; CHECK-NEXT: ret7282entry:7283 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)7284 ret void7285}7286 7287define void @test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {7288; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:7289; CHECK: # %bb.0: # %entry7290; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7291; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t7292; CHECK-NEXT: ret7293entry:7294 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7295 ret void7296}7297 7298define void @test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {7299; CHECK-LABEL: test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:7300; CHECK: # %bb.0: # %entry7301; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7302; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v147303; CHECK-NEXT: ret7304entry:7305 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)7306 ret void7307}7308 7309define void @test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {7310; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:7311; CHECK: # %bb.0: # %entry7312; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7313; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t7314; CHECK-NEXT: ret7315entry:7316 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7317 ret void7318}7319 7320define void @test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {7321; CHECK-LABEL: test_vsuxseg6_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i64:7322; CHECK: # %bb.0: # %entry7323; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7324; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v147325; CHECK-NEXT: ret7326entry:7327 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)7328 ret void7329}7330 7331define void @test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {7332; CHECK-LABEL: test_vsuxseg6_mask_nxv1i64_triscv.vector.tuple_nxv8i8_6t_nxv1i64:7333; CHECK: # %bb.0: # %entry7334; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7335; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t7336; CHECK-NEXT: ret7337entry:7338 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7339 ret void7340}7341 7342define void @test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {7343; CHECK-LABEL: test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:7344; CHECK: # %bb.0: # %entry7345; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7346; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v157347; CHECK-NEXT: ret7348entry:7349 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)7350 ret void7351}7352 7353define void @test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {7354; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:7355; CHECK: # %bb.0: # %entry7356; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7357; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t7358; CHECK-NEXT: ret7359entry:7360 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7361 ret void7362}7363 7364define void @test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {7365; CHECK-LABEL: test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:7366; CHECK: # %bb.0: # %entry7367; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7368; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v157369; CHECK-NEXT: ret7370entry:7371 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)7372 ret void7373}7374 7375define void @test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {7376; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:7377; CHECK: # %bb.0: # %entry7378; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7379; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t7380; CHECK-NEXT: ret7381entry:7382 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7383 ret void7384}7385 7386define void @test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {7387; CHECK-LABEL: test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:7388; CHECK: # %bb.0: # %entry7389; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7390; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v157391; CHECK-NEXT: ret7392entry:7393 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)7394 ret void7395}7396 7397define void @test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {7398; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:7399; CHECK: # %bb.0: # %entry7400; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7401; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t7402; CHECK-NEXT: ret7403entry:7404 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7405 ret void7406}7407 7408define void @test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {7409; CHECK-LABEL: test_vsuxseg7_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i64:7410; CHECK: # %bb.0: # %entry7411; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7412; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v157413; CHECK-NEXT: ret7414entry:7415 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)7416 ret void7417}7418 7419define void @test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {7420; CHECK-LABEL: test_vsuxseg7_mask_nxv1i64_triscv.vector.tuple_nxv8i8_7t_nxv1i64:7421; CHECK: # %bb.0: # %entry7422; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7423; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t7424; CHECK-NEXT: ret7425entry:7426 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7427 ret void7428}7429 7430define void @test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {7431; CHECK-LABEL: test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:7432; CHECK: # %bb.0: # %entry7433; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7434; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v167435; CHECK-NEXT: ret7436entry:7437 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)7438 ret void7439}7440 7441define void @test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {7442; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:7443; CHECK: # %bb.0: # %entry7444; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7445; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t7446; CHECK-NEXT: ret7447entry:7448 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7449 ret void7450}7451 7452define void @test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {7453; CHECK-LABEL: test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:7454; CHECK: # %bb.0: # %entry7455; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7456; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v167457; CHECK-NEXT: ret7458entry:7459 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)7460 ret void7461}7462 7463define void @test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {7464; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:7465; CHECK: # %bb.0: # %entry7466; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7467; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t7468; CHECK-NEXT: ret7469entry:7470 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7471 ret void7472}7473 7474define void @test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {7475; CHECK-LABEL: test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:7476; CHECK: # %bb.0: # %entry7477; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7478; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v167479; CHECK-NEXT: ret7480entry:7481 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)7482 ret void7483}7484 7485define void @test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {7486; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:7487; CHECK: # %bb.0: # %entry7488; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7489; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t7490; CHECK-NEXT: ret7491entry:7492 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7493 ret void7494}7495 7496define void @test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {7497; CHECK-LABEL: test_vsuxseg8_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i64:7498; CHECK: # %bb.0: # %entry7499; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7500; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v167501; CHECK-NEXT: ret7502entry:7503 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)7504 ret void7505}7506 7507define void @test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {7508; CHECK-LABEL: test_vsuxseg8_mask_nxv1i64_triscv.vector.tuple_nxv8i8_8t_nxv1i64:7509; CHECK: # %bb.0: # %entry7510; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma7511; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t7512; CHECK-NEXT: ret7513entry:7514 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)7515 ret void7516}7517 7518define void @test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {7519; CHECK-LABEL: test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:7520; CHECK: # %bb.0: # %entry7521; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7522; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v107523; CHECK-NEXT: ret7524entry:7525 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)7526 ret void7527}7528 7529define void @test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {7530; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:7531; CHECK: # %bb.0: # %entry7532; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7533; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t7534; CHECK-NEXT: ret7535entry:7536 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)7537 ret void7538}7539 7540define void @test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {7541; CHECK-LABEL: test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:7542; CHECK: # %bb.0: # %entry7543; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7544; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v107545; CHECK-NEXT: ret7546entry:7547 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)7548 ret void7549}7550 7551define void @test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {7552; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:7553; CHECK: # %bb.0: # %entry7554; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7555; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t7556; CHECK-NEXT: ret7557entry:7558 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)7559 ret void7560}7561 7562define void @test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {7563; CHECK-LABEL: test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:7564; CHECK: # %bb.0: # %entry7565; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7566; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v107567; CHECK-NEXT: ret7568entry:7569 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)7570 ret void7571}7572 7573define void @test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {7574; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:7575; CHECK: # %bb.0: # %entry7576; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7577; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t7578; CHECK-NEXT: ret7579entry:7580 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)7581 ret void7582}7583 7584define void @test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {7585; CHECK-LABEL: test_vsuxseg2_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i64:7586; CHECK: # %bb.0: # %entry7587; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7588; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v107589; CHECK-NEXT: ret7590entry:7591 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)7592 ret void7593}7594 7595define void @test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {7596; CHECK-LABEL: test_vsuxseg2_mask_nxv1f16_triscv.vector.tuple_nxv2i8_2t_nxv1i64:7597; CHECK: # %bb.0: # %entry7598; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7599; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t7600; CHECK-NEXT: ret7601entry:7602 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)7603 ret void7604}7605 7606define void @test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {7607; CHECK-LABEL: test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:7608; CHECK: # %bb.0: # %entry7609; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7610; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v107611; CHECK-NEXT: ret7612entry:7613 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)7614 ret void7615}7616 7617define void @test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {7618; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:7619; CHECK: # %bb.0: # %entry7620; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7621; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t7622; CHECK-NEXT: ret7623entry:7624 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)7625 ret void7626}7627 7628define void @test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {7629; CHECK-LABEL: test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:7630; CHECK: # %bb.0: # %entry7631; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7632; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v107633; CHECK-NEXT: ret7634entry:7635 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)7636 ret void7637}7638 7639define void @test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {7640; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:7641; CHECK: # %bb.0: # %entry7642; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7643; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t7644; CHECK-NEXT: ret7645entry:7646 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)7647 ret void7648}7649 7650define void @test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {7651; CHECK-LABEL: test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:7652; CHECK: # %bb.0: # %entry7653; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7654; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v107655; CHECK-NEXT: ret7656entry:7657 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)7658 ret void7659}7660 7661define void @test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {7662; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:7663; CHECK: # %bb.0: # %entry7664; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7665; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t7666; CHECK-NEXT: ret7667entry:7668 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)7669 ret void7670}7671 7672define void @test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {7673; CHECK-LABEL: test_vsuxseg2_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i64:7674; CHECK: # %bb.0: # %entry7675; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7676; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v107677; CHECK-NEXT: ret7678entry:7679 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)7680 ret void7681}7682 7683define void @test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {7684; CHECK-LABEL: test_vsuxseg2_mask_nxv2f16_triscv.vector.tuple_nxv4i8_2t_nxv2i64:7685; CHECK: # %bb.0: # %entry7686; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma7687; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t7688; CHECK-NEXT: ret7689entry:7690 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)7691 ret void7692}7693 7694define void @test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {7695; CHECK-LABEL: test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:7696; CHECK: # %bb.0: # %entry7697; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7698; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v107699; CHECK-NEXT: ret7700entry:7701 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)7702 ret void7703}7704 7705define void @test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {7706; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:7707; CHECK: # %bb.0: # %entry7708; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7709; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t7710; CHECK-NEXT: ret7711entry:7712 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)7713 ret void7714}7715 7716define void @test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {7717; CHECK-LABEL: test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:7718; CHECK: # %bb.0: # %entry7719; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7720; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v107721; CHECK-NEXT: ret7722entry:7723 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)7724 ret void7725}7726 7727define void @test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {7728; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:7729; CHECK: # %bb.0: # %entry7730; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7731; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t7732; CHECK-NEXT: ret7733entry:7734 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)7735 ret void7736}7737 7738define void @test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {7739; CHECK-LABEL: test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:7740; CHECK: # %bb.0: # %entry7741; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7742; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v107743; CHECK-NEXT: ret7744entry:7745 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)7746 ret void7747}7748 7749define void @test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {7750; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:7751; CHECK: # %bb.0: # %entry7752; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7753; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t7754; CHECK-NEXT: ret7755entry:7756 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)7757 ret void7758}7759 7760define void @test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {7761; CHECK-LABEL: test_vsuxseg2_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i64:7762; CHECK: # %bb.0: # %entry7763; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7764; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v127765; CHECK-NEXT: ret7766entry:7767 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)7768 ret void7769}7770 7771define void @test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {7772; CHECK-LABEL: test_vsuxseg2_mask_nxv4f16_triscv.vector.tuple_nxv8i8_2t_nxv4i64:7773; CHECK: # %bb.0: # %entry7774; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma7775; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t7776; CHECK-NEXT: ret7777entry:7778 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)7779 ret void7780}7781 7782define void @test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {7783; CHECK-LABEL: test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:7784; CHECK: # %bb.0: # %entry7785; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7786; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v127787; CHECK-NEXT: ret7788entry:7789 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)7790 ret void7791}7792 7793define void @test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {7794; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:7795; CHECK: # %bb.0: # %entry7796; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7797; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t7798; CHECK-NEXT: ret7799entry:7800 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)7801 ret void7802}7803 7804define void @test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {7805; CHECK-LABEL: test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:7806; CHECK: # %bb.0: # %entry7807; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7808; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v127809; CHECK-NEXT: ret7810entry:7811 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)7812 ret void7813}7814 7815define void @test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {7816; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:7817; CHECK: # %bb.0: # %entry7818; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7819; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t7820; CHECK-NEXT: ret7821entry:7822 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)7823 ret void7824}7825 7826define void @test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {7827; CHECK-LABEL: test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:7828; CHECK: # %bb.0: # %entry7829; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7830; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v127831; CHECK-NEXT: ret7832entry:7833 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)7834 ret void7835}7836 7837define void @test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {7838; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:7839; CHECK: # %bb.0: # %entry7840; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7841; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t7842; CHECK-NEXT: ret7843entry:7844 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)7845 ret void7846}7847 7848define void @test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {7849; CHECK-LABEL: test_vsuxseg2_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i64:7850; CHECK: # %bb.0: # %entry7851; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7852; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v167853; CHECK-NEXT: ret7854entry:7855 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)7856 ret void7857}7858 7859define void @test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {7860; CHECK-LABEL: test_vsuxseg2_mask_nxv8f16_triscv.vector.tuple_nxv16i8_2t_nxv8i64:7861; CHECK: # %bb.0: # %entry7862; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma7863; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t7864; CHECK-NEXT: ret7865entry:7866 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)7867 ret void7868}7869 7870define void @test_vsuxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {7871; CHECK-LABEL: test_vsuxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:7872; CHECK: # %bb.0: # %entry7873; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma7874; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v167875; CHECK-NEXT: ret7876entry:7877 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, i64 4)7878 ret void7879}7880 7881define void @test_vsuxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {7882; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:7883; CHECK: # %bb.0: # %entry7884; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma7885; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t7886; CHECK-NEXT: ret7887entry:7888 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)7889 ret void7890}7891 7892define void @test_vsuxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {7893; CHECK-LABEL: test_vsuxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:7894; CHECK: # %bb.0: # %entry7895; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma7896; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v167897; CHECK-NEXT: ret7898entry:7899 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, i64 4)7900 ret void7901}7902 7903define void @test_vsuxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {7904; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:7905; CHECK: # %bb.0: # %entry7906; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma7907; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t7908; CHECK-NEXT: ret7909entry:7910 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)7911 ret void7912}7913 7914define void @test_vsuxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {7915; CHECK-LABEL: test_vsuxseg2_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:7916; CHECK: # %bb.0: # %entry7917; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma7918; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v167919; CHECK-NEXT: ret7920entry:7921 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, i64 4)7922 ret void7923}7924 7925define void @test_vsuxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {7926; CHECK-LABEL: test_vsuxseg2_mask_nxv16f16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:7927; CHECK: # %bb.0: # %entry7928; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma7929; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t7930; CHECK-NEXT: ret7931entry:7932 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)7933 ret void7934}7935 7936define void @test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {7937; CHECK-LABEL: test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:7938; CHECK: # %bb.0: # %entry7939; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7940; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v117941; CHECK-NEXT: ret7942entry:7943 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)7944 ret void7945}7946 7947define void @test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {7948; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:7949; CHECK: # %bb.0: # %entry7950; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7951; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t7952; CHECK-NEXT: ret7953entry:7954 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)7955 ret void7956}7957 7958define void @test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {7959; CHECK-LABEL: test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:7960; CHECK: # %bb.0: # %entry7961; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7962; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v117963; CHECK-NEXT: ret7964entry:7965 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)7966 ret void7967}7968 7969define void @test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {7970; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:7971; CHECK: # %bb.0: # %entry7972; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7973; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t7974; CHECK-NEXT: ret7975entry:7976 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)7977 ret void7978}7979 7980define void @test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {7981; CHECK-LABEL: test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:7982; CHECK: # %bb.0: # %entry7983; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7984; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v117985; CHECK-NEXT: ret7986entry:7987 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)7988 ret void7989}7990 7991define void @test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {7992; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:7993; CHECK: # %bb.0: # %entry7994; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma7995; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t7996; CHECK-NEXT: ret7997entry:7998 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)7999 ret void8000}8001 8002define void @test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {8003; CHECK-LABEL: test_vsuxseg3_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i64:8004; CHECK: # %bb.0: # %entry8005; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8006; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v118007; CHECK-NEXT: ret8008entry:8009 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)8010 ret void8011}8012 8013define void @test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {8014; CHECK-LABEL: test_vsuxseg3_mask_nxv1f16_triscv.vector.tuple_nxv2i8_3t_nxv1i64:8015; CHECK: # %bb.0: # %entry8016; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8017; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t8018; CHECK-NEXT: ret8019entry:8020 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8021 ret void8022}8023 8024define void @test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {8025; CHECK-LABEL: test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:8026; CHECK: # %bb.0: # %entry8027; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8028; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v118029; CHECK-NEXT: ret8030entry:8031 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)8032 ret void8033}8034 8035define void @test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {8036; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:8037; CHECK: # %bb.0: # %entry8038; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8039; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t8040; CHECK-NEXT: ret8041entry:8042 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8043 ret void8044}8045 8046define void @test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {8047; CHECK-LABEL: test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:8048; CHECK: # %bb.0: # %entry8049; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8050; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v118051; CHECK-NEXT: ret8052entry:8053 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)8054 ret void8055}8056 8057define void @test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {8058; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:8059; CHECK: # %bb.0: # %entry8060; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8061; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t8062; CHECK-NEXT: ret8063entry:8064 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8065 ret void8066}8067 8068define void @test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {8069; CHECK-LABEL: test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:8070; CHECK: # %bb.0: # %entry8071; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8072; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v118073; CHECK-NEXT: ret8074entry:8075 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)8076 ret void8077}8078 8079define void @test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {8080; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:8081; CHECK: # %bb.0: # %entry8082; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8083; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t8084; CHECK-NEXT: ret8085entry:8086 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8087 ret void8088}8089 8090define void @test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {8091; CHECK-LABEL: test_vsuxseg3_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i64:8092; CHECK: # %bb.0: # %entry8093; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8094; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v128095; CHECK-NEXT: ret8096entry:8097 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)8098 ret void8099}8100 8101define void @test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {8102; CHECK-LABEL: test_vsuxseg3_mask_nxv2f16_triscv.vector.tuple_nxv4i8_3t_nxv2i64:8103; CHECK: # %bb.0: # %entry8104; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8105; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t8106; CHECK-NEXT: ret8107entry:8108 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8109 ret void8110}8111 8112define void @test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {8113; CHECK-LABEL: test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:8114; CHECK: # %bb.0: # %entry8115; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8116; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v118117; CHECK-NEXT: ret8118entry:8119 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)8120 ret void8121}8122 8123define void @test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {8124; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:8125; CHECK: # %bb.0: # %entry8126; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8127; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t8128; CHECK-NEXT: ret8129entry:8130 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8131 ret void8132}8133 8134define void @test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {8135; CHECK-LABEL: test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:8136; CHECK: # %bb.0: # %entry8137; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8138; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v118139; CHECK-NEXT: ret8140entry:8141 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)8142 ret void8143}8144 8145define void @test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {8146; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:8147; CHECK: # %bb.0: # %entry8148; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8149; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t8150; CHECK-NEXT: ret8151entry:8152 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8153 ret void8154}8155 8156define void @test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {8157; CHECK-LABEL: test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:8158; CHECK: # %bb.0: # %entry8159; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8160; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v128161; CHECK-NEXT: ret8162entry:8163 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)8164 ret void8165}8166 8167define void @test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {8168; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:8169; CHECK: # %bb.0: # %entry8170; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8171; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t8172; CHECK-NEXT: ret8173entry:8174 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8175 ret void8176}8177 8178define void @test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {8179; CHECK-LABEL: test_vsuxseg3_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i64:8180; CHECK: # %bb.0: # %entry8181; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8182; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v128183; CHECK-NEXT: ret8184entry:8185 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)8186 ret void8187}8188 8189define void @test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {8190; CHECK-LABEL: test_vsuxseg3_mask_nxv4f16_triscv.vector.tuple_nxv8i8_3t_nxv4i64:8191; CHECK: # %bb.0: # %entry8192; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8193; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t8194; CHECK-NEXT: ret8195entry:8196 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8197 ret void8198}8199 8200define void @test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {8201; CHECK-LABEL: test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:8202; CHECK: # %bb.0: # %entry8203; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8204; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v148205; CHECK-NEXT: ret8206entry:8207 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)8208 ret void8209}8210 8211define void @test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {8212; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:8213; CHECK: # %bb.0: # %entry8214; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8215; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t8216; CHECK-NEXT: ret8217entry:8218 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8219 ret void8220}8221 8222define void @test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {8223; CHECK-LABEL: test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:8224; CHECK: # %bb.0: # %entry8225; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8226; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v148227; CHECK-NEXT: ret8228entry:8229 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)8230 ret void8231}8232 8233define void @test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {8234; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:8235; CHECK: # %bb.0: # %entry8236; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8237; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v14, v0.t8238; CHECK-NEXT: ret8239entry:8240 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8241 ret void8242}8243 8244define void @test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {8245; CHECK-LABEL: test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:8246; CHECK: # %bb.0: # %entry8247; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8248; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v168249; CHECK-NEXT: ret8250entry:8251 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)8252 ret void8253}8254 8255define void @test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {8256; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:8257; CHECK: # %bb.0: # %entry8258; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8259; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t8260; CHECK-NEXT: ret8261entry:8262 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8263 ret void8264}8265 8266define void @test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {8267; CHECK-LABEL: test_vsuxseg3_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i64:8268; CHECK: # %bb.0: # %entry8269; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8270; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v168271; CHECK-NEXT: ret8272entry:8273 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)8274 ret void8275}8276 8277define void @test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {8278; CHECK-LABEL: test_vsuxseg3_mask_nxv8f16_triscv.vector.tuple_nxv16i8_3t_nxv8i64:8279; CHECK: # %bb.0: # %entry8280; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8281; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v16, v0.t8282; CHECK-NEXT: ret8283entry:8284 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8285 ret void8286}8287 8288define void @test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {8289; CHECK-LABEL: test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:8290; CHECK: # %bb.0: # %entry8291; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8292; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v128293; CHECK-NEXT: ret8294entry:8295 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)8296 ret void8297}8298 8299define void @test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {8300; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:8301; CHECK: # %bb.0: # %entry8302; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8303; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t8304; CHECK-NEXT: ret8305entry:8306 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8307 ret void8308}8309 8310define void @test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {8311; CHECK-LABEL: test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:8312; CHECK: # %bb.0: # %entry8313; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8314; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v128315; CHECK-NEXT: ret8316entry:8317 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)8318 ret void8319}8320 8321define void @test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {8322; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:8323; CHECK: # %bb.0: # %entry8324; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8325; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t8326; CHECK-NEXT: ret8327entry:8328 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8329 ret void8330}8331 8332define void @test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {8333; CHECK-LABEL: test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:8334; CHECK: # %bb.0: # %entry8335; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8336; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v128337; CHECK-NEXT: ret8338entry:8339 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)8340 ret void8341}8342 8343define void @test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {8344; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:8345; CHECK: # %bb.0: # %entry8346; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8347; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t8348; CHECK-NEXT: ret8349entry:8350 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8351 ret void8352}8353 8354define void @test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {8355; CHECK-LABEL: test_vsuxseg4_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i64:8356; CHECK: # %bb.0: # %entry8357; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8358; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v128359; CHECK-NEXT: ret8360entry:8361 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)8362 ret void8363}8364 8365define void @test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {8366; CHECK-LABEL: test_vsuxseg4_mask_nxv1f16_triscv.vector.tuple_nxv2i8_4t_nxv1i64:8367; CHECK: # %bb.0: # %entry8368; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8369; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t8370; CHECK-NEXT: ret8371entry:8372 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8373 ret void8374}8375 8376define void @test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {8377; CHECK-LABEL: test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:8378; CHECK: # %bb.0: # %entry8379; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8380; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v128381; CHECK-NEXT: ret8382entry:8383 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)8384 ret void8385}8386 8387define void @test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {8388; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:8389; CHECK: # %bb.0: # %entry8390; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8391; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t8392; CHECK-NEXT: ret8393entry:8394 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8395 ret void8396}8397 8398define void @test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {8399; CHECK-LABEL: test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:8400; CHECK: # %bb.0: # %entry8401; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8402; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v128403; CHECK-NEXT: ret8404entry:8405 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)8406 ret void8407}8408 8409define void @test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {8410; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:8411; CHECK: # %bb.0: # %entry8412; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8413; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t8414; CHECK-NEXT: ret8415entry:8416 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8417 ret void8418}8419 8420define void @test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {8421; CHECK-LABEL: test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:8422; CHECK: # %bb.0: # %entry8423; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8424; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v128425; CHECK-NEXT: ret8426entry:8427 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)8428 ret void8429}8430 8431define void @test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {8432; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:8433; CHECK: # %bb.0: # %entry8434; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8435; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t8436; CHECK-NEXT: ret8437entry:8438 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8439 ret void8440}8441 8442define void @test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {8443; CHECK-LABEL: test_vsuxseg4_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i64:8444; CHECK: # %bb.0: # %entry8445; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8446; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v128447; CHECK-NEXT: ret8448entry:8449 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)8450 ret void8451}8452 8453define void @test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {8454; CHECK-LABEL: test_vsuxseg4_mask_nxv2f16_triscv.vector.tuple_nxv4i8_4t_nxv2i64:8455; CHECK: # %bb.0: # %entry8456; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8457; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t8458; CHECK-NEXT: ret8459entry:8460 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8461 ret void8462}8463 8464define void @test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {8465; CHECK-LABEL: test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:8466; CHECK: # %bb.0: # %entry8467; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8468; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v128469; CHECK-NEXT: ret8470entry:8471 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)8472 ret void8473}8474 8475define void @test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {8476; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:8477; CHECK: # %bb.0: # %entry8478; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8479; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t8480; CHECK-NEXT: ret8481entry:8482 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8483 ret void8484}8485 8486define void @test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {8487; CHECK-LABEL: test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:8488; CHECK: # %bb.0: # %entry8489; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8490; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v128491; CHECK-NEXT: ret8492entry:8493 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)8494 ret void8495}8496 8497define void @test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {8498; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:8499; CHECK: # %bb.0: # %entry8500; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8501; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t8502; CHECK-NEXT: ret8503entry:8504 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8505 ret void8506}8507 8508define void @test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {8509; CHECK-LABEL: test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:8510; CHECK: # %bb.0: # %entry8511; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8512; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v128513; CHECK-NEXT: ret8514entry:8515 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)8516 ret void8517}8518 8519define void @test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {8520; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:8521; CHECK: # %bb.0: # %entry8522; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8523; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t8524; CHECK-NEXT: ret8525entry:8526 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8527 ret void8528}8529 8530define void @test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {8531; CHECK-LABEL: test_vsuxseg4_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i64:8532; CHECK: # %bb.0: # %entry8533; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8534; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v128535; CHECK-NEXT: ret8536entry:8537 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)8538 ret void8539}8540 8541define void @test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {8542; CHECK-LABEL: test_vsuxseg4_mask_nxv4f16_triscv.vector.tuple_nxv8i8_4t_nxv4i64:8543; CHECK: # %bb.0: # %entry8544; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8545; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t8546; CHECK-NEXT: ret8547entry:8548 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8549 ret void8550}8551 8552define void @test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {8553; CHECK-LABEL: test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:8554; CHECK: # %bb.0: # %entry8555; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8556; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v168557; CHECK-NEXT: ret8558entry:8559 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)8560 ret void8561}8562 8563define void @test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {8564; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:8565; CHECK: # %bb.0: # %entry8566; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8567; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t8568; CHECK-NEXT: ret8569entry:8570 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8571 ret void8572}8573 8574define void @test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {8575; CHECK-LABEL: test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:8576; CHECK: # %bb.0: # %entry8577; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8578; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v168579; CHECK-NEXT: ret8580entry:8581 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)8582 ret void8583}8584 8585define void @test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {8586; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:8587; CHECK: # %bb.0: # %entry8588; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8589; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t8590; CHECK-NEXT: ret8591entry:8592 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8593 ret void8594}8595 8596define void @test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {8597; CHECK-LABEL: test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:8598; CHECK: # %bb.0: # %entry8599; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8600; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v168601; CHECK-NEXT: ret8602entry:8603 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)8604 ret void8605}8606 8607define void @test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {8608; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:8609; CHECK: # %bb.0: # %entry8610; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8611; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t8612; CHECK-NEXT: ret8613entry:8614 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8615 ret void8616}8617 8618define void @test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {8619; CHECK-LABEL: test_vsuxseg4_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i64:8620; CHECK: # %bb.0: # %entry8621; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8622; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v168623; CHECK-NEXT: ret8624entry:8625 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)8626 ret void8627}8628 8629define void @test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {8630; CHECK-LABEL: test_vsuxseg4_mask_nxv8f16_triscv.vector.tuple_nxv16i8_4t_nxv8i64:8631; CHECK: # %bb.0: # %entry8632; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma8633; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t8634; CHECK-NEXT: ret8635entry:8636 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)8637 ret void8638}8639 8640define void @test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {8641; CHECK-LABEL: test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:8642; CHECK: # %bb.0: # %entry8643; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8644; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v138645; CHECK-NEXT: ret8646entry:8647 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)8648 ret void8649}8650 8651define void @test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {8652; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:8653; CHECK: # %bb.0: # %entry8654; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8655; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t8656; CHECK-NEXT: ret8657entry:8658 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8659 ret void8660}8661 8662define void @test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {8663; CHECK-LABEL: test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:8664; CHECK: # %bb.0: # %entry8665; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8666; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v138667; CHECK-NEXT: ret8668entry:8669 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)8670 ret void8671}8672 8673define void @test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {8674; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:8675; CHECK: # %bb.0: # %entry8676; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8677; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t8678; CHECK-NEXT: ret8679entry:8680 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8681 ret void8682}8683 8684define void @test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {8685; CHECK-LABEL: test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:8686; CHECK: # %bb.0: # %entry8687; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8688; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v138689; CHECK-NEXT: ret8690entry:8691 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)8692 ret void8693}8694 8695define void @test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {8696; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:8697; CHECK: # %bb.0: # %entry8698; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8699; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t8700; CHECK-NEXT: ret8701entry:8702 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8703 ret void8704}8705 8706define void @test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {8707; CHECK-LABEL: test_vsuxseg5_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i64:8708; CHECK: # %bb.0: # %entry8709; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8710; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v138711; CHECK-NEXT: ret8712entry:8713 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)8714 ret void8715}8716 8717define void @test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {8718; CHECK-LABEL: test_vsuxseg5_mask_nxv1f16_triscv.vector.tuple_nxv2i8_5t_nxv1i64:8719; CHECK: # %bb.0: # %entry8720; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8721; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t8722; CHECK-NEXT: ret8723entry:8724 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8725 ret void8726}8727 8728define void @test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {8729; CHECK-LABEL: test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:8730; CHECK: # %bb.0: # %entry8731; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8732; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v138733; CHECK-NEXT: ret8734entry:8735 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)8736 ret void8737}8738 8739define void @test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {8740; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:8741; CHECK: # %bb.0: # %entry8742; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8743; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t8744; CHECK-NEXT: ret8745entry:8746 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8747 ret void8748}8749 8750define void @test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {8751; CHECK-LABEL: test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:8752; CHECK: # %bb.0: # %entry8753; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8754; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v138755; CHECK-NEXT: ret8756entry:8757 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)8758 ret void8759}8760 8761define void @test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {8762; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:8763; CHECK: # %bb.0: # %entry8764; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8765; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t8766; CHECK-NEXT: ret8767entry:8768 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8769 ret void8770}8771 8772define void @test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {8773; CHECK-LABEL: test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:8774; CHECK: # %bb.0: # %entry8775; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8776; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v138777; CHECK-NEXT: ret8778entry:8779 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)8780 ret void8781}8782 8783define void @test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {8784; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:8785; CHECK: # %bb.0: # %entry8786; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8787; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t8788; CHECK-NEXT: ret8789entry:8790 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8791 ret void8792}8793 8794define void @test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {8795; CHECK-LABEL: test_vsuxseg5_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i64:8796; CHECK: # %bb.0: # %entry8797; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8798; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v148799; CHECK-NEXT: ret8800entry:8801 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)8802 ret void8803}8804 8805define void @test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {8806; CHECK-LABEL: test_vsuxseg5_mask_nxv2f16_triscv.vector.tuple_nxv4i8_5t_nxv2i64:8807; CHECK: # %bb.0: # %entry8808; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8809; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v14, v0.t8810; CHECK-NEXT: ret8811entry:8812 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)8813 ret void8814}8815 8816define void @test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {8817; CHECK-LABEL: test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:8818; CHECK: # %bb.0: # %entry8819; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8820; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v138821; CHECK-NEXT: ret8822entry:8823 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)8824 ret void8825}8826 8827define void @test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {8828; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:8829; CHECK: # %bb.0: # %entry8830; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8831; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t8832; CHECK-NEXT: ret8833entry:8834 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8835 ret void8836}8837 8838define void @test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {8839; CHECK-LABEL: test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:8840; CHECK: # %bb.0: # %entry8841; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8842; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v138843; CHECK-NEXT: ret8844entry:8845 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)8846 ret void8847}8848 8849define void @test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {8850; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:8851; CHECK: # %bb.0: # %entry8852; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8853; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t8854; CHECK-NEXT: ret8855entry:8856 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8857 ret void8858}8859 8860define void @test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {8861; CHECK-LABEL: test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:8862; CHECK: # %bb.0: # %entry8863; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8864; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v148865; CHECK-NEXT: ret8866entry:8867 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)8868 ret void8869}8870 8871define void @test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {8872; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:8873; CHECK: # %bb.0: # %entry8874; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8875; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v14, v0.t8876; CHECK-NEXT: ret8877entry:8878 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8879 ret void8880}8881 8882define void @test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {8883; CHECK-LABEL: test_vsuxseg5_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i64:8884; CHECK: # %bb.0: # %entry8885; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8886; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v168887; CHECK-NEXT: ret8888entry:8889 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)8890 ret void8891}8892 8893define void @test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {8894; CHECK-LABEL: test_vsuxseg5_mask_nxv4f16_triscv.vector.tuple_nxv8i8_5t_nxv4i64:8895; CHECK: # %bb.0: # %entry8896; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma8897; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v16, v0.t8898; CHECK-NEXT: ret8899entry:8900 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)8901 ret void8902}8903 8904define void @test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {8905; CHECK-LABEL: test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:8906; CHECK: # %bb.0: # %entry8907; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8908; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v148909; CHECK-NEXT: ret8910entry:8911 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)8912 ret void8913}8914 8915define void @test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {8916; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:8917; CHECK: # %bb.0: # %entry8918; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8919; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t8920; CHECK-NEXT: ret8921entry:8922 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8923 ret void8924}8925 8926define void @test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {8927; CHECK-LABEL: test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:8928; CHECK: # %bb.0: # %entry8929; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8930; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v148931; CHECK-NEXT: ret8932entry:8933 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)8934 ret void8935}8936 8937define void @test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {8938; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:8939; CHECK: # %bb.0: # %entry8940; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8941; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t8942; CHECK-NEXT: ret8943entry:8944 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8945 ret void8946}8947 8948define void @test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {8949; CHECK-LABEL: test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:8950; CHECK: # %bb.0: # %entry8951; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8952; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v148953; CHECK-NEXT: ret8954entry:8955 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)8956 ret void8957}8958 8959define void @test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {8960; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:8961; CHECK: # %bb.0: # %entry8962; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8963; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t8964; CHECK-NEXT: ret8965entry:8966 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8967 ret void8968}8969 8970define void @test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {8971; CHECK-LABEL: test_vsuxseg6_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i64:8972; CHECK: # %bb.0: # %entry8973; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8974; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v148975; CHECK-NEXT: ret8976entry:8977 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)8978 ret void8979}8980 8981define void @test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {8982; CHECK-LABEL: test_vsuxseg6_mask_nxv1f16_triscv.vector.tuple_nxv2i8_6t_nxv1i64:8983; CHECK: # %bb.0: # %entry8984; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma8985; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t8986; CHECK-NEXT: ret8987entry:8988 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)8989 ret void8990}8991 8992define void @test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {8993; CHECK-LABEL: test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:8994; CHECK: # %bb.0: # %entry8995; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma8996; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v148997; CHECK-NEXT: ret8998entry:8999 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)9000 ret void9001}9002 9003define void @test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {9004; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:9005; CHECK: # %bb.0: # %entry9006; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9007; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t9008; CHECK-NEXT: ret9009entry:9010 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9011 ret void9012}9013 9014define void @test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {9015; CHECK-LABEL: test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:9016; CHECK: # %bb.0: # %entry9017; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9018; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v149019; CHECK-NEXT: ret9020entry:9021 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)9022 ret void9023}9024 9025define void @test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {9026; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:9027; CHECK: # %bb.0: # %entry9028; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9029; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t9030; CHECK-NEXT: ret9031entry:9032 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9033 ret void9034}9035 9036define void @test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {9037; CHECK-LABEL: test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:9038; CHECK: # %bb.0: # %entry9039; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9040; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v149041; CHECK-NEXT: ret9042entry:9043 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)9044 ret void9045}9046 9047define void @test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {9048; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:9049; CHECK: # %bb.0: # %entry9050; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9051; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t9052; CHECK-NEXT: ret9053entry:9054 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9055 ret void9056}9057 9058define void @test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {9059; CHECK-LABEL: test_vsuxseg6_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i64:9060; CHECK: # %bb.0: # %entry9061; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9062; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v149063; CHECK-NEXT: ret9064entry:9065 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)9066 ret void9067}9068 9069define void @test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {9070; CHECK-LABEL: test_vsuxseg6_mask_nxv2f16_triscv.vector.tuple_nxv4i8_6t_nxv2i64:9071; CHECK: # %bb.0: # %entry9072; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9073; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t9074; CHECK-NEXT: ret9075entry:9076 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9077 ret void9078}9079 9080define void @test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {9081; CHECK-LABEL: test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:9082; CHECK: # %bb.0: # %entry9083; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9084; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v149085; CHECK-NEXT: ret9086entry:9087 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)9088 ret void9089}9090 9091define void @test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {9092; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:9093; CHECK: # %bb.0: # %entry9094; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9095; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t9096; CHECK-NEXT: ret9097entry:9098 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9099 ret void9100}9101 9102define void @test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {9103; CHECK-LABEL: test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:9104; CHECK: # %bb.0: # %entry9105; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9106; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v149107; CHECK-NEXT: ret9108entry:9109 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)9110 ret void9111}9112 9113define void @test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {9114; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:9115; CHECK: # %bb.0: # %entry9116; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9117; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t9118; CHECK-NEXT: ret9119entry:9120 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9121 ret void9122}9123 9124define void @test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {9125; CHECK-LABEL: test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:9126; CHECK: # %bb.0: # %entry9127; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9128; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v149129; CHECK-NEXT: ret9130entry:9131 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)9132 ret void9133}9134 9135define void @test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {9136; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:9137; CHECK: # %bb.0: # %entry9138; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9139; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t9140; CHECK-NEXT: ret9141entry:9142 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9143 ret void9144}9145 9146define void @test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {9147; CHECK-LABEL: test_vsuxseg6_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i64:9148; CHECK: # %bb.0: # %entry9149; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9150; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v169151; CHECK-NEXT: ret9152entry:9153 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)9154 ret void9155}9156 9157define void @test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {9158; CHECK-LABEL: test_vsuxseg6_mask_nxv4f16_triscv.vector.tuple_nxv8i8_6t_nxv4i64:9159; CHECK: # %bb.0: # %entry9160; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9161; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v16, v0.t9162; CHECK-NEXT: ret9163entry:9164 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9165 ret void9166}9167 9168define void @test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {9169; CHECK-LABEL: test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:9170; CHECK: # %bb.0: # %entry9171; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9172; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v159173; CHECK-NEXT: ret9174entry:9175 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)9176 ret void9177}9178 9179define void @test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {9180; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:9181; CHECK: # %bb.0: # %entry9182; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9183; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t9184; CHECK-NEXT: ret9185entry:9186 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9187 ret void9188}9189 9190define void @test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {9191; CHECK-LABEL: test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:9192; CHECK: # %bb.0: # %entry9193; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9194; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v159195; CHECK-NEXT: ret9196entry:9197 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)9198 ret void9199}9200 9201define void @test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {9202; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:9203; CHECK: # %bb.0: # %entry9204; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9205; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t9206; CHECK-NEXT: ret9207entry:9208 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9209 ret void9210}9211 9212define void @test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {9213; CHECK-LABEL: test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:9214; CHECK: # %bb.0: # %entry9215; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9216; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v159217; CHECK-NEXT: ret9218entry:9219 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)9220 ret void9221}9222 9223define void @test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {9224; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:9225; CHECK: # %bb.0: # %entry9226; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9227; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t9228; CHECK-NEXT: ret9229entry:9230 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9231 ret void9232}9233 9234define void @test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {9235; CHECK-LABEL: test_vsuxseg7_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i64:9236; CHECK: # %bb.0: # %entry9237; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9238; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v159239; CHECK-NEXT: ret9240entry:9241 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)9242 ret void9243}9244 9245define void @test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {9246; CHECK-LABEL: test_vsuxseg7_mask_nxv1f16_triscv.vector.tuple_nxv2i8_7t_nxv1i64:9247; CHECK: # %bb.0: # %entry9248; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9249; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t9250; CHECK-NEXT: ret9251entry:9252 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9253 ret void9254}9255 9256define void @test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {9257; CHECK-LABEL: test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:9258; CHECK: # %bb.0: # %entry9259; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9260; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v159261; CHECK-NEXT: ret9262entry:9263 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)9264 ret void9265}9266 9267define void @test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {9268; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:9269; CHECK: # %bb.0: # %entry9270; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9271; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t9272; CHECK-NEXT: ret9273entry:9274 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9275 ret void9276}9277 9278define void @test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {9279; CHECK-LABEL: test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:9280; CHECK: # %bb.0: # %entry9281; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9282; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v159283; CHECK-NEXT: ret9284entry:9285 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)9286 ret void9287}9288 9289define void @test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {9290; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:9291; CHECK: # %bb.0: # %entry9292; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9293; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t9294; CHECK-NEXT: ret9295entry:9296 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9297 ret void9298}9299 9300define void @test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {9301; CHECK-LABEL: test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:9302; CHECK: # %bb.0: # %entry9303; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9304; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v159305; CHECK-NEXT: ret9306entry:9307 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)9308 ret void9309}9310 9311define void @test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {9312; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:9313; CHECK: # %bb.0: # %entry9314; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9315; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t9316; CHECK-NEXT: ret9317entry:9318 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9319 ret void9320}9321 9322define void @test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {9323; CHECK-LABEL: test_vsuxseg7_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i64:9324; CHECK: # %bb.0: # %entry9325; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9326; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v169327; CHECK-NEXT: ret9328entry:9329 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)9330 ret void9331}9332 9333define void @test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {9334; CHECK-LABEL: test_vsuxseg7_mask_nxv2f16_triscv.vector.tuple_nxv4i8_7t_nxv2i64:9335; CHECK: # %bb.0: # %entry9336; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9337; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t9338; CHECK-NEXT: ret9339entry:9340 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9341 ret void9342}9343 9344define void @test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {9345; CHECK-LABEL: test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:9346; CHECK: # %bb.0: # %entry9347; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9348; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v159349; CHECK-NEXT: ret9350entry:9351 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)9352 ret void9353}9354 9355define void @test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {9356; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:9357; CHECK: # %bb.0: # %entry9358; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9359; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t9360; CHECK-NEXT: ret9361entry:9362 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9363 ret void9364}9365 9366define void @test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {9367; CHECK-LABEL: test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:9368; CHECK: # %bb.0: # %entry9369; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9370; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v159371; CHECK-NEXT: ret9372entry:9373 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)9374 ret void9375}9376 9377define void @test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {9378; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:9379; CHECK: # %bb.0: # %entry9380; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9381; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t9382; CHECK-NEXT: ret9383entry:9384 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9385 ret void9386}9387 9388define void @test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {9389; CHECK-LABEL: test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:9390; CHECK: # %bb.0: # %entry9391; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9392; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v169393; CHECK-NEXT: ret9394entry:9395 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)9396 ret void9397}9398 9399define void @test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {9400; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:9401; CHECK: # %bb.0: # %entry9402; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9403; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t9404; CHECK-NEXT: ret9405entry:9406 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9407 ret void9408}9409 9410define void @test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {9411; CHECK-LABEL: test_vsuxseg7_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i64:9412; CHECK: # %bb.0: # %entry9413; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9414; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v169415; CHECK-NEXT: ret9416entry:9417 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)9418 ret void9419}9420 9421define void @test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {9422; CHECK-LABEL: test_vsuxseg7_mask_nxv4f16_triscv.vector.tuple_nxv8i8_7t_nxv4i64:9423; CHECK: # %bb.0: # %entry9424; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9425; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t9426; CHECK-NEXT: ret9427entry:9428 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9429 ret void9430}9431 9432define void @test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {9433; CHECK-LABEL: test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:9434; CHECK: # %bb.0: # %entry9435; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9436; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v169437; CHECK-NEXT: ret9438entry:9439 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)9440 ret void9441}9442 9443define void @test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {9444; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:9445; CHECK: # %bb.0: # %entry9446; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9447; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t9448; CHECK-NEXT: ret9449entry:9450 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9451 ret void9452}9453 9454define void @test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {9455; CHECK-LABEL: test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:9456; CHECK: # %bb.0: # %entry9457; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9458; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v169459; CHECK-NEXT: ret9460entry:9461 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)9462 ret void9463}9464 9465define void @test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {9466; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:9467; CHECK: # %bb.0: # %entry9468; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9469; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t9470; CHECK-NEXT: ret9471entry:9472 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9473 ret void9474}9475 9476define void @test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {9477; CHECK-LABEL: test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:9478; CHECK: # %bb.0: # %entry9479; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9480; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v169481; CHECK-NEXT: ret9482entry:9483 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)9484 ret void9485}9486 9487define void @test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {9488; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:9489; CHECK: # %bb.0: # %entry9490; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9491; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t9492; CHECK-NEXT: ret9493entry:9494 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9495 ret void9496}9497 9498define void @test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {9499; CHECK-LABEL: test_vsuxseg8_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i64:9500; CHECK: # %bb.0: # %entry9501; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9502; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v169503; CHECK-NEXT: ret9504entry:9505 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)9506 ret void9507}9508 9509define void @test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {9510; CHECK-LABEL: test_vsuxseg8_mask_nxv1f16_triscv.vector.tuple_nxv2i8_8t_nxv1i64:9511; CHECK: # %bb.0: # %entry9512; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma9513; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t9514; CHECK-NEXT: ret9515entry:9516 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)9517 ret void9518}9519 9520define void @test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {9521; CHECK-LABEL: test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:9522; CHECK: # %bb.0: # %entry9523; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9524; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v169525; CHECK-NEXT: ret9526entry:9527 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)9528 ret void9529}9530 9531define void @test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {9532; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:9533; CHECK: # %bb.0: # %entry9534; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9535; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t9536; CHECK-NEXT: ret9537entry:9538 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9539 ret void9540}9541 9542define void @test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {9543; CHECK-LABEL: test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:9544; CHECK: # %bb.0: # %entry9545; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9546; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v169547; CHECK-NEXT: ret9548entry:9549 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)9550 ret void9551}9552 9553define void @test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {9554; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:9555; CHECK: # %bb.0: # %entry9556; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9557; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t9558; CHECK-NEXT: ret9559entry:9560 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9561 ret void9562}9563 9564define void @test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {9565; CHECK-LABEL: test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:9566; CHECK: # %bb.0: # %entry9567; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9568; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v169569; CHECK-NEXT: ret9570entry:9571 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)9572 ret void9573}9574 9575define void @test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {9576; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:9577; CHECK: # %bb.0: # %entry9578; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9579; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t9580; CHECK-NEXT: ret9581entry:9582 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9583 ret void9584}9585 9586define void @test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {9587; CHECK-LABEL: test_vsuxseg8_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i64:9588; CHECK: # %bb.0: # %entry9589; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9590; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v169591; CHECK-NEXT: ret9592entry:9593 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)9594 ret void9595}9596 9597define void @test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {9598; CHECK-LABEL: test_vsuxseg8_mask_nxv2f16_triscv.vector.tuple_nxv4i8_8t_nxv2i64:9599; CHECK: # %bb.0: # %entry9600; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma9601; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t9602; CHECK-NEXT: ret9603entry:9604 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)9605 ret void9606}9607 9608define void @test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {9609; CHECK-LABEL: test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:9610; CHECK: # %bb.0: # %entry9611; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9612; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v169613; CHECK-NEXT: ret9614entry:9615 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)9616 ret void9617}9618 9619define void @test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {9620; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:9621; CHECK: # %bb.0: # %entry9622; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9623; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t9624; CHECK-NEXT: ret9625entry:9626 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9627 ret void9628}9629 9630define void @test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {9631; CHECK-LABEL: test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:9632; CHECK: # %bb.0: # %entry9633; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9634; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v169635; CHECK-NEXT: ret9636entry:9637 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)9638 ret void9639}9640 9641define void @test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {9642; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:9643; CHECK: # %bb.0: # %entry9644; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9645; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t9646; CHECK-NEXT: ret9647entry:9648 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9649 ret void9650}9651 9652define void @test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {9653; CHECK-LABEL: test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:9654; CHECK: # %bb.0: # %entry9655; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9656; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v169657; CHECK-NEXT: ret9658entry:9659 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)9660 ret void9661}9662 9663define void @test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {9664; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:9665; CHECK: # %bb.0: # %entry9666; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9667; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t9668; CHECK-NEXT: ret9669entry:9670 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9671 ret void9672}9673 9674define void @test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {9675; CHECK-LABEL: test_vsuxseg8_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i64:9676; CHECK: # %bb.0: # %entry9677; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9678; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v169679; CHECK-NEXT: ret9680entry:9681 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)9682 ret void9683}9684 9685define void @test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {9686; CHECK-LABEL: test_vsuxseg8_mask_nxv4f16_triscv.vector.tuple_nxv8i8_8t_nxv4i64:9687; CHECK: # %bb.0: # %entry9688; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma9689; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t9690; CHECK-NEXT: ret9691entry:9692 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)9693 ret void9694}9695 9696define void @test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {9697; CHECK-LABEL: test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:9698; CHECK: # %bb.0: # %entry9699; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9700; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v109701; CHECK-NEXT: ret9702entry:9703 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)9704 ret void9705}9706 9707define void @test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {9708; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i8:9709; CHECK: # %bb.0: # %entry9710; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9711; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t9712; CHECK-NEXT: ret9713entry:9714 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)9715 ret void9716}9717 9718define void @test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {9719; CHECK-LABEL: test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:9720; CHECK: # %bb.0: # %entry9721; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9722; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v109723; CHECK-NEXT: ret9724entry:9725 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)9726 ret void9727}9728 9729define void @test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {9730; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i16:9731; CHECK: # %bb.0: # %entry9732; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9733; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t9734; CHECK-NEXT: ret9735entry:9736 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)9737 ret void9738}9739 9740define void @test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {9741; CHECK-LABEL: test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:9742; CHECK: # %bb.0: # %entry9743; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9744; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v109745; CHECK-NEXT: ret9746entry:9747 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)9748 ret void9749}9750 9751define void @test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {9752; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i32:9753; CHECK: # %bb.0: # %entry9754; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9755; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t9756; CHECK-NEXT: ret9757entry:9758 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)9759 ret void9760}9761 9762define void @test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {9763; CHECK-LABEL: test_vsuxseg2_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i64:9764; CHECK: # %bb.0: # %entry9765; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9766; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v109767; CHECK-NEXT: ret9768entry:9769 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)9770 ret void9771}9772 9773define void @test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {9774; CHECK-LABEL: test_vsuxseg2_mask_nxv1f32_triscv.vector.tuple_nxv4i8_2t_nxv1i64:9775; CHECK: # %bb.0: # %entry9776; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma9777; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t9778; CHECK-NEXT: ret9779entry:9780 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)9781 ret void9782}9783 9784define void @test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {9785; CHECK-LABEL: test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:9786; CHECK: # %bb.0: # %entry9787; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9788; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v109789; CHECK-NEXT: ret9790entry:9791 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)9792 ret void9793}9794 9795define void @test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {9796; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i8:9797; CHECK: # %bb.0: # %entry9798; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9799; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t9800; CHECK-NEXT: ret9801entry:9802 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)9803 ret void9804}9805 9806define void @test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {9807; CHECK-LABEL: test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:9808; CHECK: # %bb.0: # %entry9809; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9810; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v109811; CHECK-NEXT: ret9812entry:9813 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)9814 ret void9815}9816 9817define void @test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {9818; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i16:9819; CHECK: # %bb.0: # %entry9820; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9821; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t9822; CHECK-NEXT: ret9823entry:9824 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)9825 ret void9826}9827 9828define void @test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {9829; CHECK-LABEL: test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:9830; CHECK: # %bb.0: # %entry9831; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9832; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v109833; CHECK-NEXT: ret9834entry:9835 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)9836 ret void9837}9838 9839define void @test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {9840; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i32:9841; CHECK: # %bb.0: # %entry9842; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9843; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t9844; CHECK-NEXT: ret9845entry:9846 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)9847 ret void9848}9849 9850define void @test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {9851; CHECK-LABEL: test_vsuxseg2_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i64:9852; CHECK: # %bb.0: # %entry9853; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9854; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v109855; CHECK-NEXT: ret9856entry:9857 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)9858 ret void9859}9860 9861define void @test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {9862; CHECK-LABEL: test_vsuxseg2_mask_nxv2f32_triscv.vector.tuple_nxv8i8_2t_nxv2i64:9863; CHECK: # %bb.0: # %entry9864; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma9865; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t9866; CHECK-NEXT: ret9867entry:9868 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)9869 ret void9870}9871 9872define void @test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {9873; CHECK-LABEL: test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:9874; CHECK: # %bb.0: # %entry9875; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9876; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v129877; CHECK-NEXT: ret9878entry:9879 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 5)9880 ret void9881}9882 9883define void @test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {9884; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i8:9885; CHECK: # %bb.0: # %entry9886; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9887; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t9888; CHECK-NEXT: ret9889entry:9890 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)9891 ret void9892}9893 9894define void @test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {9895; CHECK-LABEL: test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:9896; CHECK: # %bb.0: # %entry9897; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9898; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v129899; CHECK-NEXT: ret9900entry:9901 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 5)9902 ret void9903}9904 9905define void @test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {9906; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i16:9907; CHECK: # %bb.0: # %entry9908; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9909; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t9910; CHECK-NEXT: ret9911entry:9912 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)9913 ret void9914}9915 9916define void @test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {9917; CHECK-LABEL: test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:9918; CHECK: # %bb.0: # %entry9919; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9920; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v129921; CHECK-NEXT: ret9922entry:9923 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 5)9924 ret void9925}9926 9927define void @test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {9928; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i32:9929; CHECK: # %bb.0: # %entry9930; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9931; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t9932; CHECK-NEXT: ret9933entry:9934 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)9935 ret void9936}9937 9938define void @test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {9939; CHECK-LABEL: test_vsuxseg2_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i64:9940; CHECK: # %bb.0: # %entry9941; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9942; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v129943; CHECK-NEXT: ret9944entry:9945 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 5)9946 ret void9947}9948 9949define void @test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {9950; CHECK-LABEL: test_vsuxseg2_mask_nxv4f32_triscv.vector.tuple_nxv16i8_2t_nxv4i64:9951; CHECK: # %bb.0: # %entry9952; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma9953; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t9954; CHECK-NEXT: ret9955entry:9956 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)9957 ret void9958}9959 9960define void @test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {9961; CHECK-LABEL: test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:9962; CHECK: # %bb.0: # %entry9963; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma9964; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v169965; CHECK-NEXT: ret9966entry:9967 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 5)9968 ret void9969}9970 9971define void @test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {9972; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i8:9973; CHECK: # %bb.0: # %entry9974; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma9975; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t9976; CHECK-NEXT: ret9977entry:9978 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)9979 ret void9980}9981 9982define void @test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {9983; CHECK-LABEL: test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:9984; CHECK: # %bb.0: # %entry9985; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma9986; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v169987; CHECK-NEXT: ret9988entry:9989 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 5)9990 ret void9991}9992 9993define void @test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {9994; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i16:9995; CHECK: # %bb.0: # %entry9996; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma9997; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t9998; CHECK-NEXT: ret9999entry:10000 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)10001 ret void10002}10003 10004define void @test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {10005; CHECK-LABEL: test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:10006; CHECK: # %bb.0: # %entry10007; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma10008; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1610009; CHECK-NEXT: ret10010entry:10011 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 5)10012 ret void10013}10014 10015define void @test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {10016; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i32:10017; CHECK: # %bb.0: # %entry10018; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma10019; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t10020; CHECK-NEXT: ret10021entry:10022 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)10023 ret void10024}10025 10026define void @test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {10027; CHECK-LABEL: test_vsuxseg2_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i64:10028; CHECK: # %bb.0: # %entry10029; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma10030; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1610031; CHECK-NEXT: ret10032entry:10033 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv8i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 5)10034 ret void10035}10036 10037define void @test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {10038; CHECK-LABEL: test_vsuxseg2_mask_nxv8f32_triscv.vector.tuple_nxv32i8_2t_nxv8i64:10039; CHECK: # %bb.0: # %entry10040; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma10041; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t10042; CHECK-NEXT: ret10043entry:10044 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 5)10045 ret void10046}10047 10048define void @test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {10049; CHECK-LABEL: test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:10050; CHECK: # %bb.0: # %entry10051; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10052; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1110053; CHECK-NEXT: ret10054entry:10055 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)10056 ret void10057}10058 10059define void @test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {10060; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i8:10061; CHECK: # %bb.0: # %entry10062; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10063; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t10064; CHECK-NEXT: ret10065entry:10066 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10067 ret void10068}10069 10070define void @test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {10071; CHECK-LABEL: test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:10072; CHECK: # %bb.0: # %entry10073; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10074; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1110075; CHECK-NEXT: ret10076entry:10077 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)10078 ret void10079}10080 10081define void @test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {10082; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i16:10083; CHECK: # %bb.0: # %entry10084; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10085; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t10086; CHECK-NEXT: ret10087entry:10088 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10089 ret void10090}10091 10092define void @test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {10093; CHECK-LABEL: test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:10094; CHECK: # %bb.0: # %entry10095; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10096; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1110097; CHECK-NEXT: ret10098entry:10099 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)10100 ret void10101}10102 10103define void @test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {10104; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i32:10105; CHECK: # %bb.0: # %entry10106; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10107; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t10108; CHECK-NEXT: ret10109entry:10110 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10111 ret void10112}10113 10114define void @test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {10115; CHECK-LABEL: test_vsuxseg3_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i64:10116; CHECK: # %bb.0: # %entry10117; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10118; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1110119; CHECK-NEXT: ret10120entry:10121 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)10122 ret void10123}10124 10125define void @test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {10126; CHECK-LABEL: test_vsuxseg3_mask_nxv1f32_triscv.vector.tuple_nxv4i8_3t_nxv1i64:10127; CHECK: # %bb.0: # %entry10128; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10129; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t10130; CHECK-NEXT: ret10131entry:10132 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10133 ret void10134}10135 10136define void @test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {10137; CHECK-LABEL: test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:10138; CHECK: # %bb.0: # %entry10139; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10140; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1110141; CHECK-NEXT: ret10142entry:10143 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)10144 ret void10145}10146 10147define void @test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {10148; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i8:10149; CHECK: # %bb.0: # %entry10150; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10151; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t10152; CHECK-NEXT: ret10153entry:10154 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10155 ret void10156}10157 10158define void @test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {10159; CHECK-LABEL: test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:10160; CHECK: # %bb.0: # %entry10161; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10162; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1110163; CHECK-NEXT: ret10164entry:10165 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)10166 ret void10167}10168 10169define void @test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {10170; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i16:10171; CHECK: # %bb.0: # %entry10172; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10173; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t10174; CHECK-NEXT: ret10175entry:10176 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10177 ret void10178}10179 10180define void @test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {10181; CHECK-LABEL: test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:10182; CHECK: # %bb.0: # %entry10183; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10184; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1110185; CHECK-NEXT: ret10186entry:10187 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)10188 ret void10189}10190 10191define void @test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {10192; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i32:10193; CHECK: # %bb.0: # %entry10194; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10195; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t10196; CHECK-NEXT: ret10197entry:10198 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10199 ret void10200}10201 10202define void @test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {10203; CHECK-LABEL: test_vsuxseg3_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i64:10204; CHECK: # %bb.0: # %entry10205; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10206; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1210207; CHECK-NEXT: ret10208entry:10209 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)10210 ret void10211}10212 10213define void @test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {10214; CHECK-LABEL: test_vsuxseg3_mask_nxv2f32_triscv.vector.tuple_nxv8i8_3t_nxv2i64:10215; CHECK: # %bb.0: # %entry10216; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10217; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t10218; CHECK-NEXT: ret10219entry:10220 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10221 ret void10222}10223 10224define void @test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {10225; CHECK-LABEL: test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:10226; CHECK: # %bb.0: # %entry10227; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10228; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1410229; CHECK-NEXT: ret10230entry:10231 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 5)10232 ret void10233}10234 10235define void @test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {10236; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i8:10237; CHECK: # %bb.0: # %entry10238; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10239; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t10240; CHECK-NEXT: ret10241entry:10242 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10243 ret void10244}10245 10246define void @test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {10247; CHECK-LABEL: test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:10248; CHECK: # %bb.0: # %entry10249; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10250; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1410251; CHECK-NEXT: ret10252entry:10253 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 5)10254 ret void10255}10256 10257define void @test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {10258; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i16:10259; CHECK: # %bb.0: # %entry10260; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10261; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v14, v0.t10262; CHECK-NEXT: ret10263entry:10264 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10265 ret void10266}10267 10268define void @test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {10269; CHECK-LABEL: test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:10270; CHECK: # %bb.0: # %entry10271; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10272; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1410273; CHECK-NEXT: ret10274entry:10275 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 5)10276 ret void10277}10278 10279define void @test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {10280; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i32:10281; CHECK: # %bb.0: # %entry10282; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10283; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v14, v0.t10284; CHECK-NEXT: ret10285entry:10286 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10287 ret void10288}10289 10290define void @test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {10291; CHECK-LABEL: test_vsuxseg3_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i64:10292; CHECK: # %bb.0: # %entry10293; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10294; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1610295; CHECK-NEXT: ret10296entry:10297 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 5)10298 ret void10299}10300 10301define void @test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {10302; CHECK-LABEL: test_vsuxseg3_mask_nxv4f32_triscv.vector.tuple_nxv16i8_3t_nxv4i64:10303; CHECK: # %bb.0: # %entry10304; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10305; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v16, v0.t10306; CHECK-NEXT: ret10307entry:10308 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10309 ret void10310}10311 10312define void @test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {10313; CHECK-LABEL: test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:10314; CHECK: # %bb.0: # %entry10315; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10316; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1210317; CHECK-NEXT: ret10318entry:10319 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)10320 ret void10321}10322 10323define void @test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {10324; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i8:10325; CHECK: # %bb.0: # %entry10326; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10327; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t10328; CHECK-NEXT: ret10329entry:10330 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10331 ret void10332}10333 10334define void @test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {10335; CHECK-LABEL: test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:10336; CHECK: # %bb.0: # %entry10337; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10338; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1210339; CHECK-NEXT: ret10340entry:10341 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)10342 ret void10343}10344 10345define void @test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {10346; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i16:10347; CHECK: # %bb.0: # %entry10348; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10349; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t10350; CHECK-NEXT: ret10351entry:10352 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10353 ret void10354}10355 10356define void @test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {10357; CHECK-LABEL: test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:10358; CHECK: # %bb.0: # %entry10359; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10360; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1210361; CHECK-NEXT: ret10362entry:10363 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)10364 ret void10365}10366 10367define void @test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {10368; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i32:10369; CHECK: # %bb.0: # %entry10370; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10371; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t10372; CHECK-NEXT: ret10373entry:10374 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10375 ret void10376}10377 10378define void @test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {10379; CHECK-LABEL: test_vsuxseg4_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i64:10380; CHECK: # %bb.0: # %entry10381; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10382; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1210383; CHECK-NEXT: ret10384entry:10385 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)10386 ret void10387}10388 10389define void @test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {10390; CHECK-LABEL: test_vsuxseg4_mask_nxv1f32_triscv.vector.tuple_nxv4i8_4t_nxv1i64:10391; CHECK: # %bb.0: # %entry10392; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10393; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t10394; CHECK-NEXT: ret10395entry:10396 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10397 ret void10398}10399 10400define void @test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {10401; CHECK-LABEL: test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:10402; CHECK: # %bb.0: # %entry10403; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10404; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1210405; CHECK-NEXT: ret10406entry:10407 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)10408 ret void10409}10410 10411define void @test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {10412; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i8:10413; CHECK: # %bb.0: # %entry10414; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10415; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t10416; CHECK-NEXT: ret10417entry:10418 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10419 ret void10420}10421 10422define void @test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {10423; CHECK-LABEL: test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:10424; CHECK: # %bb.0: # %entry10425; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10426; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1210427; CHECK-NEXT: ret10428entry:10429 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)10430 ret void10431}10432 10433define void @test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {10434; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i16:10435; CHECK: # %bb.0: # %entry10436; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10437; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t10438; CHECK-NEXT: ret10439entry:10440 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10441 ret void10442}10443 10444define void @test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {10445; CHECK-LABEL: test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:10446; CHECK: # %bb.0: # %entry10447; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10448; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1210449; CHECK-NEXT: ret10450entry:10451 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)10452 ret void10453}10454 10455define void @test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {10456; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i32:10457; CHECK: # %bb.0: # %entry10458; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10459; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t10460; CHECK-NEXT: ret10461entry:10462 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10463 ret void10464}10465 10466define void @test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {10467; CHECK-LABEL: test_vsuxseg4_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i64:10468; CHECK: # %bb.0: # %entry10469; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10470; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1210471; CHECK-NEXT: ret10472entry:10473 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)10474 ret void10475}10476 10477define void @test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {10478; CHECK-LABEL: test_vsuxseg4_mask_nxv2f32_triscv.vector.tuple_nxv8i8_4t_nxv2i64:10479; CHECK: # %bb.0: # %entry10480; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10481; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t10482; CHECK-NEXT: ret10483entry:10484 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10485 ret void10486}10487 10488define void @test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {10489; CHECK-LABEL: test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:10490; CHECK: # %bb.0: # %entry10491; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10492; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1610493; CHECK-NEXT: ret10494entry:10495 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 5)10496 ret void10497}10498 10499define void @test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {10500; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i8:10501; CHECK: # %bb.0: # %entry10502; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10503; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t10504; CHECK-NEXT: ret10505entry:10506 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10507 ret void10508}10509 10510define void @test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {10511; CHECK-LABEL: test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:10512; CHECK: # %bb.0: # %entry10513; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10514; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1610515; CHECK-NEXT: ret10516entry:10517 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 5)10518 ret void10519}10520 10521define void @test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {10522; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i16:10523; CHECK: # %bb.0: # %entry10524; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10525; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t10526; CHECK-NEXT: ret10527entry:10528 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10529 ret void10530}10531 10532define void @test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {10533; CHECK-LABEL: test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:10534; CHECK: # %bb.0: # %entry10535; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10536; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1610537; CHECK-NEXT: ret10538entry:10539 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 5)10540 ret void10541}10542 10543define void @test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {10544; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i32:10545; CHECK: # %bb.0: # %entry10546; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10547; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t10548; CHECK-NEXT: ret10549entry:10550 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10551 ret void10552}10553 10554define void @test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {10555; CHECK-LABEL: test_vsuxseg4_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i64:10556; CHECK: # %bb.0: # %entry10557; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10558; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1610559; CHECK-NEXT: ret10560entry:10561 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 5)10562 ret void10563}10564 10565define void @test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {10566; CHECK-LABEL: test_vsuxseg4_mask_nxv4f32_triscv.vector.tuple_nxv16i8_4t_nxv4i64:10567; CHECK: # %bb.0: # %entry10568; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma10569; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t10570; CHECK-NEXT: ret10571entry:10572 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 5)10573 ret void10574}10575 10576define void @test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {10577; CHECK-LABEL: test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:10578; CHECK: # %bb.0: # %entry10579; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10580; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v1310581; CHECK-NEXT: ret10582entry:10583 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)10584 ret void10585}10586 10587define void @test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {10588; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i8:10589; CHECK: # %bb.0: # %entry10590; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10591; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t10592; CHECK-NEXT: ret10593entry:10594 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10595 ret void10596}10597 10598define void @test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {10599; CHECK-LABEL: test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:10600; CHECK: # %bb.0: # %entry10601; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10602; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v1310603; CHECK-NEXT: ret10604entry:10605 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)10606 ret void10607}10608 10609define void @test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {10610; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i16:10611; CHECK: # %bb.0: # %entry10612; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10613; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t10614; CHECK-NEXT: ret10615entry:10616 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10617 ret void10618}10619 10620define void @test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {10621; CHECK-LABEL: test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:10622; CHECK: # %bb.0: # %entry10623; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10624; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v1310625; CHECK-NEXT: ret10626entry:10627 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)10628 ret void10629}10630 10631define void @test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {10632; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i32:10633; CHECK: # %bb.0: # %entry10634; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10635; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t10636; CHECK-NEXT: ret10637entry:10638 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10639 ret void10640}10641 10642define void @test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {10643; CHECK-LABEL: test_vsuxseg5_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i64:10644; CHECK: # %bb.0: # %entry10645; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10646; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v1310647; CHECK-NEXT: ret10648entry:10649 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)10650 ret void10651}10652 10653define void @test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {10654; CHECK-LABEL: test_vsuxseg5_mask_nxv1f32_triscv.vector.tuple_nxv4i8_5t_nxv1i64:10655; CHECK: # %bb.0: # %entry10656; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10657; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t10658; CHECK-NEXT: ret10659entry:10660 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10661 ret void10662}10663 10664define void @test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {10665; CHECK-LABEL: test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:10666; CHECK: # %bb.0: # %entry10667; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10668; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v1310669; CHECK-NEXT: ret10670entry:10671 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)10672 ret void10673}10674 10675define void @test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {10676; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i8:10677; CHECK: # %bb.0: # %entry10678; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10679; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t10680; CHECK-NEXT: ret10681entry:10682 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10683 ret void10684}10685 10686define void @test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {10687; CHECK-LABEL: test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:10688; CHECK: # %bb.0: # %entry10689; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10690; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v1310691; CHECK-NEXT: ret10692entry:10693 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)10694 ret void10695}10696 10697define void @test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {10698; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i16:10699; CHECK: # %bb.0: # %entry10700; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10701; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t10702; CHECK-NEXT: ret10703entry:10704 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10705 ret void10706}10707 10708define void @test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {10709; CHECK-LABEL: test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:10710; CHECK: # %bb.0: # %entry10711; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10712; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v1310713; CHECK-NEXT: ret10714entry:10715 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)10716 ret void10717}10718 10719define void @test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {10720; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i32:10721; CHECK: # %bb.0: # %entry10722; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10723; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t10724; CHECK-NEXT: ret10725entry:10726 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10727 ret void10728}10729 10730define void @test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {10731; CHECK-LABEL: test_vsuxseg5_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i64:10732; CHECK: # %bb.0: # %entry10733; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10734; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v1410735; CHECK-NEXT: ret10736entry:10737 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)10738 ret void10739}10740 10741define void @test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {10742; CHECK-LABEL: test_vsuxseg5_mask_nxv2f32_triscv.vector.tuple_nxv8i8_5t_nxv2i64:10743; CHECK: # %bb.0: # %entry10744; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10745; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v14, v0.t10746; CHECK-NEXT: ret10747entry:10748 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10749 ret void10750}10751 10752define void @test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {10753; CHECK-LABEL: test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:10754; CHECK: # %bb.0: # %entry10755; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10756; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v1410757; CHECK-NEXT: ret10758entry:10759 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)10760 ret void10761}10762 10763define void @test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {10764; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i8:10765; CHECK: # %bb.0: # %entry10766; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10767; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t10768; CHECK-NEXT: ret10769entry:10770 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10771 ret void10772}10773 10774define void @test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {10775; CHECK-LABEL: test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:10776; CHECK: # %bb.0: # %entry10777; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10778; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v1410779; CHECK-NEXT: ret10780entry:10781 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)10782 ret void10783}10784 10785define void @test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {10786; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i16:10787; CHECK: # %bb.0: # %entry10788; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10789; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t10790; CHECK-NEXT: ret10791entry:10792 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10793 ret void10794}10795 10796define void @test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {10797; CHECK-LABEL: test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:10798; CHECK: # %bb.0: # %entry10799; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10800; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v1410801; CHECK-NEXT: ret10802entry:10803 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)10804 ret void10805}10806 10807define void @test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {10808; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i32:10809; CHECK: # %bb.0: # %entry10810; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10811; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t10812; CHECK-NEXT: ret10813entry:10814 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10815 ret void10816}10817 10818define void @test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {10819; CHECK-LABEL: test_vsuxseg6_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i64:10820; CHECK: # %bb.0: # %entry10821; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10822; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v1410823; CHECK-NEXT: ret10824entry:10825 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)10826 ret void10827}10828 10829define void @test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {10830; CHECK-LABEL: test_vsuxseg6_mask_nxv1f32_triscv.vector.tuple_nxv4i8_6t_nxv1i64:10831; CHECK: # %bb.0: # %entry10832; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10833; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t10834; CHECK-NEXT: ret10835entry:10836 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10837 ret void10838}10839 10840define void @test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {10841; CHECK-LABEL: test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:10842; CHECK: # %bb.0: # %entry10843; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10844; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v1410845; CHECK-NEXT: ret10846entry:10847 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)10848 ret void10849}10850 10851define void @test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {10852; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i8:10853; CHECK: # %bb.0: # %entry10854; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10855; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t10856; CHECK-NEXT: ret10857entry:10858 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10859 ret void10860}10861 10862define void @test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {10863; CHECK-LABEL: test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:10864; CHECK: # %bb.0: # %entry10865; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10866; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v1410867; CHECK-NEXT: ret10868entry:10869 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)10870 ret void10871}10872 10873define void @test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {10874; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i16:10875; CHECK: # %bb.0: # %entry10876; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10877; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t10878; CHECK-NEXT: ret10879entry:10880 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10881 ret void10882}10883 10884define void @test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {10885; CHECK-LABEL: test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:10886; CHECK: # %bb.0: # %entry10887; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10888; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v1410889; CHECK-NEXT: ret10890entry:10891 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)10892 ret void10893}10894 10895define void @test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {10896; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i32:10897; CHECK: # %bb.0: # %entry10898; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10899; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t10900; CHECK-NEXT: ret10901entry:10902 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10903 ret void10904}10905 10906define void @test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {10907; CHECK-LABEL: test_vsuxseg6_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i64:10908; CHECK: # %bb.0: # %entry10909; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10910; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v1410911; CHECK-NEXT: ret10912entry:10913 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)10914 ret void10915}10916 10917define void @test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {10918; CHECK-LABEL: test_vsuxseg6_mask_nxv2f32_triscv.vector.tuple_nxv8i8_6t_nxv2i64:10919; CHECK: # %bb.0: # %entry10920; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma10921; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t10922; CHECK-NEXT: ret10923entry:10924 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)10925 ret void10926}10927 10928define void @test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {10929; CHECK-LABEL: test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:10930; CHECK: # %bb.0: # %entry10931; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10932; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v1510933; CHECK-NEXT: ret10934entry:10935 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)10936 ret void10937}10938 10939define void @test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {10940; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i8:10941; CHECK: # %bb.0: # %entry10942; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10943; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t10944; CHECK-NEXT: ret10945entry:10946 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10947 ret void10948}10949 10950define void @test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {10951; CHECK-LABEL: test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:10952; CHECK: # %bb.0: # %entry10953; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10954; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v1510955; CHECK-NEXT: ret10956entry:10957 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)10958 ret void10959}10960 10961define void @test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {10962; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i16:10963; CHECK: # %bb.0: # %entry10964; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10965; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t10966; CHECK-NEXT: ret10967entry:10968 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10969 ret void10970}10971 10972define void @test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {10973; CHECK-LABEL: test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:10974; CHECK: # %bb.0: # %entry10975; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10976; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v1510977; CHECK-NEXT: ret10978entry:10979 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)10980 ret void10981}10982 10983define void @test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {10984; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i32:10985; CHECK: # %bb.0: # %entry10986; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10987; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t10988; CHECK-NEXT: ret10989entry:10990 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)10991 ret void10992}10993 10994define void @test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {10995; CHECK-LABEL: test_vsuxseg7_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i64:10996; CHECK: # %bb.0: # %entry10997; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma10998; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v1510999; CHECK-NEXT: ret11000entry:11001 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)11002 ret void11003}11004 11005define void @test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {11006; CHECK-LABEL: test_vsuxseg7_mask_nxv1f32_triscv.vector.tuple_nxv4i8_7t_nxv1i64:11007; CHECK: # %bb.0: # %entry11008; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11009; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t11010; CHECK-NEXT: ret11011entry:11012 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)11013 ret void11014}11015 11016define void @test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {11017; CHECK-LABEL: test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:11018; CHECK: # %bb.0: # %entry11019; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11020; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v1511021; CHECK-NEXT: ret11022entry:11023 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)11024 ret void11025}11026 11027define void @test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {11028; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i8:11029; CHECK: # %bb.0: # %entry11030; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11031; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t11032; CHECK-NEXT: ret11033entry:11034 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11035 ret void11036}11037 11038define void @test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {11039; CHECK-LABEL: test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:11040; CHECK: # %bb.0: # %entry11041; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11042; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v1511043; CHECK-NEXT: ret11044entry:11045 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)11046 ret void11047}11048 11049define void @test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {11050; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i16:11051; CHECK: # %bb.0: # %entry11052; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11053; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t11054; CHECK-NEXT: ret11055entry:11056 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11057 ret void11058}11059 11060define void @test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {11061; CHECK-LABEL: test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:11062; CHECK: # %bb.0: # %entry11063; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11064; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v1511065; CHECK-NEXT: ret11066entry:11067 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)11068 ret void11069}11070 11071define void @test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {11072; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i32:11073; CHECK: # %bb.0: # %entry11074; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11075; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t11076; CHECK-NEXT: ret11077entry:11078 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11079 ret void11080}11081 11082define void @test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {11083; CHECK-LABEL: test_vsuxseg7_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i64:11084; CHECK: # %bb.0: # %entry11085; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11086; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v1611087; CHECK-NEXT: ret11088entry:11089 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)11090 ret void11091}11092 11093define void @test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {11094; CHECK-LABEL: test_vsuxseg7_mask_nxv2f32_triscv.vector.tuple_nxv8i8_7t_nxv2i64:11095; CHECK: # %bb.0: # %entry11096; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11097; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t11098; CHECK-NEXT: ret11099entry:11100 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11101 ret void11102}11103 11104define void @test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {11105; CHECK-LABEL: test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:11106; CHECK: # %bb.0: # %entry11107; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11108; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v1611109; CHECK-NEXT: ret11110entry:11111 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 5)11112 ret void11113}11114 11115define void @test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {11116; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i8:11117; CHECK: # %bb.0: # %entry11118; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11119; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t11120; CHECK-NEXT: ret11121entry:11122 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)11123 ret void11124}11125 11126define void @test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {11127; CHECK-LABEL: test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:11128; CHECK: # %bb.0: # %entry11129; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11130; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v1611131; CHECK-NEXT: ret11132entry:11133 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)11134 ret void11135}11136 11137define void @test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {11138; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i16:11139; CHECK: # %bb.0: # %entry11140; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11141; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t11142; CHECK-NEXT: ret11143entry:11144 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)11145 ret void11146}11147 11148define void @test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {11149; CHECK-LABEL: test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:11150; CHECK: # %bb.0: # %entry11151; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11152; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v1611153; CHECK-NEXT: ret11154entry:11155 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 5)11156 ret void11157}11158 11159define void @test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {11160; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i32:11161; CHECK: # %bb.0: # %entry11162; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11163; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t11164; CHECK-NEXT: ret11165entry:11166 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)11167 ret void11168}11169 11170define void @test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {11171; CHECK-LABEL: test_vsuxseg8_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i64:11172; CHECK: # %bb.0: # %entry11173; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11174; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v1611175; CHECK-NEXT: ret11176entry:11177 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 5)11178 ret void11179}11180 11181define void @test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {11182; CHECK-LABEL: test_vsuxseg8_mask_nxv1f32_triscv.vector.tuple_nxv4i8_8t_nxv1i64:11183; CHECK: # %bb.0: # %entry11184; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma11185; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t11186; CHECK-NEXT: ret11187entry:11188 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)11189 ret void11190}11191 11192define void @test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {11193; CHECK-LABEL: test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:11194; CHECK: # %bb.0: # %entry11195; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11196; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v1611197; CHECK-NEXT: ret11198entry:11199 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 5)11200 ret void11201}11202 11203define void @test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {11204; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i8:11205; CHECK: # %bb.0: # %entry11206; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11207; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t11208; CHECK-NEXT: ret11209entry:11210 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11211 ret void11212}11213 11214define void @test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {11215; CHECK-LABEL: test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:11216; CHECK: # %bb.0: # %entry11217; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11218; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v1611219; CHECK-NEXT: ret11220entry:11221 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 5)11222 ret void11223}11224 11225define void @test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {11226; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i16:11227; CHECK: # %bb.0: # %entry11228; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11229; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t11230; CHECK-NEXT: ret11231entry:11232 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11233 ret void11234}11235 11236define void @test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {11237; CHECK-LABEL: test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:11238; CHECK: # %bb.0: # %entry11239; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11240; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v1611241; CHECK-NEXT: ret11242entry:11243 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 5)11244 ret void11245}11246 11247define void @test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {11248; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i32:11249; CHECK: # %bb.0: # %entry11250; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11251; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t11252; CHECK-NEXT: ret11253entry:11254 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11255 ret void11256}11257 11258define void @test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {11259; CHECK-LABEL: test_vsuxseg8_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i64:11260; CHECK: # %bb.0: # %entry11261; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11262; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v1611263; CHECK-NEXT: ret11264entry:11265 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 5)11266 ret void11267}11268 11269define void @test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {11270; CHECK-LABEL: test_vsuxseg8_mask_nxv2f32_triscv.vector.tuple_nxv8i8_8t_nxv2i64:11271; CHECK: # %bb.0: # %entry11272; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma11273; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t11274; CHECK-NEXT: ret11275entry:11276 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 5)11277 ret void11278}11279 11280define void @test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {11281; CHECK-LABEL: test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:11282; CHECK: # %bb.0: # %entry11283; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11284; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1011285; CHECK-NEXT: ret11286entry:11287 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)11288 ret void11289}11290 11291define void @test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {11292; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i8:11293; CHECK: # %bb.0: # %entry11294; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11295; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t11296; CHECK-NEXT: ret11297entry:11298 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11299 ret void11300}11301 11302define void @test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {11303; CHECK-LABEL: test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:11304; CHECK: # %bb.0: # %entry11305; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11306; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1011307; CHECK-NEXT: ret11308entry:11309 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)11310 ret void11311}11312 11313define void @test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {11314; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i16:11315; CHECK: # %bb.0: # %entry11316; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11317; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t11318; CHECK-NEXT: ret11319entry:11320 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11321 ret void11322}11323 11324define void @test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {11325; CHECK-LABEL: test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:11326; CHECK: # %bb.0: # %entry11327; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11328; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1011329; CHECK-NEXT: ret11330entry:11331 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)11332 ret void11333}11334 11335define void @test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {11336; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i32:11337; CHECK: # %bb.0: # %entry11338; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11339; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t11340; CHECK-NEXT: ret11341entry:11342 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11343 ret void11344}11345 11346define void @test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {11347; CHECK-LABEL: test_vsuxseg2_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i64:11348; CHECK: # %bb.0: # %entry11349; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11350; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1011351; CHECK-NEXT: ret11352entry:11353 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)11354 ret void11355}11356 11357define void @test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {11358; CHECK-LABEL: test_vsuxseg2_mask_nxv1f64_triscv.vector.tuple_nxv8i8_2t_nxv1i64:11359; CHECK: # %bb.0: # %entry11360; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11361; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t11362; CHECK-NEXT: ret11363entry:11364 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11365 ret void11366}11367 11368define void @test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {11369; CHECK-LABEL: test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:11370; CHECK: # %bb.0: # %entry11371; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11372; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1211373; CHECK-NEXT: ret11374entry:11375 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 6)11376 ret void11377}11378 11379define void @test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {11380; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i8:11381; CHECK: # %bb.0: # %entry11382; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11383; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t11384; CHECK-NEXT: ret11385entry:11386 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11387 ret void11388}11389 11390define void @test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {11391; CHECK-LABEL: test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:11392; CHECK: # %bb.0: # %entry11393; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11394; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1211395; CHECK-NEXT: ret11396entry:11397 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 6)11398 ret void11399}11400 11401define void @test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {11402; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i16:11403; CHECK: # %bb.0: # %entry11404; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11405; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t11406; CHECK-NEXT: ret11407entry:11408 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11409 ret void11410}11411 11412define void @test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {11413; CHECK-LABEL: test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:11414; CHECK: # %bb.0: # %entry11415; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11416; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1211417; CHECK-NEXT: ret11418entry:11419 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 6)11420 ret void11421}11422 11423define void @test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {11424; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i32:11425; CHECK: # %bb.0: # %entry11426; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11427; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t11428; CHECK-NEXT: ret11429entry:11430 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11431 ret void11432}11433 11434define void @test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {11435; CHECK-LABEL: test_vsuxseg2_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i64:11436; CHECK: # %bb.0: # %entry11437; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11438; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1211439; CHECK-NEXT: ret11440entry:11441 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 6)11442 ret void11443}11444 11445define void @test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {11446; CHECK-LABEL: test_vsuxseg2_mask_nxv2f64_triscv.vector.tuple_nxv16i8_2t_nxv2i64:11447; CHECK: # %bb.0: # %entry11448; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11449; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t11450; CHECK-NEXT: ret11451entry:11452 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11453 ret void11454}11455 11456define void @test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {11457; CHECK-LABEL: test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:11458; CHECK: # %bb.0: # %entry11459; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11460; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1611461; CHECK-NEXT: ret11462entry:11463 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 6)11464 ret void11465}11466 11467define void @test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {11468; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i8:11469; CHECK: # %bb.0: # %entry11470; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11471; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t11472; CHECK-NEXT: ret11473entry:11474 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)11475 ret void11476}11477 11478define void @test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {11479; CHECK-LABEL: test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:11480; CHECK: # %bb.0: # %entry11481; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11482; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1611483; CHECK-NEXT: ret11484entry:11485 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 6)11486 ret void11487}11488 11489define void @test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {11490; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i16:11491; CHECK: # %bb.0: # %entry11492; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11493; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t11494; CHECK-NEXT: ret11495entry:11496 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)11497 ret void11498}11499 11500define void @test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {11501; CHECK-LABEL: test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:11502; CHECK: # %bb.0: # %entry11503; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11504; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1611505; CHECK-NEXT: ret11506entry:11507 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 6)11508 ret void11509}11510 11511define void @test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {11512; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i32:11513; CHECK: # %bb.0: # %entry11514; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11515; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t11516; CHECK-NEXT: ret11517entry:11518 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)11519 ret void11520}11521 11522define void @test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {11523; CHECK-LABEL: test_vsuxseg2_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i64:11524; CHECK: # %bb.0: # %entry11525; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11526; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1611527; CHECK-NEXT: ret11528entry:11529 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 6)11530 ret void11531}11532 11533define void @test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {11534; CHECK-LABEL: test_vsuxseg2_mask_nxv4f64_triscv.vector.tuple_nxv32i8_2t_nxv4i64:11535; CHECK: # %bb.0: # %entry11536; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma11537; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t11538; CHECK-NEXT: ret11539entry:11540 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 6)11541 ret void11542}11543 11544define void @test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {11545; CHECK-LABEL: test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:11546; CHECK: # %bb.0: # %entry11547; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11548; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1111549; CHECK-NEXT: ret11550entry:11551 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)11552 ret void11553}11554 11555define void @test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {11556; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i8:11557; CHECK: # %bb.0: # %entry11558; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11559; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t11560; CHECK-NEXT: ret11561entry:11562 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11563 ret void11564}11565 11566define void @test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {11567; CHECK-LABEL: test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:11568; CHECK: # %bb.0: # %entry11569; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11570; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1111571; CHECK-NEXT: ret11572entry:11573 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)11574 ret void11575}11576 11577define void @test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {11578; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i16:11579; CHECK: # %bb.0: # %entry11580; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11581; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t11582; CHECK-NEXT: ret11583entry:11584 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11585 ret void11586}11587 11588define void @test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {11589; CHECK-LABEL: test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:11590; CHECK: # %bb.0: # %entry11591; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11592; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1111593; CHECK-NEXT: ret11594entry:11595 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)11596 ret void11597}11598 11599define void @test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {11600; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i32:11601; CHECK: # %bb.0: # %entry11602; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11603; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t11604; CHECK-NEXT: ret11605entry:11606 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11607 ret void11608}11609 11610define void @test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {11611; CHECK-LABEL: test_vsuxseg3_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i64:11612; CHECK: # %bb.0: # %entry11613; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11614; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1111615; CHECK-NEXT: ret11616entry:11617 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)11618 ret void11619}11620 11621define void @test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {11622; CHECK-LABEL: test_vsuxseg3_mask_nxv1f64_triscv.vector.tuple_nxv8i8_3t_nxv1i64:11623; CHECK: # %bb.0: # %entry11624; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11625; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t11626; CHECK-NEXT: ret11627entry:11628 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11629 ret void11630}11631 11632define void @test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {11633; CHECK-LABEL: test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:11634; CHECK: # %bb.0: # %entry11635; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11636; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1411637; CHECK-NEXT: ret11638entry:11639 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 6)11640 ret void11641}11642 11643define void @test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {11644; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i8:11645; CHECK: # %bb.0: # %entry11646; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11647; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t11648; CHECK-NEXT: ret11649entry:11650 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11651 ret void11652}11653 11654define void @test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {11655; CHECK-LABEL: test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:11656; CHECK: # %bb.0: # %entry11657; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11658; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1411659; CHECK-NEXT: ret11660entry:11661 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 6)11662 ret void11663}11664 11665define void @test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {11666; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i16:11667; CHECK: # %bb.0: # %entry11668; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11669; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v14, v0.t11670; CHECK-NEXT: ret11671entry:11672 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11673 ret void11674}11675 11676define void @test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {11677; CHECK-LABEL: test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:11678; CHECK: # %bb.0: # %entry11679; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11680; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1411681; CHECK-NEXT: ret11682entry:11683 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 6)11684 ret void11685}11686 11687define void @test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {11688; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i32:11689; CHECK: # %bb.0: # %entry11690; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11691; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v14, v0.t11692; CHECK-NEXT: ret11693entry:11694 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11695 ret void11696}11697 11698define void @test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {11699; CHECK-LABEL: test_vsuxseg3_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i64:11700; CHECK: # %bb.0: # %entry11701; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11702; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1411703; CHECK-NEXT: ret11704entry:11705 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 6)11706 ret void11707}11708 11709define void @test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {11710; CHECK-LABEL: test_vsuxseg3_mask_nxv2f64_triscv.vector.tuple_nxv16i8_3t_nxv2i64:11711; CHECK: # %bb.0: # %entry11712; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11713; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v14, v0.t11714; CHECK-NEXT: ret11715entry:11716 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11717 ret void11718}11719 11720define void @test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {11721; CHECK-LABEL: test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:11722; CHECK: # %bb.0: # %entry11723; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11724; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1211725; CHECK-NEXT: ret11726entry:11727 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)11728 ret void11729}11730 11731define void @test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {11732; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i8:11733; CHECK: # %bb.0: # %entry11734; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11735; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t11736; CHECK-NEXT: ret11737entry:11738 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11739 ret void11740}11741 11742define void @test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {11743; CHECK-LABEL: test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:11744; CHECK: # %bb.0: # %entry11745; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11746; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1211747; CHECK-NEXT: ret11748entry:11749 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)11750 ret void11751}11752 11753define void @test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {11754; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i16:11755; CHECK: # %bb.0: # %entry11756; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11757; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t11758; CHECK-NEXT: ret11759entry:11760 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11761 ret void11762}11763 11764define void @test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {11765; CHECK-LABEL: test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:11766; CHECK: # %bb.0: # %entry11767; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11768; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1211769; CHECK-NEXT: ret11770entry:11771 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)11772 ret void11773}11774 11775define void @test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {11776; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i32:11777; CHECK: # %bb.0: # %entry11778; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11779; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t11780; CHECK-NEXT: ret11781entry:11782 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11783 ret void11784}11785 11786define void @test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {11787; CHECK-LABEL: test_vsuxseg4_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i64:11788; CHECK: # %bb.0: # %entry11789; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11790; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1211791; CHECK-NEXT: ret11792entry:11793 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)11794 ret void11795}11796 11797define void @test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {11798; CHECK-LABEL: test_vsuxseg4_mask_nxv1f64_triscv.vector.tuple_nxv8i8_4t_nxv1i64:11799; CHECK: # %bb.0: # %entry11800; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11801; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t11802; CHECK-NEXT: ret11803entry:11804 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11805 ret void11806}11807 11808define void @test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {11809; CHECK-LABEL: test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:11810; CHECK: # %bb.0: # %entry11811; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11812; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1611813; CHECK-NEXT: ret11814entry:11815 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 6)11816 ret void11817}11818 11819define void @test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {11820; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i8:11821; CHECK: # %bb.0: # %entry11822; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11823; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t11824; CHECK-NEXT: ret11825entry:11826 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11827 ret void11828}11829 11830define void @test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {11831; CHECK-LABEL: test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:11832; CHECK: # %bb.0: # %entry11833; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11834; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1611835; CHECK-NEXT: ret11836entry:11837 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 6)11838 ret void11839}11840 11841define void @test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {11842; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i16:11843; CHECK: # %bb.0: # %entry11844; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11845; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t11846; CHECK-NEXT: ret11847entry:11848 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11849 ret void11850}11851 11852define void @test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {11853; CHECK-LABEL: test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:11854; CHECK: # %bb.0: # %entry11855; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11856; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1611857; CHECK-NEXT: ret11858entry:11859 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 6)11860 ret void11861}11862 11863define void @test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {11864; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i32:11865; CHECK: # %bb.0: # %entry11866; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11867; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t11868; CHECK-NEXT: ret11869entry:11870 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11871 ret void11872}11873 11874define void @test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {11875; CHECK-LABEL: test_vsuxseg4_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i64:11876; CHECK: # %bb.0: # %entry11877; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11878; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1611879; CHECK-NEXT: ret11880entry:11881 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 6)11882 ret void11883}11884 11885define void @test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {11886; CHECK-LABEL: test_vsuxseg4_mask_nxv2f64_triscv.vector.tuple_nxv16i8_4t_nxv2i64:11887; CHECK: # %bb.0: # %entry11888; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma11889; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t11890; CHECK-NEXT: ret11891entry:11892 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 6)11893 ret void11894}11895 11896define void @test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {11897; CHECK-LABEL: test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:11898; CHECK: # %bb.0: # %entry11899; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11900; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v1311901; CHECK-NEXT: ret11902entry:11903 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)11904 ret void11905}11906 11907define void @test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {11908; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i8:11909; CHECK: # %bb.0: # %entry11910; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11911; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t11912; CHECK-NEXT: ret11913entry:11914 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11915 ret void11916}11917 11918define void @test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {11919; CHECK-LABEL: test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:11920; CHECK: # %bb.0: # %entry11921; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11922; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v1311923; CHECK-NEXT: ret11924entry:11925 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)11926 ret void11927}11928 11929define void @test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {11930; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i16:11931; CHECK: # %bb.0: # %entry11932; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11933; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t11934; CHECK-NEXT: ret11935entry:11936 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11937 ret void11938}11939 11940define void @test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {11941; CHECK-LABEL: test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:11942; CHECK: # %bb.0: # %entry11943; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11944; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v1311945; CHECK-NEXT: ret11946entry:11947 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)11948 ret void11949}11950 11951define void @test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {11952; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i32:11953; CHECK: # %bb.0: # %entry11954; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11955; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t11956; CHECK-NEXT: ret11957entry:11958 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11959 ret void11960}11961 11962define void @test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {11963; CHECK-LABEL: test_vsuxseg5_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i64:11964; CHECK: # %bb.0: # %entry11965; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11966; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v1311967; CHECK-NEXT: ret11968entry:11969 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)11970 ret void11971}11972 11973define void @test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {11974; CHECK-LABEL: test_vsuxseg5_mask_nxv1f64_triscv.vector.tuple_nxv8i8_5t_nxv1i64:11975; CHECK: # %bb.0: # %entry11976; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11977; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t11978; CHECK-NEXT: ret11979entry:11980 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)11981 ret void11982}11983 11984define void @test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {11985; CHECK-LABEL: test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:11986; CHECK: # %bb.0: # %entry11987; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11988; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v1411989; CHECK-NEXT: ret11990entry:11991 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)11992 ret void11993}11994 11995define void @test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {11996; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i8:11997; CHECK: # %bb.0: # %entry11998; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11999; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t12000; CHECK-NEXT: ret12001entry:12002 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12003 ret void12004}12005 12006define void @test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {12007; CHECK-LABEL: test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:12008; CHECK: # %bb.0: # %entry12009; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12010; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v1412011; CHECK-NEXT: ret12012entry:12013 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)12014 ret void12015}12016 12017define void @test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {12018; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i16:12019; CHECK: # %bb.0: # %entry12020; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12021; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t12022; CHECK-NEXT: ret12023entry:12024 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12025 ret void12026}12027 12028define void @test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {12029; CHECK-LABEL: test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:12030; CHECK: # %bb.0: # %entry12031; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12032; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v1412033; CHECK-NEXT: ret12034entry:12035 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)12036 ret void12037}12038 12039define void @test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {12040; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i32:12041; CHECK: # %bb.0: # %entry12042; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12043; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t12044; CHECK-NEXT: ret12045entry:12046 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12047 ret void12048}12049 12050define void @test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {12051; CHECK-LABEL: test_vsuxseg6_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i64:12052; CHECK: # %bb.0: # %entry12053; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12054; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v1412055; CHECK-NEXT: ret12056entry:12057 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)12058 ret void12059}12060 12061define void @test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {12062; CHECK-LABEL: test_vsuxseg6_mask_nxv1f64_triscv.vector.tuple_nxv8i8_6t_nxv1i64:12063; CHECK: # %bb.0: # %entry12064; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12065; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t12066; CHECK-NEXT: ret12067entry:12068 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12069 ret void12070}12071 12072define void @test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {12073; CHECK-LABEL: test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:12074; CHECK: # %bb.0: # %entry12075; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12076; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v1512077; CHECK-NEXT: ret12078entry:12079 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)12080 ret void12081}12082 12083define void @test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {12084; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i8:12085; CHECK: # %bb.0: # %entry12086; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12087; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t12088; CHECK-NEXT: ret12089entry:12090 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12091 ret void12092}12093 12094define void @test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {12095; CHECK-LABEL: test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:12096; CHECK: # %bb.0: # %entry12097; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12098; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v1512099; CHECK-NEXT: ret12100entry:12101 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)12102 ret void12103}12104 12105define void @test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {12106; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i16:12107; CHECK: # %bb.0: # %entry12108; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12109; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t12110; CHECK-NEXT: ret12111entry:12112 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12113 ret void12114}12115 12116define void @test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {12117; CHECK-LABEL: test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:12118; CHECK: # %bb.0: # %entry12119; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12120; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v1512121; CHECK-NEXT: ret12122entry:12123 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)12124 ret void12125}12126 12127define void @test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {12128; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i32:12129; CHECK: # %bb.0: # %entry12130; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12131; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t12132; CHECK-NEXT: ret12133entry:12134 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12135 ret void12136}12137 12138define void @test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {12139; CHECK-LABEL: test_vsuxseg7_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i64:12140; CHECK: # %bb.0: # %entry12141; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12142; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v1512143; CHECK-NEXT: ret12144entry:12145 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)12146 ret void12147}12148 12149define void @test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {12150; CHECK-LABEL: test_vsuxseg7_mask_nxv1f64_triscv.vector.tuple_nxv8i8_7t_nxv1i64:12151; CHECK: # %bb.0: # %entry12152; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12153; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t12154; CHECK-NEXT: ret12155entry:12156 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12157 ret void12158}12159 12160define void @test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {12161; CHECK-LABEL: test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:12162; CHECK: # %bb.0: # %entry12163; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12164; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v1612165; CHECK-NEXT: ret12166entry:12167 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 6)12168 ret void12169}12170 12171define void @test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {12172; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i8:12173; CHECK: # %bb.0: # %entry12174; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12175; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t12176; CHECK-NEXT: ret12177entry:12178 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12179 ret void12180}12181 12182define void @test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {12183; CHECK-LABEL: test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:12184; CHECK: # %bb.0: # %entry12185; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12186; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v1612187; CHECK-NEXT: ret12188entry:12189 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 6)12190 ret void12191}12192 12193define void @test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {12194; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i16:12195; CHECK: # %bb.0: # %entry12196; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12197; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t12198; CHECK-NEXT: ret12199entry:12200 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12201 ret void12202}12203 12204define void @test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {12205; CHECK-LABEL: test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:12206; CHECK: # %bb.0: # %entry12207; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12208; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v1612209; CHECK-NEXT: ret12210entry:12211 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 6)12212 ret void12213}12214 12215define void @test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {12216; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i32:12217; CHECK: # %bb.0: # %entry12218; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12219; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t12220; CHECK-NEXT: ret12221entry:12222 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12223 ret void12224}12225 12226define void @test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {12227; CHECK-LABEL: test_vsuxseg8_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i64:12228; CHECK: # %bb.0: # %entry12229; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12230; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v1612231; CHECK-NEXT: ret12232entry:12233 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 6)12234 ret void12235}12236 12237define void @test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {12238; CHECK-LABEL: test_vsuxseg8_mask_nxv1f64_triscv.vector.tuple_nxv8i8_8t_nxv1i64:12239; CHECK: # %bb.0: # %entry12240; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma12241; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t12242; CHECK-NEXT: ret12243entry:12244 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 6)12245 ret void12246}12247 12248define void @test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {12249; CHECK-LABEL: test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:12250; CHECK: # %bb.0: # %entry12251; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12252; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1012253; CHECK-NEXT: ret12254entry:12255 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)12256 ret void12257}12258 12259define void @test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {12260; CHECK-LABEL: test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i8:12261; CHECK: # %bb.0: # %entry12262; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12263; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t12264; CHECK-NEXT: ret12265entry:12266 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12267 ret void12268}12269 12270define void @test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {12271; CHECK-LABEL: test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:12272; CHECK: # %bb.0: # %entry12273; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12274; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1012275; CHECK-NEXT: ret12276entry:12277 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)12278 ret void12279}12280 12281define void @test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {12282; CHECK-LABEL: test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i16:12283; CHECK: # %bb.0: # %entry12284; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12285; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t12286; CHECK-NEXT: ret12287entry:12288 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12289 ret void12290}12291 12292define void @test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {12293; CHECK-LABEL: test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:12294; CHECK: # %bb.0: # %entry12295; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12296; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1012297; CHECK-NEXT: ret12298entry:12299 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)12300 ret void12301}12302 12303define void @test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {12304; CHECK-LABEL: test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i32:12305; CHECK: # %bb.0: # %entry12306; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12307; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t12308; CHECK-NEXT: ret12309entry:12310 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12311 ret void12312}12313 12314define void @test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {12315; CHECK-LABEL: test_vsuxseg2_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i64:12316; CHECK: # %bb.0: # %entry12317; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12318; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1012319; CHECK-NEXT: ret12320entry:12321 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv2i8_2t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)12322 ret void12323}12324 12325define void @test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {12326; CHECK-LABEL: test_vsuxseg2_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_2t_nxv1i64:12327; CHECK: # %bb.0: # %entry12328; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12329; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t12330; CHECK-NEXT: ret12331entry:12332 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12333 ret void12334}12335 12336define void @test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {12337; CHECK-LABEL: test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:12338; CHECK: # %bb.0: # %entry12339; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12340; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1012341; CHECK-NEXT: ret12342entry:12343 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)12344 ret void12345}12346 12347define void @test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {12348; CHECK-LABEL: test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i8:12349; CHECK: # %bb.0: # %entry12350; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12351; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t12352; CHECK-NEXT: ret12353entry:12354 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12355 ret void12356}12357 12358define void @test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {12359; CHECK-LABEL: test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:12360; CHECK: # %bb.0: # %entry12361; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12362; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1012363; CHECK-NEXT: ret12364entry:12365 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)12366 ret void12367}12368 12369define void @test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {12370; CHECK-LABEL: test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i16:12371; CHECK: # %bb.0: # %entry12372; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12373; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t12374; CHECK-NEXT: ret12375entry:12376 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12377 ret void12378}12379 12380define void @test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {12381; CHECK-LABEL: test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:12382; CHECK: # %bb.0: # %entry12383; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12384; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1012385; CHECK-NEXT: ret12386entry:12387 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)12388 ret void12389}12390 12391define void @test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {12392; CHECK-LABEL: test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i32:12393; CHECK: # %bb.0: # %entry12394; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12395; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t12396; CHECK-NEXT: ret12397entry:12398 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12399 ret void12400}12401 12402define void @test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {12403; CHECK-LABEL: test_vsuxseg2_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i64:12404; CHECK: # %bb.0: # %entry12405; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12406; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1012407; CHECK-NEXT: ret12408entry:12409 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)12410 ret void12411}12412 12413define void @test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {12414; CHECK-LABEL: test_vsuxseg2_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_2t_nxv2i64:12415; CHECK: # %bb.0: # %entry12416; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12417; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v10, v0.t12418; CHECK-NEXT: ret12419entry:12420 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12421 ret void12422}12423 12424define void @test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {12425; CHECK-LABEL: test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:12426; CHECK: # %bb.0: # %entry12427; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12428; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1012429; CHECK-NEXT: ret12430entry:12431 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)12432 ret void12433}12434 12435define void @test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {12436; CHECK-LABEL: test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i8:12437; CHECK: # %bb.0: # %entry12438; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12439; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v10, v0.t12440; CHECK-NEXT: ret12441entry:12442 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12443 ret void12444}12445 12446define void @test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {12447; CHECK-LABEL: test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:12448; CHECK: # %bb.0: # %entry12449; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12450; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1012451; CHECK-NEXT: ret12452entry:12453 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)12454 ret void12455}12456 12457define void @test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {12458; CHECK-LABEL: test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i16:12459; CHECK: # %bb.0: # %entry12460; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12461; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v10, v0.t12462; CHECK-NEXT: ret12463entry:12464 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12465 ret void12466}12467 12468define void @test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {12469; CHECK-LABEL: test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:12470; CHECK: # %bb.0: # %entry12471; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12472; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1012473; CHECK-NEXT: ret12474entry:12475 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)12476 ret void12477}12478 12479define void @test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {12480; CHECK-LABEL: test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i32:12481; CHECK: # %bb.0: # %entry12482; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12483; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v10, v0.t12484; CHECK-NEXT: ret12485entry:12486 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12487 ret void12488}12489 12490define void @test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {12491; CHECK-LABEL: test_vsuxseg2_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i64:12492; CHECK: # %bb.0: # %entry12493; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12494; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1212495; CHECK-NEXT: ret12496entry:12497 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv8i8_2t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)12498 ret void12499}12500 12501define void @test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {12502; CHECK-LABEL: test_vsuxseg2_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_2t_nxv4i64:12503; CHECK: # %bb.0: # %entry12504; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12505; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v12, v0.t12506; CHECK-NEXT: ret12507entry:12508 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv8i8_2t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12509 ret void12510}12511 12512define void @test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {12513; CHECK-LABEL: test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:12514; CHECK: # %bb.0: # %entry12515; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12516; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1212517; CHECK-NEXT: ret12518entry:12519 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)12520 ret void12521}12522 12523define void @test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {12524; CHECK-LABEL: test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i8:12525; CHECK: # %bb.0: # %entry12526; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12527; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v12, v0.t12528; CHECK-NEXT: ret12529entry:12530 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)12531 ret void12532}12533 12534define void @test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {12535; CHECK-LABEL: test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:12536; CHECK: # %bb.0: # %entry12537; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12538; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1212539; CHECK-NEXT: ret12540entry:12541 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)12542 ret void12543}12544 12545define void @test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {12546; CHECK-LABEL: test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i16:12547; CHECK: # %bb.0: # %entry12548; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12549; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v12, v0.t12550; CHECK-NEXT: ret12551entry:12552 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)12553 ret void12554}12555 12556define void @test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {12557; CHECK-LABEL: test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:12558; CHECK: # %bb.0: # %entry12559; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12560; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1212561; CHECK-NEXT: ret12562entry:12563 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)12564 ret void12565}12566 12567define void @test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {12568; CHECK-LABEL: test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i32:12569; CHECK: # %bb.0: # %entry12570; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12571; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v12, v0.t12572; CHECK-NEXT: ret12573entry:12574 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)12575 ret void12576}12577 12578define void @test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {12579; CHECK-LABEL: test_vsuxseg2_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i64:12580; CHECK: # %bb.0: # %entry12581; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12582; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v1612583; CHECK-NEXT: ret12584entry:12585 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv16i8_2t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)12586 ret void12587}12588 12589define void @test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {12590; CHECK-LABEL: test_vsuxseg2_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_2t_nxv8i64:12591; CHECK: # %bb.0: # %entry12592; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12593; CHECK-NEXT: vsuxseg2ei64.v v8, (a0), v16, v0.t12594; CHECK-NEXT: ret12595entry:12596 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv16i8_2t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 2) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)12597 ret void12598}12599 12600define void @test_vsuxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl) {12601; CHECK-LABEL: test_vsuxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:12602; CHECK: # %bb.0: # %entry12603; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma12604; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v1612605; CHECK-NEXT: ret12606entry:12607 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, i64 4)12608 ret void12609}12610 12611define void @test_vsuxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, i64 %vl, <vscale x 16 x i1> %mask) {12612; CHECK-LABEL: test_vsuxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i8:12613; CHECK: # %bb.0: # %entry12614; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma12615; CHECK-NEXT: vsuxseg2ei8.v v8, (a0), v16, v0.t12616; CHECK-NEXT: ret12617entry:12618 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i8.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)12619 ret void12620}12621 12622define void @test_vsuxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl) {12623; CHECK-LABEL: test_vsuxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:12624; CHECK: # %bb.0: # %entry12625; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma12626; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v1612627; CHECK-NEXT: ret12628entry:12629 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, i64 4)12630 ret void12631}12632 12633define void @test_vsuxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 %vl, <vscale x 16 x i1> %mask) {12634; CHECK-LABEL: test_vsuxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i16:12635; CHECK: # %bb.0: # %entry12636; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma12637; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t12638; CHECK-NEXT: ret12639entry:12640 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)12641 ret void12642}12643 12644define void @test_vsuxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl) {12645; CHECK-LABEL: test_vsuxseg2_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:12646; CHECK: # %bb.0: # %entry12647; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma12648; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v1612649; CHECK-NEXT: ret12650entry:12651 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, i64 4)12652 ret void12653}12654 12655define void @test_vsuxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, i64 %vl, <vscale x 16 x i1> %mask) {12656; CHECK-LABEL: test_vsuxseg2_mask_nxv16bf16_triscv.vector.tuple_nxv32i8_2t_nxv16i32:12657; CHECK: # %bb.0: # %entry12658; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma12659; CHECK-NEXT: vsuxseg2ei32.v v8, (a0), v16, v0.t12660; CHECK-NEXT: ret12661entry:12662 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i32.nxv16i1(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl, i64 4)12663 ret void12664}12665 12666define void @test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {12667; CHECK-LABEL: test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:12668; CHECK: # %bb.0: # %entry12669; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12670; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1112671; CHECK-NEXT: ret12672entry:12673 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)12674 ret void12675}12676 12677define void @test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {12678; CHECK-LABEL: test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i8:12679; CHECK: # %bb.0: # %entry12680; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12681; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t12682; CHECK-NEXT: ret12683entry:12684 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12685 ret void12686}12687 12688define void @test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {12689; CHECK-LABEL: test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:12690; CHECK: # %bb.0: # %entry12691; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12692; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1112693; CHECK-NEXT: ret12694entry:12695 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)12696 ret void12697}12698 12699define void @test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {12700; CHECK-LABEL: test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i16:12701; CHECK: # %bb.0: # %entry12702; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12703; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t12704; CHECK-NEXT: ret12705entry:12706 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12707 ret void12708}12709 12710define void @test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {12711; CHECK-LABEL: test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:12712; CHECK: # %bb.0: # %entry12713; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12714; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1112715; CHECK-NEXT: ret12716entry:12717 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)12718 ret void12719}12720 12721define void @test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {12722; CHECK-LABEL: test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i32:12723; CHECK: # %bb.0: # %entry12724; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12725; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t12726; CHECK-NEXT: ret12727entry:12728 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12729 ret void12730}12731 12732define void @test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {12733; CHECK-LABEL: test_vsuxseg3_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i64:12734; CHECK: # %bb.0: # %entry12735; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12736; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1112737; CHECK-NEXT: ret12738entry:12739 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv2i8_3t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)12740 ret void12741}12742 12743define void @test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {12744; CHECK-LABEL: test_vsuxseg3_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_3t_nxv1i64:12745; CHECK: # %bb.0: # %entry12746; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma12747; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v11, v0.t12748; CHECK-NEXT: ret12749entry:12750 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)12751 ret void12752}12753 12754define void @test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {12755; CHECK-LABEL: test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:12756; CHECK: # %bb.0: # %entry12757; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12758; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1112759; CHECK-NEXT: ret12760entry:12761 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)12762 ret void12763}12764 12765define void @test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {12766; CHECK-LABEL: test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i8:12767; CHECK: # %bb.0: # %entry12768; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12769; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t12770; CHECK-NEXT: ret12771entry:12772 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12773 ret void12774}12775 12776define void @test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {12777; CHECK-LABEL: test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:12778; CHECK: # %bb.0: # %entry12779; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12780; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1112781; CHECK-NEXT: ret12782entry:12783 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)12784 ret void12785}12786 12787define void @test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {12788; CHECK-LABEL: test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i16:12789; CHECK: # %bb.0: # %entry12790; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12791; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t12792; CHECK-NEXT: ret12793entry:12794 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12795 ret void12796}12797 12798define void @test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {12799; CHECK-LABEL: test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:12800; CHECK: # %bb.0: # %entry12801; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12802; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1112803; CHECK-NEXT: ret12804entry:12805 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)12806 ret void12807}12808 12809define void @test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {12810; CHECK-LABEL: test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i32:12811; CHECK: # %bb.0: # %entry12812; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12813; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v11, v0.t12814; CHECK-NEXT: ret12815entry:12816 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12817 ret void12818}12819 12820define void @test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {12821; CHECK-LABEL: test_vsuxseg3_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i64:12822; CHECK: # %bb.0: # %entry12823; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12824; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1212825; CHECK-NEXT: ret12826entry:12827 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)12828 ret void12829}12830 12831define void @test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {12832; CHECK-LABEL: test_vsuxseg3_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_3t_nxv2i64:12833; CHECK: # %bb.0: # %entry12834; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma12835; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t12836; CHECK-NEXT: ret12837entry:12838 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)12839 ret void12840}12841 12842define void @test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {12843; CHECK-LABEL: test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:12844; CHECK: # %bb.0: # %entry12845; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12846; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1112847; CHECK-NEXT: ret12848entry:12849 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)12850 ret void12851}12852 12853define void @test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {12854; CHECK-LABEL: test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i8:12855; CHECK: # %bb.0: # %entry12856; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12857; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v11, v0.t12858; CHECK-NEXT: ret12859entry:12860 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12861 ret void12862}12863 12864define void @test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {12865; CHECK-LABEL: test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:12866; CHECK: # %bb.0: # %entry12867; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12868; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1112869; CHECK-NEXT: ret12870entry:12871 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)12872 ret void12873}12874 12875define void @test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {12876; CHECK-LABEL: test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i16:12877; CHECK: # %bb.0: # %entry12878; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12879; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v11, v0.t12880; CHECK-NEXT: ret12881entry:12882 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12883 ret void12884}12885 12886define void @test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {12887; CHECK-LABEL: test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:12888; CHECK: # %bb.0: # %entry12889; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12890; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1212891; CHECK-NEXT: ret12892entry:12893 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)12894 ret void12895}12896 12897define void @test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {12898; CHECK-LABEL: test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i32:12899; CHECK: # %bb.0: # %entry12900; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12901; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v12, v0.t12902; CHECK-NEXT: ret12903entry:12904 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12905 ret void12906}12907 12908define void @test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {12909; CHECK-LABEL: test_vsuxseg3_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i64:12910; CHECK: # %bb.0: # %entry12911; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12912; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1212913; CHECK-NEXT: ret12914entry:12915 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv8i8_3t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)12916 ret void12917}12918 12919define void @test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {12920; CHECK-LABEL: test_vsuxseg3_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_3t_nxv4i64:12921; CHECK: # %bb.0: # %entry12922; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma12923; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v12, v0.t12924; CHECK-NEXT: ret12925entry:12926 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv8i8_3t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 3) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)12927 ret void12928}12929 12930define void @test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {12931; CHECK-LABEL: test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:12932; CHECK: # %bb.0: # %entry12933; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12934; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v1412935; CHECK-NEXT: ret12936entry:12937 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)12938 ret void12939}12940 12941define void @test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {12942; CHECK-LABEL: test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i8:12943; CHECK: # %bb.0: # %entry12944; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12945; CHECK-NEXT: vsuxseg3ei8.v v8, (a0), v14, v0.t12946; CHECK-NEXT: ret12947entry:12948 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)12949 ret void12950}12951 12952define void @test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {12953; CHECK-LABEL: test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:12954; CHECK: # %bb.0: # %entry12955; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12956; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v1412957; CHECK-NEXT: ret12958entry:12959 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)12960 ret void12961}12962 12963define void @test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {12964; CHECK-LABEL: test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i16:12965; CHECK: # %bb.0: # %entry12966; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12967; CHECK-NEXT: vsuxseg3ei16.v v8, (a0), v14, v0.t12968; CHECK-NEXT: ret12969entry:12970 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)12971 ret void12972}12973 12974define void @test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {12975; CHECK-LABEL: test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:12976; CHECK: # %bb.0: # %entry12977; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12978; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v1612979; CHECK-NEXT: ret12980entry:12981 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)12982 ret void12983}12984 12985define void @test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {12986; CHECK-LABEL: test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i32:12987; CHECK: # %bb.0: # %entry12988; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma12989; CHECK-NEXT: vsuxseg3ei32.v v8, (a0), v16, v0.t12990; CHECK-NEXT: ret12991entry:12992 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)12993 ret void12994}12995 12996define void @test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {12997; CHECK-LABEL: test_vsuxseg3_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i64:12998; CHECK: # %bb.0: # %entry12999; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13000; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v1613001; CHECK-NEXT: ret13002entry:13003 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv16i8_3t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)13004 ret void13005}13006 13007define void @test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {13008; CHECK-LABEL: test_vsuxseg3_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_3t_nxv8i64:13009; CHECK: # %bb.0: # %entry13010; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13011; CHECK-NEXT: vsuxseg3ei64.v v8, (a0), v16, v0.t13012; CHECK-NEXT: ret13013entry:13014 tail call void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv16i8_3t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 3) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)13015 ret void13016}13017 13018define void @test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {13019; CHECK-LABEL: test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:13020; CHECK: # %bb.0: # %entry13021; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13022; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1213023; CHECK-NEXT: ret13024entry:13025 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)13026 ret void13027}13028 13029define void @test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {13030; CHECK-LABEL: test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i8:13031; CHECK: # %bb.0: # %entry13032; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13033; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t13034; CHECK-NEXT: ret13035entry:13036 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13037 ret void13038}13039 13040define void @test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {13041; CHECK-LABEL: test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:13042; CHECK: # %bb.0: # %entry13043; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13044; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1213045; CHECK-NEXT: ret13046entry:13047 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)13048 ret void13049}13050 13051define void @test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {13052; CHECK-LABEL: test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i16:13053; CHECK: # %bb.0: # %entry13054; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13055; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t13056; CHECK-NEXT: ret13057entry:13058 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13059 ret void13060}13061 13062define void @test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {13063; CHECK-LABEL: test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:13064; CHECK: # %bb.0: # %entry13065; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13066; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1213067; CHECK-NEXT: ret13068entry:13069 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)13070 ret void13071}13072 13073define void @test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {13074; CHECK-LABEL: test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i32:13075; CHECK: # %bb.0: # %entry13076; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13077; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t13078; CHECK-NEXT: ret13079entry:13080 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13081 ret void13082}13083 13084define void @test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {13085; CHECK-LABEL: test_vsuxseg4_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i64:13086; CHECK: # %bb.0: # %entry13087; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13088; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1213089; CHECK-NEXT: ret13090entry:13091 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv2i8_4t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)13092 ret void13093}13094 13095define void @test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {13096; CHECK-LABEL: test_vsuxseg4_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_4t_nxv1i64:13097; CHECK: # %bb.0: # %entry13098; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13099; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t13100; CHECK-NEXT: ret13101entry:13102 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13103 ret void13104}13105 13106define void @test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {13107; CHECK-LABEL: test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:13108; CHECK: # %bb.0: # %entry13109; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13110; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1213111; CHECK-NEXT: ret13112entry:13113 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)13114 ret void13115}13116 13117define void @test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {13118; CHECK-LABEL: test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i8:13119; CHECK: # %bb.0: # %entry13120; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13121; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t13122; CHECK-NEXT: ret13123entry:13124 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13125 ret void13126}13127 13128define void @test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {13129; CHECK-LABEL: test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:13130; CHECK: # %bb.0: # %entry13131; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13132; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1213133; CHECK-NEXT: ret13134entry:13135 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)13136 ret void13137}13138 13139define void @test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {13140; CHECK-LABEL: test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i16:13141; CHECK: # %bb.0: # %entry13142; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13143; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t13144; CHECK-NEXT: ret13145entry:13146 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13147 ret void13148}13149 13150define void @test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {13151; CHECK-LABEL: test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:13152; CHECK: # %bb.0: # %entry13153; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13154; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1213155; CHECK-NEXT: ret13156entry:13157 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)13158 ret void13159}13160 13161define void @test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {13162; CHECK-LABEL: test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i32:13163; CHECK: # %bb.0: # %entry13164; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13165; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t13166; CHECK-NEXT: ret13167entry:13168 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13169 ret void13170}13171 13172define void @test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {13173; CHECK-LABEL: test_vsuxseg4_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i64:13174; CHECK: # %bb.0: # %entry13175; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13176; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1213177; CHECK-NEXT: ret13178entry:13179 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)13180 ret void13181}13182 13183define void @test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {13184; CHECK-LABEL: test_vsuxseg4_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_4t_nxv2i64:13185; CHECK: # %bb.0: # %entry13186; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13187; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t13188; CHECK-NEXT: ret13189entry:13190 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13191 ret void13192}13193 13194define void @test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {13195; CHECK-LABEL: test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:13196; CHECK: # %bb.0: # %entry13197; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13198; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1213199; CHECK-NEXT: ret13200entry:13201 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)13202 ret void13203}13204 13205define void @test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {13206; CHECK-LABEL: test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i8:13207; CHECK: # %bb.0: # %entry13208; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13209; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v12, v0.t13210; CHECK-NEXT: ret13211entry:13212 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13213 ret void13214}13215 13216define void @test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {13217; CHECK-LABEL: test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:13218; CHECK: # %bb.0: # %entry13219; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13220; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1213221; CHECK-NEXT: ret13222entry:13223 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)13224 ret void13225}13226 13227define void @test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {13228; CHECK-LABEL: test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i16:13229; CHECK: # %bb.0: # %entry13230; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13231; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v12, v0.t13232; CHECK-NEXT: ret13233entry:13234 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13235 ret void13236}13237 13238define void @test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {13239; CHECK-LABEL: test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:13240; CHECK: # %bb.0: # %entry13241; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13242; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1213243; CHECK-NEXT: ret13244entry:13245 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)13246 ret void13247}13248 13249define void @test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {13250; CHECK-LABEL: test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i32:13251; CHECK: # %bb.0: # %entry13252; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13253; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v12, v0.t13254; CHECK-NEXT: ret13255entry:13256 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13257 ret void13258}13259 13260define void @test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {13261; CHECK-LABEL: test_vsuxseg4_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i64:13262; CHECK: # %bb.0: # %entry13263; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13264; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1213265; CHECK-NEXT: ret13266entry:13267 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv8i8_4t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)13268 ret void13269}13270 13271define void @test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {13272; CHECK-LABEL: test_vsuxseg4_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_4t_nxv4i64:13273; CHECK: # %bb.0: # %entry13274; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13275; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v12, v0.t13276; CHECK-NEXT: ret13277entry:13278 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv8i8_4t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 4) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13279 ret void13280}13281 13282define void @test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl) {13283; CHECK-LABEL: test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:13284; CHECK: # %bb.0: # %entry13285; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13286; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v1613287; CHECK-NEXT: ret13288entry:13289 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, i64 4)13290 ret void13291}13292 13293define void @test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, i64 %vl, <vscale x 8 x i1> %mask) {13294; CHECK-LABEL: test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i8:13295; CHECK: # %bb.0: # %entry13296; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13297; CHECK-NEXT: vsuxseg4ei8.v v8, (a0), v16, v0.t13298; CHECK-NEXT: ret13299entry:13300 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i8.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)13301 ret void13302}13303 13304define void @test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl) {13305; CHECK-LABEL: test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:13306; CHECK: # %bb.0: # %entry13307; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13308; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v1613309; CHECK-NEXT: ret13310entry:13311 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, i64 4)13312 ret void13313}13314 13315define void @test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, i64 %vl, <vscale x 8 x i1> %mask) {13316; CHECK-LABEL: test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i16:13317; CHECK: # %bb.0: # %entry13318; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13319; CHECK-NEXT: vsuxseg4ei16.v v8, (a0), v16, v0.t13320; CHECK-NEXT: ret13321entry:13322 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i16.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)13323 ret void13324}13325 13326define void @test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl) {13327; CHECK-LABEL: test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:13328; CHECK: # %bb.0: # %entry13329; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13330; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v1613331; CHECK-NEXT: ret13332entry:13333 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, i64 4)13334 ret void13335}13336 13337define void @test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, i64 %vl, <vscale x 8 x i1> %mask) {13338; CHECK-LABEL: test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i32:13339; CHECK: # %bb.0: # %entry13340; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13341; CHECK-NEXT: vsuxseg4ei32.v v8, (a0), v16, v0.t13342; CHECK-NEXT: ret13343entry:13344 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i32.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)13345 ret void13346}13347 13348define void @test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl) {13349; CHECK-LABEL: test_vsuxseg4_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i64:13350; CHECK: # %bb.0: # %entry13351; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13352; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v1613353; CHECK-NEXT: ret13354entry:13355 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv16i8_4t.nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, i64 4)13356 ret void13357}13358 13359define void @test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i64(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, i64 %vl, <vscale x 8 x i1> %mask) {13360; CHECK-LABEL: test_vsuxseg4_mask_nxv8bf16_triscv.vector.tuple_nxv16i8_4t_nxv8i64:13361; CHECK: # %bb.0: # %entry13362; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma13363; CHECK-NEXT: vsuxseg4ei64.v v8, (a0), v16, v0.t13364; CHECK-NEXT: ret13365entry:13366 tail call void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv16i8_4t.nxv8i64.nxv8i1(target("riscv.vector.tuple", <vscale x 16 x i8>, 4) %val, ptr %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl, i64 4)13367 ret void13368}13369 13370define void @test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {13371; CHECK-LABEL: test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:13372; CHECK: # %bb.0: # %entry13373; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13374; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v1313375; CHECK-NEXT: ret13376entry:13377 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)13378 ret void13379}13380 13381define void @test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {13382; CHECK-LABEL: test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i8:13383; CHECK: # %bb.0: # %entry13384; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13385; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t13386; CHECK-NEXT: ret13387entry:13388 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13389 ret void13390}13391 13392define void @test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {13393; CHECK-LABEL: test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:13394; CHECK: # %bb.0: # %entry13395; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13396; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v1313397; CHECK-NEXT: ret13398entry:13399 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)13400 ret void13401}13402 13403define void @test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {13404; CHECK-LABEL: test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i16:13405; CHECK: # %bb.0: # %entry13406; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13407; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t13408; CHECK-NEXT: ret13409entry:13410 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13411 ret void13412}13413 13414define void @test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {13415; CHECK-LABEL: test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:13416; CHECK: # %bb.0: # %entry13417; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13418; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v1313419; CHECK-NEXT: ret13420entry:13421 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)13422 ret void13423}13424 13425define void @test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {13426; CHECK-LABEL: test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i32:13427; CHECK: # %bb.0: # %entry13428; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13429; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t13430; CHECK-NEXT: ret13431entry:13432 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13433 ret void13434}13435 13436define void @test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {13437; CHECK-LABEL: test_vsuxseg5_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i64:13438; CHECK: # %bb.0: # %entry13439; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13440; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v1313441; CHECK-NEXT: ret13442entry:13443 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv2i8_5t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)13444 ret void13445}13446 13447define void @test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {13448; CHECK-LABEL: test_vsuxseg5_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_5t_nxv1i64:13449; CHECK: # %bb.0: # %entry13450; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13451; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v13, v0.t13452; CHECK-NEXT: ret13453entry:13454 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13455 ret void13456}13457 13458define void @test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {13459; CHECK-LABEL: test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:13460; CHECK: # %bb.0: # %entry13461; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13462; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v1313463; CHECK-NEXT: ret13464entry:13465 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)13466 ret void13467}13468 13469define void @test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {13470; CHECK-LABEL: test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i8:13471; CHECK: # %bb.0: # %entry13472; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13473; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t13474; CHECK-NEXT: ret13475entry:13476 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13477 ret void13478}13479 13480define void @test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {13481; CHECK-LABEL: test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:13482; CHECK: # %bb.0: # %entry13483; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13484; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v1313485; CHECK-NEXT: ret13486entry:13487 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)13488 ret void13489}13490 13491define void @test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {13492; CHECK-LABEL: test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i16:13493; CHECK: # %bb.0: # %entry13494; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13495; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t13496; CHECK-NEXT: ret13497entry:13498 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13499 ret void13500}13501 13502define void @test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {13503; CHECK-LABEL: test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:13504; CHECK: # %bb.0: # %entry13505; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13506; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v1313507; CHECK-NEXT: ret13508entry:13509 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)13510 ret void13511}13512 13513define void @test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {13514; CHECK-LABEL: test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i32:13515; CHECK: # %bb.0: # %entry13516; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13517; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v13, v0.t13518; CHECK-NEXT: ret13519entry:13520 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13521 ret void13522}13523 13524define void @test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {13525; CHECK-LABEL: test_vsuxseg5_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i64:13526; CHECK: # %bb.0: # %entry13527; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13528; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v1413529; CHECK-NEXT: ret13530entry:13531 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)13532 ret void13533}13534 13535define void @test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {13536; CHECK-LABEL: test_vsuxseg5_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_5t_nxv2i64:13537; CHECK: # %bb.0: # %entry13538; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13539; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v14, v0.t13540; CHECK-NEXT: ret13541entry:13542 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13543 ret void13544}13545 13546define void @test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {13547; CHECK-LABEL: test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:13548; CHECK: # %bb.0: # %entry13549; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13550; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v1313551; CHECK-NEXT: ret13552entry:13553 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)13554 ret void13555}13556 13557define void @test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {13558; CHECK-LABEL: test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i8:13559; CHECK: # %bb.0: # %entry13560; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13561; CHECK-NEXT: vsuxseg5ei8.v v8, (a0), v13, v0.t13562; CHECK-NEXT: ret13563entry:13564 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13565 ret void13566}13567 13568define void @test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {13569; CHECK-LABEL: test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:13570; CHECK: # %bb.0: # %entry13571; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13572; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v1313573; CHECK-NEXT: ret13574entry:13575 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)13576 ret void13577}13578 13579define void @test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {13580; CHECK-LABEL: test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i16:13581; CHECK: # %bb.0: # %entry13582; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13583; CHECK-NEXT: vsuxseg5ei16.v v8, (a0), v13, v0.t13584; CHECK-NEXT: ret13585entry:13586 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13587 ret void13588}13589 13590define void @test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {13591; CHECK-LABEL: test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:13592; CHECK: # %bb.0: # %entry13593; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13594; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v1413595; CHECK-NEXT: ret13596entry:13597 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)13598 ret void13599}13600 13601define void @test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {13602; CHECK-LABEL: test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i32:13603; CHECK: # %bb.0: # %entry13604; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13605; CHECK-NEXT: vsuxseg5ei32.v v8, (a0), v14, v0.t13606; CHECK-NEXT: ret13607entry:13608 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13609 ret void13610}13611 13612define void @test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {13613; CHECK-LABEL: test_vsuxseg5_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i64:13614; CHECK: # %bb.0: # %entry13615; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13616; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v1613617; CHECK-NEXT: ret13618entry:13619 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv8i8_5t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)13620 ret void13621}13622 13623define void @test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {13624; CHECK-LABEL: test_vsuxseg5_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_5t_nxv4i64:13625; CHECK: # %bb.0: # %entry13626; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13627; CHECK-NEXT: vsuxseg5ei64.v v8, (a0), v16, v0.t13628; CHECK-NEXT: ret13629entry:13630 tail call void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv8i8_5t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 5) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13631 ret void13632}13633 13634define void @test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {13635; CHECK-LABEL: test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:13636; CHECK: # %bb.0: # %entry13637; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13638; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v1413639; CHECK-NEXT: ret13640entry:13641 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)13642 ret void13643}13644 13645define void @test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {13646; CHECK-LABEL: test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i8:13647; CHECK: # %bb.0: # %entry13648; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13649; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t13650; CHECK-NEXT: ret13651entry:13652 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13653 ret void13654}13655 13656define void @test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {13657; CHECK-LABEL: test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:13658; CHECK: # %bb.0: # %entry13659; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13660; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v1413661; CHECK-NEXT: ret13662entry:13663 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)13664 ret void13665}13666 13667define void @test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {13668; CHECK-LABEL: test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i16:13669; CHECK: # %bb.0: # %entry13670; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13671; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t13672; CHECK-NEXT: ret13673entry:13674 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13675 ret void13676}13677 13678define void @test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {13679; CHECK-LABEL: test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:13680; CHECK: # %bb.0: # %entry13681; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13682; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v1413683; CHECK-NEXT: ret13684entry:13685 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)13686 ret void13687}13688 13689define void @test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {13690; CHECK-LABEL: test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i32:13691; CHECK: # %bb.0: # %entry13692; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13693; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t13694; CHECK-NEXT: ret13695entry:13696 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13697 ret void13698}13699 13700define void @test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {13701; CHECK-LABEL: test_vsuxseg6_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i64:13702; CHECK: # %bb.0: # %entry13703; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13704; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v1413705; CHECK-NEXT: ret13706entry:13707 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv2i8_6t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)13708 ret void13709}13710 13711define void @test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {13712; CHECK-LABEL: test_vsuxseg6_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_6t_nxv1i64:13713; CHECK: # %bb.0: # %entry13714; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13715; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t13716; CHECK-NEXT: ret13717entry:13718 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13719 ret void13720}13721 13722define void @test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {13723; CHECK-LABEL: test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:13724; CHECK: # %bb.0: # %entry13725; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13726; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v1413727; CHECK-NEXT: ret13728entry:13729 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)13730 ret void13731}13732 13733define void @test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {13734; CHECK-LABEL: test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i8:13735; CHECK: # %bb.0: # %entry13736; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13737; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t13738; CHECK-NEXT: ret13739entry:13740 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13741 ret void13742}13743 13744define void @test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {13745; CHECK-LABEL: test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:13746; CHECK: # %bb.0: # %entry13747; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13748; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v1413749; CHECK-NEXT: ret13750entry:13751 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)13752 ret void13753}13754 13755define void @test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {13756; CHECK-LABEL: test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i16:13757; CHECK: # %bb.0: # %entry13758; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13759; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t13760; CHECK-NEXT: ret13761entry:13762 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13763 ret void13764}13765 13766define void @test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {13767; CHECK-LABEL: test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:13768; CHECK: # %bb.0: # %entry13769; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13770; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v1413771; CHECK-NEXT: ret13772entry:13773 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)13774 ret void13775}13776 13777define void @test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {13778; CHECK-LABEL: test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i32:13779; CHECK: # %bb.0: # %entry13780; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13781; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t13782; CHECK-NEXT: ret13783entry:13784 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13785 ret void13786}13787 13788define void @test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {13789; CHECK-LABEL: test_vsuxseg6_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i64:13790; CHECK: # %bb.0: # %entry13791; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13792; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v1413793; CHECK-NEXT: ret13794entry:13795 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)13796 ret void13797}13798 13799define void @test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {13800; CHECK-LABEL: test_vsuxseg6_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_6t_nxv2i64:13801; CHECK: # %bb.0: # %entry13802; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13803; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v14, v0.t13804; CHECK-NEXT: ret13805entry:13806 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)13807 ret void13808}13809 13810define void @test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {13811; CHECK-LABEL: test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:13812; CHECK: # %bb.0: # %entry13813; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13814; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v1413815; CHECK-NEXT: ret13816entry:13817 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)13818 ret void13819}13820 13821define void @test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {13822; CHECK-LABEL: test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i8:13823; CHECK: # %bb.0: # %entry13824; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13825; CHECK-NEXT: vsuxseg6ei8.v v8, (a0), v14, v0.t13826; CHECK-NEXT: ret13827entry:13828 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13829 ret void13830}13831 13832define void @test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {13833; CHECK-LABEL: test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:13834; CHECK: # %bb.0: # %entry13835; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13836; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v1413837; CHECK-NEXT: ret13838entry:13839 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)13840 ret void13841}13842 13843define void @test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {13844; CHECK-LABEL: test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i16:13845; CHECK: # %bb.0: # %entry13846; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13847; CHECK-NEXT: vsuxseg6ei16.v v8, (a0), v14, v0.t13848; CHECK-NEXT: ret13849entry:13850 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13851 ret void13852}13853 13854define void @test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {13855; CHECK-LABEL: test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:13856; CHECK: # %bb.0: # %entry13857; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13858; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v1413859; CHECK-NEXT: ret13860entry:13861 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)13862 ret void13863}13864 13865define void @test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {13866; CHECK-LABEL: test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i32:13867; CHECK: # %bb.0: # %entry13868; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13869; CHECK-NEXT: vsuxseg6ei32.v v8, (a0), v14, v0.t13870; CHECK-NEXT: ret13871entry:13872 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13873 ret void13874}13875 13876define void @test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {13877; CHECK-LABEL: test_vsuxseg6_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i64:13878; CHECK: # %bb.0: # %entry13879; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13880; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v1613881; CHECK-NEXT: ret13882entry:13883 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv8i8_6t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)13884 ret void13885}13886 13887define void @test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {13888; CHECK-LABEL: test_vsuxseg6_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_6t_nxv4i64:13889; CHECK: # %bb.0: # %entry13890; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma13891; CHECK-NEXT: vsuxseg6ei64.v v8, (a0), v16, v0.t13892; CHECK-NEXT: ret13893entry:13894 tail call void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv8i8_6t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 6) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)13895 ret void13896}13897 13898define void @test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {13899; CHECK-LABEL: test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:13900; CHECK: # %bb.0: # %entry13901; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13902; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v1513903; CHECK-NEXT: ret13904entry:13905 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)13906 ret void13907}13908 13909define void @test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {13910; CHECK-LABEL: test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i8:13911; CHECK: # %bb.0: # %entry13912; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13913; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t13914; CHECK-NEXT: ret13915entry:13916 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13917 ret void13918}13919 13920define void @test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {13921; CHECK-LABEL: test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:13922; CHECK: # %bb.0: # %entry13923; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13924; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v1513925; CHECK-NEXT: ret13926entry:13927 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)13928 ret void13929}13930 13931define void @test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {13932; CHECK-LABEL: test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i16:13933; CHECK: # %bb.0: # %entry13934; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13935; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t13936; CHECK-NEXT: ret13937entry:13938 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13939 ret void13940}13941 13942define void @test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {13943; CHECK-LABEL: test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:13944; CHECK: # %bb.0: # %entry13945; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13946; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v1513947; CHECK-NEXT: ret13948entry:13949 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)13950 ret void13951}13952 13953define void @test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {13954; CHECK-LABEL: test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i32:13955; CHECK: # %bb.0: # %entry13956; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13957; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t13958; CHECK-NEXT: ret13959entry:13960 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13961 ret void13962}13963 13964define void @test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {13965; CHECK-LABEL: test_vsuxseg7_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i64:13966; CHECK: # %bb.0: # %entry13967; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13968; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v1513969; CHECK-NEXT: ret13970entry:13971 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv2i8_7t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)13972 ret void13973}13974 13975define void @test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {13976; CHECK-LABEL: test_vsuxseg7_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_7t_nxv1i64:13977; CHECK: # %bb.0: # %entry13978; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma13979; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v15, v0.t13980; CHECK-NEXT: ret13981entry:13982 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)13983 ret void13984}13985 13986define void @test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {13987; CHECK-LABEL: test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:13988; CHECK: # %bb.0: # %entry13989; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma13990; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v1513991; CHECK-NEXT: ret13992entry:13993 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)13994 ret void13995}13996 13997define void @test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {13998; CHECK-LABEL: test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i8:13999; CHECK: # %bb.0: # %entry14000; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14001; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t14002; CHECK-NEXT: ret14003entry:14004 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14005 ret void14006}14007 14008define void @test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {14009; CHECK-LABEL: test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:14010; CHECK: # %bb.0: # %entry14011; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14012; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v1514013; CHECK-NEXT: ret14014entry:14015 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)14016 ret void14017}14018 14019define void @test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {14020; CHECK-LABEL: test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i16:14021; CHECK: # %bb.0: # %entry14022; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14023; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t14024; CHECK-NEXT: ret14025entry:14026 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14027 ret void14028}14029 14030define void @test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {14031; CHECK-LABEL: test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:14032; CHECK: # %bb.0: # %entry14033; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14034; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v1514035; CHECK-NEXT: ret14036entry:14037 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)14038 ret void14039}14040 14041define void @test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {14042; CHECK-LABEL: test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i32:14043; CHECK: # %bb.0: # %entry14044; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14045; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v15, v0.t14046; CHECK-NEXT: ret14047entry:14048 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14049 ret void14050}14051 14052define void @test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {14053; CHECK-LABEL: test_vsuxseg7_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i64:14054; CHECK: # %bb.0: # %entry14055; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14056; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v1614057; CHECK-NEXT: ret14058entry:14059 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)14060 ret void14061}14062 14063define void @test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {14064; CHECK-LABEL: test_vsuxseg7_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_7t_nxv2i64:14065; CHECK: # %bb.0: # %entry14066; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14067; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t14068; CHECK-NEXT: ret14069entry:14070 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14071 ret void14072}14073 14074define void @test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {14075; CHECK-LABEL: test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:14076; CHECK: # %bb.0: # %entry14077; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14078; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v1514079; CHECK-NEXT: ret14080entry:14081 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)14082 ret void14083}14084 14085define void @test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {14086; CHECK-LABEL: test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i8:14087; CHECK: # %bb.0: # %entry14088; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14089; CHECK-NEXT: vsuxseg7ei8.v v8, (a0), v15, v0.t14090; CHECK-NEXT: ret14091entry:14092 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14093 ret void14094}14095 14096define void @test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {14097; CHECK-LABEL: test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:14098; CHECK: # %bb.0: # %entry14099; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14100; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v1514101; CHECK-NEXT: ret14102entry:14103 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)14104 ret void14105}14106 14107define void @test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {14108; CHECK-LABEL: test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i16:14109; CHECK: # %bb.0: # %entry14110; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14111; CHECK-NEXT: vsuxseg7ei16.v v8, (a0), v15, v0.t14112; CHECK-NEXT: ret14113entry:14114 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14115 ret void14116}14117 14118define void @test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {14119; CHECK-LABEL: test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:14120; CHECK: # %bb.0: # %entry14121; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14122; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v1614123; CHECK-NEXT: ret14124entry:14125 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)14126 ret void14127}14128 14129define void @test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {14130; CHECK-LABEL: test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i32:14131; CHECK: # %bb.0: # %entry14132; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14133; CHECK-NEXT: vsuxseg7ei32.v v8, (a0), v16, v0.t14134; CHECK-NEXT: ret14135entry:14136 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14137 ret void14138}14139 14140define void @test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {14141; CHECK-LABEL: test_vsuxseg7_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i64:14142; CHECK: # %bb.0: # %entry14143; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14144; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v1614145; CHECK-NEXT: ret14146entry:14147 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv8i8_7t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)14148 ret void14149}14150 14151define void @test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {14152; CHECK-LABEL: test_vsuxseg7_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_7t_nxv4i64:14153; CHECK: # %bb.0: # %entry14154; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14155; CHECK-NEXT: vsuxseg7ei64.v v8, (a0), v16, v0.t14156; CHECK-NEXT: ret14157entry:14158 tail call void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv8i8_7t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 7) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14159 ret void14160}14161 14162define void @test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl) {14163; CHECK-LABEL: test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:14164; CHECK: # %bb.0: # %entry14165; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14166; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v1614167; CHECK-NEXT: ret14168entry:14169 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, i64 4)14170 ret void14171}14172 14173define void @test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, i64 %vl, <vscale x 1 x i1> %mask) {14174; CHECK-LABEL: test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i8:14175; CHECK: # %bb.0: # %entry14176; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14177; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t14178; CHECK-NEXT: ret14179entry:14180 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i8.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)14181 ret void14182}14183 14184define void @test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) {14185; CHECK-LABEL: test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:14186; CHECK: # %bb.0: # %entry14187; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14188; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v1614189; CHECK-NEXT: ret14190entry:14191 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 4)14192 ret void14193}14194 14195define void @test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) {14196; CHECK-LABEL: test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i16:14197; CHECK: # %bb.0: # %entry14198; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14199; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t14200; CHECK-NEXT: ret14201entry:14202 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)14203 ret void14204}14205 14206define void @test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl) {14207; CHECK-LABEL: test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:14208; CHECK: # %bb.0: # %entry14209; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14210; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v1614211; CHECK-NEXT: ret14212entry:14213 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, i64 4)14214 ret void14215}14216 14217define void @test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, i64 %vl, <vscale x 1 x i1> %mask) {14218; CHECK-LABEL: test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i32:14219; CHECK: # %bb.0: # %entry14220; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14221; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t14222; CHECK-NEXT: ret14223entry:14224 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i32.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)14225 ret void14226}14227 14228define void @test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl) {14229; CHECK-LABEL: test_vsuxseg8_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i64:14230; CHECK: # %bb.0: # %entry14231; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14232; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v1614233; CHECK-NEXT: ret14234entry:14235 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv2i8_8t.nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, i64 4)14236 ret void14237}14238 14239define void @test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i64(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, i64 %vl, <vscale x 1 x i1> %mask) {14240; CHECK-LABEL: test_vsuxseg8_mask_nxv1bf16_triscv.vector.tuple_nxv2i8_8t_nxv1i64:14241; CHECK: # %bb.0: # %entry14242; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma14243; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t14244; CHECK-NEXT: ret14245entry:14246 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv1i64.nxv1i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8) %val, ptr %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 4)14247 ret void14248}14249 14250define void @test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl) {14251; CHECK-LABEL: test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:14252; CHECK: # %bb.0: # %entry14253; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14254; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v1614255; CHECK-NEXT: ret14256entry:14257 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, i64 4)14258 ret void14259}14260 14261define void @test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, i64 %vl, <vscale x 2 x i1> %mask) {14262; CHECK-LABEL: test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i8:14263; CHECK: # %bb.0: # %entry14264; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14265; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t14266; CHECK-NEXT: ret14267entry:14268 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i8.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14269 ret void14270}14271 14272define void @test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl) {14273; CHECK-LABEL: test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:14274; CHECK: # %bb.0: # %entry14275; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14276; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v1614277; CHECK-NEXT: ret14278entry:14279 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, i64 4)14280 ret void14281}14282 14283define void @test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, i64 %vl, <vscale x 2 x i1> %mask) {14284; CHECK-LABEL: test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i16:14285; CHECK: # %bb.0: # %entry14286; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14287; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t14288; CHECK-NEXT: ret14289entry:14290 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i16.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14291 ret void14292}14293 14294define void @test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl) {14295; CHECK-LABEL: test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:14296; CHECK: # %bb.0: # %entry14297; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14298; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v1614299; CHECK-NEXT: ret14300entry:14301 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, i64 4)14302 ret void14303}14304 14305define void @test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, i64 %vl, <vscale x 2 x i1> %mask) {14306; CHECK-LABEL: test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i32:14307; CHECK: # %bb.0: # %entry14308; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14309; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t14310; CHECK-NEXT: ret14311entry:14312 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i32.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14313 ret void14314}14315 14316define void @test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl) {14317; CHECK-LABEL: test_vsuxseg8_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i64:14318; CHECK: # %bb.0: # %entry14319; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14320; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v1614321; CHECK-NEXT: ret14322entry:14323 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, i64 4)14324 ret void14325}14326 14327define void @test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, i64 %vl, <vscale x 2 x i1> %mask) {14328; CHECK-LABEL: test_vsuxseg8_mask_nxv2bf16_triscv.vector.tuple_nxv4i8_8t_nxv2i64:14329; CHECK: # %bb.0: # %entry14330; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma14331; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t14332; CHECK-NEXT: ret14333entry:14334 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv2i64.nxv2i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl, i64 4)14335 ret void14336}14337 14338define void @test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl) {14339; CHECK-LABEL: test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:14340; CHECK: # %bb.0: # %entry14341; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14342; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v1614343; CHECK-NEXT: ret14344entry:14345 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, i64 4)14346 ret void14347}14348 14349define void @test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, i64 %vl, <vscale x 4 x i1> %mask) {14350; CHECK-LABEL: test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i8:14351; CHECK: # %bb.0: # %entry14352; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14353; CHECK-NEXT: vsuxseg8ei8.v v8, (a0), v16, v0.t14354; CHECK-NEXT: ret14355entry:14356 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14357 ret void14358}14359 14360define void @test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl) {14361; CHECK-LABEL: test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:14362; CHECK: # %bb.0: # %entry14363; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14364; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v1614365; CHECK-NEXT: ret14366entry:14367 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, i64 4)14368 ret void14369}14370 14371define void @test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, i64 %vl, <vscale x 4 x i1> %mask) {14372; CHECK-LABEL: test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i16:14373; CHECK: # %bb.0: # %entry14374; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14375; CHECK-NEXT: vsuxseg8ei16.v v8, (a0), v16, v0.t14376; CHECK-NEXT: ret14377entry:14378 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i16.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14379 ret void14380}14381 14382define void @test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl) {14383; CHECK-LABEL: test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:14384; CHECK: # %bb.0: # %entry14385; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14386; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v1614387; CHECK-NEXT: ret14388entry:14389 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, i64 4)14390 ret void14391}14392 14393define void @test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, i64 %vl, <vscale x 4 x i1> %mask) {14394; CHECK-LABEL: test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i32:14395; CHECK: # %bb.0: # %entry14396; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14397; CHECK-NEXT: vsuxseg8ei32.v v8, (a0), v16, v0.t14398; CHECK-NEXT: ret14399entry:14400 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i32.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14401 ret void14402}14403 14404define void @test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl) {14405; CHECK-LABEL: test_vsuxseg8_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i64:14406; CHECK: # %bb.0: # %entry14407; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14408; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v1614409; CHECK-NEXT: ret14410entry:14411 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv8i8_8t.nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, i64 4)14412 ret void14413}14414 14415define void @test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i64(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, i64 %vl, <vscale x 4 x i1> %mask) {14416; CHECK-LABEL: test_vsuxseg8_mask_nxv4bf16_triscv.vector.tuple_nxv8i8_8t_nxv4i64:14417; CHECK: # %bb.0: # %entry14418; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma14419; CHECK-NEXT: vsuxseg8ei64.v v8, (a0), v16, v0.t14420; CHECK-NEXT: ret14421entry:14422 tail call void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv8i8_8t.nxv4i64.nxv4i1(target("riscv.vector.tuple", <vscale x 8 x i8>, 8) %val, ptr %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl, i64 4)14423 ret void14424}14425 14426