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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {6; CHECK-LABEL: vtrunc_nxv2i1_nxv2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma9; CHECK-NEXT: vand.vi v8, v8, 1, v0.t10; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t11; CHECK-NEXT: ret12 %v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)13 ret <vscale x 2 x i1> %v14}15 16define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i16_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {17; CHECK-LABEL: vtrunc_nxv2i1_nxv2i16_unmasked:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma20; CHECK-NEXT: vand.vi v8, v8, 121; CHECK-NEXT: vmsne.vi v0, v8, 022; CHECK-NEXT: ret23 %v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)24 ret <vscale x 2 x i1> %v25}26 27define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {28; CHECK-LABEL: vtrunc_nxv2i1_nxv2i32:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma31; CHECK-NEXT: vand.vi v8, v8, 1, v0.t32; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t33; CHECK-NEXT: ret34 %v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)35 ret <vscale x 2 x i1> %v36}37 38define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {39; CHECK-LABEL: vtrunc_nxv2i1_nxv2i32_unmasked:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma42; CHECK-NEXT: vand.vi v8, v8, 143; CHECK-NEXT: vmsne.vi v0, v8, 044; CHECK-NEXT: ret45 %v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)46 ret <vscale x 2 x i1> %v47}48 49define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {50; CHECK-LABEL: vtrunc_nxv2i1_nxv2i64:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma53; CHECK-NEXT: vand.vi v10, v8, 1, v0.t54; CHECK-NEXT: vmsne.vi v8, v10, 0, v0.t55; CHECK-NEXT: vmv1r.v v0, v856; CHECK-NEXT: ret57 %v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)58 ret <vscale x 2 x i1> %v59}60 61define <vscale x 2 x i1> @vtrunc_nxv2i1_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {62; CHECK-LABEL: vtrunc_nxv2i1_nxv2i64_unmasked:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma65; CHECK-NEXT: vand.vi v8, v8, 166; CHECK-NEXT: vmsne.vi v0, v8, 067; CHECK-NEXT: ret68 %v = call <vscale x 2 x i1> @llvm.vp.trunc.nxv2i1.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)69 ret <vscale x 2 x i1> %v70}71