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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 2 x i7> @vtrunc_nxv2i7_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {6; CHECK-LABEL: vtrunc_nxv2i7_nxv2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma9; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t10; CHECK-NEXT: ret11 %v = call <vscale x 2 x i7> @llvm.vp.trunc.nxv2i7.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)12 ret <vscale x 2 x i7> %v13}14 15define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i15(<vscale x 2 x i15> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {16; CHECK-LABEL: vtrunc_nxv2i8_nxv2i15:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma19; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t20; CHECK-NEXT: ret21 %v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i15(<vscale x 2 x i15> %a, <vscale x 2 x i1> %m, i32 %vl)22 ret <vscale x 2 x i8> %v23}24 25define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {26; CHECK-LABEL: vtrunc_nxv2i8_nxv2i16:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma29; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t30; CHECK-NEXT: ret31 %v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)32 ret <vscale x 2 x i8> %v33}34 35define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {36; CHECK-LABEL: vtrunc_nxv2i8_nxv2i16_unmasked:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma39; CHECK-NEXT: vnsrl.wi v8, v8, 040; CHECK-NEXT: ret41 %v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)42 ret <vscale x 2 x i8> %v43}44 45define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {46; CHECK-LABEL: vtrunc_nxv2i8_nxv2i32:47; CHECK: # %bb.0:48; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma49; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t50; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma51; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t52; CHECK-NEXT: ret53 %v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)54 ret <vscale x 2 x i8> %v55}56 57define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {58; CHECK-LABEL: vtrunc_nxv2i8_nxv2i32_unmasked:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma61; CHECK-NEXT: vnsrl.wi v8, v8, 062; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma63; CHECK-NEXT: vnsrl.wi v8, v8, 064; CHECK-NEXT: ret65 %v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)66 ret <vscale x 2 x i8> %v67}68 69define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {70; CHECK-LABEL: vtrunc_nxv2i8_nxv2i64:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma73; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t74; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma75; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t76; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma77; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t78; CHECK-NEXT: ret79 %v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)80 ret <vscale x 2 x i8> %v81}82 83define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {84; CHECK-LABEL: vtrunc_nxv2i8_nxv2i64_unmasked:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma87; CHECK-NEXT: vnsrl.wi v10, v8, 088; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma89; CHECK-NEXT: vnsrl.wi v8, v10, 090; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma91; CHECK-NEXT: vnsrl.wi v8, v8, 092; CHECK-NEXT: ret93 %v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)94 ret <vscale x 2 x i8> %v95}96 97define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {98; CHECK-LABEL: vtrunc_nxv2i16_nxv2i32:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma101; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t102; CHECK-NEXT: ret103 %v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)104 ret <vscale x 2 x i16> %v105}106 107define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {108; CHECK-LABEL: vtrunc_nxv2i16_nxv2i32_unmasked:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma111; CHECK-NEXT: vnsrl.wi v8, v8, 0112; CHECK-NEXT: ret113 %v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)114 ret <vscale x 2 x i16> %v115}116 117define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {118; CHECK-LABEL: vtrunc_nxv2i16_nxv2i64:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma121; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t122; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma123; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t124; CHECK-NEXT: ret125 %v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)126 ret <vscale x 2 x i16> %v127}128 129define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {130; CHECK-LABEL: vtrunc_nxv2i16_nxv2i64_unmasked:131; CHECK: # %bb.0:132; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma133; CHECK-NEXT: vnsrl.wi v10, v8, 0134; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma135; CHECK-NEXT: vnsrl.wi v8, v10, 0136; CHECK-NEXT: ret137 %v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)138 ret <vscale x 2 x i16> %v139}140 141define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vscale x 15 x i1> %m, i32 zeroext %vl) {142; CHECK-LABEL: vtrunc_nxv15i16_nxv15i64:143; CHECK: # %bb.0:144; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma145; CHECK-NEXT: vmv1r.v v24, v0146; CHECK-NEXT: csrr a1, vlenb147; CHECK-NEXT: srli a2, a1, 3148; CHECK-NEXT: sub a3, a0, a1149; CHECK-NEXT: vslidedown.vx v0, v0, a2150; CHECK-NEXT: sltu a2, a0, a3151; CHECK-NEXT: addi a2, a2, -1152; CHECK-NEXT: and a2, a2, a3153; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma154; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t155; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma156; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t157; CHECK-NEXT: bltu a0, a1, .LBB12_2158; CHECK-NEXT: # %bb.1:159; CHECK-NEXT: mv a0, a1160; CHECK-NEXT: .LBB12_2:161; CHECK-NEXT: vmv1r.v v0, v24162; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma163; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t164; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma165; CHECK-NEXT: vnsrl.wi v16, v20, 0, v0.t166; CHECK-NEXT: vmv4r.v v8, v16167; CHECK-NEXT: ret168 %v = call <vscale x 15 x i16> @llvm.vp.trunc.nxv15i16.nxv15i64(<vscale x 15 x i64> %a, <vscale x 15 x i1> %m, i32 %vl)169 ret <vscale x 15 x i16> %v170}171 172define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {173; CHECK-LABEL: vtrunc_nxv2i32_nxv2i64:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma176; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t177; CHECK-NEXT: vmv.v.v v8, v10178; CHECK-NEXT: ret179 %v = call <vscale x 2 x i32> @llvm.vp.trunc.nxv2i32.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)180 ret <vscale x 2 x i32> %v181}182 183define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {184; CHECK-LABEL: vtrunc_nxv2i32_nxv2i64_unmasked:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma187; CHECK-NEXT: vnsrl.wi v10, v8, 0188; CHECK-NEXT: vmv.v.v v8, v10189; CHECK-NEXT: ret190 %v = call <vscale x 2 x i32> @llvm.vp.trunc.nxv2i32.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)191 ret <vscale x 2 x i32> %v192}193 194define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {195; CHECK-LABEL: vtrunc_nxv32i7_nxv32i32:196; CHECK: # %bb.0:197; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma198; CHECK-NEXT: vmv1r.v v24, v0199; CHECK-NEXT: csrr a1, vlenb200; CHECK-NEXT: srli a2, a1, 2201; CHECK-NEXT: slli a1, a1, 1202; CHECK-NEXT: vslidedown.vx v0, v0, a2203; CHECK-NEXT: sub a2, a0, a1204; CHECK-NEXT: sltu a3, a0, a2205; CHECK-NEXT: addi a3, a3, -1206; CHECK-NEXT: and a2, a3, a2207; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma208; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t209; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma210; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t211; CHECK-NEXT: bltu a0, a1, .LBB15_2212; CHECK-NEXT: # %bb.1:213; CHECK-NEXT: mv a0, a1214; CHECK-NEXT: .LBB15_2:215; CHECK-NEXT: vmv1r.v v0, v24216; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma217; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t218; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma219; CHECK-NEXT: vnsrl.wi v16, v20, 0, v0.t220; CHECK-NEXT: vmv4r.v v8, v16221; CHECK-NEXT: ret222 %v = call <vscale x 32 x i7> @llvm.vp.trunc.nxv32i7.nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 %vl)223 ret <vscale x 32 x i7> %v224}225 226define <vscale x 32 x i8> @vtrunc_nxv32i8_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {227; CHECK-LABEL: vtrunc_nxv32i8_nxv32i32:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma230; CHECK-NEXT: vmv1r.v v24, v0231; CHECK-NEXT: csrr a1, vlenb232; CHECK-NEXT: srli a2, a1, 2233; CHECK-NEXT: slli a1, a1, 1234; CHECK-NEXT: vslidedown.vx v0, v0, a2235; CHECK-NEXT: sub a2, a0, a1236; CHECK-NEXT: sltu a3, a0, a2237; CHECK-NEXT: addi a3, a3, -1238; CHECK-NEXT: and a2, a3, a2239; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma240; CHECK-NEXT: vnsrl.wi v28, v16, 0, v0.t241; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma242; CHECK-NEXT: vnsrl.wi v18, v28, 0, v0.t243; CHECK-NEXT: bltu a0, a1, .LBB16_2244; CHECK-NEXT: # %bb.1:245; CHECK-NEXT: mv a0, a1246; CHECK-NEXT: .LBB16_2:247; CHECK-NEXT: vmv1r.v v0, v24248; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma249; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t250; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma251; CHECK-NEXT: vnsrl.wi v16, v20, 0, v0.t252; CHECK-NEXT: vmv4r.v v8, v16253; CHECK-NEXT: ret254 %v = call <vscale x 32 x i8> @llvm.vp.trunc.nxv32i8.nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 %vl)255 ret <vscale x 32 x i8> %v256}257 258define <vscale x 32 x i32> @vtrunc_nxv32i64_nxv32i32(<vscale x 32 x i64> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {259; CHECK-LABEL: vtrunc_nxv32i64_nxv32i32:260; CHECK: # %bb.0:261; CHECK-NEXT: addi sp, sp, -16262; CHECK-NEXT: .cfi_def_cfa_offset 16263; CHECK-NEXT: csrr a1, vlenb264; CHECK-NEXT: slli a1, a1, 4265; CHECK-NEXT: sub sp, sp, a1266; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb267; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma268; CHECK-NEXT: vmv1r.v v7, v0269; CHECK-NEXT: addi a1, sp, 16270; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill271; CHECK-NEXT: csrr a1, vlenb272; CHECK-NEXT: slli a1, a1, 3273; CHECK-NEXT: add a1, sp, a1274; CHECK-NEXT: addi a1, a1, 16275; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill276; CHECK-NEXT: csrr a1, vlenb277; CHECK-NEXT: vl8re64.v v16, (a0)278; CHECK-NEXT: srli a5, a1, 3279; CHECK-NEXT: slli a4, a1, 3280; CHECK-NEXT: slli a3, a1, 1281; CHECK-NEXT: add a6, a0, a4282; CHECK-NEXT: sub a0, a2, a3283; CHECK-NEXT: sltu a4, a2, a0284; CHECK-NEXT: addi a4, a4, -1285; CHECK-NEXT: and a0, a4, a0286; CHECK-NEXT: sub a4, a0, a1287; CHECK-NEXT: sltu a7, a0, a4288; CHECK-NEXT: addi a7, a7, -1289; CHECK-NEXT: and a4, a7, a4290; CHECK-NEXT: srli a7, a1, 2291; CHECK-NEXT: vl8re64.v v8, (a6)292; CHECK-NEXT: vslidedown.vx v24, v0, a7293; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma294; CHECK-NEXT: vslidedown.vx v6, v0, a5295; CHECK-NEXT: vslidedown.vx v0, v24, a5296; CHECK-NEXT: bltu a0, a1, .LBB17_2297; CHECK-NEXT: # %bb.1:298; CHECK-NEXT: mv a0, a1299; CHECK-NEXT: .LBB17_2:300; CHECK-NEXT: vsetvli zero, a4, e32, m4, ta, ma301; CHECK-NEXT: vnsrl.wi v28, v8, 0, v0.t302; CHECK-NEXT: vmv1r.v v0, v24303; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma304; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t305; CHECK-NEXT: bltu a2, a3, .LBB17_4306; CHECK-NEXT: # %bb.3:307; CHECK-NEXT: mv a2, a3308; CHECK-NEXT: .LBB17_4:309; CHECK-NEXT: sub a0, a2, a1310; CHECK-NEXT: sltu a3, a2, a0311; CHECK-NEXT: addi a3, a3, -1312; CHECK-NEXT: and a0, a3, a0313; CHECK-NEXT: vmv1r.v v0, v6314; CHECK-NEXT: addi a3, sp, 16315; CHECK-NEXT: vl8r.v v16, (a3) # vscale x 64-byte Folded Reload316; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma317; CHECK-NEXT: vnsrl.wi v12, v16, 0, v0.t318; CHECK-NEXT: bltu a2, a1, .LBB17_6319; CHECK-NEXT: # %bb.5:320; CHECK-NEXT: mv a2, a1321; CHECK-NEXT: .LBB17_6:322; CHECK-NEXT: vmv1r.v v0, v7323; CHECK-NEXT: csrr a0, vlenb324; CHECK-NEXT: slli a0, a0, 3325; CHECK-NEXT: add a0, sp, a0326; CHECK-NEXT: addi a0, a0, 16327; CHECK-NEXT: vl8r.v v16, (a0) # vscale x 64-byte Folded Reload328; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma329; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t330; CHECK-NEXT: vmv8r.v v16, v24331; CHECK-NEXT: csrr a0, vlenb332; CHECK-NEXT: slli a0, a0, 4333; CHECK-NEXT: add sp, sp, a0334; CHECK-NEXT: .cfi_def_cfa sp, 16335; CHECK-NEXT: addi sp, sp, 16336; CHECK-NEXT: .cfi_def_cfa_offset 0337; CHECK-NEXT: ret338 %v = call <vscale x 32 x i32> @llvm.vp.trunc.nxv32i32.nxv32i64(<vscale x 32 x i64> %a, <vscale x 32 x i1> %m, i32 %vl)339 ret <vscale x 32 x i32> %v340}341