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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i8> @vtrunc_nxv1i16_nxv1i8(<vscale x 1 x i16> %va) {6; CHECK-LABEL: vtrunc_nxv1i16_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vnsrl.wi v8, v8, 010; CHECK-NEXT: ret11 %tvec = trunc <vscale x 1 x i16> %va to <vscale x 1 x i8>12 ret <vscale x 1 x i8> %tvec13}14 15define <vscale x 2 x i8> @vtrunc_nxv2i16_nxv2i8(<vscale x 2 x i16> %va) {16; CHECK-LABEL: vtrunc_nxv2i16_nxv2i8:17; CHECK: # %bb.0:18; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma19; CHECK-NEXT: vnsrl.wi v8, v8, 020; CHECK-NEXT: ret21 %tvec = trunc <vscale x 2 x i16> %va to <vscale x 2 x i8>22 ret <vscale x 2 x i8> %tvec23}24 25define <vscale x 4 x i8> @vtrunc_nxv4i16_nxv4i8(<vscale x 4 x i16> %va) {26; CHECK-LABEL: vtrunc_nxv4i16_nxv4i8:27; CHECK: # %bb.0:28; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma29; CHECK-NEXT: vnsrl.wi v8, v8, 030; CHECK-NEXT: ret31 %tvec = trunc <vscale x 4 x i16> %va to <vscale x 4 x i8>32 ret <vscale x 4 x i8> %tvec33}34 35define <vscale x 8 x i8> @vtrunc_nxv8i16_nxv8i8(<vscale x 8 x i16> %va) {36; CHECK-LABEL: vtrunc_nxv8i16_nxv8i8:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma39; CHECK-NEXT: vnsrl.wi v10, v8, 040; CHECK-NEXT: vmv.v.v v8, v1041; CHECK-NEXT: ret42 %tvec = trunc <vscale x 8 x i16> %va to <vscale x 8 x i8>43 ret <vscale x 8 x i8> %tvec44}45 46define <vscale x 16 x i8> @vtrunc_nxv16i16_nxv16i8(<vscale x 16 x i16> %va) {47; CHECK-LABEL: vtrunc_nxv16i16_nxv16i8:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma50; CHECK-NEXT: vnsrl.wi v12, v8, 051; CHECK-NEXT: vmv.v.v v8, v1252; CHECK-NEXT: ret53 %tvec = trunc <vscale x 16 x i16> %va to <vscale x 16 x i8>54 ret <vscale x 16 x i8> %tvec55}56 57define <vscale x 1 x i8> @vtrunc_nxv1i32_nxv1i8(<vscale x 1 x i32> %va) {58; CHECK-LABEL: vtrunc_nxv1i32_nxv1i8:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma61; CHECK-NEXT: vnsrl.wi v8, v8, 062; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma63; CHECK-NEXT: vnsrl.wi v8, v8, 064; CHECK-NEXT: ret65 %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i8>66 ret <vscale x 1 x i8> %tvec67}68 69define <vscale x 1 x i16> @vtrunc_nxv1i32_nxv1i16(<vscale x 1 x i32> %va) {70; CHECK-LABEL: vtrunc_nxv1i32_nxv1i16:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma73; CHECK-NEXT: vnsrl.wi v8, v8, 074; CHECK-NEXT: ret75 %tvec = trunc <vscale x 1 x i32> %va to <vscale x 1 x i16>76 ret <vscale x 1 x i16> %tvec77}78 79define <vscale x 2 x i8> @vtrunc_nxv2i32_nxv2i8(<vscale x 2 x i32> %va) {80; CHECK-LABEL: vtrunc_nxv2i32_nxv2i8:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma83; CHECK-NEXT: vnsrl.wi v8, v8, 084; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma85; CHECK-NEXT: vnsrl.wi v8, v8, 086; CHECK-NEXT: ret87 %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i8>88 ret <vscale x 2 x i8> %tvec89}90 91define <vscale x 2 x i16> @vtrunc_nxv2i32_nxv2i16(<vscale x 2 x i32> %va) {92; CHECK-LABEL: vtrunc_nxv2i32_nxv2i16:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma95; CHECK-NEXT: vnsrl.wi v8, v8, 096; CHECK-NEXT: ret97 %tvec = trunc <vscale x 2 x i32> %va to <vscale x 2 x i16>98 ret <vscale x 2 x i16> %tvec99}100 101define <vscale x 4 x i8> @vtrunc_nxv4i32_nxv4i8(<vscale x 4 x i32> %va) {102; CHECK-LABEL: vtrunc_nxv4i32_nxv4i8:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma105; CHECK-NEXT: vnsrl.wi v10, v8, 0106; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma107; CHECK-NEXT: vnsrl.wi v8, v10, 0108; CHECK-NEXT: ret109 %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i8>110 ret <vscale x 4 x i8> %tvec111}112 113define <vscale x 4 x i16> @vtrunc_nxv4i32_nxv4i16(<vscale x 4 x i32> %va) {114; CHECK-LABEL: vtrunc_nxv4i32_nxv4i16:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma117; CHECK-NEXT: vnsrl.wi v10, v8, 0118; CHECK-NEXT: vmv.v.v v8, v10119; CHECK-NEXT: ret120 %tvec = trunc <vscale x 4 x i32> %va to <vscale x 4 x i16>121 ret <vscale x 4 x i16> %tvec122}123 124define <vscale x 8 x i8> @vtrunc_nxv8i32_nxv8i8(<vscale x 8 x i32> %va) {125; CHECK-LABEL: vtrunc_nxv8i32_nxv8i8:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma128; CHECK-NEXT: vnsrl.wi v12, v8, 0129; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma130; CHECK-NEXT: vnsrl.wi v8, v12, 0131; CHECK-NEXT: ret132 %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i8>133 ret <vscale x 8 x i8> %tvec134}135 136define <vscale x 8 x i16> @vtrunc_nxv8i32_nxv8i16(<vscale x 8 x i32> %va) {137; CHECK-LABEL: vtrunc_nxv8i32_nxv8i16:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma140; CHECK-NEXT: vnsrl.wi v12, v8, 0141; CHECK-NEXT: vmv.v.v v8, v12142; CHECK-NEXT: ret143 %tvec = trunc <vscale x 8 x i32> %va to <vscale x 8 x i16>144 ret <vscale x 8 x i16> %tvec145}146 147define <vscale x 16 x i8> @vtrunc_nxv16i32_nxv16i8(<vscale x 16 x i32> %va) {148; CHECK-LABEL: vtrunc_nxv16i32_nxv16i8:149; CHECK: # %bb.0:150; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma151; CHECK-NEXT: vnsrl.wi v16, v8, 0152; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma153; CHECK-NEXT: vnsrl.wi v8, v16, 0154; CHECK-NEXT: ret155 %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i8>156 ret <vscale x 16 x i8> %tvec157}158 159define <vscale x 16 x i16> @vtrunc_nxv16i32_nxv16i16(<vscale x 16 x i32> %va) {160; CHECK-LABEL: vtrunc_nxv16i32_nxv16i16:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma163; CHECK-NEXT: vnsrl.wi v16, v8, 0164; CHECK-NEXT: vmv.v.v v8, v16165; CHECK-NEXT: ret166 %tvec = trunc <vscale x 16 x i32> %va to <vscale x 16 x i16>167 ret <vscale x 16 x i16> %tvec168}169 170define <vscale x 1 x i8> @vtrunc_nxv1i64_nxv1i8(<vscale x 1 x i64> %va) {171; CHECK-LABEL: vtrunc_nxv1i64_nxv1i8:172; CHECK: # %bb.0:173; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma174; CHECK-NEXT: vnsrl.wi v8, v8, 0175; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma176; CHECK-NEXT: vnsrl.wi v8, v8, 0177; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma178; CHECK-NEXT: vnsrl.wi v8, v8, 0179; CHECK-NEXT: ret180 %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i8>181 ret <vscale x 1 x i8> %tvec182}183 184define <vscale x 1 x i16> @vtrunc_nxv1i64_nxv1i16(<vscale x 1 x i64> %va) {185; CHECK-LABEL: vtrunc_nxv1i64_nxv1i16:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma188; CHECK-NEXT: vnsrl.wi v8, v8, 0189; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma190; CHECK-NEXT: vnsrl.wi v8, v8, 0191; CHECK-NEXT: ret192 %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i16>193 ret <vscale x 1 x i16> %tvec194}195 196define <vscale x 1 x i32> @vtrunc_nxv1i64_nxv1i32(<vscale x 1 x i64> %va) {197; CHECK-LABEL: vtrunc_nxv1i64_nxv1i32:198; CHECK: # %bb.0:199; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma200; CHECK-NEXT: vnsrl.wi v8, v8, 0201; CHECK-NEXT: ret202 %tvec = trunc <vscale x 1 x i64> %va to <vscale x 1 x i32>203 ret <vscale x 1 x i32> %tvec204}205 206define <vscale x 2 x i8> @vtrunc_nxv2i64_nxv2i8(<vscale x 2 x i64> %va) {207; CHECK-LABEL: vtrunc_nxv2i64_nxv2i8:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma210; CHECK-NEXT: vnsrl.wi v10, v8, 0211; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma212; CHECK-NEXT: vnsrl.wi v8, v10, 0213; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma214; CHECK-NEXT: vnsrl.wi v8, v8, 0215; CHECK-NEXT: ret216 %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i8>217 ret <vscale x 2 x i8> %tvec218}219 220define <vscale x 2 x i16> @vtrunc_nxv2i64_nxv2i16(<vscale x 2 x i64> %va) {221; CHECK-LABEL: vtrunc_nxv2i64_nxv2i16:222; CHECK: # %bb.0:223; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma224; CHECK-NEXT: vnsrl.wi v10, v8, 0225; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma226; CHECK-NEXT: vnsrl.wi v8, v10, 0227; CHECK-NEXT: ret228 %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i16>229 ret <vscale x 2 x i16> %tvec230}231 232define <vscale x 2 x i32> @vtrunc_nxv2i64_nxv2i32(<vscale x 2 x i64> %va) {233; CHECK-LABEL: vtrunc_nxv2i64_nxv2i32:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma236; CHECK-NEXT: vnsrl.wi v10, v8, 0237; CHECK-NEXT: vmv.v.v v8, v10238; CHECK-NEXT: ret239 %tvec = trunc <vscale x 2 x i64> %va to <vscale x 2 x i32>240 ret <vscale x 2 x i32> %tvec241}242 243define <vscale x 4 x i8> @vtrunc_nxv4i64_nxv4i8(<vscale x 4 x i64> %va) {244; CHECK-LABEL: vtrunc_nxv4i64_nxv4i8:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma247; CHECK-NEXT: vnsrl.wi v12, v8, 0248; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma249; CHECK-NEXT: vnsrl.wi v8, v12, 0250; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma251; CHECK-NEXT: vnsrl.wi v8, v8, 0252; CHECK-NEXT: ret253 %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i8>254 ret <vscale x 4 x i8> %tvec255}256 257define <vscale x 4 x i16> @vtrunc_nxv4i64_nxv4i16(<vscale x 4 x i64> %va) {258; CHECK-LABEL: vtrunc_nxv4i64_nxv4i16:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma261; CHECK-NEXT: vnsrl.wi v12, v8, 0262; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma263; CHECK-NEXT: vnsrl.wi v8, v12, 0264; CHECK-NEXT: ret265 %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i16>266 ret <vscale x 4 x i16> %tvec267}268 269define <vscale x 4 x i32> @vtrunc_nxv4i64_nxv4i32(<vscale x 4 x i64> %va) {270; CHECK-LABEL: vtrunc_nxv4i64_nxv4i32:271; CHECK: # %bb.0:272; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma273; CHECK-NEXT: vnsrl.wi v12, v8, 0274; CHECK-NEXT: vmv.v.v v8, v12275; CHECK-NEXT: ret276 %tvec = trunc <vscale x 4 x i64> %va to <vscale x 4 x i32>277 ret <vscale x 4 x i32> %tvec278}279 280define <vscale x 8 x i8> @vtrunc_nxv8i64_nxv8i8(<vscale x 8 x i64> %va) {281; CHECK-LABEL: vtrunc_nxv8i64_nxv8i8:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma284; CHECK-NEXT: vnsrl.wi v16, v8, 0285; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma286; CHECK-NEXT: vnsrl.wi v10, v16, 0287; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma288; CHECK-NEXT: vnsrl.wi v8, v10, 0289; CHECK-NEXT: ret290 %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i8>291 ret <vscale x 8 x i8> %tvec292}293 294define <vscale x 8 x i16> @vtrunc_nxv8i64_nxv8i16(<vscale x 8 x i64> %va) {295; CHECK-LABEL: vtrunc_nxv8i64_nxv8i16:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma298; CHECK-NEXT: vnsrl.wi v16, v8, 0299; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma300; CHECK-NEXT: vnsrl.wi v8, v16, 0301; CHECK-NEXT: ret302 %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i16>303 ret <vscale x 8 x i16> %tvec304}305 306define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) {307; CHECK-LABEL: vtrunc_nxv8i64_nxv8i32:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma310; CHECK-NEXT: vnsrl.wi v16, v8, 0311; CHECK-NEXT: vmv.v.v v8, v16312; CHECK-NEXT: ret313 %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32>314 ret <vscale x 8 x i32> %tvec315}316