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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK4 5define <vscale x 8 x i64> @vwadd_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {6; CHECK-LABEL: vwadd_wv_mask_v8i32:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma9; CHECK-NEXT: vmv4r.v v24, v810; CHECK-NEXT: li a0, 4211; CHECK-NEXT: vmslt.vx v0, v8, a012; CHECK-NEXT: vmv8r.v v8, v1613; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu14; CHECK-NEXT: vwadd.wv v8, v8, v24, v0.t15; CHECK-NEXT: ret16 %mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)17 %a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer18 %sa = sext <vscale x 8 x i32> %a to <vscale x 8 x i64>19 %ret = add <vscale x 8 x i64> %sa, %y20 ret <vscale x 8 x i64> %ret21}22 23define <vscale x 8 x i64> @vwaddu_wv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {24; CHECK-LABEL: vwaddu_wv_mask_v8i32:25; CHECK: # %bb.0:26; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma27; CHECK-NEXT: vmv4r.v v24, v828; CHECK-NEXT: li a0, 4229; CHECK-NEXT: vmslt.vx v0, v8, a030; CHECK-NEXT: vmv8r.v v8, v1631; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu32; CHECK-NEXT: vwaddu.wv v8, v8, v24, v0.t33; CHECK-NEXT: ret34 %mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)35 %a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer36 %sa = zext <vscale x 8 x i32> %a to <vscale x 8 x i64>37 %ret = add <vscale x 8 x i64> %sa, %y38 ret <vscale x 8 x i64> %ret39}40 41define <vscale x 8 x i64> @vwaddu_vv_mask_v8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {42; CHECK-LABEL: vwaddu_vv_mask_v8i32:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma45; CHECK-NEXT: vmv4r.v v16, v1246; CHECK-NEXT: li a0, 4247; CHECK-NEXT: vmslt.vx v0, v8, a048; CHECK-NEXT: vmv.v.i v12, 049; CHECK-NEXT: vmerge.vvm v20, v12, v8, v050; CHECK-NEXT: vwaddu.vv v8, v20, v1651; CHECK-NEXT: ret52 %mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)53 %a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer54 %sa = zext <vscale x 8 x i32> %a to <vscale x 8 x i64>55 %sy = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>56 %ret = add <vscale x 8 x i64> %sa, %sy57 ret <vscale x 8 x i64> %ret58}59 60define <vscale x 8 x i64> @vwadd_wv_mask_v8i32_commutative(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {61; CHECK-LABEL: vwadd_wv_mask_v8i32_commutative:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma64; CHECK-NEXT: vmv4r.v v24, v865; CHECK-NEXT: li a0, 4266; CHECK-NEXT: vmslt.vx v0, v8, a067; CHECK-NEXT: vmv8r.v v8, v1668; CHECK-NEXT: vsetvli zero, zero, e32, m4, tu, mu69; CHECK-NEXT: vwadd.wv v8, v8, v24, v0.t70; CHECK-NEXT: ret71 %mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)72 %a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> zeroinitializer73 %sa = sext <vscale x 8 x i32> %a to <vscale x 8 x i64>74 %ret = add <vscale x 8 x i64> %y, %sa75 ret <vscale x 8 x i64> %ret76}77 78define <vscale x 8 x i64> @vwadd_wv_mask_v8i32_nonzero(<vscale x 8 x i32> %x, <vscale x 8 x i64> %y) {79; CHECK-LABEL: vwadd_wv_mask_v8i32_nonzero:80; CHECK: # %bb.0:81; CHECK-NEXT: li a0, 4282; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma83; CHECK-NEXT: vmslt.vx v0, v8, a084; CHECK-NEXT: vmv.v.i v12, 185; CHECK-NEXT: vmerge.vvm v24, v12, v8, v086; CHECK-NEXT: vwadd.wv v8, v16, v2487; CHECK-NEXT: ret88 %mask = icmp slt <vscale x 8 x i32> %x, splat (i32 42)89 %a = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %x, <vscale x 8 x i32> splat (i32 1)90 %sa = sext <vscale x 8 x i32> %a to <vscale x 8 x i64>91 %ret = add <vscale x 8 x i64> %sa, %y92 ret <vscale x 8 x i64> %ret93}94