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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4define <vscale x 2 x i32> @vwadd_tu(<vscale x 2 x i8> %arg, <vscale x 2 x i32> %arg1, i32 signext %arg2) {5; CHECK-LABEL: vwadd_tu:6; CHECK: # %bb.0: # %bb7; CHECK-NEXT: slli a0, a0, 328; CHECK-NEXT: srli a0, a0, 329; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma10; CHECK-NEXT: vsext.vf2 v10, v811; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, ma12; CHECK-NEXT: vwadd.wv v9, v9, v1013; CHECK-NEXT: vmv1r.v v8, v914; CHECK-NEXT: ret15bb:16 %tmp = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i8(<vscale x 2 x i8> %arg, <vscale x 2 x i1> splat (i1 true), i32 %arg2)17 %tmp3 = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %arg1, <vscale x 2 x i32> %tmp, <vscale x 2 x i1> splat (i1 true), i32 %arg2)18 %tmp4 = call <vscale x 2 x i32> @llvm.vp.merge.nxv2i32(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i32> %tmp3, <vscale x 2 x i32> %arg1, i32 %arg2)19 ret <vscale x 2 x i32> %tmp420}21 22define <vscale x 2 x i32> @vwaddu_tu(<vscale x 2 x i8> %arg, <vscale x 2 x i32> %arg1, i32 signext %arg2) {23; CHECK-LABEL: vwaddu_tu:24; CHECK: # %bb.0: # %bb25; CHECK-NEXT: slli a0, a0, 3226; CHECK-NEXT: srli a0, a0, 3227; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma28; CHECK-NEXT: vzext.vf2 v10, v829; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, ma30; CHECK-NEXT: vwaddu.wv v9, v9, v1031; CHECK-NEXT: vmv1r.v v8, v932; CHECK-NEXT: ret33bb:34 %tmp = call <vscale x 2 x i32> @llvm.vp.zext.nxv2i32.nxv2i8(<vscale x 2 x i8> %arg, <vscale x 2 x i1> splat (i1 true), i32 %arg2)35 %tmp3 = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %arg1, <vscale x 2 x i32> %tmp, <vscale x 2 x i1> splat (i1 true), i32 %arg2)36 %tmp4 = call <vscale x 2 x i32> @llvm.vp.merge.nxv2i32(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i32> %tmp3, <vscale x 2 x i32> %arg1, i32 %arg2)37 ret <vscale x 2 x i32> %tmp438}39 40define <vscale x 2 x i32> @vwadd_vv_vpnxv2i32_vpnxv2i16_vpnxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 signext %evl) {41; CHECK-LABEL: vwadd_vv_vpnxv2i32_vpnxv2i16_vpnxv2i16:42; CHECK: # %bb.0:43; CHECK-NEXT: slli a0, a0, 3244; CHECK-NEXT: srli a0, a0, 3245; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma46; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t47; CHECK-NEXT: vmv1r.v v8, v1048; CHECK-NEXT: ret49 %x.sext = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i1> %m, i32 %evl)50 %y.sext = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i16(<vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 %evl)51 %add = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %x.sext, <vscale x 2 x i32> %y.sext, <vscale x 2 x i1> %m, i32 %evl)52 ret <vscale x 2 x i32> %add53}54 55define <vscale x 2 x i32> @vwadd_vv_vpnxv2i32_vpnxv2i16_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 signext %evl) {56; CHECK-LABEL: vwadd_vv_vpnxv2i32_vpnxv2i16_nxv2i16:57; CHECK: # %bb.0:58; CHECK-NEXT: slli a0, a0, 3259; CHECK-NEXT: srli a0, a0, 3260; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma61; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t62; CHECK-NEXT: vmv1r.v v8, v1063; CHECK-NEXT: ret64 %x.sext = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i1> %m, i32 %evl)65 %y.sext = sext <vscale x 2 x i16> %y to <vscale x 2 x i32>66 %add = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %x.sext, <vscale x 2 x i32> %y.sext, <vscale x 2 x i1> %m, i32 %evl)67 ret <vscale x 2 x i32> %add68}69 70define <vscale x 2 x i32> @vwadd_vv_vpnxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 signext %evl) {71; CHECK-LABEL: vwadd_vv_vpnxv2i32_nxv2i16_nxv2i16:72; CHECK: # %bb.0:73; CHECK-NEXT: slli a0, a0, 3274; CHECK-NEXT: srli a0, a0, 3275; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma76; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t77; CHECK-NEXT: vmv1r.v v8, v1078; CHECK-NEXT: ret79 %x.sext = sext <vscale x 2 x i16> %x to <vscale x 2 x i32>80 %y.sext = sext <vscale x 2 x i16> %y to <vscale x 2 x i32>81 %add = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %x.sext, <vscale x 2 x i32> %y.sext, <vscale x 2 x i1> %m, i32 %evl)82 ret <vscale x 2 x i32> %add83}84 85define <vscale x 2 x i32> @vwadd_vv_nxv2i32_vpnxv2i16_vpnxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 signext %evl) {86; CHECK-LABEL: vwadd_vv_nxv2i32_vpnxv2i16_vpnxv2i16:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma89; CHECK-NEXT: vwadd.vv v10, v8, v990; CHECK-NEXT: vmv1r.v v8, v1091; CHECK-NEXT: ret92 %x.sext = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i16(<vscale x 2 x i16> %x, <vscale x 2 x i1> %m, i32 %evl)93 %y.sext = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i16(<vscale x 2 x i16> %y, <vscale x 2 x i1> %m, i32 %evl)94 %add = add <vscale x 2 x i32> %x.sext, %y.sext95 ret <vscale x 2 x i32> %add96}97