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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \5; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s6; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \7; RUN: -verify-machineinstrs | FileCheck %s8; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \9; RUN: -verify-machineinstrs -early-live-intervals | FileCheck %s10 11define <vscale x 1 x i16> @intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {12; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i16_nxv1i16_nxv1i8:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; CHECK-NEXT: vwadd.wv v8, v8, v916; CHECK-NEXT: ret17entry:18 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8(19 <vscale x 1 x i16> poison,20 <vscale x 1 x i16> %0,21 <vscale x 1 x i8> %1,22 iXLen %2)23 24 ret <vscale x 1 x i16> %a25}26 27define <vscale x 1 x i16> @intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {28; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i16_nxv1i16_nxv1i8:29; CHECK: # %bb.0: # %entry30; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu31; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t32; CHECK-NEXT: ret33entry:34 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.mask.nxv1i16.nxv1i8(35 <vscale x 1 x i16> %0,36 <vscale x 1 x i16> %1,37 <vscale x 1 x i8> %2,38 <vscale x 1 x i1> %3,39 iXLen %4, iXLen 1)40 41 ret <vscale x 1 x i16> %a42}43 44define <vscale x 2 x i16> @intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {45; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i16_nxv2i16_nxv2i8:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma48; CHECK-NEXT: vwadd.wv v8, v8, v949; CHECK-NEXT: ret50entry:51 %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8(52 <vscale x 2 x i16> poison,53 <vscale x 2 x i16> %0,54 <vscale x 2 x i8> %1,55 iXLen %2)56 57 ret <vscale x 2 x i16> %a58}59 60define <vscale x 2 x i16> @intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {61; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i16_nxv2i16_nxv2i8:62; CHECK: # %bb.0: # %entry63; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu64; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t65; CHECK-NEXT: ret66entry:67 %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.mask.nxv2i16.nxv2i8(68 <vscale x 2 x i16> %0,69 <vscale x 2 x i16> %1,70 <vscale x 2 x i8> %2,71 <vscale x 2 x i1> %3,72 iXLen %4, iXLen 1)73 74 ret <vscale x 2 x i16> %a75}76 77define <vscale x 4 x i16> @intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {78; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i16_nxv4i16_nxv4i8:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma81; CHECK-NEXT: vwadd.wv v8, v8, v982; CHECK-NEXT: ret83entry:84 %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.nxv4i8(85 <vscale x 4 x i16> poison,86 <vscale x 4 x i16> %0,87 <vscale x 4 x i8> %1,88 iXLen %2)89 90 ret <vscale x 4 x i16> %a91}92 93define <vscale x 4 x i16> @intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {94; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i16_nxv4i16_nxv4i8:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu97; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t98; CHECK-NEXT: ret99entry:100 %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.mask.nxv4i16.nxv4i8(101 <vscale x 4 x i16> %0,102 <vscale x 4 x i16> %1,103 <vscale x 4 x i8> %2,104 <vscale x 4 x i1> %3,105 iXLen %4, iXLen 1)106 107 ret <vscale x 4 x i16> %a108}109 110define <vscale x 8 x i16> @intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {111; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i16_nxv8i16_nxv8i8:112; CHECK: # %bb.0: # %entry113; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma114; CHECK-NEXT: vwadd.wv v8, v8, v10115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.nxv8i8(118 <vscale x 8 x i16> poison,119 <vscale x 8 x i16> %0,120 <vscale x 8 x i8> %1,121 iXLen %2)122 123 ret <vscale x 8 x i16> %a124}125 126define <vscale x 8 x i16> @intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i16_nxv8i16_nxv8i8:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu130; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.mask.nxv8i16.nxv8i8(134 <vscale x 8 x i16> %0,135 <vscale x 8 x i16> %1,136 <vscale x 8 x i8> %2,137 <vscale x 8 x i1> %3,138 iXLen %4, iXLen 1)139 140 ret <vscale x 8 x i16> %a141}142 143define <vscale x 16 x i16> @intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i16_nxv16i16_nxv16i8:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma147; CHECK-NEXT: vwadd.wv v8, v8, v12148; CHECK-NEXT: ret149entry:150 %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.nxv16i8(151 <vscale x 16 x i16> poison,152 <vscale x 16 x i16> %0,153 <vscale x 16 x i8> %1,154 iXLen %2)155 156 ret <vscale x 16 x i16> %a157}158 159define <vscale x 16 x i16> @intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {160; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i16_nxv16i16_nxv16i8:161; CHECK: # %bb.0: # %entry162; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu163; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t164; CHECK-NEXT: ret165entry:166 %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.mask.nxv16i16.nxv16i8(167 <vscale x 16 x i16> %0,168 <vscale x 16 x i16> %1,169 <vscale x 16 x i8> %2,170 <vscale x 16 x i1> %3,171 iXLen %4, iXLen 1)172 173 ret <vscale x 16 x i16> %a174}175 176define <vscale x 32 x i16> @intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {177; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv32i16_nxv32i16_nxv32i8:178; CHECK: # %bb.0: # %entry179; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma180; CHECK-NEXT: vwadd.wv v8, v8, v16181; CHECK-NEXT: ret182entry:183 %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.nxv32i8(184 <vscale x 32 x i16> poison,185 <vscale x 32 x i16> %0,186 <vscale x 32 x i8> %1,187 iXLen %2)188 189 ret <vscale x 32 x i16> %a190}191 192define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {193; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:194; CHECK: # %bb.0: # %entry195; CHECK-NEXT: vl4r.v v24, (a0)196; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu197; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t198; CHECK-NEXT: ret199entry:200 %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(201 <vscale x 32 x i16> %0,202 <vscale x 32 x i16> %1,203 <vscale x 32 x i8> %2,204 <vscale x 32 x i1> %3,205 iXLen %4, iXLen 1)206 207 ret <vscale x 32 x i16> %a208}209 210define <vscale x 1 x i32> @intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {211; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i32_nxv1i32_nxv1i16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma214; CHECK-NEXT: vwadd.wv v8, v8, v9215; CHECK-NEXT: ret216entry:217 %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.nxv1i16(218 <vscale x 1 x i32> poison,219 <vscale x 1 x i32> %0,220 <vscale x 1 x i16> %1,221 iXLen %2)222 223 ret <vscale x 1 x i32> %a224}225 226define <vscale x 1 x i32> @intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {227; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i32_nxv1i32_nxv1i16:228; CHECK: # %bb.0: # %entry229; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu230; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t231; CHECK-NEXT: ret232entry:233 %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.mask.nxv1i32.nxv1i16(234 <vscale x 1 x i32> %0,235 <vscale x 1 x i32> %1,236 <vscale x 1 x i16> %2,237 <vscale x 1 x i1> %3,238 iXLen %4, iXLen 1)239 240 ret <vscale x 1 x i32> %a241}242 243define <vscale x 2 x i32> @intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {244; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i32_nxv2i32_nxv2i16:245; CHECK: # %bb.0: # %entry246; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma247; CHECK-NEXT: vwadd.wv v8, v8, v9248; CHECK-NEXT: ret249entry:250 %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(251 <vscale x 2 x i32> poison,252 <vscale x 2 x i32> %0,253 <vscale x 2 x i16> %1,254 iXLen %2)255 256 ret <vscale x 2 x i32> %a257}258 259define <vscale x 2 x i32> @intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {260; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i32_nxv2i32_nxv2i16:261; CHECK: # %bb.0: # %entry262; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu263; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t264; CHECK-NEXT: ret265entry:266 %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.mask.nxv2i32.nxv2i16(267 <vscale x 2 x i32> %0,268 <vscale x 2 x i32> %1,269 <vscale x 2 x i16> %2,270 <vscale x 2 x i1> %3,271 iXLen %4, iXLen 1)272 273 ret <vscale x 2 x i32> %a274}275 276define <vscale x 4 x i32> @intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {277; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i32_nxv4i32_nxv4i16:278; CHECK: # %bb.0: # %entry279; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma280; CHECK-NEXT: vwadd.wv v8, v8, v10281; CHECK-NEXT: ret282entry:283 %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.nxv4i16(284 <vscale x 4 x i32> poison,285 <vscale x 4 x i32> %0,286 <vscale x 4 x i16> %1,287 iXLen %2)288 289 ret <vscale x 4 x i32> %a290}291 292define <vscale x 4 x i32> @intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {293; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i32_nxv4i32_nxv4i16:294; CHECK: # %bb.0: # %entry295; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu296; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t297; CHECK-NEXT: ret298entry:299 %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.mask.nxv4i32.nxv4i16(300 <vscale x 4 x i32> %0,301 <vscale x 4 x i32> %1,302 <vscale x 4 x i16> %2,303 <vscale x 4 x i1> %3,304 iXLen %4, iXLen 1)305 306 ret <vscale x 4 x i32> %a307}308 309define <vscale x 8 x i32> @intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {310; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i32_nxv8i32_nxv8i16:311; CHECK: # %bb.0: # %entry312; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma313; CHECK-NEXT: vwadd.wv v8, v8, v12314; CHECK-NEXT: ret315entry:316 %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.nxv8i16(317 <vscale x 8 x i32> poison,318 <vscale x 8 x i32> %0,319 <vscale x 8 x i16> %1,320 iXLen %2)321 322 ret <vscale x 8 x i32> %a323}324 325define <vscale x 8 x i32> @intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {326; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i32_nxv8i32_nxv8i16:327; CHECK: # %bb.0: # %entry328; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu329; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t330; CHECK-NEXT: ret331entry:332 %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.mask.nxv8i32.nxv8i16(333 <vscale x 8 x i32> %0,334 <vscale x 8 x i32> %1,335 <vscale x 8 x i16> %2,336 <vscale x 8 x i1> %3,337 iXLen %4, iXLen 1)338 339 ret <vscale x 8 x i32> %a340}341 342define <vscale x 16 x i32> @intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {343; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv16i32_nxv16i32_nxv16i16:344; CHECK: # %bb.0: # %entry345; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma346; CHECK-NEXT: vwadd.wv v8, v8, v16347; CHECK-NEXT: ret348entry:349 %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.nxv16i16(350 <vscale x 16 x i32> poison,351 <vscale x 16 x i32> %0,352 <vscale x 16 x i16> %1,353 iXLen %2)354 355 ret <vscale x 16 x i32> %a356}357 358define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {359; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:360; CHECK: # %bb.0: # %entry361; CHECK-NEXT: vl4re16.v v24, (a0)362; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu363; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t364; CHECK-NEXT: ret365entry:366 %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(367 <vscale x 16 x i32> %0,368 <vscale x 16 x i32> %1,369 <vscale x 16 x i16> %2,370 <vscale x 16 x i1> %3,371 iXLen %4, iXLen 1)372 373 ret <vscale x 16 x i32> %a374}375 376define <vscale x 1 x i64> @intrinsic_vwadd.w_wv_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {377; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv1i64_nxv1i64_nxv1i32:378; CHECK: # %bb.0: # %entry379; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma380; CHECK-NEXT: vwadd.wv v8, v8, v9381; CHECK-NEXT: ret382entry:383 %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.nxv1i32(384 <vscale x 1 x i64> poison,385 <vscale x 1 x i64> %0,386 <vscale x 1 x i32> %1,387 iXLen %2)388 389 ret <vscale x 1 x i64> %a390}391 392define <vscale x 1 x i64> @intrinsic_vwadd.w_mask_wv_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {393; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv1i64_nxv1i64_nxv1i32:394; CHECK: # %bb.0: # %entry395; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu396; CHECK-NEXT: vwadd.wv v8, v9, v10, v0.t397; CHECK-NEXT: ret398entry:399 %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.mask.nxv1i64.nxv1i32(400 <vscale x 1 x i64> %0,401 <vscale x 1 x i64> %1,402 <vscale x 1 x i32> %2,403 <vscale x 1 x i1> %3,404 iXLen %4, iXLen 1)405 406 ret <vscale x 1 x i64> %a407}408 409define <vscale x 2 x i64> @intrinsic_vwadd.w_wv_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {410; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv2i64_nxv2i64_nxv2i32:411; CHECK: # %bb.0: # %entry412; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma413; CHECK-NEXT: vwadd.wv v8, v8, v10414; CHECK-NEXT: ret415entry:416 %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.nxv2i32(417 <vscale x 2 x i64> poison,418 <vscale x 2 x i64> %0,419 <vscale x 2 x i32> %1,420 iXLen %2)421 422 ret <vscale x 2 x i64> %a423}424 425define <vscale x 2 x i64> @intrinsic_vwadd.w_mask_wv_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {426; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv2i64_nxv2i64_nxv2i32:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu429; CHECK-NEXT: vwadd.wv v8, v10, v12, v0.t430; CHECK-NEXT: ret431entry:432 %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.mask.nxv2i64.nxv2i32(433 <vscale x 2 x i64> %0,434 <vscale x 2 x i64> %1,435 <vscale x 2 x i32> %2,436 <vscale x 2 x i1> %3,437 iXLen %4, iXLen 1)438 439 ret <vscale x 2 x i64> %a440}441 442define <vscale x 4 x i64> @intrinsic_vwadd.w_wv_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {443; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv4i64_nxv4i64_nxv4i32:444; CHECK: # %bb.0: # %entry445; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma446; CHECK-NEXT: vwadd.wv v8, v8, v12447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.nxv4i32(450 <vscale x 4 x i64> poison,451 <vscale x 4 x i64> %0,452 <vscale x 4 x i32> %1,453 iXLen %2)454 455 ret <vscale x 4 x i64> %a456}457 458define <vscale x 4 x i64> @intrinsic_vwadd.w_mask_wv_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {459; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv4i64_nxv4i64_nxv4i32:460; CHECK: # %bb.0: # %entry461; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu462; CHECK-NEXT: vwadd.wv v8, v12, v16, v0.t463; CHECK-NEXT: ret464entry:465 %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.mask.nxv4i64.nxv4i32(466 <vscale x 4 x i64> %0,467 <vscale x 4 x i64> %1,468 <vscale x 4 x i32> %2,469 <vscale x 4 x i1> %3,470 iXLen %4, iXLen 1)471 472 ret <vscale x 4 x i64> %a473}474 475define <vscale x 8 x i64> @intrinsic_vwadd.w_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {476; CHECK-LABEL: intrinsic_vwadd.w_wv_nxv8i64_nxv8i64_nxv8i32:477; CHECK: # %bb.0: # %entry478; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma479; CHECK-NEXT: vwadd.wv v8, v8, v16480; CHECK-NEXT: ret481entry:482 %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.nxv8i32(483 <vscale x 8 x i64> poison,484 <vscale x 8 x i64> %0,485 <vscale x 8 x i32> %1,486 iXLen %2)487 488 ret <vscale x 8 x i64> %a489}490 491define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {492; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:493; CHECK: # %bb.0: # %entry494; CHECK-NEXT: vl4re32.v v24, (a0)495; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu496; CHECK-NEXT: vwadd.wv v8, v16, v24, v0.t497; CHECK-NEXT: ret498entry:499 %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(500 <vscale x 8 x i64> %0,501 <vscale x 8 x i64> %1,502 <vscale x 8 x i32> %2,503 <vscale x 8 x i1> %3,504 iXLen %4, iXLen 1)505 506 ret <vscale x 8 x i64> %a507}508 509define <vscale x 1 x i16> @intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, iXLen %2) nounwind {510; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8:511; CHECK: # %bb.0: # %entry512; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma513; CHECK-NEXT: vwadd.wx v8, v8, a0514; CHECK-NEXT: ret515entry:516 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8(517 <vscale x 1 x i16> poison,518 <vscale x 1 x i16> %0,519 i8 %1,520 iXLen %2)521 522 ret <vscale x 1 x i16> %a523}524 525define <vscale x 1 x i16> @intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {526; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i16_nxv1i16_i8:527; CHECK: # %bb.0: # %entry528; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu529; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t530; CHECK-NEXT: ret531entry:532 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.mask.nxv1i16.i8(533 <vscale x 1 x i16> %0,534 <vscale x 1 x i16> %1,535 i8 %2,536 <vscale x 1 x i1> %3,537 iXLen %4, iXLen 1)538 539 ret <vscale x 1 x i16> %a540}541 542define <vscale x 2 x i16> @intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, iXLen %2) nounwind {543; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8:544; CHECK: # %bb.0: # %entry545; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma546; CHECK-NEXT: vwadd.wx v8, v8, a0547; CHECK-NEXT: ret548entry:549 %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8(550 <vscale x 2 x i16> poison,551 <vscale x 2 x i16> %0,552 i8 %1,553 iXLen %2)554 555 ret <vscale x 2 x i16> %a556}557 558define <vscale x 2 x i16> @intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {559; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i16_nxv2i16_i8:560; CHECK: # %bb.0: # %entry561; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu562; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t563; CHECK-NEXT: ret564entry:565 %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.mask.nxv2i16.i8(566 <vscale x 2 x i16> %0,567 <vscale x 2 x i16> %1,568 i8 %2,569 <vscale x 2 x i1> %3,570 iXLen %4, iXLen 1)571 572 ret <vscale x 2 x i16> %a573}574 575define <vscale x 4 x i16> @intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, iXLen %2) nounwind {576; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8:577; CHECK: # %bb.0: # %entry578; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma579; CHECK-NEXT: vwadd.wx v8, v8, a0580; CHECK-NEXT: ret581entry:582 %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.i8(583 <vscale x 4 x i16> poison,584 <vscale x 4 x i16> %0,585 i8 %1,586 iXLen %2)587 588 ret <vscale x 4 x i16> %a589}590 591define <vscale x 4 x i16> @intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {592; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i16_nxv4i16_i8:593; CHECK: # %bb.0: # %entry594; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu595; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t596; CHECK-NEXT: ret597entry:598 %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.mask.nxv4i16.i8(599 <vscale x 4 x i16> %0,600 <vscale x 4 x i16> %1,601 i8 %2,602 <vscale x 4 x i1> %3,603 iXLen %4, iXLen 1)604 605 ret <vscale x 4 x i16> %a606}607 608define <vscale x 8 x i16> @intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, iXLen %2) nounwind {609; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8:610; CHECK: # %bb.0: # %entry611; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma612; CHECK-NEXT: vwadd.wx v8, v8, a0613; CHECK-NEXT: ret614entry:615 %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.i8(616 <vscale x 8 x i16> poison,617 <vscale x 8 x i16> %0,618 i8 %1,619 iXLen %2)620 621 ret <vscale x 8 x i16> %a622}623 624define <vscale x 8 x i16> @intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {625; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i16_nxv8i16_i8:626; CHECK: # %bb.0: # %entry627; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu628; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t629; CHECK-NEXT: ret630entry:631 %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.mask.nxv8i16.i8(632 <vscale x 8 x i16> %0,633 <vscale x 8 x i16> %1,634 i8 %2,635 <vscale x 8 x i1> %3,636 iXLen %4, iXLen 1)637 638 ret <vscale x 8 x i16> %a639}640 641define <vscale x 16 x i16> @intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, iXLen %2) nounwind {642; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8:643; CHECK: # %bb.0: # %entry644; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma645; CHECK-NEXT: vwadd.wx v8, v8, a0646; CHECK-NEXT: ret647entry:648 %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.i8(649 <vscale x 16 x i16> poison,650 <vscale x 16 x i16> %0,651 i8 %1,652 iXLen %2)653 654 ret <vscale x 16 x i16> %a655}656 657define <vscale x 16 x i16> @intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {658; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i16_nxv16i16_i8:659; CHECK: # %bb.0: # %entry660; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu661; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t662; CHECK-NEXT: ret663entry:664 %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.mask.nxv16i16.i8(665 <vscale x 16 x i16> %0,666 <vscale x 16 x i16> %1,667 i8 %2,668 <vscale x 16 x i1> %3,669 iXLen %4, iXLen 1)670 671 ret <vscale x 16 x i16> %a672}673 674define <vscale x 32 x i16> @intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, iXLen %2) nounwind {675; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8:676; CHECK: # %bb.0: # %entry677; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma678; CHECK-NEXT: vwadd.wx v8, v8, a0679; CHECK-NEXT: ret680entry:681 %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.i8(682 <vscale x 32 x i16> poison,683 <vscale x 32 x i16> %0,684 i8 %1,685 iXLen %2)686 687 ret <vscale x 32 x i16> %a688}689 690define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {691; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv32i16_nxv32i16_i8:692; CHECK: # %bb.0: # %entry693; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu694; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t695; CHECK-NEXT: ret696entry:697 %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.i8(698 <vscale x 32 x i16> %0,699 <vscale x 32 x i16> %1,700 i8 %2,701 <vscale x 32 x i1> %3,702 iXLen %4, iXLen 1)703 704 ret <vscale x 32 x i16> %a705}706 707define <vscale x 1 x i32> @intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, iXLen %2) nounwind {708; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16:709; CHECK: # %bb.0: # %entry710; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma711; CHECK-NEXT: vwadd.wx v8, v8, a0712; CHECK-NEXT: ret713entry:714 %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.i16(715 <vscale x 1 x i32> poison,716 <vscale x 1 x i32> %0,717 i16 %1,718 iXLen %2)719 720 ret <vscale x 1 x i32> %a721}722 723define <vscale x 1 x i32> @intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {724; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i32_nxv1i32_i16:725; CHECK: # %bb.0: # %entry726; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu727; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t728; CHECK-NEXT: ret729entry:730 %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.mask.nxv1i32.i16(731 <vscale x 1 x i32> %0,732 <vscale x 1 x i32> %1,733 i16 %2,734 <vscale x 1 x i1> %3,735 iXLen %4, iXLen 1)736 737 ret <vscale x 1 x i32> %a738}739 740define <vscale x 2 x i32> @intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, iXLen %2) nounwind {741; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16:742; CHECK: # %bb.0: # %entry743; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma744; CHECK-NEXT: vwadd.wx v8, v8, a0745; CHECK-NEXT: ret746entry:747 %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.i16(748 <vscale x 2 x i32> poison,749 <vscale x 2 x i32> %0,750 i16 %1,751 iXLen %2)752 753 ret <vscale x 2 x i32> %a754}755 756define <vscale x 2 x i32> @intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {757; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i32_nxv2i32_i16:758; CHECK: # %bb.0: # %entry759; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu760; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t761; CHECK-NEXT: ret762entry:763 %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.mask.nxv2i32.i16(764 <vscale x 2 x i32> %0,765 <vscale x 2 x i32> %1,766 i16 %2,767 <vscale x 2 x i1> %3,768 iXLen %4, iXLen 1)769 770 ret <vscale x 2 x i32> %a771}772 773define <vscale x 4 x i32> @intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, iXLen %2) nounwind {774; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16:775; CHECK: # %bb.0: # %entry776; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma777; CHECK-NEXT: vwadd.wx v8, v8, a0778; CHECK-NEXT: ret779entry:780 %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.i16(781 <vscale x 4 x i32> poison,782 <vscale x 4 x i32> %0,783 i16 %1,784 iXLen %2)785 786 ret <vscale x 4 x i32> %a787}788 789define <vscale x 4 x i32> @intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {790; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i32_nxv4i32_i16:791; CHECK: # %bb.0: # %entry792; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu793; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t794; CHECK-NEXT: ret795entry:796 %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.mask.nxv4i32.i16(797 <vscale x 4 x i32> %0,798 <vscale x 4 x i32> %1,799 i16 %2,800 <vscale x 4 x i1> %3,801 iXLen %4, iXLen 1)802 803 ret <vscale x 4 x i32> %a804}805 806define <vscale x 8 x i32> @intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, iXLen %2) nounwind {807; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16:808; CHECK: # %bb.0: # %entry809; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma810; CHECK-NEXT: vwadd.wx v8, v8, a0811; CHECK-NEXT: ret812entry:813 %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.i16(814 <vscale x 8 x i32> poison,815 <vscale x 8 x i32> %0,816 i16 %1,817 iXLen %2)818 819 ret <vscale x 8 x i32> %a820}821 822define <vscale x 8 x i32> @intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {823; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i32_nxv8i32_i16:824; CHECK: # %bb.0: # %entry825; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu826; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t827; CHECK-NEXT: ret828entry:829 %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.mask.nxv8i32.i16(830 <vscale x 8 x i32> %0,831 <vscale x 8 x i32> %1,832 i16 %2,833 <vscale x 8 x i1> %3,834 iXLen %4, iXLen 1)835 836 ret <vscale x 8 x i32> %a837}838 839define <vscale x 16 x i32> @intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, iXLen %2) nounwind {840; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16:841; CHECK: # %bb.0: # %entry842; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma843; CHECK-NEXT: vwadd.wx v8, v8, a0844; CHECK-NEXT: ret845entry:846 %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.i16(847 <vscale x 16 x i32> poison,848 <vscale x 16 x i32> %0,849 i16 %1,850 iXLen %2)851 852 ret <vscale x 16 x i32> %a853}854 855define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {856; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv16i32_nxv16i32_i16:857; CHECK: # %bb.0: # %entry858; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu859; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t860; CHECK-NEXT: ret861entry:862 %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.i16(863 <vscale x 16 x i32> %0,864 <vscale x 16 x i32> %1,865 i16 %2,866 <vscale x 16 x i1> %3,867 iXLen %4, iXLen 1)868 869 ret <vscale x 16 x i32> %a870}871 872define <vscale x 1 x i64> @intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, iXLen %2) nounwind {873; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32:874; CHECK: # %bb.0: # %entry875; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma876; CHECK-NEXT: vwadd.wx v8, v8, a0877; CHECK-NEXT: ret878entry:879 %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.i32(880 <vscale x 1 x i64> poison,881 <vscale x 1 x i64> %0,882 i32 %1,883 iXLen %2)884 885 ret <vscale x 1 x i64> %a886}887 888define <vscale x 1 x i64> @intrinsic_vwadd.w_mask_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {889; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv1i64_nxv1i64_i32:890; CHECK: # %bb.0: # %entry891; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu892; CHECK-NEXT: vwadd.wx v8, v9, a0, v0.t893; CHECK-NEXT: ret894entry:895 %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.mask.nxv1i64.i32(896 <vscale x 1 x i64> %0,897 <vscale x 1 x i64> %1,898 i32 %2,899 <vscale x 1 x i1> %3,900 iXLen %4, iXLen 1)901 902 ret <vscale x 1 x i64> %a903}904 905define <vscale x 2 x i64> @intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, iXLen %2) nounwind {906; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32:907; CHECK: # %bb.0: # %entry908; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma909; CHECK-NEXT: vwadd.wx v8, v8, a0910; CHECK-NEXT: ret911entry:912 %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.i32(913 <vscale x 2 x i64> poison,914 <vscale x 2 x i64> %0,915 i32 %1,916 iXLen %2)917 918 ret <vscale x 2 x i64> %a919}920 921define <vscale x 2 x i64> @intrinsic_vwadd.w_mask_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {922; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv2i64_nxv2i64_i32:923; CHECK: # %bb.0: # %entry924; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu925; CHECK-NEXT: vwadd.wx v8, v10, a0, v0.t926; CHECK-NEXT: ret927entry:928 %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.mask.nxv2i64.i32(929 <vscale x 2 x i64> %0,930 <vscale x 2 x i64> %1,931 i32 %2,932 <vscale x 2 x i1> %3,933 iXLen %4, iXLen 1)934 935 ret <vscale x 2 x i64> %a936}937 938define <vscale x 4 x i64> @intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, iXLen %2) nounwind {939; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32:940; CHECK: # %bb.0: # %entry941; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma942; CHECK-NEXT: vwadd.wx v8, v8, a0943; CHECK-NEXT: ret944entry:945 %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.i32(946 <vscale x 4 x i64> poison,947 <vscale x 4 x i64> %0,948 i32 %1,949 iXLen %2)950 951 ret <vscale x 4 x i64> %a952}953 954define <vscale x 4 x i64> @intrinsic_vwadd.w_mask_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {955; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv4i64_nxv4i64_i32:956; CHECK: # %bb.0: # %entry957; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu958; CHECK-NEXT: vwadd.wx v8, v12, a0, v0.t959; CHECK-NEXT: ret960entry:961 %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.mask.nxv4i64.i32(962 <vscale x 4 x i64> %0,963 <vscale x 4 x i64> %1,964 i32 %2,965 <vscale x 4 x i1> %3,966 iXLen %4, iXLen 1)967 968 ret <vscale x 4 x i64> %a969}970 971define <vscale x 8 x i64> @intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, iXLen %2) nounwind {972; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32:973; CHECK: # %bb.0: # %entry974; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma975; CHECK-NEXT: vwadd.wx v8, v8, a0976; CHECK-NEXT: ret977entry:978 %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.i32(979 <vscale x 8 x i64> poison,980 <vscale x 8 x i64> %0,981 i32 %1,982 iXLen %2)983 984 ret <vscale x 8 x i64> %a985}986 987define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {988; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_nxv8i64_nxv8i64_i32:989; CHECK: # %bb.0: # %entry990; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu991; CHECK-NEXT: vwadd.wx v8, v16, a0, v0.t992; CHECK-NEXT: ret993entry:994 %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.i32(995 <vscale x 8 x i64> %0,996 <vscale x 8 x i64> %1,997 i32 %2,998 <vscale x 8 x i1> %3,999 iXLen %4, iXLen 1)1000 1001 ret <vscale x 8 x i64> %a1002}1003 1004define <vscale x 1 x i16> @intrinsic_vwadd.w_mask_wv_tie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1005; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv1i16_nxv1i16_nxv1i8:1006; CHECK: # %bb.0: # %entry1007; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu1008; CHECK-NEXT: vwadd.wv v8, v8, v9, v0.t1009; CHECK-NEXT: ret1010entry:1011 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.mask.nxv1i16.nxv1i8(1012 <vscale x 1 x i16> %0,1013 <vscale x 1 x i16> %0,1014 <vscale x 1 x i8> %1,1015 <vscale x 1 x i1> %2,1016 iXLen %3, iXLen 1)1017 1018 ret <vscale x 1 x i16> %a1019}1020 1021define <vscale x 2 x i16> @intrinsic_vwadd.w_mask_wv_tie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1022; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv2i16_nxv2i16_nxv2i8:1023; CHECK: # %bb.0: # %entry1024; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu1025; CHECK-NEXT: vwadd.wv v8, v8, v9, v0.t1026; CHECK-NEXT: ret1027entry:1028 %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.mask.nxv2i16.nxv2i8(1029 <vscale x 2 x i16> %0,1030 <vscale x 2 x i16> %0,1031 <vscale x 2 x i8> %1,1032 <vscale x 2 x i1> %2,1033 iXLen %3, iXLen 1)1034 1035 ret <vscale x 2 x i16> %a1036}1037 1038define <vscale x 4 x i16> @intrinsic_vwadd.w_mask_wv_tie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1039; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv4i16_nxv4i16_nxv4i8:1040; CHECK: # %bb.0: # %entry1041; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu1042; CHECK-NEXT: vwadd.wv v8, v8, v9, v0.t1043; CHECK-NEXT: ret1044entry:1045 %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.mask.nxv4i16.nxv4i8(1046 <vscale x 4 x i16> %0,1047 <vscale x 4 x i16> %0,1048 <vscale x 4 x i8> %1,1049 <vscale x 4 x i1> %2,1050 iXLen %3, iXLen 1)1051 1052 ret <vscale x 4 x i16> %a1053}1054 1055define <vscale x 8 x i16> @intrinsic_vwadd.w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1056; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8:1057; CHECK: # %bb.0: # %entry1058; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu1059; CHECK-NEXT: vwadd.wv v8, v8, v10, v0.t1060; CHECK-NEXT: ret1061entry:1062 %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.mask.nxv8i16.nxv8i8(1063 <vscale x 8 x i16> %0,1064 <vscale x 8 x i16> %0,1065 <vscale x 8 x i8> %1,1066 <vscale x 8 x i1> %2,1067 iXLen %3, iXLen 1)1068 1069 ret <vscale x 8 x i16> %a1070}1071 1072define <vscale x 16 x i16> @intrinsic_vwadd.w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1073; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8:1074; CHECK: # %bb.0: # %entry1075; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu1076; CHECK-NEXT: vwadd.wv v8, v8, v12, v0.t1077; CHECK-NEXT: ret1078entry:1079 %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.mask.nxv16i16.nxv16i8(1080 <vscale x 16 x i16> %0,1081 <vscale x 16 x i16> %0,1082 <vscale x 16 x i8> %1,1083 <vscale x 16 x i1> %2,1084 iXLen %3, iXLen 1)1085 1086 ret <vscale x 16 x i16> %a1087}1088 1089define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1090; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8:1091; CHECK: # %bb.0: # %entry1092; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu1093; CHECK-NEXT: vwadd.wv v8, v8, v16, v0.t1094; CHECK-NEXT: ret1095entry:1096 %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.nxv32i8(1097 <vscale x 32 x i16> %0,1098 <vscale x 32 x i16> %0,1099 <vscale x 32 x i8> %1,1100 <vscale x 32 x i1> %2,1101 iXLen %3, iXLen 1)1102 1103 ret <vscale x 32 x i16> %a1104}1105 1106define <vscale x 1 x i32> @intrinsic_vwadd.w_mask_wv_tie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1107; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv1i32_nxv1i32_nxv1i16:1108; CHECK: # %bb.0: # %entry1109; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1110; CHECK-NEXT: vwadd.wv v8, v8, v9, v0.t1111; CHECK-NEXT: ret1112entry:1113 %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.mask.nxv1i32.nxv1i16(1114 <vscale x 1 x i32> %0,1115 <vscale x 1 x i32> %0,1116 <vscale x 1 x i16> %1,1117 <vscale x 1 x i1> %2,1118 iXLen %3, iXLen 1)1119 1120 ret <vscale x 1 x i32> %a1121}1122 1123define <vscale x 2 x i32> @intrinsic_vwadd.w_mask_wv_tie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1124; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv2i32_nxv2i32_nxv2i16:1125; CHECK: # %bb.0: # %entry1126; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1127; CHECK-NEXT: vwadd.wv v8, v8, v9, v0.t1128; CHECK-NEXT: ret1129entry:1130 %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.mask.nxv2i32.nxv2i16(1131 <vscale x 2 x i32> %0,1132 <vscale x 2 x i32> %0,1133 <vscale x 2 x i16> %1,1134 <vscale x 2 x i1> %2,1135 iXLen %3, iXLen 1)1136 1137 ret <vscale x 2 x i32> %a1138}1139 1140define <vscale x 4 x i32> @intrinsic_vwadd.w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1141; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16:1142; CHECK: # %bb.0: # %entry1143; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1144; CHECK-NEXT: vwadd.wv v8, v8, v10, v0.t1145; CHECK-NEXT: ret1146entry:1147 %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.mask.nxv4i32.nxv4i16(1148 <vscale x 4 x i32> %0,1149 <vscale x 4 x i32> %0,1150 <vscale x 4 x i16> %1,1151 <vscale x 4 x i1> %2,1152 iXLen %3, iXLen 1)1153 1154 ret <vscale x 4 x i32> %a1155}1156 1157define <vscale x 8 x i32> @intrinsic_vwadd.w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1158; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16:1159; CHECK: # %bb.0: # %entry1160; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1161; CHECK-NEXT: vwadd.wv v8, v8, v12, v0.t1162; CHECK-NEXT: ret1163entry:1164 %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.mask.nxv8i32.nxv8i16(1165 <vscale x 8 x i32> %0,1166 <vscale x 8 x i32> %0,1167 <vscale x 8 x i16> %1,1168 <vscale x 8 x i1> %2,1169 iXLen %3, iXLen 1)1170 1171 ret <vscale x 8 x i32> %a1172}1173 1174define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1175; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16:1176; CHECK: # %bb.0: # %entry1177; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1178; CHECK-NEXT: vwadd.wv v8, v8, v16, v0.t1179; CHECK-NEXT: ret1180entry:1181 %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.nxv16i16(1182 <vscale x 16 x i32> %0,1183 <vscale x 16 x i32> %0,1184 <vscale x 16 x i16> %1,1185 <vscale x 16 x i1> %2,1186 iXLen %3, iXLen 1)1187 1188 ret <vscale x 16 x i32> %a1189}1190 1191define <vscale x 1 x i64> @intrinsic_vwadd.w_mask_wv_tie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1192; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv1i64_nxv1i64_nxv1i32:1193; CHECK: # %bb.0: # %entry1194; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu1195; CHECK-NEXT: vwadd.wv v8, v8, v9, v0.t1196; CHECK-NEXT: ret1197entry:1198 %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.mask.nxv1i64.nxv1i32(1199 <vscale x 1 x i64> %0,1200 <vscale x 1 x i64> %0,1201 <vscale x 1 x i32> %1,1202 <vscale x 1 x i1> %2,1203 iXLen %3, iXLen 1)1204 1205 ret <vscale x 1 x i64> %a1206}1207 1208define <vscale x 2 x i64> @intrinsic_vwadd.w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1209; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32:1210; CHECK: # %bb.0: # %entry1211; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu1212; CHECK-NEXT: vwadd.wv v8, v8, v10, v0.t1213; CHECK-NEXT: ret1214entry:1215 %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.mask.nxv2i64.nxv2i32(1216 <vscale x 2 x i64> %0,1217 <vscale x 2 x i64> %0,1218 <vscale x 2 x i32> %1,1219 <vscale x 2 x i1> %2,1220 iXLen %3, iXLen 1)1221 1222 ret <vscale x 2 x i64> %a1223}1224 1225define <vscale x 4 x i64> @intrinsic_vwadd.w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1226; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32:1227; CHECK: # %bb.0: # %entry1228; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu1229; CHECK-NEXT: vwadd.wv v8, v8, v12, v0.t1230; CHECK-NEXT: ret1231entry:1232 %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.mask.nxv4i64.nxv4i32(1233 <vscale x 4 x i64> %0,1234 <vscale x 4 x i64> %0,1235 <vscale x 4 x i32> %1,1236 <vscale x 4 x i1> %2,1237 iXLen %3, iXLen 1)1238 1239 ret <vscale x 4 x i64> %a1240}1241 1242define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1243; CHECK-LABEL: intrinsic_vwadd.w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32:1244; CHECK: # %bb.0: # %entry1245; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu1246; CHECK-NEXT: vwadd.wv v8, v8, v16, v0.t1247; CHECK-NEXT: ret1248entry:1249 %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.nxv8i32(1250 <vscale x 8 x i64> %0,1251 <vscale x 8 x i64> %0,1252 <vscale x 8 x i32> %1,1253 <vscale x 8 x i1> %2,1254 iXLen %3, iXLen 1)1255 1256 ret <vscale x 8 x i64> %a1257}1258 1259define <vscale x 1 x i16> @intrinsic_vwadd.w_mask_wx_tie_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1260; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv1i16_nxv1i16_i8:1261; CHECK: # %bb.0: # %entry1262; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu1263; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1264; CHECK-NEXT: ret1265entry:1266 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.mask.nxv1i16.i8(1267 <vscale x 1 x i16> %0,1268 <vscale x 1 x i16> %0,1269 i8 %1,1270 <vscale x 1 x i1> %2,1271 iXLen %3, iXLen 1)1272 1273 ret <vscale x 1 x i16> %a1274}1275 1276define <vscale x 2 x i16> @intrinsic_vwadd.w_mask_wx_tie_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1277; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv2i16_nxv2i16_i8:1278; CHECK: # %bb.0: # %entry1279; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu1280; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1281; CHECK-NEXT: ret1282entry:1283 %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.mask.nxv2i16.i8(1284 <vscale x 2 x i16> %0,1285 <vscale x 2 x i16> %0,1286 i8 %1,1287 <vscale x 2 x i1> %2,1288 iXLen %3, iXLen 1)1289 1290 ret <vscale x 2 x i16> %a1291}1292 1293define <vscale x 4 x i16> @intrinsic_vwadd.w_mask_wx_tie_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1294; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv4i16_nxv4i16_i8:1295; CHECK: # %bb.0: # %entry1296; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu1297; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1298; CHECK-NEXT: ret1299entry:1300 %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.mask.nxv4i16.i8(1301 <vscale x 4 x i16> %0,1302 <vscale x 4 x i16> %0,1303 i8 %1,1304 <vscale x 4 x i1> %2,1305 iXLen %3, iXLen 1)1306 1307 ret <vscale x 4 x i16> %a1308}1309 1310define <vscale x 8 x i16> @intrinsic_vwadd.w_mask_wx_tie_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1311; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv8i16_nxv8i16_i8:1312; CHECK: # %bb.0: # %entry1313; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu1314; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1315; CHECK-NEXT: ret1316entry:1317 %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.mask.nxv8i16.i8(1318 <vscale x 8 x i16> %0,1319 <vscale x 8 x i16> %0,1320 i8 %1,1321 <vscale x 8 x i1> %2,1322 iXLen %3, iXLen 1)1323 1324 ret <vscale x 8 x i16> %a1325}1326 1327define <vscale x 16 x i16> @intrinsic_vwadd.w_mask_wx_tie_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1328; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv16i16_nxv16i16_i8:1329; CHECK: # %bb.0: # %entry1330; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu1331; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1332; CHECK-NEXT: ret1333entry:1334 %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.mask.nxv16i16.i8(1335 <vscale x 16 x i16> %0,1336 <vscale x 16 x i16> %0,1337 i8 %1,1338 <vscale x 16 x i1> %2,1339 iXLen %3, iXLen 1)1340 1341 ret <vscale x 16 x i16> %a1342}1343 1344define <vscale x 32 x i16> @intrinsic_vwadd.w_mask_wx_tie_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1345; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv32i16_nxv32i16_i8:1346; CHECK: # %bb.0: # %entry1347; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu1348; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1349; CHECK-NEXT: ret1350entry:1351 %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.mask.nxv32i16.i8(1352 <vscale x 32 x i16> %0,1353 <vscale x 32 x i16> %0,1354 i8 %1,1355 <vscale x 32 x i1> %2,1356 iXLen %3, iXLen 1)1357 1358 ret <vscale x 32 x i16> %a1359}1360 1361define <vscale x 1 x i32> @intrinsic_vwadd.w_mask_wx_tie_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1362; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv1i32_nxv1i32_i16:1363; CHECK: # %bb.0: # %entry1364; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1365; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1366; CHECK-NEXT: ret1367entry:1368 %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.mask.nxv1i32.i16(1369 <vscale x 1 x i32> %0,1370 <vscale x 1 x i32> %0,1371 i16 %1,1372 <vscale x 1 x i1> %2,1373 iXLen %3, iXLen 1)1374 1375 ret <vscale x 1 x i32> %a1376}1377 1378define <vscale x 2 x i32> @intrinsic_vwadd.w_mask_wx_tie_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1379; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv2i32_nxv2i32_i16:1380; CHECK: # %bb.0: # %entry1381; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1382; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1383; CHECK-NEXT: ret1384entry:1385 %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.mask.nxv2i32.i16(1386 <vscale x 2 x i32> %0,1387 <vscale x 2 x i32> %0,1388 i16 %1,1389 <vscale x 2 x i1> %2,1390 iXLen %3, iXLen 1)1391 1392 ret <vscale x 2 x i32> %a1393}1394 1395define <vscale x 4 x i32> @intrinsic_vwadd.w_mask_wx_tie_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1396; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv4i32_nxv4i32_i16:1397; CHECK: # %bb.0: # %entry1398; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1399; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1400; CHECK-NEXT: ret1401entry:1402 %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.mask.nxv4i32.i16(1403 <vscale x 4 x i32> %0,1404 <vscale x 4 x i32> %0,1405 i16 %1,1406 <vscale x 4 x i1> %2,1407 iXLen %3, iXLen 1)1408 1409 ret <vscale x 4 x i32> %a1410}1411 1412define <vscale x 8 x i32> @intrinsic_vwadd.w_mask_wx_tie_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1413; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv8i32_nxv8i32_i16:1414; CHECK: # %bb.0: # %entry1415; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1416; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1417; CHECK-NEXT: ret1418entry:1419 %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.mask.nxv8i32.i16(1420 <vscale x 8 x i32> %0,1421 <vscale x 8 x i32> %0,1422 i16 %1,1423 <vscale x 8 x i1> %2,1424 iXLen %3, iXLen 1)1425 1426 ret <vscale x 8 x i32> %a1427}1428 1429define <vscale x 16 x i32> @intrinsic_vwadd.w_mask_wx_tie_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1430; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv16i32_nxv16i32_i16:1431; CHECK: # %bb.0: # %entry1432; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1433; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1434; CHECK-NEXT: ret1435entry:1436 %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.mask.nxv16i32.i16(1437 <vscale x 16 x i32> %0,1438 <vscale x 16 x i32> %0,1439 i16 %1,1440 <vscale x 16 x i1> %2,1441 iXLen %3, iXLen 1)1442 1443 ret <vscale x 16 x i32> %a1444}1445 1446define <vscale x 1 x i64> @intrinsic_vwadd.w_mask_wx_tie_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1447; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv1i64_nxv1i64_i32:1448; CHECK: # %bb.0: # %entry1449; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1450; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1451; CHECK-NEXT: ret1452entry:1453 %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.mask.nxv1i64.i32(1454 <vscale x 1 x i64> %0,1455 <vscale x 1 x i64> %0,1456 i32 %1,1457 <vscale x 1 x i1> %2,1458 iXLen %3, iXLen 1)1459 1460 ret <vscale x 1 x i64> %a1461}1462 1463define <vscale x 2 x i64> @intrinsic_vwadd.w_mask_wx_tie_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1464; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv2i64_nxv2i64_i32:1465; CHECK: # %bb.0: # %entry1466; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1467; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1468; CHECK-NEXT: ret1469entry:1470 %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.mask.nxv2i64.i32(1471 <vscale x 2 x i64> %0,1472 <vscale x 2 x i64> %0,1473 i32 %1,1474 <vscale x 2 x i1> %2,1475 iXLen %3, iXLen 1)1476 1477 ret <vscale x 2 x i64> %a1478}1479 1480define <vscale x 4 x i64> @intrinsic_vwadd.w_mask_wx_tie_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1481; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv4i64_nxv4i64_i32:1482; CHECK: # %bb.0: # %entry1483; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1484; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1485; CHECK-NEXT: ret1486entry:1487 %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.mask.nxv4i64.i32(1488 <vscale x 4 x i64> %0,1489 <vscale x 4 x i64> %0,1490 i32 %1,1491 <vscale x 4 x i1> %2,1492 iXLen %3, iXLen 1)1493 1494 ret <vscale x 4 x i64> %a1495}1496 1497define <vscale x 8 x i64> @intrinsic_vwadd.w_mask_wx_tie_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1498; CHECK-LABEL: intrinsic_vwadd.w_mask_wx_tie_nxv8i64_nxv8i64_i32:1499; CHECK: # %bb.0: # %entry1500; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1501; CHECK-NEXT: vwadd.wx v8, v8, a0, v0.t1502; CHECK-NEXT: ret1503entry:1504 %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.mask.nxv8i64.i32(1505 <vscale x 8 x i64> %0,1506 <vscale x 8 x i64> %0,1507 i32 %1,1508 <vscale x 8 x i1> %2,1509 iXLen %3, iXLen 1)1510 1511 ret <vscale x 8 x i64> %a1512}1513 1514define <vscale x 1 x i16> @intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1515; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:1516; CHECK: # %bb.0: # %entry1517; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1518; CHECK-NEXT: vwadd.wv v10, v9, v81519; CHECK-NEXT: vmv1r.v v8, v101520; CHECK-NEXT: ret1521entry:1522 %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.nxv1i8(1523 <vscale x 1 x i16> poison,1524 <vscale x 1 x i16> %1,1525 <vscale x 1 x i8> %0,1526 iXLen %2)1527 1528 ret <vscale x 1 x i16> %a1529}1530 1531define <vscale x 2 x i16> @intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1532; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:1533; CHECK: # %bb.0: # %entry1534; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1535; CHECK-NEXT: vwadd.wv v10, v9, v81536; CHECK-NEXT: vmv1r.v v8, v101537; CHECK-NEXT: ret1538entry:1539 %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.nxv2i8(1540 <vscale x 2 x i16> poison,1541 <vscale x 2 x i16> %1,1542 <vscale x 2 x i8> %0,1543 iXLen %2)1544 1545 ret <vscale x 2 x i16> %a1546}1547 1548define <vscale x 4 x i16> @intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1549; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:1550; CHECK: # %bb.0: # %entry1551; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma1552; CHECK-NEXT: vwadd.wv v10, v9, v81553; CHECK-NEXT: vmv1r.v v8, v101554; CHECK-NEXT: ret1555entry:1556 %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.nxv4i8(1557 <vscale x 4 x i16> poison,1558 <vscale x 4 x i16> %1,1559 <vscale x 4 x i8> %0,1560 iXLen %2)1561 1562 ret <vscale x 4 x i16> %a1563}1564 1565define <vscale x 8 x i16> @intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1566; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:1567; CHECK: # %bb.0: # %entry1568; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma1569; CHECK-NEXT: vmv1r.v v12, v81570; CHECK-NEXT: vwadd.wv v8, v10, v121571; CHECK-NEXT: ret1572entry:1573 %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.nxv8i8(1574 <vscale x 8 x i16> poison,1575 <vscale x 8 x i16> %1,1576 <vscale x 8 x i8> %0,1577 iXLen %2)1578 1579 ret <vscale x 8 x i16> %a1580}1581 1582define <vscale x 16 x i16> @intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1583; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:1584; CHECK: # %bb.0: # %entry1585; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1586; CHECK-NEXT: vmv2r.v v16, v81587; CHECK-NEXT: vwadd.wv v8, v12, v161588; CHECK-NEXT: ret1589entry:1590 %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.nxv16i8(1591 <vscale x 16 x i16> poison,1592 <vscale x 16 x i16> %1,1593 <vscale x 16 x i8> %0,1594 iXLen %2)1595 1596 ret <vscale x 16 x i16> %a1597}1598 1599define <vscale x 32 x i16> @intrinsic_vwadd.w_wv_untie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1600; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv32i16_nxv32i16_nxv32i8:1601; CHECK: # %bb.0: # %entry1602; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma1603; CHECK-NEXT: vmv4r.v v24, v81604; CHECK-NEXT: vwadd.wv v8, v16, v241605; CHECK-NEXT: ret1606entry:1607 %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.nxv32i8(1608 <vscale x 32 x i16> poison,1609 <vscale x 32 x i16> %1,1610 <vscale x 32 x i8> %0,1611 iXLen %2)1612 1613 ret <vscale x 32 x i16> %a1614}1615 1616define <vscale x 1 x i32> @intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {1617; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:1618; CHECK: # %bb.0: # %entry1619; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1620; CHECK-NEXT: vwadd.wv v10, v9, v81621; CHECK-NEXT: vmv1r.v v8, v101622; CHECK-NEXT: ret1623entry:1624 %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.nxv1i16(1625 <vscale x 1 x i32> poison,1626 <vscale x 1 x i32> %1,1627 <vscale x 1 x i16> %0,1628 iXLen %2)1629 1630 ret <vscale x 1 x i32> %a1631}1632 1633define <vscale x 2 x i32> @intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {1634; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:1635; CHECK: # %bb.0: # %entry1636; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1637; CHECK-NEXT: vwadd.wv v10, v9, v81638; CHECK-NEXT: vmv1r.v v8, v101639; CHECK-NEXT: ret1640entry:1641 %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(1642 <vscale x 2 x i32> poison,1643 <vscale x 2 x i32> %1,1644 <vscale x 2 x i16> %0,1645 iXLen %2)1646 1647 ret <vscale x 2 x i32> %a1648}1649 1650define <vscale x 4 x i32> @intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {1651; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:1652; CHECK: # %bb.0: # %entry1653; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1654; CHECK-NEXT: vmv1r.v v12, v81655; CHECK-NEXT: vwadd.wv v8, v10, v121656; CHECK-NEXT: ret1657entry:1658 %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.nxv4i16(1659 <vscale x 4 x i32> poison,1660 <vscale x 4 x i32> %1,1661 <vscale x 4 x i16> %0,1662 iXLen %2)1663 1664 ret <vscale x 4 x i32> %a1665}1666 1667define <vscale x 8 x i32> @intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {1668; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:1669; CHECK: # %bb.0: # %entry1670; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1671; CHECK-NEXT: vmv2r.v v16, v81672; CHECK-NEXT: vwadd.wv v8, v12, v161673; CHECK-NEXT: ret1674entry:1675 %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.nxv8i16(1676 <vscale x 8 x i32> poison,1677 <vscale x 8 x i32> %1,1678 <vscale x 8 x i16> %0,1679 iXLen %2)1680 1681 ret <vscale x 8 x i32> %a1682}1683 1684define <vscale x 1 x i64> @intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {1685; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:1686; CHECK: # %bb.0: # %entry1687; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1688; CHECK-NEXT: vwadd.wv v10, v9, v81689; CHECK-NEXT: vmv1r.v v8, v101690; CHECK-NEXT: ret1691entry:1692 %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.nxv1i32(1693 <vscale x 1 x i64> poison,1694 <vscale x 1 x i64> %1,1695 <vscale x 1 x i32> %0,1696 iXLen %2)1697 1698 ret <vscale x 1 x i64> %a1699}1700 1701define <vscale x 2 x i64> @intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {1702; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:1703; CHECK: # %bb.0: # %entry1704; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1705; CHECK-NEXT: vmv1r.v v12, v81706; CHECK-NEXT: vwadd.wv v8, v10, v121707; CHECK-NEXT: ret1708entry:1709 %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.nxv2i32(1710 <vscale x 2 x i64> poison,1711 <vscale x 2 x i64> %1,1712 <vscale x 2 x i32> %0,1713 iXLen %2)1714 1715 ret <vscale x 2 x i64> %a1716}1717 1718define <vscale x 4 x i64> @intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {1719; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:1720; CHECK: # %bb.0: # %entry1721; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1722; CHECK-NEXT: vmv2r.v v16, v81723; CHECK-NEXT: vwadd.wv v8, v12, v161724; CHECK-NEXT: ret1725entry:1726 %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.nxv4i32(1727 <vscale x 4 x i64> poison,1728 <vscale x 4 x i64> %1,1729 <vscale x 4 x i32> %0,1730 iXLen %2)1731 1732 ret <vscale x 4 x i64> %a1733}1734 1735define <vscale x 8 x i64> @intrinsic_vwadd.w_wv_untie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {1736; CHECK-LABEL: intrinsic_vwadd.w_wv_untie_nxv8i64_nxv8i64_nxv8i32:1737; CHECK: # %bb.0: # %entry1738; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1739; CHECK-NEXT: vmv4r.v v24, v81740; CHECK-NEXT: vwadd.wv v8, v16, v241741; CHECK-NEXT: ret1742entry:1743 %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.nxv8i32(1744 <vscale x 8 x i64> poison,1745 <vscale x 8 x i64> %1,1746 <vscale x 8 x i32> %0,1747 iXLen %2)1748 1749 ret <vscale x 8 x i64> %a1750}1751