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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {8; CHECK-LABEL: vwmacc_vv_nxv1i32:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma11; CHECK-NEXT: vwmacc.vv v10, v8, v912; CHECK-NEXT: vmv1r.v v8, v1013; CHECK-NEXT: ret14 %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>15 %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>16 17 %x = mul <vscale x 1 x i64> %vd, %ve18 %y = add <vscale x 1 x i64> %x, %vc19 ret <vscale x 1 x i64> %y20}21 22define <vscale x 1 x i64> @vwmacc_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {23; CHECK-LABEL: vwmacc_vx_nxv1i32:24; CHECK: # %bb.0:25; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma26; CHECK-NEXT: vwmacc.vx v9, a0, v827; CHECK-NEXT: vmv1r.v v8, v928; CHECK-NEXT: ret29 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 030 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer31 %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>32 %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>33 34 %x = mul <vscale x 1 x i64> %vd, %ve35 %y = add <vscale x 1 x i64> %x, %vc36 ret <vscale x 1 x i64> %y37}38 39define <vscale x 1 x i64> @vwmaccu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {40; CHECK-LABEL: vwmaccu_vv_nxv1i32:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma43; CHECK-NEXT: vwmaccu.vv v10, v8, v944; CHECK-NEXT: vmv1r.v v8, v1045; CHECK-NEXT: ret46 %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>47 %ve = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>48 49 %x = mul <vscale x 1 x i64> %vd, %ve50 %y = add <vscale x 1 x i64> %x, %vc51 ret <vscale x 1 x i64> %y52}53 54define <vscale x 1 x i64> @vwmaccu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {55; CHECK-LABEL: vwmaccu_vx_nxv1i32:56; CHECK: # %bb.0:57; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma58; CHECK-NEXT: vwmaccu.vx v9, a0, v859; CHECK-NEXT: vmv1r.v v8, v960; CHECK-NEXT: ret61 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 062 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer63 %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>64 %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>65 66 %x = mul <vscale x 1 x i64> %vd, %ve67 %y = add <vscale x 1 x i64> %x, %vc68 ret <vscale x 1 x i64> %y69}70 71define <vscale x 1 x i64> @vwmaccsu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {72; CHECK-LABEL: vwmaccsu_vv_nxv1i32:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma75; CHECK-NEXT: vwmaccsu.vv v10, v9, v876; CHECK-NEXT: vmv1r.v v8, v1077; CHECK-NEXT: ret78 %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>79 %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>80 81 %x = mul <vscale x 1 x i64> %vd, %ve82 %y = add <vscale x 1 x i64> %x, %vc83 ret <vscale x 1 x i64> %y84}85 86define <vscale x 1 x i64> @vwmaccsu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {87; CHECK-LABEL: vwmaccsu_vx_nxv1i32:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma90; CHECK-NEXT: vwmaccsu.vx v9, a0, v891; CHECK-NEXT: vmv1r.v v8, v992; CHECK-NEXT: ret93 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 094 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer95 %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>96 %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>97 98 %x = mul <vscale x 1 x i64> %vd, %ve99 %y = add <vscale x 1 x i64> %x, %vc100 ret <vscale x 1 x i64> %y101}102 103define <vscale x 1 x i64> @vwmaccus_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {104; CHECK-LABEL: vwmaccus_vx_nxv1i32:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma107; CHECK-NEXT: vwmaccus.vx v9, a0, v8108; CHECK-NEXT: vmv1r.v v8, v9109; CHECK-NEXT: ret110 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0111 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer112 %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>113 %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>114 115 %x = mul <vscale x 1 x i64> %vd, %ve116 %y = add <vscale x 1 x i64> %x, %vc117 ret <vscale x 1 x i64> %y118}119 120define <vscale x 2 x i64> @vwmacc_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {121; CHECK-LABEL: vwmacc_vv_nxv2i32:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma124; CHECK-NEXT: vwmacc.vv v10, v8, v9125; CHECK-NEXT: vmv2r.v v8, v10126; CHECK-NEXT: ret127 %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>128 %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>129 130 %x = mul <vscale x 2 x i64> %vd, %ve131 %y = add <vscale x 2 x i64> %x, %vc132 ret <vscale x 2 x i64> %y133}134 135define <vscale x 2 x i64> @vwmacc_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {136; CHECK-LABEL: vwmacc_vx_nxv2i32:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma139; CHECK-NEXT: vwmacc.vx v10, a0, v8140; CHECK-NEXT: vmv2r.v v8, v10141; CHECK-NEXT: ret142 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0143 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer144 %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>145 %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>146 147 %x = mul <vscale x 2 x i64> %vd, %ve148 %y = add <vscale x 2 x i64> %x, %vc149 ret <vscale x 2 x i64> %y150}151 152define <vscale x 2 x i64> @vwmaccu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {153; CHECK-LABEL: vwmaccu_vv_nxv2i32:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma156; CHECK-NEXT: vwmaccu.vv v10, v8, v9157; CHECK-NEXT: vmv2r.v v8, v10158; CHECK-NEXT: ret159 %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>160 %ve = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>161 162 %x = mul <vscale x 2 x i64> %vd, %ve163 %y = add <vscale x 2 x i64> %x, %vc164 ret <vscale x 2 x i64> %y165}166 167define <vscale x 2 x i64> @vwmaccu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {168; CHECK-LABEL: vwmaccu_vx_nxv2i32:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma171; CHECK-NEXT: vwmaccu.vx v10, a0, v8172; CHECK-NEXT: vmv2r.v v8, v10173; CHECK-NEXT: ret174 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0175 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer176 %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>177 %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>178 179 %x = mul <vscale x 2 x i64> %vd, %ve180 %y = add <vscale x 2 x i64> %x, %vc181 ret <vscale x 2 x i64> %y182}183 184define <vscale x 2 x i64> @vwmaccsu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {185; CHECK-LABEL: vwmaccsu_vv_nxv2i32:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma188; CHECK-NEXT: vwmaccsu.vv v10, v9, v8189; CHECK-NEXT: vmv2r.v v8, v10190; CHECK-NEXT: ret191 %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>192 %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>193 194 %x = mul <vscale x 2 x i64> %vd, %ve195 %y = add <vscale x 2 x i64> %x, %vc196 ret <vscale x 2 x i64> %y197}198 199define <vscale x 2 x i64> @vwmaccsu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {200; CHECK-LABEL: vwmaccsu_vx_nxv2i32:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma203; CHECK-NEXT: vwmaccsu.vx v10, a0, v8204; CHECK-NEXT: vmv2r.v v8, v10205; CHECK-NEXT: ret206 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0207 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer208 %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>209 %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>210 211 %x = mul <vscale x 2 x i64> %vd, %ve212 %y = add <vscale x 2 x i64> %x, %vc213 ret <vscale x 2 x i64> %y214}215 216define <vscale x 2 x i64> @vwmaccus_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {217; CHECK-LABEL: vwmaccus_vx_nxv2i32:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma220; CHECK-NEXT: vwmaccus.vx v10, a0, v8221; CHECK-NEXT: vmv2r.v v8, v10222; CHECK-NEXT: ret223 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0224 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer225 %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>226 %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>227 228 %x = mul <vscale x 2 x i64> %vd, %ve229 %y = add <vscale x 2 x i64> %x, %vc230 ret <vscale x 2 x i64> %y231}232 233define <vscale x 4 x i64> @vwmacc_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {234; CHECK-LABEL: vwmacc_vv_nxv4i32:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma237; CHECK-NEXT: vwmacc.vv v12, v8, v10238; CHECK-NEXT: vmv4r.v v8, v12239; CHECK-NEXT: ret240 %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>241 %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>242 243 %x = mul <vscale x 4 x i64> %vd, %ve244 %y = add <vscale x 4 x i64> %x, %vc245 ret <vscale x 4 x i64> %y246}247 248define <vscale x 4 x i64> @vwmacc_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {249; CHECK-LABEL: vwmacc_vx_nxv4i32:250; CHECK: # %bb.0:251; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma252; CHECK-NEXT: vwmacc.vx v12, a0, v8253; CHECK-NEXT: vmv4r.v v8, v12254; CHECK-NEXT: ret255 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0256 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer257 %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>258 %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>259 260 %x = mul <vscale x 4 x i64> %vd, %ve261 %y = add <vscale x 4 x i64> %x, %vc262 ret <vscale x 4 x i64> %y263}264 265define <vscale x 4 x i64> @vwmaccu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {266; CHECK-LABEL: vwmaccu_vv_nxv4i32:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma269; CHECK-NEXT: vwmaccu.vv v12, v8, v10270; CHECK-NEXT: vmv4r.v v8, v12271; CHECK-NEXT: ret272 %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>273 %ve = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>274 275 %x = mul <vscale x 4 x i64> %vd, %ve276 %y = add <vscale x 4 x i64> %x, %vc277 ret <vscale x 4 x i64> %y278}279 280define <vscale x 4 x i64> @vwmaccu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {281; CHECK-LABEL: vwmaccu_vx_nxv4i32:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma284; CHECK-NEXT: vwmaccu.vx v12, a0, v8285; CHECK-NEXT: vmv4r.v v8, v12286; CHECK-NEXT: ret287 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0288 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer289 %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>290 %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>291 292 %x = mul <vscale x 4 x i64> %vd, %ve293 %y = add <vscale x 4 x i64> %x, %vc294 ret <vscale x 4 x i64> %y295}296 297define <vscale x 4 x i64> @vwmaccsu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {298; CHECK-LABEL: vwmaccsu_vv_nxv4i32:299; CHECK: # %bb.0:300; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma301; CHECK-NEXT: vwmaccsu.vv v12, v10, v8302; CHECK-NEXT: vmv4r.v v8, v12303; CHECK-NEXT: ret304 %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>305 %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>306 307 %x = mul <vscale x 4 x i64> %vd, %ve308 %y = add <vscale x 4 x i64> %x, %vc309 ret <vscale x 4 x i64> %y310}311 312define <vscale x 4 x i64> @vwmaccsu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {313; CHECK-LABEL: vwmaccsu_vx_nxv4i32:314; CHECK: # %bb.0:315; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma316; CHECK-NEXT: vwmaccsu.vx v12, a0, v8317; CHECK-NEXT: vmv4r.v v8, v12318; CHECK-NEXT: ret319 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0320 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer321 %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>322 %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>323 324 %x = mul <vscale x 4 x i64> %vd, %ve325 %y = add <vscale x 4 x i64> %x, %vc326 ret <vscale x 4 x i64> %y327}328 329define <vscale x 4 x i64> @vwmaccus_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {330; CHECK-LABEL: vwmaccus_vx_nxv4i32:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma333; CHECK-NEXT: vwmaccus.vx v12, a0, v8334; CHECK-NEXT: vmv4r.v v8, v12335; CHECK-NEXT: ret336 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0337 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer338 %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>339 %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>340 341 %x = mul <vscale x 4 x i64> %vd, %ve342 %y = add <vscale x 4 x i64> %x, %vc343 ret <vscale x 4 x i64> %y344}345 346define <vscale x 8 x i64> @vwmacc_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {347; CHECK-LABEL: vwmacc_vv_nxv8i32:348; CHECK: # %bb.0:349; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma350; CHECK-NEXT: vwmacc.vv v16, v8, v12351; CHECK-NEXT: vmv8r.v v8, v16352; CHECK-NEXT: ret353 %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>354 %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>355 356 %x = mul <vscale x 8 x i64> %vd, %ve357 %y = add <vscale x 8 x i64> %x, %vc358 ret <vscale x 8 x i64> %y359}360 361define <vscale x 8 x i64> @vwmacc_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {362; CHECK-LABEL: vwmacc_vx_nxv8i32:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma365; CHECK-NEXT: vwmacc.vx v16, a0, v8366; CHECK-NEXT: vmv8r.v v8, v16367; CHECK-NEXT: ret368 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0369 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer370 %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>371 %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>372 373 %x = mul <vscale x 8 x i64> %vd, %ve374 %y = add <vscale x 8 x i64> %x, %vc375 ret <vscale x 8 x i64> %y376}377 378define <vscale x 8 x i64> @vwmaccu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {379; CHECK-LABEL: vwmaccu_vv_nxv8i32:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma382; CHECK-NEXT: vwmaccu.vv v16, v8, v12383; CHECK-NEXT: vmv8r.v v8, v16384; CHECK-NEXT: ret385 %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>386 %ve = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>387 388 %x = mul <vscale x 8 x i64> %vd, %ve389 %y = add <vscale x 8 x i64> %x, %vc390 ret <vscale x 8 x i64> %y391}392 393define <vscale x 8 x i64> @vwmaccu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {394; CHECK-LABEL: vwmaccu_vx_nxv8i32:395; CHECK: # %bb.0:396; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma397; CHECK-NEXT: vwmaccu.vx v16, a0, v8398; CHECK-NEXT: vmv8r.v v8, v16399; CHECK-NEXT: ret400 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0401 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer402 %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>403 %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>404 405 %x = mul <vscale x 8 x i64> %vd, %ve406 %y = add <vscale x 8 x i64> %x, %vc407 ret <vscale x 8 x i64> %y408}409 410define <vscale x 8 x i64> @vwmaccsu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {411; CHECK-LABEL: vwmaccsu_vv_nxv8i32:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma414; CHECK-NEXT: vwmaccsu.vv v16, v12, v8415; CHECK-NEXT: vmv8r.v v8, v16416; CHECK-NEXT: ret417 %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>418 %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>419 420 %x = mul <vscale x 8 x i64> %vd, %ve421 %y = add <vscale x 8 x i64> %x, %vc422 ret <vscale x 8 x i64> %y423}424 425define <vscale x 8 x i64> @vwmaccsu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {426; CHECK-LABEL: vwmaccsu_vx_nxv8i32:427; CHECK: # %bb.0:428; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma429; CHECK-NEXT: vwmaccsu.vx v16, a0, v8430; CHECK-NEXT: vmv8r.v v8, v16431; CHECK-NEXT: ret432 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0433 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer434 %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>435 %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>436 437 %x = mul <vscale x 8 x i64> %vd, %ve438 %y = add <vscale x 8 x i64> %x, %vc439 ret <vscale x 8 x i64> %y440}441 442define <vscale x 8 x i64> @vwmaccus_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {443; CHECK-LABEL: vwmaccus_vx_nxv8i32:444; CHECK: # %bb.0:445; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma446; CHECK-NEXT: vwmaccus.vx v16, a0, v8447; CHECK-NEXT: vmv8r.v v8, v16448; CHECK-NEXT: ret449 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0450 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer451 %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>452 %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>453 454 %x = mul <vscale x 8 x i64> %vd, %ve455 %y = add <vscale x 8 x i64> %x, %vc456 ret <vscale x 8 x i64> %y457}458