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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i16> @intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, ma11; CHECK-NEXT: vwmaccus.vx v8, a0, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8(15 <vscale x 1 x i16> %0,16 i8 %1,17 <vscale x 1 x i8> %2,18 iXLen %3, iXLen 0)19 20 ret <vscale x 1 x i16> %a21}22 23define <vscale x 1 x i16> @intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a1, e8, mf8, tu, mu27; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(31 <vscale x 1 x i16> %0,32 i8 %1,33 <vscale x 1 x i8> %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 0)36 37 ret <vscale x 1 x i16> %a38}39 40define <vscale x 2 x i16> @intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {41; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, ma44; CHECK-NEXT: vwmaccus.vx v8, a0, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8(48 <vscale x 2 x i16> %0,49 i8 %1,50 <vscale x 2 x i8> %2,51 iXLen %3, iXLen 0)52 53 ret <vscale x 2 x i16> %a54}55 56define <vscale x 2 x i16> @intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, mu60; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(64 <vscale x 2 x i16> %0,65 i8 %1,66 <vscale x 2 x i8> %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 0)69 70 ret <vscale x 2 x i16> %a71}72 73define <vscale x 4 x i16> @intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {74; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma77; CHECK-NEXT: vwmaccus.vx v8, a0, v978; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8(81 <vscale x 4 x i16> %0,82 i8 %1,83 <vscale x 4 x i8> %2,84 iXLen %3, iXLen 0)85 86 ret <vscale x 4 x i16> %a87}88 89define <vscale x 4 x i16> @intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, mu93; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(97 <vscale x 4 x i16> %0,98 i8 %1,99 <vscale x 4 x i8> %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 0)102 103 ret <vscale x 4 x i16> %a104}105 106define <vscale x 8 x i16> @intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {107; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma110; CHECK-NEXT: vwmaccus.vx v8, a0, v10111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8(114 <vscale x 8 x i16> %0,115 i8 %1,116 <vscale x 8 x i8> %2,117 iXLen %3, iXLen 0)118 119 ret <vscale x 8 x i16> %a120}121 122define <vscale x 8 x i16> @intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, mu126; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(130 <vscale x 8 x i16> %0,131 i8 %1,132 <vscale x 8 x i8> %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 0)135 136 ret <vscale x 8 x i16> %a137}138 139define <vscale x 16 x i16> @intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {140; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, ma143; CHECK-NEXT: vwmaccus.vx v8, a0, v12144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8(147 <vscale x 16 x i16> %0,148 i8 %1,149 <vscale x 16 x i8> %2,150 iXLen %3, iXLen 0)151 152 ret <vscale x 16 x i16> %a153}154 155define <vscale x 16 x i16> @intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a1, e8, m2, tu, mu159; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(163 <vscale x 16 x i16> %0,164 i8 %1,165 <vscale x 16 x i8> %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 0)168 169 ret <vscale x 16 x i16> %a170}171 172define <vscale x 32 x i16> @intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {173; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, ma176; CHECK-NEXT: vwmaccus.vx v8, a0, v16177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8(180 <vscale x 32 x i16> %0,181 i8 %1,182 <vscale x 32 x i8> %2,183 iXLen %3, iXLen 0)184 185 ret <vscale x 32 x i16> %a186}187 188define <vscale x 32 x i16> @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a1, e8, m4, tu, mu192; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(196 <vscale x 32 x i16> %0,197 i8 %1,198 <vscale x 32 x i8> %2,199 <vscale x 32 x i1> %3,200 iXLen %4, iXLen 0)201 202 ret <vscale x 32 x i16> %a203}204 205define <vscale x 1 x i32> @intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma209; CHECK-NEXT: vwmaccus.vx v8, a0, v9210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16(213 <vscale x 1 x i32> %0,214 i16 %1,215 <vscale x 1 x i16> %2,216 iXLen %3, iXLen 0)217 218 ret <vscale x 1 x i32> %a219}220 221define <vscale x 1 x i32> @intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, mu225; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(229 <vscale x 1 x i32> %0,230 i16 %1,231 <vscale x 1 x i16> %2,232 <vscale x 1 x i1> %3,233 iXLen %4, iXLen 0)234 235 ret <vscale x 1 x i32> %a236}237 238define <vscale x 2 x i32> @intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {239; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma242; CHECK-NEXT: vwmaccus.vx v8, a0, v9243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16(246 <vscale x 2 x i32> %0,247 i16 %1,248 <vscale x 2 x i16> %2,249 iXLen %3, iXLen 0)250 251 ret <vscale x 2 x i32> %a252}253 254define <vscale x 2 x i32> @intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, mu258; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(262 <vscale x 2 x i32> %0,263 i16 %1,264 <vscale x 2 x i16> %2,265 <vscale x 2 x i1> %3,266 iXLen %4, iXLen 0)267 268 ret <vscale x 2 x i32> %a269}270 271define <vscale x 4 x i32> @intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {272; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma275; CHECK-NEXT: vwmaccus.vx v8, a0, v10276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(279 <vscale x 4 x i32> %0,280 i16 %1,281 <vscale x 4 x i16> %2,282 iXLen %3, iXLen 0)283 284 ret <vscale x 4 x i32> %a285}286 287define <vscale x 4 x i32> @intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, mu291; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(295 <vscale x 4 x i32> %0,296 i16 %1,297 <vscale x 4 x i16> %2,298 <vscale x 4 x i1> %3,299 iXLen %4, iXLen 0)300 301 ret <vscale x 4 x i32> %a302}303 304define <vscale x 8 x i32> @intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {305; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, ma308; CHECK-NEXT: vwmaccus.vx v8, a0, v12309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16(312 <vscale x 8 x i32> %0,313 i16 %1,314 <vscale x 8 x i16> %2,315 iXLen %3, iXLen 0)316 317 ret <vscale x 8 x i32> %a318}319 320define <vscale x 8 x i32> @intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a1, e16, m2, tu, mu324; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(328 <vscale x 8 x i32> %0,329 i16 %1,330 <vscale x 8 x i16> %2,331 <vscale x 8 x i1> %3,332 iXLen %4, iXLen 0)333 334 ret <vscale x 8 x i32> %a335}336 337define <vscale x 16 x i32> @intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {338; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, ma341; CHECK-NEXT: vwmaccus.vx v8, a0, v16342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16(345 <vscale x 16 x i32> %0,346 i16 %1,347 <vscale x 16 x i16> %2,348 iXLen %3, iXLen 0)349 350 ret <vscale x 16 x i32> %a351}352 353define <vscale x 16 x i32> @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a1, e16, m4, tu, mu357; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(361 <vscale x 16 x i32> %0,362 i16 %1,363 <vscale x 16 x i16> %2,364 <vscale x 16 x i1> %3,365 iXLen %4, iXLen 0)366 367 ret <vscale x 16 x i32> %a368}369 370define <vscale x 1 x i64> @intrinsic_vwmaccus_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {371; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i64_i32_nxv1i32:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma374; CHECK-NEXT: vwmaccus.vx v8, a0, v9375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32(378 <vscale x 1 x i64> %0,379 i32 %1,380 <vscale x 1 x i32> %2,381 iXLen %3, iXLen 0)382 383 ret <vscale x 1 x i64> %a384}385 386define <vscale x 1 x i64> @intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu390; CHECK-NEXT: vwmaccus.vx v8, a0, v9, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32(394 <vscale x 1 x i64> %0,395 i32 %1,396 <vscale x 1 x i32> %2,397 <vscale x 1 x i1> %3,398 iXLen %4, iXLen 0)399 400 ret <vscale x 1 x i64> %a401}402 403define <vscale x 2 x i64> @intrinsic_vwmaccus_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {404; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i64_i32_nxv2i32:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma407; CHECK-NEXT: vwmaccus.vx v8, a0, v10408; CHECK-NEXT: ret409entry:410 %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32(411 <vscale x 2 x i64> %0,412 i32 %1,413 <vscale x 2 x i32> %2,414 iXLen %3, iXLen 0)415 416 ret <vscale x 2 x i64> %a417}418 419define <vscale x 2 x i64> @intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu423; CHECK-NEXT: vwmaccus.vx v8, a0, v10, v0.t424; CHECK-NEXT: ret425entry:426 %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32(427 <vscale x 2 x i64> %0,428 i32 %1,429 <vscale x 2 x i32> %2,430 <vscale x 2 x i1> %3,431 iXLen %4, iXLen 0)432 433 ret <vscale x 2 x i64> %a434}435 436define <vscale x 4 x i64> @intrinsic_vwmaccus_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {437; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i64_i32_nxv4i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma440; CHECK-NEXT: vwmaccus.vx v8, a0, v12441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32(444 <vscale x 4 x i64> %0,445 i32 %1,446 <vscale x 4 x i32> %2,447 iXLen %3, iXLen 0)448 449 ret <vscale x 4 x i64> %a450}451 452define <vscale x 4 x i64> @intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu456; CHECK-NEXT: vwmaccus.vx v8, a0, v12, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32(460 <vscale x 4 x i64> %0,461 i32 %1,462 <vscale x 4 x i32> %2,463 <vscale x 4 x i1> %3,464 iXLen %4, iXLen 0)465 466 ret <vscale x 4 x i64> %a467}468 469define <vscale x 8 x i64> @intrinsic_vwmaccus_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {470; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i64_i32_nxv8i32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma473; CHECK-NEXT: vwmaccus.vx v8, a0, v16474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32(477 <vscale x 8 x i64> %0,478 i32 %1,479 <vscale x 8 x i32> %2,480 iXLen %3, iXLen 0)481 482 ret <vscale x 8 x i64> %a483}484 485define <vscale x 8 x i64> @intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu489; CHECK-NEXT: vwmaccus.vx v8, a0, v16, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32(493 <vscale x 8 x i64> %0,494 i32 %1,495 <vscale x 8 x i32> %2,496 <vscale x 8 x i1> %3,497 iXLen %4, iXLen 0)498 499 ret <vscale x 8 x i64> %a500}501