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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i64> @vwmul_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {6; CHECK-LABEL: vwmul_vv_nxv1i64_nxv1i32:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma9; CHECK-NEXT: vwmul.vv v10, v8, v910; CHECK-NEXT: vmv1r.v v8, v1011; CHECK-NEXT: ret12 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>13 %vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>14 %ve = mul <vscale x 1 x i64> %vc, %vd15 ret <vscale x 1 x i64> %ve16}17 18define <vscale x 1 x i64> @vwmulu_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {19; CHECK-LABEL: vwmulu_vv_nxv1i64_nxv1i32:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma22; CHECK-NEXT: vwmulu.vv v10, v8, v923; CHECK-NEXT: vmv1r.v v8, v1024; CHECK-NEXT: ret25 %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>26 %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>27 %ve = mul <vscale x 1 x i64> %vc, %vd28 ret <vscale x 1 x i64> %ve29}30 31define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {32; CHECK-LABEL: vwmulsu_vv_nxv1i64_nxv1i32:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma35; CHECK-NEXT: vwmulsu.vv v10, v8, v936; CHECK-NEXT: vmv1r.v v8, v1037; CHECK-NEXT: ret38 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>39 %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>40 %ve = mul <vscale x 1 x i64> %vc, %vd41 ret <vscale x 1 x i64> %ve42}43 44define <vscale x 1 x i64> @vwmul_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {45; CHECK-LABEL: vwmul_vx_nxv1i64_nxv1i32:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma48; CHECK-NEXT: vwmul.vx v9, v8, a049; CHECK-NEXT: vmv1r.v v8, v950; CHECK-NEXT: ret51 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 052 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer53 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>54 %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>55 %ve = mul <vscale x 1 x i64> %vc, %vd56 ret <vscale x 1 x i64> %ve57}58 59define <vscale x 1 x i64> @vwmulu_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {60; CHECK-LABEL: vwmulu_vx_nxv1i64_nxv1i32:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma63; CHECK-NEXT: vwmulu.vx v9, v8, a064; CHECK-NEXT: vmv1r.v v8, v965; CHECK-NEXT: ret66 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 067 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer68 %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>69 %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>70 %ve = mul <vscale x 1 x i64> %vc, %vd71 ret <vscale x 1 x i64> %ve72}73 74define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {75; CHECK-LABEL: vwmulsu_vx_nxv1i64_nxv1i32:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma78; CHECK-NEXT: vwmulsu.vx v9, v8, a079; CHECK-NEXT: vmv1r.v v8, v980; CHECK-NEXT: ret81 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 082 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer83 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>84 %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>85 %ve = mul <vscale x 1 x i64> %vc, %vd86 ret <vscale x 1 x i64> %ve87}88 89define <vscale x 2 x i64> @vwmul_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {90; CHECK-LABEL: vwmul_vv_nxv2i64_nxv2i32:91; CHECK: # %bb.0:92; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma93; CHECK-NEXT: vmv1r.v v10, v994; CHECK-NEXT: vmv1r.v v11, v895; CHECK-NEXT: vwmul.vv v8, v11, v1096; CHECK-NEXT: ret97 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>98 %vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>99 %ve = mul <vscale x 2 x i64> %vc, %vd100 ret <vscale x 2 x i64> %ve101}102 103define <vscale x 2 x i64> @vwmulu_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {104; CHECK-LABEL: vwmulu_vv_nxv2i64_nxv2i32:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma107; CHECK-NEXT: vmv1r.v v10, v9108; CHECK-NEXT: vmv1r.v v11, v8109; CHECK-NEXT: vwmulu.vv v8, v11, v10110; CHECK-NEXT: ret111 %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>112 %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>113 %ve = mul <vscale x 2 x i64> %vc, %vd114 ret <vscale x 2 x i64> %ve115}116 117define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {118; CHECK-LABEL: vwmulsu_vv_nxv2i64_nxv2i32:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma121; CHECK-NEXT: vmv1r.v v10, v9122; CHECK-NEXT: vmv1r.v v11, v8123; CHECK-NEXT: vwmulsu.vv v8, v11, v10124; CHECK-NEXT: ret125 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>126 %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>127 %ve = mul <vscale x 2 x i64> %vc, %vd128 ret <vscale x 2 x i64> %ve129}130 131define <vscale x 2 x i64> @vwmul_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {132; CHECK-LABEL: vwmul_vx_nxv2i64_nxv2i32:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma135; CHECK-NEXT: vmv1r.v v10, v8136; CHECK-NEXT: vwmul.vx v8, v10, a0137; CHECK-NEXT: ret138 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0139 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer140 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>141 %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>142 %ve = mul <vscale x 2 x i64> %vc, %vd143 ret <vscale x 2 x i64> %ve144}145 146define <vscale x 2 x i64> @vwmulu_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {147; CHECK-LABEL: vwmulu_vx_nxv2i64_nxv2i32:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma150; CHECK-NEXT: vmv1r.v v10, v8151; CHECK-NEXT: vwmulu.vx v8, v10, a0152; CHECK-NEXT: ret153 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0154 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer155 %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>156 %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>157 %ve = mul <vscale x 2 x i64> %vc, %vd158 ret <vscale x 2 x i64> %ve159}160 161define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {162; CHECK-LABEL: vwmulsu_vx_nxv2i64_nxv2i32:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma165; CHECK-NEXT: vmv1r.v v10, v8166; CHECK-NEXT: vwmulsu.vx v8, v10, a0167; CHECK-NEXT: ret168 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0169 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer170 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>171 %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>172 %ve = mul <vscale x 2 x i64> %vc, %vd173 ret <vscale x 2 x i64> %ve174}175 176define <vscale x 4 x i64> @vwmul_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {177; CHECK-LABEL: vwmul_vv_nxv4i64_nxv4i32:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma180; CHECK-NEXT: vmv2r.v v12, v10181; CHECK-NEXT: vmv2r.v v14, v8182; CHECK-NEXT: vwmul.vv v8, v14, v12183; CHECK-NEXT: ret184 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>185 %vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>186 %ve = mul <vscale x 4 x i64> %vc, %vd187 ret <vscale x 4 x i64> %ve188}189 190define <vscale x 4 x i64> @vwmulu_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {191; CHECK-LABEL: vwmulu_vv_nxv4i64_nxv4i32:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma194; CHECK-NEXT: vmv2r.v v12, v10195; CHECK-NEXT: vmv2r.v v14, v8196; CHECK-NEXT: vwmulu.vv v8, v14, v12197; CHECK-NEXT: ret198 %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>199 %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>200 %ve = mul <vscale x 4 x i64> %vc, %vd201 ret <vscale x 4 x i64> %ve202}203 204define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {205; CHECK-LABEL: vwmulsu_vv_nxv4i64_nxv4i32:206; CHECK: # %bb.0:207; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma208; CHECK-NEXT: vmv2r.v v12, v10209; CHECK-NEXT: vmv2r.v v14, v8210; CHECK-NEXT: vwmulsu.vv v8, v14, v12211; CHECK-NEXT: ret212 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>213 %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>214 %ve = mul <vscale x 4 x i64> %vc, %vd215 ret <vscale x 4 x i64> %ve216}217 218define <vscale x 4 x i64> @vwmul_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {219; CHECK-LABEL: vwmul_vx_nxv4i64_nxv4i32:220; CHECK: # %bb.0:221; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma222; CHECK-NEXT: vmv2r.v v12, v8223; CHECK-NEXT: vwmul.vx v8, v12, a0224; CHECK-NEXT: ret225 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0226 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer227 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>228 %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>229 %ve = mul <vscale x 4 x i64> %vc, %vd230 ret <vscale x 4 x i64> %ve231}232 233define <vscale x 4 x i64> @vwmulu_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {234; CHECK-LABEL: vwmulu_vx_nxv4i64_nxv4i32:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma237; CHECK-NEXT: vmv2r.v v12, v8238; CHECK-NEXT: vwmulu.vx v8, v12, a0239; CHECK-NEXT: ret240 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0241 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer242 %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>243 %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>244 %ve = mul <vscale x 4 x i64> %vc, %vd245 ret <vscale x 4 x i64> %ve246}247 248define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {249; CHECK-LABEL: vwmulsu_vx_nxv4i64_nxv4i32:250; CHECK: # %bb.0:251; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma252; CHECK-NEXT: vmv2r.v v12, v8253; CHECK-NEXT: vwmulsu.vx v8, v12, a0254; CHECK-NEXT: ret255 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0256 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer257 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>258 %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>259 %ve = mul <vscale x 4 x i64> %vc, %vd260 ret <vscale x 4 x i64> %ve261}262 263define <vscale x 8 x i64> @vwmul_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {264; CHECK-LABEL: vwmul_vv_nxv8i64_nxv8i32:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma267; CHECK-NEXT: vmv4r.v v16, v12268; CHECK-NEXT: vmv4r.v v20, v8269; CHECK-NEXT: vwmul.vv v8, v20, v16270; CHECK-NEXT: ret271 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>272 %vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>273 %ve = mul <vscale x 8 x i64> %vc, %vd274 ret <vscale x 8 x i64> %ve275}276 277define <vscale x 8 x i64> @vwmulu_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {278; CHECK-LABEL: vwmulu_vv_nxv8i64_nxv8i32:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma281; CHECK-NEXT: vmv4r.v v16, v12282; CHECK-NEXT: vmv4r.v v20, v8283; CHECK-NEXT: vwmulu.vv v8, v20, v16284; CHECK-NEXT: ret285 %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>286 %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>287 %ve = mul <vscale x 8 x i64> %vc, %vd288 ret <vscale x 8 x i64> %ve289}290 291define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {292; CHECK-LABEL: vwmulsu_vv_nxv8i64_nxv8i32:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma295; CHECK-NEXT: vmv4r.v v16, v12296; CHECK-NEXT: vmv4r.v v20, v8297; CHECK-NEXT: vwmulsu.vv v8, v20, v16298; CHECK-NEXT: ret299 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>300 %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>301 %ve = mul <vscale x 8 x i64> %vc, %vd302 ret <vscale x 8 x i64> %ve303}304 305define <vscale x 8 x i64> @vwmul_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {306; CHECK-LABEL: vwmul_vx_nxv8i64_nxv8i32:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma309; CHECK-NEXT: vmv4r.v v16, v8310; CHECK-NEXT: vwmul.vx v8, v16, a0311; CHECK-NEXT: ret312 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0313 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer314 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>315 %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>316 %ve = mul <vscale x 8 x i64> %vc, %vd317 ret <vscale x 8 x i64> %ve318}319 320define <vscale x 8 x i64> @vwmulu_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {321; CHECK-LABEL: vwmulu_vx_nxv8i64_nxv8i32:322; CHECK: # %bb.0:323; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma324; CHECK-NEXT: vmv4r.v v16, v8325; CHECK-NEXT: vwmulu.vx v8, v16, a0326; CHECK-NEXT: ret327 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0328 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer329 %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>330 %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>331 %ve = mul <vscale x 8 x i64> %vc, %vd332 ret <vscale x 8 x i64> %ve333}334 335define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {336; CHECK-LABEL: vwmulsu_vx_nxv8i64_nxv8i32:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma339; CHECK-NEXT: vmv4r.v v16, v8340; CHECK-NEXT: vwmulsu.vx v8, v16, a0341; CHECK-NEXT: ret342 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0343 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer344 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>345 %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>346 %ve = mul <vscale x 8 x i64> %vc, %vd347 ret <vscale x 8 x i64> %ve348}349 350define <vscale x 1 x i64> @vwmul_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {351; CHECK-LABEL: vwmul_vv_nxv1i64_nxv1i16:352; CHECK: # %bb.0:353; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma354; CHECK-NEXT: vsext.vf2 v10, v8355; CHECK-NEXT: vsext.vf2 v11, v9356; CHECK-NEXT: vwmul.vv v8, v10, v11357; CHECK-NEXT: ret358 %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>359 %vd = sext <vscale x 1 x i16> %vb to <vscale x 1 x i64>360 %ve = mul <vscale x 1 x i64> %vc, %vd361 ret <vscale x 1 x i64> %ve362}363 364define <vscale x 1 x i64> @vwmulu_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {365; CHECK-LABEL: vwmulu_vv_nxv1i64_nxv1i16:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma368; CHECK-NEXT: vwmulu.vv v10, v8, v9369; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma370; CHECK-NEXT: vzext.vf2 v8, v10371; CHECK-NEXT: ret372 %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>373 %vd = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>374 %ve = mul <vscale x 1 x i64> %vc, %vd375 ret <vscale x 1 x i64> %ve376}377 378define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {379; CHECK-LABEL: vwmulsu_vv_nxv1i64_nxv1i16:380; CHECK: # %bb.0:381; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma382; CHECK-NEXT: vsext.vf2 v10, v8383; CHECK-NEXT: vzext.vf2 v11, v9384; CHECK-NEXT: vwmulsu.vv v8, v10, v11385; CHECK-NEXT: ret386 %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>387 %vd = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>388 %ve = mul <vscale x 1 x i64> %vc, %vd389 ret <vscale x 1 x i64> %ve390}391 392define <vscale x 1 x i64> @vwmul_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {393; CHECK-LABEL: vwmul_vx_nxv1i64_nxv1i16:394; CHECK: # %bb.0:395; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma396; CHECK-NEXT: vmv.v.x v9, a0397; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma398; CHECK-NEXT: vsext.vf2 v10, v8399; CHECK-NEXT: vsext.vf2 v11, v9400; CHECK-NEXT: vwmul.vv v8, v10, v11401; CHECK-NEXT: ret402 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0403 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer404 %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>405 %vd = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>406 %ve = mul <vscale x 1 x i64> %vc, %vd407 ret <vscale x 1 x i64> %ve408}409 410define <vscale x 1 x i64> @vwmulu_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {411; CHECK-LABEL: vwmulu_vx_nxv1i64_nxv1i16:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma414; CHECK-NEXT: vwmulu.vx v9, v8, a0415; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma416; CHECK-NEXT: vzext.vf2 v8, v9417; CHECK-NEXT: ret418 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0419 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer420 %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>421 %vd = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>422 %ve = mul <vscale x 1 x i64> %vc, %vd423 ret <vscale x 1 x i64> %ve424}425 426define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {427; CHECK-LABEL: vwmulsu_vx_nxv1i64_nxv1i16:428; CHECK: # %bb.0:429; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma430; CHECK-NEXT: vmv.v.x v9, a0431; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma432; CHECK-NEXT: vsext.vf2 v10, v8433; CHECK-NEXT: vzext.vf2 v11, v9434; CHECK-NEXT: vwmulsu.vv v8, v10, v11435; CHECK-NEXT: ret436 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0437 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer438 %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>439 %vd = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>440 %ve = mul <vscale x 1 x i64> %vc, %vd441 ret <vscale x 1 x i64> %ve442}443 444define <vscale x 2 x i64> @vwmul_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {445; CHECK-LABEL: vwmul_vv_nxv2i64_nxv2i16:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma448; CHECK-NEXT: vsext.vf2 v10, v8449; CHECK-NEXT: vsext.vf2 v11, v9450; CHECK-NEXT: vwmul.vv v8, v10, v11451; CHECK-NEXT: ret452 %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>453 %vd = sext <vscale x 2 x i16> %vb to <vscale x 2 x i64>454 %ve = mul <vscale x 2 x i64> %vc, %vd455 ret <vscale x 2 x i64> %ve456}457 458define <vscale x 2 x i64> @vwmulu_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {459; CHECK-LABEL: vwmulu_vv_nxv2i64_nxv2i16:460; CHECK: # %bb.0:461; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma462; CHECK-NEXT: vwmulu.vv v10, v8, v9463; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma464; CHECK-NEXT: vzext.vf2 v8, v10465; CHECK-NEXT: ret466 %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>467 %vd = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>468 %ve = mul <vscale x 2 x i64> %vc, %vd469 ret <vscale x 2 x i64> %ve470}471 472define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {473; CHECK-LABEL: vwmulsu_vv_nxv2i64_nxv2i16:474; CHECK: # %bb.0:475; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma476; CHECK-NEXT: vsext.vf2 v10, v8477; CHECK-NEXT: vzext.vf2 v11, v9478; CHECK-NEXT: vwmulsu.vv v8, v10, v11479; CHECK-NEXT: ret480 %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>481 %vd = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>482 %ve = mul <vscale x 2 x i64> %vc, %vd483 ret <vscale x 2 x i64> %ve484}485 486define <vscale x 2 x i64> @vwmul_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {487; CHECK-LABEL: vwmul_vx_nxv2i64_nxv2i16:488; CHECK: # %bb.0:489; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma490; CHECK-NEXT: vmv.v.x v9, a0491; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma492; CHECK-NEXT: vsext.vf2 v10, v8493; CHECK-NEXT: vsext.vf2 v11, v9494; CHECK-NEXT: vwmul.vv v8, v10, v11495; CHECK-NEXT: ret496 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0497 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer498 %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>499 %vd = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>500 %ve = mul <vscale x 2 x i64> %vc, %vd501 ret <vscale x 2 x i64> %ve502}503 504define <vscale x 2 x i64> @vwmulu_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {505; CHECK-LABEL: vwmulu_vx_nxv2i64_nxv2i16:506; CHECK: # %bb.0:507; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma508; CHECK-NEXT: vwmulu.vx v10, v8, a0509; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma510; CHECK-NEXT: vzext.vf2 v8, v10511; CHECK-NEXT: ret512 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0513 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer514 %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>515 %vd = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>516 %ve = mul <vscale x 2 x i64> %vc, %vd517 ret <vscale x 2 x i64> %ve518}519 520define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {521; CHECK-LABEL: vwmulsu_vx_nxv2i64_nxv2i16:522; CHECK: # %bb.0:523; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma524; CHECK-NEXT: vmv.v.x v9, a0525; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma526; CHECK-NEXT: vsext.vf2 v10, v8527; CHECK-NEXT: vzext.vf2 v11, v9528; CHECK-NEXT: vwmulsu.vv v8, v10, v11529; CHECK-NEXT: ret530 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0531 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer532 %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>533 %vd = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>534 %ve = mul <vscale x 2 x i64> %vc, %vd535 ret <vscale x 2 x i64> %ve536}537 538define <vscale x 4 x i64> @vwmul_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {539; CHECK-LABEL: vwmul_vv_nxv4i64_nxv4i16:540; CHECK: # %bb.0:541; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma542; CHECK-NEXT: vsext.vf2 v12, v8543; CHECK-NEXT: vsext.vf2 v14, v9544; CHECK-NEXT: vwmul.vv v8, v12, v14545; CHECK-NEXT: ret546 %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>547 %vd = sext <vscale x 4 x i16> %vb to <vscale x 4 x i64>548 %ve = mul <vscale x 4 x i64> %vc, %vd549 ret <vscale x 4 x i64> %ve550}551 552define <vscale x 4 x i64> @vwmulu_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {553; CHECK-LABEL: vwmulu_vv_nxv4i64_nxv4i16:554; CHECK: # %bb.0:555; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma556; CHECK-NEXT: vwmulu.vv v12, v8, v9557; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma558; CHECK-NEXT: vzext.vf2 v8, v12559; CHECK-NEXT: ret560 %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>561 %vd = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>562 %ve = mul <vscale x 4 x i64> %vc, %vd563 ret <vscale x 4 x i64> %ve564}565 566define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {567; CHECK-LABEL: vwmulsu_vv_nxv4i64_nxv4i16:568; CHECK: # %bb.0:569; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma570; CHECK-NEXT: vsext.vf2 v12, v8571; CHECK-NEXT: vzext.vf2 v14, v9572; CHECK-NEXT: vwmulsu.vv v8, v12, v14573; CHECK-NEXT: ret574 %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>575 %vd = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>576 %ve = mul <vscale x 4 x i64> %vc, %vd577 ret <vscale x 4 x i64> %ve578}579 580define <vscale x 4 x i64> @vwmul_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {581; CHECK-LABEL: vwmul_vx_nxv4i64_nxv4i16:582; CHECK: # %bb.0:583; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma584; CHECK-NEXT: vmv.v.x v9, a0585; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma586; CHECK-NEXT: vsext.vf2 v12, v8587; CHECK-NEXT: vsext.vf2 v14, v9588; CHECK-NEXT: vwmul.vv v8, v12, v14589; CHECK-NEXT: ret590 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0591 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer592 %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>593 %vd = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>594 %ve = mul <vscale x 4 x i64> %vc, %vd595 ret <vscale x 4 x i64> %ve596}597 598define <vscale x 4 x i64> @vwmulu_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {599; CHECK-LABEL: vwmulu_vx_nxv4i64_nxv4i16:600; CHECK: # %bb.0:601; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma602; CHECK-NEXT: vwmulu.vx v12, v8, a0603; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma604; CHECK-NEXT: vzext.vf2 v8, v12605; CHECK-NEXT: ret606 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0607 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer608 %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>609 %vd = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>610 %ve = mul <vscale x 4 x i64> %vc, %vd611 ret <vscale x 4 x i64> %ve612}613 614define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {615; CHECK-LABEL: vwmulsu_vx_nxv4i64_nxv4i16:616; CHECK: # %bb.0:617; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma618; CHECK-NEXT: vmv.v.x v9, a0619; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma620; CHECK-NEXT: vsext.vf2 v12, v8621; CHECK-NEXT: vzext.vf2 v14, v9622; CHECK-NEXT: vwmulsu.vv v8, v12, v14623; CHECK-NEXT: ret624 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0625 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer626 %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>627 %vd = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>628 %ve = mul <vscale x 4 x i64> %vc, %vd629 ret <vscale x 4 x i64> %ve630}631 632define <vscale x 8 x i64> @vwmul_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {633; CHECK-LABEL: vwmul_vv_nxv8i64_nxv8i16:634; CHECK: # %bb.0:635; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma636; CHECK-NEXT: vsext.vf2 v16, v8637; CHECK-NEXT: vsext.vf2 v20, v10638; CHECK-NEXT: vwmul.vv v8, v16, v20639; CHECK-NEXT: ret640 %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>641 %vd = sext <vscale x 8 x i16> %vb to <vscale x 8 x i64>642 %ve = mul <vscale x 8 x i64> %vc, %vd643 ret <vscale x 8 x i64> %ve644}645 646define <vscale x 8 x i64> @vwmulu_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {647; CHECK-LABEL: vwmulu_vv_nxv8i64_nxv8i16:648; CHECK: # %bb.0:649; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma650; CHECK-NEXT: vwmulu.vv v16, v8, v10651; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma652; CHECK-NEXT: vzext.vf2 v8, v16653; CHECK-NEXT: ret654 %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>655 %vd = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>656 %ve = mul <vscale x 8 x i64> %vc, %vd657 ret <vscale x 8 x i64> %ve658}659 660define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {661; CHECK-LABEL: vwmulsu_vv_nxv8i64_nxv8i16:662; CHECK: # %bb.0:663; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma664; CHECK-NEXT: vsext.vf2 v16, v8665; CHECK-NEXT: vzext.vf2 v20, v10666; CHECK-NEXT: vwmulsu.vv v8, v16, v20667; CHECK-NEXT: ret668 %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>669 %vd = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>670 %ve = mul <vscale x 8 x i64> %vc, %vd671 ret <vscale x 8 x i64> %ve672}673 674define <vscale x 8 x i64> @vwmul_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {675; CHECK-LABEL: vwmul_vx_nxv8i64_nxv8i16:676; CHECK: # %bb.0:677; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma678; CHECK-NEXT: vmv.v.x v10, a0679; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma680; CHECK-NEXT: vsext.vf2 v16, v8681; CHECK-NEXT: vsext.vf2 v20, v10682; CHECK-NEXT: vwmul.vv v8, v16, v20683; CHECK-NEXT: ret684 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0685 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer686 %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>687 %vd = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>688 %ve = mul <vscale x 8 x i64> %vc, %vd689 ret <vscale x 8 x i64> %ve690}691 692define <vscale x 8 x i64> @vwmulu_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {693; CHECK-LABEL: vwmulu_vx_nxv8i64_nxv8i16:694; CHECK: # %bb.0:695; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma696; CHECK-NEXT: vwmulu.vx v16, v8, a0697; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma698; CHECK-NEXT: vzext.vf2 v8, v16699; CHECK-NEXT: ret700 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0701 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer702 %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>703 %vd = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>704 %ve = mul <vscale x 8 x i64> %vc, %vd705 ret <vscale x 8 x i64> %ve706}707 708define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {709; CHECK-LABEL: vwmulsu_vx_nxv8i64_nxv8i16:710; CHECK: # %bb.0:711; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma712; CHECK-NEXT: vmv.v.x v10, a0713; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma714; CHECK-NEXT: vsext.vf2 v16, v8715; CHECK-NEXT: vzext.vf2 v20, v10716; CHECK-NEXT: vwmulsu.vv v8, v16, v20717; CHECK-NEXT: ret718 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0719 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer720 %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>721 %vd = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>722 %ve = mul <vscale x 8 x i64> %vc, %vd723 ret <vscale x 8 x i64> %ve724}725 726define <vscale x 1 x i64> @vwmul_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {727; CHECK-LABEL: vwmul_vv_nxv1i64_nxv1i8:728; CHECK: # %bb.0:729; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma730; CHECK-NEXT: vsext.vf4 v10, v8731; CHECK-NEXT: vsext.vf4 v11, v9732; CHECK-NEXT: vwmul.vv v8, v10, v11733; CHECK-NEXT: ret734 %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>735 %vd = sext <vscale x 1 x i8> %vb to <vscale x 1 x i64>736 %ve = mul <vscale x 1 x i64> %vc, %vd737 ret <vscale x 1 x i64> %ve738}739 740define <vscale x 1 x i64> @vwmulu_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {741; CHECK-LABEL: vwmulu_vv_nxv1i64_nxv1i8:742; CHECK: # %bb.0:743; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma744; CHECK-NEXT: vwmulu.vv v10, v8, v9745; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma746; CHECK-NEXT: vzext.vf4 v8, v10747; CHECK-NEXT: ret748 %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>749 %vd = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>750 %ve = mul <vscale x 1 x i64> %vc, %vd751 ret <vscale x 1 x i64> %ve752}753 754define <vscale x 1 x i64> @vwmulsu_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {755; CHECK-LABEL: vwmulsu_vv_nxv1i64_nxv1i8:756; CHECK: # %bb.0:757; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma758; CHECK-NEXT: vsext.vf4 v10, v8759; CHECK-NEXT: vzext.vf4 v11, v9760; CHECK-NEXT: vwmulsu.vv v8, v10, v11761; CHECK-NEXT: ret762 %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>763 %vd = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>764 %ve = mul <vscale x 1 x i64> %vc, %vd765 ret <vscale x 1 x i64> %ve766}767 768define <vscale x 1 x i64> @vwmul_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {769; CHECK-LABEL: vwmul_vx_nxv1i64_nxv1i8:770; CHECK: # %bb.0:771; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma772; CHECK-NEXT: vmv.v.x v9, a0773; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma774; CHECK-NEXT: vsext.vf4 v10, v8775; CHECK-NEXT: vsext.vf4 v11, v9776; CHECK-NEXT: vwmul.vv v8, v10, v11777; CHECK-NEXT: ret778 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0779 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer780 %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>781 %vd = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>782 %ve = mul <vscale x 1 x i64> %vc, %vd783 ret <vscale x 1 x i64> %ve784}785 786define <vscale x 1 x i64> @vwmulu_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {787; CHECK-LABEL: vwmulu_vx_nxv1i64_nxv1i8:788; CHECK: # %bb.0:789; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma790; CHECK-NEXT: vwmulu.vx v9, v8, a0791; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma792; CHECK-NEXT: vzext.vf4 v8, v9793; CHECK-NEXT: ret794 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0795 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer796 %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>797 %vd = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>798 %ve = mul <vscale x 1 x i64> %vc, %vd799 ret <vscale x 1 x i64> %ve800}801 802define <vscale x 1 x i64> @vwmulsu_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {803; CHECK-LABEL: vwmulsu_vx_nxv1i64_nxv1i8:804; CHECK: # %bb.0:805; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma806; CHECK-NEXT: vmv.v.x v9, a0807; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma808; CHECK-NEXT: vsext.vf4 v10, v8809; CHECK-NEXT: vzext.vf4 v11, v9810; CHECK-NEXT: vwmulsu.vv v8, v10, v11811; CHECK-NEXT: ret812 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0813 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer814 %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>815 %vd = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>816 %ve = mul <vscale x 1 x i64> %vc, %vd817 ret <vscale x 1 x i64> %ve818}819 820define <vscale x 2 x i64> @vwmul_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {821; CHECK-LABEL: vwmul_vv_nxv2i64_nxv2i8:822; CHECK: # %bb.0:823; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma824; CHECK-NEXT: vsext.vf4 v10, v8825; CHECK-NEXT: vsext.vf4 v11, v9826; CHECK-NEXT: vwmul.vv v8, v10, v11827; CHECK-NEXT: ret828 %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>829 %vd = sext <vscale x 2 x i8> %vb to <vscale x 2 x i64>830 %ve = mul <vscale x 2 x i64> %vc, %vd831 ret <vscale x 2 x i64> %ve832}833 834define <vscale x 2 x i64> @vwmulu_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {835; CHECK-LABEL: vwmulu_vv_nxv2i64_nxv2i8:836; CHECK: # %bb.0:837; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma838; CHECK-NEXT: vwmulu.vv v10, v8, v9839; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma840; CHECK-NEXT: vzext.vf4 v8, v10841; CHECK-NEXT: ret842 %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>843 %vd = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>844 %ve = mul <vscale x 2 x i64> %vc, %vd845 ret <vscale x 2 x i64> %ve846}847 848define <vscale x 2 x i64> @vwmulsu_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {849; CHECK-LABEL: vwmulsu_vv_nxv2i64_nxv2i8:850; CHECK: # %bb.0:851; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma852; CHECK-NEXT: vsext.vf4 v10, v8853; CHECK-NEXT: vzext.vf4 v11, v9854; CHECK-NEXT: vwmulsu.vv v8, v10, v11855; CHECK-NEXT: ret856 %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>857 %vd = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>858 %ve = mul <vscale x 2 x i64> %vc, %vd859 ret <vscale x 2 x i64> %ve860}861 862define <vscale x 2 x i64> @vwmul_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {863; CHECK-LABEL: vwmul_vx_nxv2i64_nxv2i8:864; CHECK: # %bb.0:865; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma866; CHECK-NEXT: vmv.v.x v9, a0867; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma868; CHECK-NEXT: vsext.vf4 v10, v8869; CHECK-NEXT: vsext.vf4 v11, v9870; CHECK-NEXT: vwmul.vv v8, v10, v11871; CHECK-NEXT: ret872 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 0873 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer874 %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>875 %vd = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>876 %ve = mul <vscale x 2 x i64> %vc, %vd877 ret <vscale x 2 x i64> %ve878}879 880define <vscale x 2 x i64> @vwmulu_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {881; CHECK-LABEL: vwmulu_vx_nxv2i64_nxv2i8:882; CHECK: # %bb.0:883; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma884; CHECK-NEXT: vwmulu.vx v10, v8, a0885; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma886; CHECK-NEXT: vzext.vf4 v8, v10887; CHECK-NEXT: ret888 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 0889 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer890 %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>891 %vd = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>892 %ve = mul <vscale x 2 x i64> %vc, %vd893 ret <vscale x 2 x i64> %ve894}895 896define <vscale x 2 x i64> @vwmulsu_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {897; CHECK-LABEL: vwmulsu_vx_nxv2i64_nxv2i8:898; CHECK: # %bb.0:899; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma900; CHECK-NEXT: vmv.v.x v9, a0901; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma902; CHECK-NEXT: vsext.vf4 v10, v8903; CHECK-NEXT: vzext.vf4 v11, v9904; CHECK-NEXT: vwmulsu.vv v8, v10, v11905; CHECK-NEXT: ret906 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 0907 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer908 %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>909 %vd = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>910 %ve = mul <vscale x 2 x i64> %vc, %vd911 ret <vscale x 2 x i64> %ve912}913 914define <vscale x 4 x i64> @vwmul_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {915; CHECK-LABEL: vwmul_vv_nxv4i64_nxv4i8:916; CHECK: # %bb.0:917; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma918; CHECK-NEXT: vsext.vf4 v12, v8919; CHECK-NEXT: vsext.vf4 v14, v9920; CHECK-NEXT: vwmul.vv v8, v12, v14921; CHECK-NEXT: ret922 %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>923 %vd = sext <vscale x 4 x i8> %vb to <vscale x 4 x i64>924 %ve = mul <vscale x 4 x i64> %vc, %vd925 ret <vscale x 4 x i64> %ve926}927 928define <vscale x 4 x i64> @vwmulu_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {929; CHECK-LABEL: vwmulu_vv_nxv4i64_nxv4i8:930; CHECK: # %bb.0:931; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma932; CHECK-NEXT: vwmulu.vv v12, v8, v9933; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma934; CHECK-NEXT: vzext.vf4 v8, v12935; CHECK-NEXT: ret936 %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>937 %vd = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>938 %ve = mul <vscale x 4 x i64> %vc, %vd939 ret <vscale x 4 x i64> %ve940}941 942define <vscale x 4 x i64> @vwmulsu_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {943; CHECK-LABEL: vwmulsu_vv_nxv4i64_nxv4i8:944; CHECK: # %bb.0:945; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma946; CHECK-NEXT: vsext.vf4 v12, v8947; CHECK-NEXT: vzext.vf4 v14, v9948; CHECK-NEXT: vwmulsu.vv v8, v12, v14949; CHECK-NEXT: ret950 %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>951 %vd = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>952 %ve = mul <vscale x 4 x i64> %vc, %vd953 ret <vscale x 4 x i64> %ve954}955 956define <vscale x 4 x i64> @vwmul_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {957; CHECK-LABEL: vwmul_vx_nxv4i64_nxv4i8:958; CHECK: # %bb.0:959; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma960; CHECK-NEXT: vmv.v.x v9, a0961; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma962; CHECK-NEXT: vsext.vf4 v12, v8963; CHECK-NEXT: vsext.vf4 v14, v9964; CHECK-NEXT: vwmul.vv v8, v12, v14965; CHECK-NEXT: ret966 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 0967 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer968 %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>969 %vd = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>970 %ve = mul <vscale x 4 x i64> %vc, %vd971 ret <vscale x 4 x i64> %ve972}973 974define <vscale x 4 x i64> @vwmulu_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {975; CHECK-LABEL: vwmulu_vx_nxv4i64_nxv4i8:976; CHECK: # %bb.0:977; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma978; CHECK-NEXT: vwmulu.vx v12, v8, a0979; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma980; CHECK-NEXT: vzext.vf4 v8, v12981; CHECK-NEXT: ret982 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 0983 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer984 %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>985 %vd = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>986 %ve = mul <vscale x 4 x i64> %vc, %vd987 ret <vscale x 4 x i64> %ve988}989 990define <vscale x 4 x i64> @vwmulsu_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {991; CHECK-LABEL: vwmulsu_vx_nxv4i64_nxv4i8:992; CHECK: # %bb.0:993; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma994; CHECK-NEXT: vmv.v.x v9, a0995; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma996; CHECK-NEXT: vsext.vf4 v12, v8997; CHECK-NEXT: vzext.vf4 v14, v9998; CHECK-NEXT: vwmulsu.vv v8, v12, v14999; CHECK-NEXT: ret1000 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 01001 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer1002 %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>1003 %vd = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>1004 %ve = mul <vscale x 4 x i64> %vc, %vd1005 ret <vscale x 4 x i64> %ve1006}1007 1008define <vscale x 8 x i64> @vwmul_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {1009; CHECK-LABEL: vwmul_vv_nxv8i64_nxv8i8:1010; CHECK: # %bb.0:1011; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1012; CHECK-NEXT: vsext.vf4 v16, v81013; CHECK-NEXT: vsext.vf4 v20, v91014; CHECK-NEXT: vwmul.vv v8, v16, v201015; CHECK-NEXT: ret1016 %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>1017 %vd = sext <vscale x 8 x i8> %vb to <vscale x 8 x i64>1018 %ve = mul <vscale x 8 x i64> %vc, %vd1019 ret <vscale x 8 x i64> %ve1020}1021 1022define <vscale x 8 x i64> @vwmulu_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {1023; CHECK-LABEL: vwmulu_vv_nxv8i64_nxv8i8:1024; CHECK: # %bb.0:1025; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma1026; CHECK-NEXT: vwmulu.vv v16, v8, v91027; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1028; CHECK-NEXT: vzext.vf4 v8, v161029; CHECK-NEXT: ret1030 %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>1031 %vd = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>1032 %ve = mul <vscale x 8 x i64> %vc, %vd1033 ret <vscale x 8 x i64> %ve1034}1035 1036define <vscale x 8 x i64> @vwmulsu_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {1037; CHECK-LABEL: vwmulsu_vv_nxv8i64_nxv8i8:1038; CHECK: # %bb.0:1039; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1040; CHECK-NEXT: vsext.vf4 v16, v81041; CHECK-NEXT: vzext.vf4 v20, v91042; CHECK-NEXT: vwmulsu.vv v8, v16, v201043; CHECK-NEXT: ret1044 %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>1045 %vd = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>1046 %ve = mul <vscale x 8 x i64> %vc, %vd1047 ret <vscale x 8 x i64> %ve1048}1049 1050define <vscale x 8 x i64> @vwmul_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {1051; CHECK-LABEL: vwmul_vx_nxv8i64_nxv8i8:1052; CHECK: # %bb.0:1053; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1054; CHECK-NEXT: vmv.v.x v9, a01055; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1056; CHECK-NEXT: vsext.vf4 v16, v81057; CHECK-NEXT: vsext.vf4 v20, v91058; CHECK-NEXT: vwmul.vv v8, v16, v201059; CHECK-NEXT: ret1060 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 01061 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer1062 %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>1063 %vd = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>1064 %ve = mul <vscale x 8 x i64> %vc, %vd1065 ret <vscale x 8 x i64> %ve1066}1067 1068define <vscale x 8 x i64> @vwmulu_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {1069; CHECK-LABEL: vwmulu_vx_nxv8i64_nxv8i8:1070; CHECK: # %bb.0:1071; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1072; CHECK-NEXT: vwmulu.vx v16, v8, a01073; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1074; CHECK-NEXT: vzext.vf4 v8, v161075; CHECK-NEXT: ret1076 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 01077 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer1078 %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>1079 %vd = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>1080 %ve = mul <vscale x 8 x i64> %vc, %vd1081 ret <vscale x 8 x i64> %ve1082}1083 1084define <vscale x 8 x i64> @vwmulsu_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {1085; CHECK-LABEL: vwmulsu_vx_nxv8i64_nxv8i8:1086; CHECK: # %bb.0:1087; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1088; CHECK-NEXT: vmv.v.x v9, a01089; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1090; CHECK-NEXT: vsext.vf4 v16, v81091; CHECK-NEXT: vzext.vf4 v20, v91092; CHECK-NEXT: vwmulsu.vv v8, v16, v201093; CHECK-NEXT: ret1094 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 01095 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer1096 %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>1097 %vd = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>1098 %ve = mul <vscale x 8 x i64> %vc, %vd1099 ret <vscale x 8 x i64> %ve1100}1101