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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i16> @intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i16_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vwmul.vv v10, v8, v912; CHECK-NEXT: vmv1r.v v8, v1013; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.nxv1i8(16 <vscale x 1 x i16> poison,17 <vscale x 1 x i8> %0,18 <vscale x 1 x i8> %1,19 iXLen %2)20 21 ret <vscale x 1 x i16> %a22}23 24define <vscale x 1 x i16> @intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i16_nxv1i8_nxv1i8:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu28; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t29; CHECK-NEXT: ret30entry:31 %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.nxv1i8(32 <vscale x 1 x i16> %0,33 <vscale x 1 x i8> %1,34 <vscale x 1 x i8> %2,35 <vscale x 1 x i1> %3,36 iXLen %4, iXLen 1)37 38 ret <vscale x 1 x i16> %a39}40 41define <vscale x 2 x i16> @intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i16_nxv2i8_nxv2i8:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma45; CHECK-NEXT: vwmul.vv v10, v8, v946; CHECK-NEXT: vmv1r.v v8, v1047; CHECK-NEXT: ret48entry:49 %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.nxv2i8(50 <vscale x 2 x i16> poison,51 <vscale x 2 x i8> %0,52 <vscale x 2 x i8> %1,53 iXLen %2)54 55 ret <vscale x 2 x i16> %a56}57 58define <vscale x 2 x i16> @intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i16_nxv2i8_nxv2i8:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu62; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t63; CHECK-NEXT: ret64entry:65 %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.nxv2i8(66 <vscale x 2 x i16> %0,67 <vscale x 2 x i8> %1,68 <vscale x 2 x i8> %2,69 <vscale x 2 x i1> %3,70 iXLen %4, iXLen 1)71 72 ret <vscale x 2 x i16> %a73}74 75define <vscale x 4 x i16> @intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i16_nxv4i8_nxv4i8:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma79; CHECK-NEXT: vwmul.vv v10, v8, v980; CHECK-NEXT: vmv1r.v v8, v1081; CHECK-NEXT: ret82entry:83 %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.nxv4i8(84 <vscale x 4 x i16> poison,85 <vscale x 4 x i8> %0,86 <vscale x 4 x i8> %1,87 iXLen %2)88 89 ret <vscale x 4 x i16> %a90}91 92define <vscale x 4 x i16> @intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i16_nxv4i8_nxv4i8:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu96; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t97; CHECK-NEXT: ret98entry:99 %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.nxv4i8(100 <vscale x 4 x i16> %0,101 <vscale x 4 x i8> %1,102 <vscale x 4 x i8> %2,103 <vscale x 4 x i1> %3,104 iXLen %4, iXLen 1)105 106 ret <vscale x 4 x i16> %a107}108 109define <vscale x 8 x i16> @intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i16_nxv8i8_nxv8i8:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma113; CHECK-NEXT: vmv1r.v v10, v9114; CHECK-NEXT: vmv1r.v v11, v8115; CHECK-NEXT: vwmul.vv v8, v11, v10116; CHECK-NEXT: ret117entry:118 %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.nxv8i8(119 <vscale x 8 x i16> poison,120 <vscale x 8 x i8> %0,121 <vscale x 8 x i8> %1,122 iXLen %2)123 124 ret <vscale x 8 x i16> %a125}126 127define <vscale x 8 x i16> @intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {128; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i16_nxv8i8_nxv8i8:129; CHECK: # %bb.0: # %entry130; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu131; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t132; CHECK-NEXT: ret133entry:134 %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.nxv8i8(135 <vscale x 8 x i16> %0,136 <vscale x 8 x i8> %1,137 <vscale x 8 x i8> %2,138 <vscale x 8 x i1> %3,139 iXLen %4, iXLen 1)140 141 ret <vscale x 8 x i16> %a142}143 144define <vscale x 16 x i16> @intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {145; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i16_nxv16i8_nxv16i8:146; CHECK: # %bb.0: # %entry147; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma148; CHECK-NEXT: vmv2r.v v12, v10149; CHECK-NEXT: vmv2r.v v14, v8150; CHECK-NEXT: vwmul.vv v8, v14, v12151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.nxv16i8(154 <vscale x 16 x i16> poison,155 <vscale x 16 x i8> %0,156 <vscale x 16 x i8> %1,157 iXLen %2)158 159 ret <vscale x 16 x i16> %a160}161 162define <vscale x 16 x i16> @intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {163; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i16_nxv16i8_nxv16i8:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu166; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t167; CHECK-NEXT: ret168entry:169 %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.nxv16i8(170 <vscale x 16 x i16> %0,171 <vscale x 16 x i8> %1,172 <vscale x 16 x i8> %2,173 <vscale x 16 x i1> %3,174 iXLen %4, iXLen 1)175 176 ret <vscale x 16 x i16> %a177}178 179define <vscale x 32 x i16> @intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {180; CHECK-LABEL: intrinsic_vwmul_vv_nxv32i16_nxv32i8_nxv32i8:181; CHECK: # %bb.0: # %entry182; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma183; CHECK-NEXT: vmv4r.v v16, v12184; CHECK-NEXT: vmv4r.v v20, v8185; CHECK-NEXT: vwmul.vv v8, v20, v16186; CHECK-NEXT: ret187entry:188 %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.nxv32i8(189 <vscale x 32 x i16> poison,190 <vscale x 32 x i8> %0,191 <vscale x 32 x i8> %1,192 iXLen %2)193 194 ret <vscale x 32 x i16> %a195}196 197define <vscale x 32 x i16> @intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {198; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv32i16_nxv32i8_nxv32i8:199; CHECK: # %bb.0: # %entry200; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu201; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t202; CHECK-NEXT: ret203entry:204 %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.nxv32i8(205 <vscale x 32 x i16> %0,206 <vscale x 32 x i8> %1,207 <vscale x 32 x i8> %2,208 <vscale x 32 x i1> %3,209 iXLen %4, iXLen 1)210 211 ret <vscale x 32 x i16> %a212}213 214define <vscale x 1 x i32> @intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {215; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i32_nxv1i16_nxv1i16:216; CHECK: # %bb.0: # %entry217; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma218; CHECK-NEXT: vwmul.vv v10, v8, v9219; CHECK-NEXT: vmv1r.v v8, v10220; CHECK-NEXT: ret221entry:222 %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.nxv1i16(223 <vscale x 1 x i32> poison,224 <vscale x 1 x i16> %0,225 <vscale x 1 x i16> %1,226 iXLen %2)227 228 ret <vscale x 1 x i32> %a229}230 231define <vscale x 1 x i32> @intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {232; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i32_nxv1i16_nxv1i16:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu235; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t236; CHECK-NEXT: ret237entry:238 %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.nxv1i16(239 <vscale x 1 x i32> %0,240 <vscale x 1 x i16> %1,241 <vscale x 1 x i16> %2,242 <vscale x 1 x i1> %3,243 iXLen %4, iXLen 1)244 245 ret <vscale x 1 x i32> %a246}247 248define <vscale x 2 x i32> @intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {249; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i32_nxv2i16_nxv2i16:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma252; CHECK-NEXT: vwmul.vv v10, v8, v9253; CHECK-NEXT: vmv1r.v v8, v10254; CHECK-NEXT: ret255entry:256 %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.nxv2i16(257 <vscale x 2 x i32> poison,258 <vscale x 2 x i16> %0,259 <vscale x 2 x i16> %1,260 iXLen %2)261 262 ret <vscale x 2 x i32> %a263}264 265define <vscale x 2 x i32> @intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {266; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i32_nxv2i16_nxv2i16:267; CHECK: # %bb.0: # %entry268; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu269; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t270; CHECK-NEXT: ret271entry:272 %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.nxv2i16(273 <vscale x 2 x i32> %0,274 <vscale x 2 x i16> %1,275 <vscale x 2 x i16> %2,276 <vscale x 2 x i1> %3,277 iXLen %4, iXLen 1)278 279 ret <vscale x 2 x i32> %a280}281 282define <vscale x 4 x i32> @intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {283; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i32_nxv4i16_nxv4i16:284; CHECK: # %bb.0: # %entry285; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma286; CHECK-NEXT: vmv1r.v v10, v9287; CHECK-NEXT: vmv1r.v v11, v8288; CHECK-NEXT: vwmul.vv v8, v11, v10289; CHECK-NEXT: ret290entry:291 %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.nxv4i16(292 <vscale x 4 x i32> poison,293 <vscale x 4 x i16> %0,294 <vscale x 4 x i16> %1,295 iXLen %2)296 297 ret <vscale x 4 x i32> %a298}299 300define <vscale x 4 x i32> @intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {301; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i32_nxv4i16_nxv4i16:302; CHECK: # %bb.0: # %entry303; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu304; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t305; CHECK-NEXT: ret306entry:307 %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.nxv4i16(308 <vscale x 4 x i32> %0,309 <vscale x 4 x i16> %1,310 <vscale x 4 x i16> %2,311 <vscale x 4 x i1> %3,312 iXLen %4, iXLen 1)313 314 ret <vscale x 4 x i32> %a315}316 317define <vscale x 8 x i32> @intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {318; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i32_nxv8i16_nxv8i16:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma321; CHECK-NEXT: vmv2r.v v12, v10322; CHECK-NEXT: vmv2r.v v14, v8323; CHECK-NEXT: vwmul.vv v8, v14, v12324; CHECK-NEXT: ret325entry:326 %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.nxv8i16(327 <vscale x 8 x i32> poison,328 <vscale x 8 x i16> %0,329 <vscale x 8 x i16> %1,330 iXLen %2)331 332 ret <vscale x 8 x i32> %a333}334 335define <vscale x 8 x i32> @intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {336; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i32_nxv8i16_nxv8i16:337; CHECK: # %bb.0: # %entry338; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu339; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t340; CHECK-NEXT: ret341entry:342 %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.nxv8i16(343 <vscale x 8 x i32> %0,344 <vscale x 8 x i16> %1,345 <vscale x 8 x i16> %2,346 <vscale x 8 x i1> %3,347 iXLen %4, iXLen 1)348 349 ret <vscale x 8 x i32> %a350}351 352define <vscale x 16 x i32> @intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {353; CHECK-LABEL: intrinsic_vwmul_vv_nxv16i32_nxv16i16_nxv16i16:354; CHECK: # %bb.0: # %entry355; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma356; CHECK-NEXT: vmv4r.v v16, v12357; CHECK-NEXT: vmv4r.v v20, v8358; CHECK-NEXT: vwmul.vv v8, v20, v16359; CHECK-NEXT: ret360entry:361 %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.nxv16i16(362 <vscale x 16 x i32> poison,363 <vscale x 16 x i16> %0,364 <vscale x 16 x i16> %1,365 iXLen %2)366 367 ret <vscale x 16 x i32> %a368}369 370define <vscale x 16 x i32> @intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {371; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv16i32_nxv16i16_nxv16i16:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu374; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.nxv16i16(378 <vscale x 16 x i32> %0,379 <vscale x 16 x i16> %1,380 <vscale x 16 x i16> %2,381 <vscale x 16 x i1> %3,382 iXLen %4, iXLen 1)383 384 ret <vscale x 16 x i32> %a385}386 387define <vscale x 1 x i64> @intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {388; CHECK-LABEL: intrinsic_vwmul_vv_nxv1i64_nxv1i32_nxv1i32:389; CHECK: # %bb.0: # %entry390; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma391; CHECK-NEXT: vwmul.vv v10, v8, v9392; CHECK-NEXT: vmv1r.v v8, v10393; CHECK-NEXT: ret394entry:395 %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32(396 <vscale x 1 x i64> poison,397 <vscale x 1 x i32> %0,398 <vscale x 1 x i32> %1,399 iXLen %2)400 401 ret <vscale x 1 x i64> %a402}403 404define <vscale x 1 x i64> @intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {405; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv1i64_nxv1i32_nxv1i32:406; CHECK: # %bb.0: # %entry407; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu408; CHECK-NEXT: vwmul.vv v8, v9, v10, v0.t409; CHECK-NEXT: ret410entry:411 %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32(412 <vscale x 1 x i64> %0,413 <vscale x 1 x i32> %1,414 <vscale x 1 x i32> %2,415 <vscale x 1 x i1> %3,416 iXLen %4, iXLen 1)417 418 ret <vscale x 1 x i64> %a419}420 421define <vscale x 2 x i64> @intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {422; CHECK-LABEL: intrinsic_vwmul_vv_nxv2i64_nxv2i32_nxv2i32:423; CHECK: # %bb.0: # %entry424; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma425; CHECK-NEXT: vmv1r.v v10, v9426; CHECK-NEXT: vmv1r.v v11, v8427; CHECK-NEXT: vwmul.vv v8, v11, v10428; CHECK-NEXT: ret429entry:430 %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.nxv2i32(431 <vscale x 2 x i64> poison,432 <vscale x 2 x i32> %0,433 <vscale x 2 x i32> %1,434 iXLen %2)435 436 ret <vscale x 2 x i64> %a437}438 439define <vscale x 2 x i64> @intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {440; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv2i64_nxv2i32_nxv2i32:441; CHECK: # %bb.0: # %entry442; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu443; CHECK-NEXT: vwmul.vv v8, v10, v11, v0.t444; CHECK-NEXT: ret445entry:446 %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.nxv2i32(447 <vscale x 2 x i64> %0,448 <vscale x 2 x i32> %1,449 <vscale x 2 x i32> %2,450 <vscale x 2 x i1> %3,451 iXLen %4, iXLen 1)452 453 ret <vscale x 2 x i64> %a454}455 456define <vscale x 4 x i64> @intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {457; CHECK-LABEL: intrinsic_vwmul_vv_nxv4i64_nxv4i32_nxv4i32:458; CHECK: # %bb.0: # %entry459; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma460; CHECK-NEXT: vmv2r.v v12, v10461; CHECK-NEXT: vmv2r.v v14, v8462; CHECK-NEXT: vwmul.vv v8, v14, v12463; CHECK-NEXT: ret464entry:465 %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.nxv4i32(466 <vscale x 4 x i64> poison,467 <vscale x 4 x i32> %0,468 <vscale x 4 x i32> %1,469 iXLen %2)470 471 ret <vscale x 4 x i64> %a472}473 474define <vscale x 4 x i64> @intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {475; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv4i64_nxv4i32_nxv4i32:476; CHECK: # %bb.0: # %entry477; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu478; CHECK-NEXT: vwmul.vv v8, v12, v14, v0.t479; CHECK-NEXT: ret480entry:481 %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.nxv4i32(482 <vscale x 4 x i64> %0,483 <vscale x 4 x i32> %1,484 <vscale x 4 x i32> %2,485 <vscale x 4 x i1> %3,486 iXLen %4, iXLen 1)487 488 ret <vscale x 4 x i64> %a489}490 491define <vscale x 8 x i64> @intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {492; CHECK-LABEL: intrinsic_vwmul_vv_nxv8i64_nxv8i32_nxv8i32:493; CHECK: # %bb.0: # %entry494; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma495; CHECK-NEXT: vmv4r.v v16, v12496; CHECK-NEXT: vmv4r.v v20, v8497; CHECK-NEXT: vwmul.vv v8, v20, v16498; CHECK-NEXT: ret499entry:500 %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.nxv8i32(501 <vscale x 8 x i64> poison,502 <vscale x 8 x i32> %0,503 <vscale x 8 x i32> %1,504 iXLen %2)505 506 ret <vscale x 8 x i64> %a507}508 509define <vscale x 8 x i64> @intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {510; CHECK-LABEL: intrinsic_vwmul_mask_vv_nxv8i64_nxv8i32_nxv8i32:511; CHECK: # %bb.0: # %entry512; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu513; CHECK-NEXT: vwmul.vv v8, v16, v20, v0.t514; CHECK-NEXT: ret515entry:516 %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.nxv8i32(517 <vscale x 8 x i64> %0,518 <vscale x 8 x i32> %1,519 <vscale x 8 x i32> %2,520 <vscale x 8 x i1> %3,521 iXLen %4, iXLen 1)522 523 ret <vscale x 8 x i64> %a524}525 526define <vscale x 1 x i16> @intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {527; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i16_nxv1i8_i8:528; CHECK: # %bb.0: # %entry529; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma530; CHECK-NEXT: vwmul.vx v9, v8, a0531; CHECK-NEXT: vmv1r.v v8, v9532; CHECK-NEXT: ret533entry:534 %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.nxv1i16.nxv1i8.i8(535 <vscale x 1 x i16> poison,536 <vscale x 1 x i8> %0,537 i8 %1,538 iXLen %2)539 540 ret <vscale x 1 x i16> %a541}542 543define <vscale x 1 x i16> @intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {544; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i16_nxv1i8_i8:545; CHECK: # %bb.0: # %entry546; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu547; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t548; CHECK-NEXT: ret549entry:550 %a = call <vscale x 1 x i16> @llvm.riscv.vwmul.mask.nxv1i16.nxv1i8.i8(551 <vscale x 1 x i16> %0,552 <vscale x 1 x i8> %1,553 i8 %2,554 <vscale x 1 x i1> %3,555 iXLen %4, iXLen 1)556 557 ret <vscale x 1 x i16> %a558}559 560define <vscale x 2 x i16> @intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {561; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i16_nxv2i8_i8:562; CHECK: # %bb.0: # %entry563; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma564; CHECK-NEXT: vwmul.vx v9, v8, a0565; CHECK-NEXT: vmv1r.v v8, v9566; CHECK-NEXT: ret567entry:568 %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.nxv2i16.nxv2i8.i8(569 <vscale x 2 x i16> poison,570 <vscale x 2 x i8> %0,571 i8 %1,572 iXLen %2)573 574 ret <vscale x 2 x i16> %a575}576 577define <vscale x 2 x i16> @intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {578; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i16_nxv2i8_i8:579; CHECK: # %bb.0: # %entry580; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu581; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t582; CHECK-NEXT: ret583entry:584 %a = call <vscale x 2 x i16> @llvm.riscv.vwmul.mask.nxv2i16.nxv2i8.i8(585 <vscale x 2 x i16> %0,586 <vscale x 2 x i8> %1,587 i8 %2,588 <vscale x 2 x i1> %3,589 iXLen %4, iXLen 1)590 591 ret <vscale x 2 x i16> %a592}593 594define <vscale x 4 x i16> @intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {595; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i16_nxv4i8_i8:596; CHECK: # %bb.0: # %entry597; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma598; CHECK-NEXT: vwmul.vx v9, v8, a0599; CHECK-NEXT: vmv1r.v v8, v9600; CHECK-NEXT: ret601entry:602 %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.nxv4i16.nxv4i8.i8(603 <vscale x 4 x i16> poison,604 <vscale x 4 x i8> %0,605 i8 %1,606 iXLen %2)607 608 ret <vscale x 4 x i16> %a609}610 611define <vscale x 4 x i16> @intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {612; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i16_nxv4i8_i8:613; CHECK: # %bb.0: # %entry614; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu615; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t616; CHECK-NEXT: ret617entry:618 %a = call <vscale x 4 x i16> @llvm.riscv.vwmul.mask.nxv4i16.nxv4i8.i8(619 <vscale x 4 x i16> %0,620 <vscale x 4 x i8> %1,621 i8 %2,622 <vscale x 4 x i1> %3,623 iXLen %4, iXLen 1)624 625 ret <vscale x 4 x i16> %a626}627 628define <vscale x 8 x i16> @intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {629; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i16_nxv8i8_i8:630; CHECK: # %bb.0: # %entry631; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma632; CHECK-NEXT: vmv1r.v v10, v8633; CHECK-NEXT: vwmul.vx v8, v10, a0634; CHECK-NEXT: ret635entry:636 %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.nxv8i16.nxv8i8.i8(637 <vscale x 8 x i16> poison,638 <vscale x 8 x i8> %0,639 i8 %1,640 iXLen %2)641 642 ret <vscale x 8 x i16> %a643}644 645define <vscale x 8 x i16> @intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {646; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i16_nxv8i8_i8:647; CHECK: # %bb.0: # %entry648; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu649; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t650; CHECK-NEXT: ret651entry:652 %a = call <vscale x 8 x i16> @llvm.riscv.vwmul.mask.nxv8i16.nxv8i8.i8(653 <vscale x 8 x i16> %0,654 <vscale x 8 x i8> %1,655 i8 %2,656 <vscale x 8 x i1> %3,657 iXLen %4, iXLen 1)658 659 ret <vscale x 8 x i16> %a660}661 662define <vscale x 16 x i16> @intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {663; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i16_nxv16i8_i8:664; CHECK: # %bb.0: # %entry665; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma666; CHECK-NEXT: vmv2r.v v12, v8667; CHECK-NEXT: vwmul.vx v8, v12, a0668; CHECK-NEXT: ret669entry:670 %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.nxv16i16.nxv16i8.i8(671 <vscale x 16 x i16> poison,672 <vscale x 16 x i8> %0,673 i8 %1,674 iXLen %2)675 676 ret <vscale x 16 x i16> %a677}678 679define <vscale x 16 x i16> @intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {680; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i16_nxv16i8_i8:681; CHECK: # %bb.0: # %entry682; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu683; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t684; CHECK-NEXT: ret685entry:686 %a = call <vscale x 16 x i16> @llvm.riscv.vwmul.mask.nxv16i16.nxv16i8.i8(687 <vscale x 16 x i16> %0,688 <vscale x 16 x i8> %1,689 i8 %2,690 <vscale x 16 x i1> %3,691 iXLen %4, iXLen 1)692 693 ret <vscale x 16 x i16> %a694}695 696define <vscale x 32 x i16> @intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {697; CHECK-LABEL: intrinsic_vwmul_vx_nxv32i16_nxv32i8_i8:698; CHECK: # %bb.0: # %entry699; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma700; CHECK-NEXT: vmv4r.v v16, v8701; CHECK-NEXT: vwmul.vx v8, v16, a0702; CHECK-NEXT: ret703entry:704 %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.nxv32i16.nxv32i8.i8(705 <vscale x 32 x i16> poison,706 <vscale x 32 x i8> %0,707 i8 %1,708 iXLen %2)709 710 ret <vscale x 32 x i16> %a711}712 713define <vscale x 32 x i16> @intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {714; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv32i16_nxv32i8_i8:715; CHECK: # %bb.0: # %entry716; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu717; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t718; CHECK-NEXT: ret719entry:720 %a = call <vscale x 32 x i16> @llvm.riscv.vwmul.mask.nxv32i16.nxv32i8.i8(721 <vscale x 32 x i16> %0,722 <vscale x 32 x i8> %1,723 i8 %2,724 <vscale x 32 x i1> %3,725 iXLen %4, iXLen 1)726 727 ret <vscale x 32 x i16> %a728}729 730define <vscale x 1 x i32> @intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {731; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i32_nxv1i16_i16:732; CHECK: # %bb.0: # %entry733; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma734; CHECK-NEXT: vwmul.vx v9, v8, a0735; CHECK-NEXT: vmv1r.v v8, v9736; CHECK-NEXT: ret737entry:738 %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.nxv1i32.nxv1i16.i16(739 <vscale x 1 x i32> poison,740 <vscale x 1 x i16> %0,741 i16 %1,742 iXLen %2)743 744 ret <vscale x 1 x i32> %a745}746 747define <vscale x 1 x i32> @intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {748; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i32_nxv1i16_i16:749; CHECK: # %bb.0: # %entry750; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu751; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t752; CHECK-NEXT: ret753entry:754 %a = call <vscale x 1 x i32> @llvm.riscv.vwmul.mask.nxv1i32.nxv1i16.i16(755 <vscale x 1 x i32> %0,756 <vscale x 1 x i16> %1,757 i16 %2,758 <vscale x 1 x i1> %3,759 iXLen %4, iXLen 1)760 761 ret <vscale x 1 x i32> %a762}763 764define <vscale x 2 x i32> @intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {765; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i32_nxv2i16_i16:766; CHECK: # %bb.0: # %entry767; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma768; CHECK-NEXT: vwmul.vx v9, v8, a0769; CHECK-NEXT: vmv1r.v v8, v9770; CHECK-NEXT: ret771entry:772 %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.nxv2i32.nxv2i16.i16(773 <vscale x 2 x i32> poison,774 <vscale x 2 x i16> %0,775 i16 %1,776 iXLen %2)777 778 ret <vscale x 2 x i32> %a779}780 781define <vscale x 2 x i32> @intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {782; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i32_nxv2i16_i16:783; CHECK: # %bb.0: # %entry784; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu785; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t786; CHECK-NEXT: ret787entry:788 %a = call <vscale x 2 x i32> @llvm.riscv.vwmul.mask.nxv2i32.nxv2i16.i16(789 <vscale x 2 x i32> %0,790 <vscale x 2 x i16> %1,791 i16 %2,792 <vscale x 2 x i1> %3,793 iXLen %4, iXLen 1)794 795 ret <vscale x 2 x i32> %a796}797 798define <vscale x 4 x i32> @intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {799; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i32_nxv4i16_i16:800; CHECK: # %bb.0: # %entry801; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma802; CHECK-NEXT: vmv1r.v v10, v8803; CHECK-NEXT: vwmul.vx v8, v10, a0804; CHECK-NEXT: ret805entry:806 %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.nxv4i32.nxv4i16.i16(807 <vscale x 4 x i32> poison,808 <vscale x 4 x i16> %0,809 i16 %1,810 iXLen %2)811 812 ret <vscale x 4 x i32> %a813}814 815define <vscale x 4 x i32> @intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {816; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i32_nxv4i16_i16:817; CHECK: # %bb.0: # %entry818; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu819; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t820; CHECK-NEXT: ret821entry:822 %a = call <vscale x 4 x i32> @llvm.riscv.vwmul.mask.nxv4i32.nxv4i16.i16(823 <vscale x 4 x i32> %0,824 <vscale x 4 x i16> %1,825 i16 %2,826 <vscale x 4 x i1> %3,827 iXLen %4, iXLen 1)828 829 ret <vscale x 4 x i32> %a830}831 832define <vscale x 8 x i32> @intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {833; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i32_nxv8i16_i16:834; CHECK: # %bb.0: # %entry835; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma836; CHECK-NEXT: vmv2r.v v12, v8837; CHECK-NEXT: vwmul.vx v8, v12, a0838; CHECK-NEXT: ret839entry:840 %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.nxv8i32.nxv8i16.i16(841 <vscale x 8 x i32> poison,842 <vscale x 8 x i16> %0,843 i16 %1,844 iXLen %2)845 846 ret <vscale x 8 x i32> %a847}848 849define <vscale x 8 x i32> @intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {850; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i32_nxv8i16_i16:851; CHECK: # %bb.0: # %entry852; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu853; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t854; CHECK-NEXT: ret855entry:856 %a = call <vscale x 8 x i32> @llvm.riscv.vwmul.mask.nxv8i32.nxv8i16.i16(857 <vscale x 8 x i32> %0,858 <vscale x 8 x i16> %1,859 i16 %2,860 <vscale x 8 x i1> %3,861 iXLen %4, iXLen 1)862 863 ret <vscale x 8 x i32> %a864}865 866define <vscale x 16 x i32> @intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {867; CHECK-LABEL: intrinsic_vwmul_vx_nxv16i32_nxv16i16_i16:868; CHECK: # %bb.0: # %entry869; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma870; CHECK-NEXT: vmv4r.v v16, v8871; CHECK-NEXT: vwmul.vx v8, v16, a0872; CHECK-NEXT: ret873entry:874 %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.nxv16i32.nxv16i16.i16(875 <vscale x 16 x i32> poison,876 <vscale x 16 x i16> %0,877 i16 %1,878 iXLen %2)879 880 ret <vscale x 16 x i32> %a881}882 883define <vscale x 16 x i32> @intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {884; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv16i32_nxv16i16_i16:885; CHECK: # %bb.0: # %entry886; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu887; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t888; CHECK-NEXT: ret889entry:890 %a = call <vscale x 16 x i32> @llvm.riscv.vwmul.mask.nxv16i32.nxv16i16.i16(891 <vscale x 16 x i32> %0,892 <vscale x 16 x i16> %1,893 i16 %2,894 <vscale x 16 x i1> %3,895 iXLen %4, iXLen 1)896 897 ret <vscale x 16 x i32> %a898}899 900define <vscale x 1 x i64> @intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {901; CHECK-LABEL: intrinsic_vwmul_vx_nxv1i64_nxv1i32_i32:902; CHECK: # %bb.0: # %entry903; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma904; CHECK-NEXT: vwmul.vx v9, v8, a0905; CHECK-NEXT: vmv1r.v v8, v9906; CHECK-NEXT: ret907entry:908 %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.nxv1i64.nxv1i32.i32(909 <vscale x 1 x i64> poison,910 <vscale x 1 x i32> %0,911 i32 %1,912 iXLen %2)913 914 ret <vscale x 1 x i64> %a915}916 917define <vscale x 1 x i64> @intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {918; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv1i64_nxv1i32_i32:919; CHECK: # %bb.0: # %entry920; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu921; CHECK-NEXT: vwmul.vx v8, v9, a0, v0.t922; CHECK-NEXT: ret923entry:924 %a = call <vscale x 1 x i64> @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.i32(925 <vscale x 1 x i64> %0,926 <vscale x 1 x i32> %1,927 i32 %2,928 <vscale x 1 x i1> %3,929 iXLen %4, iXLen 1)930 931 ret <vscale x 1 x i64> %a932}933 934define <vscale x 2 x i64> @intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {935; CHECK-LABEL: intrinsic_vwmul_vx_nxv2i64_nxv2i32_i32:936; CHECK: # %bb.0: # %entry937; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma938; CHECK-NEXT: vmv1r.v v10, v8939; CHECK-NEXT: vwmul.vx v8, v10, a0940; CHECK-NEXT: ret941entry:942 %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.nxv2i64.nxv2i32.i32(943 <vscale x 2 x i64> poison,944 <vscale x 2 x i32> %0,945 i32 %1,946 iXLen %2)947 948 ret <vscale x 2 x i64> %a949}950 951define <vscale x 2 x i64> @intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {952; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv2i64_nxv2i32_i32:953; CHECK: # %bb.0: # %entry954; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu955; CHECK-NEXT: vwmul.vx v8, v10, a0, v0.t956; CHECK-NEXT: ret957entry:958 %a = call <vscale x 2 x i64> @llvm.riscv.vwmul.mask.nxv2i64.nxv2i32.i32(959 <vscale x 2 x i64> %0,960 <vscale x 2 x i32> %1,961 i32 %2,962 <vscale x 2 x i1> %3,963 iXLen %4, iXLen 1)964 965 ret <vscale x 2 x i64> %a966}967 968define <vscale x 4 x i64> @intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {969; CHECK-LABEL: intrinsic_vwmul_vx_nxv4i64_nxv4i32_i32:970; CHECK: # %bb.0: # %entry971; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma972; CHECK-NEXT: vmv2r.v v12, v8973; CHECK-NEXT: vwmul.vx v8, v12, a0974; CHECK-NEXT: ret975entry:976 %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.nxv4i64.nxv4i32.i32(977 <vscale x 4 x i64> poison,978 <vscale x 4 x i32> %0,979 i32 %1,980 iXLen %2)981 982 ret <vscale x 4 x i64> %a983}984 985define <vscale x 4 x i64> @intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {986; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv4i64_nxv4i32_i32:987; CHECK: # %bb.0: # %entry988; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu989; CHECK-NEXT: vwmul.vx v8, v12, a0, v0.t990; CHECK-NEXT: ret991entry:992 %a = call <vscale x 4 x i64> @llvm.riscv.vwmul.mask.nxv4i64.nxv4i32.i32(993 <vscale x 4 x i64> %0,994 <vscale x 4 x i32> %1,995 i32 %2,996 <vscale x 4 x i1> %3,997 iXLen %4, iXLen 1)998 999 ret <vscale x 4 x i64> %a1000}1001 1002define <vscale x 8 x i64> @intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1003; CHECK-LABEL: intrinsic_vwmul_vx_nxv8i64_nxv8i32_i32:1004; CHECK: # %bb.0: # %entry1005; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1006; CHECK-NEXT: vmv4r.v v16, v81007; CHECK-NEXT: vwmul.vx v8, v16, a01008; CHECK-NEXT: ret1009entry:1010 %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.nxv8i64.nxv8i32.i32(1011 <vscale x 8 x i64> poison,1012 <vscale x 8 x i32> %0,1013 i32 %1,1014 iXLen %2)1015 1016 ret <vscale x 8 x i64> %a1017}1018 1019define <vscale x 8 x i64> @intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1020; CHECK-LABEL: intrinsic_vwmul_mask_vx_nxv8i64_nxv8i32_i32:1021; CHECK: # %bb.0: # %entry1022; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1023; CHECK-NEXT: vwmul.vx v8, v16, a0, v0.t1024; CHECK-NEXT: ret1025entry:1026 %a = call <vscale x 8 x i64> @llvm.riscv.vwmul.mask.nxv8i64.nxv8i32.i32(1027 <vscale x 8 x i64> %0,1028 <vscale x 8 x i32> %1,1029 i32 %2,1030 <vscale x 8 x i1> %3,1031 iXLen %4, iXLen 1)1032 1033 ret <vscale x 8 x i64> %a1034}1035