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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV32ZVBB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,RV64ZVBB6 7; ==============================================================================8; i32 -> i649; ==============================================================================10 11define <vscale x 2 x i64> @vwsll_vv_nxv2i64_sext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {12; CHECK-LABEL: vwsll_vv_nxv2i64_sext:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma15; CHECK-NEXT: vzext.vf2 v10, v816; CHECK-NEXT: vsext.vf2 v12, v917; CHECK-NEXT: vsll.vv v8, v10, v1218; CHECK-NEXT: ret19;20; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_sext:21; CHECK-ZVBB: # %bb.0:22; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma23; CHECK-ZVBB-NEXT: vmv1r.v v10, v924; CHECK-ZVBB-NEXT: vmv1r.v v11, v825; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v1026; CHECK-ZVBB-NEXT: ret27 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>28 %y = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>29 %z = shl <vscale x 2 x i64> %x, %y30 ret <vscale x 2 x i64> %z31}32 33define <vscale x 2 x i64> @vwsll_vv_nxv2i64_zext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {34; CHECK-LABEL: vwsll_vv_nxv2i64_zext:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma37; CHECK-NEXT: vzext.vf2 v10, v838; CHECK-NEXT: vzext.vf2 v12, v939; CHECK-NEXT: vsll.vv v8, v10, v1240; CHECK-NEXT: ret41;42; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_zext:43; CHECK-ZVBB: # %bb.0:44; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma45; CHECK-ZVBB-NEXT: vmv1r.v v10, v946; CHECK-ZVBB-NEXT: vmv1r.v v11, v847; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v1048; CHECK-ZVBB-NEXT: ret49 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>50 %y = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>51 %z = shl <vscale x 2 x i64> %x, %y52 ret <vscale x 2 x i64> %z53}54 55define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64(<vscale x 2 x i32> %a, i64 %b) {56; CHECK-LABEL: vwsll_vx_i64_nxv2i64:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma59; CHECK-NEXT: vzext.vf2 v10, v860; CHECK-NEXT: vsll.vx v8, v10, a061; CHECK-NEXT: ret62;63; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64:64; CHECK-ZVBB: # %bb.0:65; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma66; CHECK-ZVBB-NEXT: vmv1r.v v10, v867; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a068; CHECK-ZVBB-NEXT: ret69 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 070 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer71 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>72 %z = shl <vscale x 2 x i64> %x, %splat73 ret <vscale x 2 x i64> %z74}75 76define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_sext(<vscale x 2 x i32> %a, i32 %b) {77; CHECK-LABEL: vwsll_vx_i32_nxv2i64_sext:78; CHECK: # %bb.0:79; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma80; CHECK-NEXT: vmv.v.x v12, a081; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma82; CHECK-NEXT: vzext.vf2 v10, v883; CHECK-NEXT: vsext.vf2 v8, v1284; CHECK-NEXT: vsll.vv v8, v10, v885; CHECK-NEXT: ret86;87; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_sext:88; CHECK-ZVBB: # %bb.0:89; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma90; CHECK-ZVBB-NEXT: vmv1r.v v10, v891; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a092; CHECK-ZVBB-NEXT: ret93 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 094 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer95 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>96 %y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>97 %z = shl <vscale x 2 x i64> %x, %y98 ret <vscale x 2 x i64> %z99}100 101define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_zext(<vscale x 2 x i32> %a, i32 %b) {102; CHECK-LABEL: vwsll_vx_i32_nxv2i64_zext:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma105; CHECK-NEXT: vmv.v.x v12, a0106; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma107; CHECK-NEXT: vzext.vf2 v10, v8108; CHECK-NEXT: vzext.vf2 v8, v12109; CHECK-NEXT: vsll.vv v8, v10, v8110; CHECK-NEXT: ret111;112; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_zext:113; CHECK-ZVBB: # %bb.0:114; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma115; CHECK-ZVBB-NEXT: vmv1r.v v10, v8116; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0117; CHECK-ZVBB-NEXT: ret118 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0119 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer120 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>121 %y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>122 %z = shl <vscale x 2 x i64> %x, %y123 ret <vscale x 2 x i64> %z124}125 126define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_sext(<vscale x 2 x i32> %a, i16 %b) {127; CHECK-LABEL: vwsll_vx_i16_nxv2i64_sext:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma130; CHECK-NEXT: vmv.v.x v12, a0131; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma132; CHECK-NEXT: vzext.vf2 v10, v8133; CHECK-NEXT: vsext.vf4 v8, v12134; CHECK-NEXT: vsll.vv v8, v10, v8135; CHECK-NEXT: ret136;137; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_sext:138; CHECK-ZVBB: # %bb.0:139; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma140; CHECK-ZVBB-NEXT: vmv1r.v v10, v8141; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0142; CHECK-ZVBB-NEXT: ret143 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0144 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer145 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>146 %y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>147 %z = shl <vscale x 2 x i64> %x, %y148 ret <vscale x 2 x i64> %z149}150 151define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_zext(<vscale x 2 x i32> %a, i16 %b) {152; CHECK-LABEL: vwsll_vx_i16_nxv2i64_zext:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma155; CHECK-NEXT: vmv.v.x v12, a0156; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma157; CHECK-NEXT: vzext.vf2 v10, v8158; CHECK-NEXT: vzext.vf4 v8, v12159; CHECK-NEXT: vsll.vv v8, v10, v8160; CHECK-NEXT: ret161;162; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_zext:163; CHECK-ZVBB: # %bb.0:164; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma165; CHECK-ZVBB-NEXT: vmv1r.v v10, v8166; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0167; CHECK-ZVBB-NEXT: ret168 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0169 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer170 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>171 %y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>172 %z = shl <vscale x 2 x i64> %x, %y173 ret <vscale x 2 x i64> %z174}175 176define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_sext(<vscale x 2 x i32> %a, i8 %b) {177; CHECK-LABEL: vwsll_vx_i8_nxv2i64_sext:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma180; CHECK-NEXT: vmv.v.x v12, a0181; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma182; CHECK-NEXT: vzext.vf2 v10, v8183; CHECK-NEXT: vsext.vf8 v8, v12184; CHECK-NEXT: vsll.vv v8, v10, v8185; CHECK-NEXT: ret186;187; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_sext:188; CHECK-ZVBB: # %bb.0:189; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma190; CHECK-ZVBB-NEXT: vmv1r.v v10, v8191; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0192; CHECK-ZVBB-NEXT: ret193 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0194 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer195 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>196 %y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>197 %z = shl <vscale x 2 x i64> %x, %y198 ret <vscale x 2 x i64> %z199}200 201define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b) {202; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma205; CHECK-NEXT: vmv.v.x v12, a0206; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma207; CHECK-NEXT: vzext.vf2 v10, v8208; CHECK-NEXT: vzext.vf8 v8, v12209; CHECK-NEXT: vsll.vv v8, v10, v8210; CHECK-NEXT: ret211;212; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_zext:213; CHECK-ZVBB: # %bb.0:214; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma215; CHECK-ZVBB-NEXT: vmv1r.v v10, v8216; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0217; CHECK-ZVBB-NEXT: ret218 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0219 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer220 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>221 %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>222 %z = shl <vscale x 2 x i64> %x, %y223 ret <vscale x 2 x i64> %z224}225 226define <vscale x 2 x i64> @vwsll_vi_nxv2i64(<vscale x 2 x i32> %a) {227; CHECK-LABEL: vwsll_vi_nxv2i64:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma230; CHECK-NEXT: vmv1r.v v10, v8231; CHECK-NEXT: li a0, 4232; CHECK-NEXT: vwmulu.vx v8, v10, a0233; CHECK-NEXT: ret234;235; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64:236; CHECK-ZVBB: # %bb.0:237; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma238; CHECK-ZVBB-NEXT: vmv1r.v v10, v8239; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2240; CHECK-ZVBB-NEXT: ret241 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>242 %z = shl <vscale x 2 x i64> %x, splat (i64 2)243 ret <vscale x 2 x i64> %z244}245 246; ==============================================================================247; i16 -> i32248; ==============================================================================249 250define <vscale x 4 x i32> @vwsll_vv_nxv4i32_sext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {251; CHECK-LABEL: vwsll_vv_nxv4i32_sext:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma254; CHECK-NEXT: vzext.vf2 v10, v8255; CHECK-NEXT: vsext.vf2 v12, v9256; CHECK-NEXT: vsll.vv v8, v10, v12257; CHECK-NEXT: ret258;259; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_sext:260; CHECK-ZVBB: # %bb.0:261; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma262; CHECK-ZVBB-NEXT: vmv1r.v v10, v9263; CHECK-ZVBB-NEXT: vmv1r.v v11, v8264; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10265; CHECK-ZVBB-NEXT: ret266 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>267 %y = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>268 %z = shl <vscale x 4 x i32> %x, %y269 ret <vscale x 4 x i32> %z270}271 272define <vscale x 4 x i32> @vwsll_vv_nxv4i32_zext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {273; CHECK-LABEL: vwsll_vv_nxv4i32_zext:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma276; CHECK-NEXT: vzext.vf2 v10, v8277; CHECK-NEXT: vzext.vf2 v12, v9278; CHECK-NEXT: vsll.vv v8, v10, v12279; CHECK-NEXT: ret280;281; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_zext:282; CHECK-ZVBB: # %bb.0:283; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma284; CHECK-ZVBB-NEXT: vmv1r.v v10, v9285; CHECK-ZVBB-NEXT: vmv1r.v v11, v8286; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10287; CHECK-ZVBB-NEXT: ret288 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>289 %y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>290 %z = shl <vscale x 4 x i32> %x, %y291 ret <vscale x 4 x i32> %z292}293 294define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b) {295; CHECK-LABEL: vwsll_vx_i64_nxv4i32:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma298; CHECK-NEXT: vzext.vf2 v10, v8299; CHECK-NEXT: vsll.vx v8, v10, a0300; CHECK-NEXT: ret301;302; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv4i32:303; CHECK-ZVBB: # %bb.0:304; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma305; CHECK-ZVBB-NEXT: vmv1r.v v10, v8306; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0307; CHECK-ZVBB-NEXT: ret308 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0309 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer310 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>311 %y = trunc <vscale x 4 x i64> %splat to <vscale x 4 x i32>312 %z = shl <vscale x 4 x i32> %x, %y313 ret <vscale x 4 x i32> %z314}315 316define <vscale x 4 x i32> @vwsll_vx_i32_nxv4i32(<vscale x 4 x i16> %a, i32 %b) {317; CHECK-LABEL: vwsll_vx_i32_nxv4i32:318; CHECK: # %bb.0:319; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma320; CHECK-NEXT: vzext.vf2 v10, v8321; CHECK-NEXT: vsll.vx v8, v10, a0322; CHECK-NEXT: ret323;324; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv4i32:325; CHECK-ZVBB: # %bb.0:326; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma327; CHECK-ZVBB-NEXT: vmv1r.v v10, v8328; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0329; CHECK-ZVBB-NEXT: ret330 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0331 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer332 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>333 %z = shl <vscale x 4 x i32> %x, %splat334 ret <vscale x 4 x i32> %z335}336 337define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_sext(<vscale x 4 x i16> %a, i16 %b) {338; CHECK-LABEL: vwsll_vx_i16_nxv4i32_sext:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma341; CHECK-NEXT: vmv.v.x v12, a0342; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma343; CHECK-NEXT: vzext.vf2 v10, v8344; CHECK-NEXT: vsext.vf2 v8, v12345; CHECK-NEXT: vsll.vv v8, v10, v8346; CHECK-NEXT: ret347;348; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_sext:349; CHECK-ZVBB: # %bb.0:350; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma351; CHECK-ZVBB-NEXT: vmv1r.v v10, v8352; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0353; CHECK-ZVBB-NEXT: ret354 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0355 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer356 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>357 %y = sext <vscale x 4 x i16> %splat to <vscale x 4 x i32>358 %z = shl <vscale x 4 x i32> %x, %y359 ret <vscale x 4 x i32> %z360}361 362define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_zext(<vscale x 4 x i16> %a, i16 %b) {363; CHECK-LABEL: vwsll_vx_i16_nxv4i32_zext:364; CHECK: # %bb.0:365; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma366; CHECK-NEXT: vmv.v.x v12, a0367; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma368; CHECK-NEXT: vzext.vf2 v10, v8369; CHECK-NEXT: vzext.vf2 v8, v12370; CHECK-NEXT: vsll.vv v8, v10, v8371; CHECK-NEXT: ret372;373; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_zext:374; CHECK-ZVBB: # %bb.0:375; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma376; CHECK-ZVBB-NEXT: vmv1r.v v10, v8377; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0378; CHECK-ZVBB-NEXT: ret379 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0380 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer381 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>382 %y = zext <vscale x 4 x i16> %splat to <vscale x 4 x i32>383 %z = shl <vscale x 4 x i32> %x, %y384 ret <vscale x 4 x i32> %z385}386 387define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_sext(<vscale x 4 x i16> %a, i8 %b) {388; CHECK-LABEL: vwsll_vx_i8_nxv4i32_sext:389; CHECK: # %bb.0:390; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma391; CHECK-NEXT: vmv.v.x v12, a0392; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma393; CHECK-NEXT: vzext.vf2 v10, v8394; CHECK-NEXT: vsext.vf4 v8, v12395; CHECK-NEXT: vsll.vv v8, v10, v8396; CHECK-NEXT: ret397;398; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_sext:399; CHECK-ZVBB: # %bb.0:400; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma401; CHECK-ZVBB-NEXT: vmv1r.v v10, v8402; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0403; CHECK-ZVBB-NEXT: ret404 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0405 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer406 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>407 %y = sext <vscale x 4 x i8> %splat to <vscale x 4 x i32>408 %z = shl <vscale x 4 x i32> %x, %y409 ret <vscale x 4 x i32> %z410}411 412define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_zext(<vscale x 4 x i16> %a, i8 %b) {413; CHECK-LABEL: vwsll_vx_i8_nxv4i32_zext:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma416; CHECK-NEXT: vmv.v.x v12, a0417; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma418; CHECK-NEXT: vzext.vf2 v10, v8419; CHECK-NEXT: vzext.vf4 v8, v12420; CHECK-NEXT: vsll.vv v8, v10, v8421; CHECK-NEXT: ret422;423; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_zext:424; CHECK-ZVBB: # %bb.0:425; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma426; CHECK-ZVBB-NEXT: vmv1r.v v10, v8427; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0428; CHECK-ZVBB-NEXT: ret429 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0430 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer431 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>432 %y = zext <vscale x 4 x i8> %splat to <vscale x 4 x i32>433 %z = shl <vscale x 4 x i32> %x, %y434 ret <vscale x 4 x i32> %z435}436 437define <vscale x 4 x i32> @vwsll_vi_nxv4i32(<vscale x 4 x i16> %a) {438; CHECK-LABEL: vwsll_vi_nxv4i32:439; CHECK: # %bb.0:440; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma441; CHECK-NEXT: vmv1r.v v10, v8442; CHECK-NEXT: li a0, 4443; CHECK-NEXT: vwmulu.vx v8, v10, a0444; CHECK-NEXT: ret445;446; CHECK-ZVBB-LABEL: vwsll_vi_nxv4i32:447; CHECK-ZVBB: # %bb.0:448; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma449; CHECK-ZVBB-NEXT: vmv1r.v v10, v8450; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2451; CHECK-ZVBB-NEXT: ret452 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>453 %z = shl <vscale x 4 x i32> %x, splat (i32 2)454 ret <vscale x 4 x i32> %z455}456 457; ==============================================================================458; i8 -> i16459; ==============================================================================460 461define <vscale x 8 x i16> @vwsll_vv_nxv8i16_sext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {462; CHECK-LABEL: vwsll_vv_nxv8i16_sext:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma465; CHECK-NEXT: vzext.vf2 v10, v8466; CHECK-NEXT: vsext.vf2 v12, v9467; CHECK-NEXT: vsll.vv v8, v10, v12468; CHECK-NEXT: ret469;470; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_sext:471; CHECK-ZVBB: # %bb.0:472; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma473; CHECK-ZVBB-NEXT: vmv1r.v v10, v9474; CHECK-ZVBB-NEXT: vmv1r.v v11, v8475; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10476; CHECK-ZVBB-NEXT: ret477 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>478 %y = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>479 %z = shl <vscale x 8 x i16> %x, %y480 ret <vscale x 8 x i16> %z481}482 483define <vscale x 8 x i16> @vwsll_vv_nxv8i16_zext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {484; CHECK-LABEL: vwsll_vv_nxv8i16_zext:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma487; CHECK-NEXT: vzext.vf2 v10, v8488; CHECK-NEXT: vzext.vf2 v12, v9489; CHECK-NEXT: vsll.vv v8, v10, v12490; CHECK-NEXT: ret491;492; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_zext:493; CHECK-ZVBB: # %bb.0:494; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma495; CHECK-ZVBB-NEXT: vmv1r.v v10, v9496; CHECK-ZVBB-NEXT: vmv1r.v v11, v8497; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10498; CHECK-ZVBB-NEXT: ret499 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>500 %y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>501 %z = shl <vscale x 8 x i16> %x, %y502 ret <vscale x 8 x i16> %z503}504 505define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b) {506; CHECK-LABEL: vwsll_vx_i64_nxv8i16:507; CHECK: # %bb.0:508; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma509; CHECK-NEXT: vzext.vf2 v10, v8510; CHECK-NEXT: vsll.vx v8, v10, a0511; CHECK-NEXT: ret512;513; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv8i16:514; CHECK-ZVBB: # %bb.0:515; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma516; CHECK-ZVBB-NEXT: vmv1r.v v10, v8517; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0518; CHECK-ZVBB-NEXT: ret519 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0520 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer521 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>522 %y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16>523 %z = shl <vscale x 8 x i16> %x, %y524 ret <vscale x 8 x i16> %z525}526 527define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b) {528; CHECK-LABEL: vwsll_vx_i32_nxv8i16:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma531; CHECK-NEXT: vzext.vf2 v10, v8532; CHECK-NEXT: vsll.vx v8, v10, a0533; CHECK-NEXT: ret534;535; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16:536; CHECK-ZVBB: # %bb.0:537; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma538; CHECK-ZVBB-NEXT: vmv1r.v v10, v8539; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0540; CHECK-ZVBB-NEXT: ret541 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0542 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer543 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>544 %y = trunc <vscale x 8 x i32> %splat to <vscale x 8 x i16>545 %z = shl <vscale x 8 x i16> %x, %y546 ret <vscale x 8 x i16> %z547}548 549define <vscale x 8 x i16> @vwsll_vx_i16_nxv8i16(<vscale x 8 x i8> %a, i16 %b) {550; CHECK-LABEL: vwsll_vx_i16_nxv8i16:551; CHECK: # %bb.0:552; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma553; CHECK-NEXT: vzext.vf2 v10, v8554; CHECK-NEXT: vsll.vx v8, v10, a0555; CHECK-NEXT: ret556;557; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv8i16:558; CHECK-ZVBB: # %bb.0:559; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma560; CHECK-ZVBB-NEXT: vmv1r.v v10, v8561; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0562; CHECK-ZVBB-NEXT: ret563 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0564 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer565 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>566 %z = shl <vscale x 8 x i16> %x, %splat567 ret <vscale x 8 x i16> %z568}569 570define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_sext(<vscale x 8 x i8> %a, i8 %b) {571; CHECK-LABEL: vwsll_vx_i8_nxv8i16_sext:572; CHECK: # %bb.0:573; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma574; CHECK-NEXT: vmv.v.x v12, a0575; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma576; CHECK-NEXT: vzext.vf2 v10, v8577; CHECK-NEXT: vsext.vf2 v8, v12578; CHECK-NEXT: vsll.vv v8, v10, v8579; CHECK-NEXT: ret580;581; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_sext:582; CHECK-ZVBB: # %bb.0:583; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma584; CHECK-ZVBB-NEXT: vmv1r.v v10, v8585; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0586; CHECK-ZVBB-NEXT: ret587 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0588 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer589 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>590 %y = sext <vscale x 8 x i8> %splat to <vscale x 8 x i16>591 %z = shl <vscale x 8 x i16> %x, %y592 ret <vscale x 8 x i16> %z593}594 595define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_zext(<vscale x 8 x i8> %a, i8 %b) {596; CHECK-LABEL: vwsll_vx_i8_nxv8i16_zext:597; CHECK: # %bb.0:598; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma599; CHECK-NEXT: vmv.v.x v12, a0600; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma601; CHECK-NEXT: vzext.vf2 v10, v8602; CHECK-NEXT: vzext.vf2 v8, v12603; CHECK-NEXT: vsll.vv v8, v10, v8604; CHECK-NEXT: ret605;606; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_zext:607; CHECK-ZVBB: # %bb.0:608; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma609; CHECK-ZVBB-NEXT: vmv1r.v v10, v8610; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0611; CHECK-ZVBB-NEXT: ret612 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0613 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer614 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>615 %y = zext <vscale x 8 x i8> %splat to <vscale x 8 x i16>616 %z = shl <vscale x 8 x i16> %x, %y617 ret <vscale x 8 x i16> %z618}619 620define <vscale x 8 x i16> @vwsll_vi_nxv8i16(<vscale x 8 x i8> %a) {621; CHECK-LABEL: vwsll_vi_nxv8i16:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma624; CHECK-NEXT: vmv1r.v v10, v8625; CHECK-NEXT: li a0, 4626; CHECK-NEXT: vwmulu.vx v8, v10, a0627; CHECK-NEXT: ret628;629; CHECK-ZVBB-LABEL: vwsll_vi_nxv8i16:630; CHECK-ZVBB: # %bb.0:631; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma632; CHECK-ZVBB-NEXT: vmv1r.v v10, v8633; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2634; CHECK-ZVBB-NEXT: ret635 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>636 %z = shl <vscale x 8 x i16> %x, splat (i16 2)637 ret <vscale x 8 x i16> %z638}639 640; ==============================================================================641; i8 -> i64642; ==============================================================================643 644define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {645; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:646; CHECK: # %bb.0:647; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma648; CHECK-NEXT: vzext.vf8 v10, v8649; CHECK-NEXT: vsext.vf8 v12, v9650; CHECK-NEXT: vsll.vv v8, v10, v12651; CHECK-NEXT: ret652;653; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:654; CHECK-ZVBB: # %bb.0:655; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma656; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8657; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9658; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12659; CHECK-ZVBB-NEXT: ret660 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>661 %y = sext <vscale x 2 x i8> %b to <vscale x 2 x i64>662 %z = shl <vscale x 2 x i64> %x, %y663 ret <vscale x 2 x i64> %z664}665 666define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {667; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:668; CHECK: # %bb.0:669; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma670; CHECK-NEXT: vzext.vf8 v10, v8671; CHECK-NEXT: vzext.vf8 v12, v9672; CHECK-NEXT: vsll.vv v8, v10, v12673; CHECK-NEXT: ret674;675; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:676; CHECK-ZVBB: # %bb.0:677; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma678; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8679; CHECK-ZVBB-NEXT: vzext.vf4 v11, v9680; CHECK-ZVBB-NEXT: vwsll.vv v8, v10, v11681; CHECK-ZVBB-NEXT: ret682 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>683 %y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64>684 %z = shl <vscale x 2 x i64> %x, %y685 ret <vscale x 2 x i64> %z686}687 688define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64_nxv2i8(<vscale x 2 x i8> %a, i64 %b) {689; CHECK-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:690; CHECK: # %bb.0:691; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma692; CHECK-NEXT: vzext.vf8 v10, v8693; CHECK-NEXT: vsll.vx v8, v10, a0694; CHECK-NEXT: ret695;696; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:697; CHECK-ZVBB: # %bb.0:698; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma699; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8700; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0701; CHECK-ZVBB-NEXT: ret702 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0703 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer704 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>705 %z = shl <vscale x 2 x i64> %x, %splat706 ret <vscale x 2 x i64> %z707}708 709define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i32 %b) {710; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma713; CHECK-NEXT: vmv.v.x v12, a0714; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma715; CHECK-NEXT: vzext.vf8 v10, v8716; CHECK-NEXT: vsext.vf2 v8, v12717; CHECK-NEXT: vsll.vv v8, v10, v8718; CHECK-NEXT: ret719;720; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:721; CHECK-ZVBB: # %bb.0:722; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma723; CHECK-ZVBB-NEXT: vmv.v.x v12, a0724; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma725; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8726; CHECK-ZVBB-NEXT: vsext.vf2 v8, v12727; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8728; CHECK-ZVBB-NEXT: ret729 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0730 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer731 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>732 %y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>733 %z = shl <vscale x 2 x i64> %x, %y734 ret <vscale x 2 x i64> %z735}736 737define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i32 %b) {738; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:739; CHECK: # %bb.0:740; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma741; CHECK-NEXT: vmv.v.x v12, a0742; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma743; CHECK-NEXT: vzext.vf8 v10, v8744; CHECK-NEXT: vzext.vf2 v8, v12745; CHECK-NEXT: vsll.vv v8, v10, v8746; CHECK-NEXT: ret747;748; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:749; CHECK-ZVBB: # %bb.0:750; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma751; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8752; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0753; CHECK-ZVBB-NEXT: ret754 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0755 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer756 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>757 %y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>758 %z = shl <vscale x 2 x i64> %x, %y759 ret <vscale x 2 x i64> %z760}761 762define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i16 %b) {763; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:764; CHECK: # %bb.0:765; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma766; CHECK-NEXT: vmv.v.x v12, a0767; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma768; CHECK-NEXT: vzext.vf8 v10, v8769; CHECK-NEXT: vsext.vf4 v8, v12770; CHECK-NEXT: vsll.vv v8, v10, v8771; CHECK-NEXT: ret772;773; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:774; CHECK-ZVBB: # %bb.0:775; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma776; CHECK-ZVBB-NEXT: vmv.v.x v12, a0777; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma778; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8779; CHECK-ZVBB-NEXT: vsext.vf4 v8, v12780; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8781; CHECK-ZVBB-NEXT: ret782 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0783 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer784 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>785 %y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>786 %z = shl <vscale x 2 x i64> %x, %y787 ret <vscale x 2 x i64> %z788}789 790define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i16 %b) {791; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:792; CHECK: # %bb.0:793; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma794; CHECK-NEXT: vmv.v.x v12, a0795; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma796; CHECK-NEXT: vzext.vf8 v10, v8797; CHECK-NEXT: vzext.vf4 v8, v12798; CHECK-NEXT: vsll.vv v8, v10, v8799; CHECK-NEXT: ret800;801; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:802; CHECK-ZVBB: # %bb.0:803; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma804; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8805; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0806; CHECK-ZVBB-NEXT: ret807 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0808 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer809 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>810 %y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>811 %z = shl <vscale x 2 x i64> %x, %y812 ret <vscale x 2 x i64> %z813}814 815define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i8 %b) {816; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:817; CHECK: # %bb.0:818; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma819; CHECK-NEXT: vmv.v.x v12, a0820; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma821; CHECK-NEXT: vzext.vf8 v10, v8822; CHECK-NEXT: vsext.vf8 v8, v12823; CHECK-NEXT: vsll.vv v8, v10, v8824; CHECK-NEXT: ret825;826; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:827; CHECK-ZVBB: # %bb.0:828; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma829; CHECK-ZVBB-NEXT: vmv.v.x v12, a0830; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma831; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8832; CHECK-ZVBB-NEXT: vsext.vf8 v8, v12833; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v8834; CHECK-ZVBB-NEXT: ret835 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0836 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer837 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>838 %y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>839 %z = shl <vscale x 2 x i64> %x, %y840 ret <vscale x 2 x i64> %z841}842 843define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i8 %b) {844; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:845; CHECK: # %bb.0:846; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma847; CHECK-NEXT: vmv.v.x v12, a0848; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma849; CHECK-NEXT: vzext.vf8 v10, v8850; CHECK-NEXT: vzext.vf8 v8, v12851; CHECK-NEXT: vsll.vv v8, v10, v8852; CHECK-NEXT: ret853;854; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:855; CHECK-ZVBB: # %bb.0:856; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma857; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8858; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0859; CHECK-ZVBB-NEXT: ret860 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0861 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer862 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>863 %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>864 %z = shl <vscale x 2 x i64> %x, %y865 ret <vscale x 2 x i64> %z866}867 868define <vscale x 2 x i64> @vwsll_vi_nxv2i64_nxv2i8(<vscale x 2 x i8> %a) {869; CHECK-LABEL: vwsll_vi_nxv2i64_nxv2i8:870; CHECK: # %bb.0:871; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma872; CHECK-NEXT: vzext.vf8 v10, v8873; CHECK-NEXT: vsll.vi v8, v10, 2874; CHECK-NEXT: ret875;876; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:877; CHECK-ZVBB: # %bb.0:878; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma879; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8880; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2881; CHECK-ZVBB-NEXT: ret882 %x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>883 %z = shl <vscale x 2 x i64> %x, splat (i64 2)884 ret <vscale x 2 x i64> %z885}886;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:887; RV32ZVBB: {{.*}}888; RV64ZVBB: {{.*}}889