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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB325; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB646 7; ==============================================================================8; i32 -> i649; ==============================================================================10 11define <vscale x 2 x i64> @vwsll_vv_nxv2i64_sext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {12; CHECK-LABEL: vwsll_vv_nxv2i64_sext:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma15; CHECK-NEXT: vzext.vf2 v10, v816; CHECK-NEXT: vsext.vf2 v12, v917; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t18; CHECK-NEXT: ret19;20; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_sext:21; CHECK-ZVBB: # %bb.0:22; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma23; CHECK-ZVBB-NEXT: vmv1r.v v10, v924; CHECK-ZVBB-NEXT: vmv1r.v v11, v825; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10, v0.t26; CHECK-ZVBB-NEXT: ret27 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>28 %y = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>29 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)30 ret <vscale x 2 x i64> %z31}32 33define <vscale x 2 x i64> @vwsll_vv_nxv2i64_zext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {34; CHECK-LABEL: vwsll_vv_nxv2i64_zext:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma37; CHECK-NEXT: vzext.vf2 v10, v838; CHECK-NEXT: vzext.vf2 v12, v939; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t40; CHECK-NEXT: ret41;42; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_zext:43; CHECK-ZVBB: # %bb.0:44; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma45; CHECK-ZVBB-NEXT: vmv1r.v v10, v946; CHECK-ZVBB-NEXT: vmv1r.v v11, v847; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10, v0.t48; CHECK-ZVBB-NEXT: ret49 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>50 %y = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>51 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)52 ret <vscale x 2 x i64> %z53}54 55define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64(<vscale x 2 x i32> %a, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {56; CHECK-RV32-LABEL: vwsll_vx_i64_nxv2i64:57; CHECK-RV32: # %bb.0:58; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma59; CHECK-RV32-NEXT: vzext.vf2 v10, v860; CHECK-RV32-NEXT: vsll.vx v8, v10, a0, v0.t61; CHECK-RV32-NEXT: ret62;63; CHECK-RV64-LABEL: vwsll_vx_i64_nxv2i64:64; CHECK-RV64: # %bb.0:65; CHECK-RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma66; CHECK-RV64-NEXT: vzext.vf2 v10, v867; CHECK-RV64-NEXT: vsll.vx v8, v10, a0, v0.t68; CHECK-RV64-NEXT: ret69;70; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv2i64:71; CHECK-ZVBB32: # %bb.0:72; CHECK-ZVBB32-NEXT: vsetvli zero, a2, e32, m1, ta, ma73; CHECK-ZVBB32-NEXT: vmv1r.v v10, v874; CHECK-ZVBB32-NEXT: vwsll.vx v8, v10, a0, v0.t75; CHECK-ZVBB32-NEXT: ret76;77; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv2i64:78; CHECK-ZVBB64: # %bb.0:79; CHECK-ZVBB64-NEXT: vsetvli zero, a1, e32, m1, ta, ma80; CHECK-ZVBB64-NEXT: vmv1r.v v10, v881; CHECK-ZVBB64-NEXT: vwsll.vx v8, v10, a0, v0.t82; CHECK-ZVBB64-NEXT: ret83 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 084 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer85 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>86 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %splat, <vscale x 2 x i1> %m, i32 %vl)87 ret <vscale x 2 x i64> %z88}89 90define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_sext(<vscale x 2 x i32> %a, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {91; CHECK-LABEL: vwsll_vx_i32_nxv2i64_sext:92; CHECK: # %bb.0:93; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma94; CHECK-NEXT: vmv.v.x v12, a095; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma96; CHECK-NEXT: vzext.vf2 v10, v897; CHECK-NEXT: vsext.vf2 v8, v1298; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t99; CHECK-NEXT: ret100;101; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_sext:102; CHECK-ZVBB: # %bb.0:103; CHECK-ZVBB-NEXT: vsetvli zero, a1, e32, m1, ta, ma104; CHECK-ZVBB-NEXT: vmv1r.v v10, v8105; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t106; CHECK-ZVBB-NEXT: ret107 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0108 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer109 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>110 %y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>111 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)112 ret <vscale x 2 x i64> %z113}114 115define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_zext(<vscale x 2 x i32> %a, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {116; CHECK-LABEL: vwsll_vx_i32_nxv2i64_zext:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma119; CHECK-NEXT: vmv.v.x v12, a0120; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma121; CHECK-NEXT: vzext.vf2 v10, v8122; CHECK-NEXT: vzext.vf2 v8, v12123; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t124; CHECK-NEXT: ret125;126; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_zext:127; CHECK-ZVBB: # %bb.0:128; CHECK-ZVBB-NEXT: vsetvli zero, a1, e32, m1, ta, ma129; CHECK-ZVBB-NEXT: vmv1r.v v10, v8130; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t131; CHECK-ZVBB-NEXT: ret132 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0133 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer134 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>135 %y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>136 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)137 ret <vscale x 2 x i64> %z138}139 140define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_sext(<vscale x 2 x i32> %a, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {141; CHECK-LABEL: vwsll_vx_i16_nxv2i64_sext:142; CHECK: # %bb.0:143; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma144; CHECK-NEXT: vmv.v.x v12, a0145; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma146; CHECK-NEXT: vzext.vf2 v10, v8147; CHECK-NEXT: vsext.vf4 v8, v12148; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t149; CHECK-NEXT: ret150;151; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_sext:152; CHECK-ZVBB: # %bb.0:153; CHECK-ZVBB-NEXT: vsetvli zero, a1, e32, m1, ta, ma154; CHECK-ZVBB-NEXT: vmv1r.v v10, v8155; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t156; CHECK-ZVBB-NEXT: ret157 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0158 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer159 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>160 %y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>161 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)162 ret <vscale x 2 x i64> %z163}164 165define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_zext(<vscale x 2 x i32> %a, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {166; CHECK-LABEL: vwsll_vx_i16_nxv2i64_zext:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma169; CHECK-NEXT: vmv.v.x v12, a0170; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma171; CHECK-NEXT: vzext.vf2 v10, v8172; CHECK-NEXT: vzext.vf4 v8, v12173; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t174; CHECK-NEXT: ret175;176; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_zext:177; CHECK-ZVBB: # %bb.0:178; CHECK-ZVBB-NEXT: vsetvli zero, a1, e32, m1, ta, ma179; CHECK-ZVBB-NEXT: vmv1r.v v10, v8180; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t181; CHECK-ZVBB-NEXT: ret182 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0183 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer184 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>185 %y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>186 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)187 ret <vscale x 2 x i64> %z188}189 190define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_sext(<vscale x 2 x i32> %a, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {191; CHECK-LABEL: vwsll_vx_i8_nxv2i64_sext:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma194; CHECK-NEXT: vmv.v.x v12, a0195; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma196; CHECK-NEXT: vzext.vf2 v10, v8197; CHECK-NEXT: vsext.vf8 v8, v12198; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t199; CHECK-NEXT: ret200;201; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_sext:202; CHECK-ZVBB: # %bb.0:203; CHECK-ZVBB-NEXT: vsetvli zero, a1, e32, m1, ta, ma204; CHECK-ZVBB-NEXT: vmv1r.v v10, v8205; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t206; CHECK-ZVBB-NEXT: ret207 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0208 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer209 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>210 %y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>211 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)212 ret <vscale x 2 x i64> %z213}214 215define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %vl) {216; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma219; CHECK-NEXT: vmv.v.x v12, a0220; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma221; CHECK-NEXT: vzext.vf2 v10, v8222; CHECK-NEXT: vzext.vf8 v8, v12223; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t224; CHECK-NEXT: ret225;226; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_zext:227; CHECK-ZVBB: # %bb.0:228; CHECK-ZVBB-NEXT: vsetvli zero, a1, e32, m1, ta, ma229; CHECK-ZVBB-NEXT: vmv1r.v v10, v8230; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t231; CHECK-ZVBB-NEXT: ret232 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0233 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer234 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>235 %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>236 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m, i32 %vl)237 ret <vscale x 2 x i64> %z238}239 240define <vscale x 2 x i64> @vwsll_vi_nxv2i64(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {241; CHECK-LABEL: vwsll_vi_nxv2i64:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma244; CHECK-NEXT: vmv1r.v v10, v8245; CHECK-NEXT: li a0, 4246; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t247; CHECK-NEXT: ret248;249; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64:250; CHECK-ZVBB: # %bb.0:251; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma252; CHECK-ZVBB-NEXT: vmv1r.v v10, v8253; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2, v0.t254; CHECK-ZVBB-NEXT: ret255 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>256 %z = call <vscale x 2 x i64> @llvm.vp.shl.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> splat (i64 2), <vscale x 2 x i1> %m, i32 %vl)257 ret <vscale x 2 x i64> %z258}259 260; ==============================================================================261; i16 -> i32262; ==============================================================================263 264define <vscale x 4 x i32> @vwsll_vv_nxv4i32_sext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {265; CHECK-LABEL: vwsll_vv_nxv4i32_sext:266; CHECK: # %bb.0:267; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma268; CHECK-NEXT: vzext.vf2 v10, v8269; CHECK-NEXT: vsext.vf2 v12, v9270; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t271; CHECK-NEXT: ret272;273; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_sext:274; CHECK-ZVBB: # %bb.0:275; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma276; CHECK-ZVBB-NEXT: vmv1r.v v10, v9277; CHECK-ZVBB-NEXT: vmv1r.v v11, v8278; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10, v0.t279; CHECK-ZVBB-NEXT: ret280 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>281 %y = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>282 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)283 ret <vscale x 4 x i32> %z284}285 286define <vscale x 4 x i32> @vwsll_vv_nxv4i32_zext(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {287; CHECK-LABEL: vwsll_vv_nxv4i32_zext:288; CHECK: # %bb.0:289; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma290; CHECK-NEXT: vzext.vf2 v10, v8291; CHECK-NEXT: vzext.vf2 v12, v9292; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t293; CHECK-NEXT: ret294;295; CHECK-ZVBB-LABEL: vwsll_vv_nxv4i32_zext:296; CHECK-ZVBB: # %bb.0:297; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma298; CHECK-ZVBB-NEXT: vmv1r.v v10, v9299; CHECK-ZVBB-NEXT: vmv1r.v v11, v8300; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10, v0.t301; CHECK-ZVBB-NEXT: ret302 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>303 %y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>304 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)305 ret <vscale x 4 x i32> %z306}307 308define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {309; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32:310; CHECK-RV32: # %bb.0:311; CHECK-RV32-NEXT: vsetvli zero, a2, e32, m2, ta, ma312; CHECK-RV32-NEXT: vzext.vf2 v10, v8313; CHECK-RV32-NEXT: vsll.vx v8, v10, a0, v0.t314; CHECK-RV32-NEXT: ret315;316; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32:317; CHECK-RV64: # %bb.0:318; CHECK-RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma319; CHECK-RV64-NEXT: vzext.vf2 v10, v8320; CHECK-RV64-NEXT: vsll.vx v8, v10, a0, v0.t321; CHECK-RV64-NEXT: ret322;323; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32:324; CHECK-ZVBB32: # %bb.0:325; CHECK-ZVBB32-NEXT: vsetvli zero, a2, e16, m1, ta, ma326; CHECK-ZVBB32-NEXT: vmv1r.v v10, v8327; CHECK-ZVBB32-NEXT: vwsll.vx v8, v10, a0, v0.t328; CHECK-ZVBB32-NEXT: ret329;330; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32:331; CHECK-ZVBB64: # %bb.0:332; CHECK-ZVBB64-NEXT: vsetvli zero, a1, e16, m1, ta, ma333; CHECK-ZVBB64-NEXT: vmv1r.v v10, v8334; CHECK-ZVBB64-NEXT: vwsll.vx v8, v10, a0, v0.t335; CHECK-ZVBB64-NEXT: ret336 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0337 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer338 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>339 %y = trunc <vscale x 4 x i64> %splat to <vscale x 4 x i32>340 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)341 ret <vscale x 4 x i32> %z342}343 344define <vscale x 4 x i32> @vwsll_vx_i32_nxv4i32(<vscale x 4 x i16> %a, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {345; CHECK-LABEL: vwsll_vx_i32_nxv4i32:346; CHECK: # %bb.0:347; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma348; CHECK-NEXT: vzext.vf2 v10, v8349; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t350; CHECK-NEXT: ret351;352; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv4i32:353; CHECK-ZVBB: # %bb.0:354; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m1, ta, ma355; CHECK-ZVBB-NEXT: vmv1r.v v10, v8356; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t357; CHECK-ZVBB-NEXT: ret358 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0359 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer360 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>361 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %splat, <vscale x 4 x i1> %m, i32 %vl)362 ret <vscale x 4 x i32> %z363}364 365define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_sext(<vscale x 4 x i16> %a, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {366; CHECK-LABEL: vwsll_vx_i16_nxv4i32_sext:367; CHECK: # %bb.0:368; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma369; CHECK-NEXT: vmv.v.x v12, a0370; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma371; CHECK-NEXT: vzext.vf2 v10, v8372; CHECK-NEXT: vsext.vf2 v8, v12373; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t374; CHECK-NEXT: ret375;376; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_sext:377; CHECK-ZVBB: # %bb.0:378; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m1, ta, ma379; CHECK-ZVBB-NEXT: vmv1r.v v10, v8380; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t381; CHECK-ZVBB-NEXT: ret382 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0383 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer384 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>385 %y = sext <vscale x 4 x i16> %splat to <vscale x 4 x i32>386 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)387 ret <vscale x 4 x i32> %z388}389 390define <vscale x 4 x i32> @vwsll_vx_i16_nxv4i32_zext(<vscale x 4 x i16> %a, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {391; CHECK-LABEL: vwsll_vx_i16_nxv4i32_zext:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma394; CHECK-NEXT: vmv.v.x v12, a0395; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma396; CHECK-NEXT: vzext.vf2 v10, v8397; CHECK-NEXT: vzext.vf2 v8, v12398; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t399; CHECK-NEXT: ret400;401; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv4i32_zext:402; CHECK-ZVBB: # %bb.0:403; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m1, ta, ma404; CHECK-ZVBB-NEXT: vmv1r.v v10, v8405; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t406; CHECK-ZVBB-NEXT: ret407 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0408 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer409 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>410 %y = zext <vscale x 4 x i16> %splat to <vscale x 4 x i32>411 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)412 ret <vscale x 4 x i32> %z413}414 415define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_sext(<vscale x 4 x i16> %a, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {416; CHECK-LABEL: vwsll_vx_i8_nxv4i32_sext:417; CHECK: # %bb.0:418; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma419; CHECK-NEXT: vmv.v.x v12, a0420; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma421; CHECK-NEXT: vzext.vf2 v10, v8422; CHECK-NEXT: vsext.vf4 v8, v12423; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t424; CHECK-NEXT: ret425;426; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_sext:427; CHECK-ZVBB: # %bb.0:428; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m1, ta, ma429; CHECK-ZVBB-NEXT: vmv1r.v v10, v8430; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t431; CHECK-ZVBB-NEXT: ret432 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0433 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer434 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>435 %y = sext <vscale x 4 x i8> %splat to <vscale x 4 x i32>436 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)437 ret <vscale x 4 x i32> %z438}439 440define <vscale x 4 x i32> @vwsll_vx_i8_nxv4i32_zext(<vscale x 4 x i16> %a, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {441; CHECK-LABEL: vwsll_vx_i8_nxv4i32_zext:442; CHECK: # %bb.0:443; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma444; CHECK-NEXT: vmv.v.x v12, a0445; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma446; CHECK-NEXT: vzext.vf2 v10, v8447; CHECK-NEXT: vzext.vf4 v8, v12448; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t449; CHECK-NEXT: ret450;451; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv4i32_zext:452; CHECK-ZVBB: # %bb.0:453; CHECK-ZVBB-NEXT: vsetvli zero, a1, e16, m1, ta, ma454; CHECK-ZVBB-NEXT: vmv1r.v v10, v8455; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t456; CHECK-ZVBB-NEXT: ret457 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0458 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer459 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>460 %y = zext <vscale x 4 x i8> %splat to <vscale x 4 x i32>461 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)462 ret <vscale x 4 x i32> %z463}464 465define <vscale x 4 x i32> @vwsll_vi_nxv4i32(<vscale x 4 x i16> %a, <vscale x 4 x i1> %m, i32 zeroext %vl) {466; CHECK-LABEL: vwsll_vi_nxv4i32:467; CHECK: # %bb.0:468; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma469; CHECK-NEXT: vmv1r.v v10, v8470; CHECK-NEXT: li a0, 4471; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t472; CHECK-NEXT: ret473;474; CHECK-ZVBB-LABEL: vwsll_vi_nxv4i32:475; CHECK-ZVBB: # %bb.0:476; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma477; CHECK-ZVBB-NEXT: vmv1r.v v10, v8478; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2, v0.t479; CHECK-ZVBB-NEXT: ret480 %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>481 %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> splat (i32 2), <vscale x 4 x i1> %m, i32 %vl)482 ret <vscale x 4 x i32> %z483}484 485; ==============================================================================486; i8 -> i16487; ==============================================================================488 489define <vscale x 8 x i16> @vwsll_vv_nxv8i16_sext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {490; CHECK-LABEL: vwsll_vv_nxv8i16_sext:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma493; CHECK-NEXT: vzext.vf2 v10, v8494; CHECK-NEXT: vsext.vf2 v12, v9495; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t496; CHECK-NEXT: ret497;498; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_sext:499; CHECK-ZVBB: # %bb.0:500; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma501; CHECK-ZVBB-NEXT: vmv1r.v v10, v9502; CHECK-ZVBB-NEXT: vmv1r.v v11, v8503; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10, v0.t504; CHECK-ZVBB-NEXT: ret505 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>506 %y = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>507 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)508 ret <vscale x 8 x i16> %z509}510 511define <vscale x 8 x i16> @vwsll_vv_nxv8i16_zext(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {512; CHECK-LABEL: vwsll_vv_nxv8i16_zext:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma515; CHECK-NEXT: vzext.vf2 v10, v8516; CHECK-NEXT: vzext.vf2 v12, v9517; CHECK-NEXT: vsll.vv v8, v10, v12, v0.t518; CHECK-NEXT: ret519;520; CHECK-ZVBB-LABEL: vwsll_vv_nxv8i16_zext:521; CHECK-ZVBB: # %bb.0:522; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma523; CHECK-ZVBB-NEXT: vmv1r.v v10, v9524; CHECK-ZVBB-NEXT: vmv1r.v v11, v8525; CHECK-ZVBB-NEXT: vwsll.vv v8, v11, v10, v0.t526; CHECK-ZVBB-NEXT: ret527 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>528 %y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>529 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)530 ret <vscale x 8 x i16> %z531}532 533define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {534; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16:535; CHECK-RV32: # %bb.0:536; CHECK-RV32-NEXT: vsetvli zero, a2, e16, m2, ta, ma537; CHECK-RV32-NEXT: vzext.vf2 v10, v8538; CHECK-RV32-NEXT: vsll.vx v8, v10, a0, v0.t539; CHECK-RV32-NEXT: ret540;541; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16:542; CHECK-RV64: # %bb.0:543; CHECK-RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma544; CHECK-RV64-NEXT: vzext.vf2 v10, v8545; CHECK-RV64-NEXT: vsll.vx v8, v10, a0, v0.t546; CHECK-RV64-NEXT: ret547;548; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16:549; CHECK-ZVBB32: # %bb.0:550; CHECK-ZVBB32-NEXT: vsetvli zero, a2, e8, m1, ta, ma551; CHECK-ZVBB32-NEXT: vmv1r.v v10, v8552; CHECK-ZVBB32-NEXT: vwsll.vx v8, v10, a0, v0.t553; CHECK-ZVBB32-NEXT: ret554;555; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16:556; CHECK-ZVBB64: # %bb.0:557; CHECK-ZVBB64-NEXT: vsetvli zero, a1, e8, m1, ta, ma558; CHECK-ZVBB64-NEXT: vmv1r.v v10, v8559; CHECK-ZVBB64-NEXT: vwsll.vx v8, v10, a0, v0.t560; CHECK-ZVBB64-NEXT: ret561 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0562 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer563 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>564 %y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16>565 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)566 ret <vscale x 8 x i16> %z567}568 569define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {570; CHECK-LABEL: vwsll_vx_i32_nxv8i16:571; CHECK: # %bb.0:572; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma573; CHECK-NEXT: vzext.vf2 v10, v8574; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t575; CHECK-NEXT: ret576;577; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16:578; CHECK-ZVBB: # %bb.0:579; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma580; CHECK-ZVBB-NEXT: vmv1r.v v10, v8581; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t582; CHECK-ZVBB-NEXT: ret583 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0584 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer585 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>586 %y = trunc <vscale x 8 x i32> %splat to <vscale x 8 x i16>587 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)588 ret <vscale x 8 x i16> %z589}590 591define <vscale x 8 x i16> @vwsll_vx_i16_nxv8i16(<vscale x 8 x i8> %a, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {592; CHECK-LABEL: vwsll_vx_i16_nxv8i16:593; CHECK: # %bb.0:594; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma595; CHECK-NEXT: vzext.vf2 v10, v8596; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t597; CHECK-NEXT: ret598;599; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv8i16:600; CHECK-ZVBB: # %bb.0:601; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma602; CHECK-ZVBB-NEXT: vmv1r.v v10, v8603; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t604; CHECK-ZVBB-NEXT: ret605 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0606 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer607 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>608 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %splat, <vscale x 8 x i1> %m, i32 %vl)609 ret <vscale x 8 x i16> %z610}611 612define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_sext(<vscale x 8 x i8> %a, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {613; CHECK-LABEL: vwsll_vx_i8_nxv8i16_sext:614; CHECK: # %bb.0:615; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma616; CHECK-NEXT: vmv.v.x v12, a0617; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma618; CHECK-NEXT: vzext.vf2 v10, v8619; CHECK-NEXT: vsext.vf2 v8, v12620; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t621; CHECK-NEXT: ret622;623; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_sext:624; CHECK-ZVBB: # %bb.0:625; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma626; CHECK-ZVBB-NEXT: vmv1r.v v10, v8627; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t628; CHECK-ZVBB-NEXT: ret629 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0630 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer631 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>632 %y = sext <vscale x 8 x i8> %splat to <vscale x 8 x i16>633 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)634 ret <vscale x 8 x i16> %z635}636 637define <vscale x 8 x i16> @vwsll_vx_i8_nxv8i16_zext(<vscale x 8 x i8> %a, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {638; CHECK-LABEL: vwsll_vx_i8_nxv8i16_zext:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma641; CHECK-NEXT: vmv.v.x v12, a0642; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma643; CHECK-NEXT: vzext.vf2 v10, v8644; CHECK-NEXT: vzext.vf2 v8, v12645; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t646; CHECK-NEXT: ret647;648; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv8i16_zext:649; CHECK-ZVBB: # %bb.0:650; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma651; CHECK-ZVBB-NEXT: vmv1r.v v10, v8652; CHECK-ZVBB-NEXT: vwsll.vx v8, v10, a0, v0.t653; CHECK-ZVBB-NEXT: ret654 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0655 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer656 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>657 %y = zext <vscale x 8 x i8> %splat to <vscale x 8 x i16>658 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)659 ret <vscale x 8 x i16> %z660}661 662define <vscale x 8 x i16> @vwsll_vi_nxv8i16(<vscale x 8 x i8> %a, <vscale x 8 x i1> %m, i32 zeroext %vl) {663; CHECK-LABEL: vwsll_vi_nxv8i16:664; CHECK: # %bb.0:665; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma666; CHECK-NEXT: vmv1r.v v10, v8667; CHECK-NEXT: li a0, 4668; CHECK-NEXT: vwmulu.vx v8, v10, a0, v0.t669; CHECK-NEXT: ret670;671; CHECK-ZVBB-LABEL: vwsll_vi_nxv8i16:672; CHECK-ZVBB: # %bb.0:673; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma674; CHECK-ZVBB-NEXT: vmv1r.v v10, v8675; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2, v0.t676; CHECK-ZVBB-NEXT: ret677 %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>678 %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> splat (i16 2), <vscale x 8 x i1> %m, i32 %vl)679 ret <vscale x 8 x i16> %z680}681