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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i64> @vwsub_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {6; CHECK-LABEL: vwsub_vv_nxv1i64_nxv1i32:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma9; CHECK-NEXT: vwsub.vv v10, v8, v910; CHECK-NEXT: vmv1r.v v8, v1011; CHECK-NEXT: ret12 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>13 %vd = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>14 %ve = sub <vscale x 1 x i64> %vc, %vd15 ret <vscale x 1 x i64> %ve16}17 18define <vscale x 1 x i64> @vwsubu_vv_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {19; CHECK-LABEL: vwsubu_vv_nxv1i64_nxv1i32:20; CHECK: # %bb.0:21; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma22; CHECK-NEXT: vwsubu.vv v10, v8, v923; CHECK-NEXT: vmv1r.v v8, v1024; CHECK-NEXT: ret25 %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>26 %vd = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>27 %ve = sub <vscale x 1 x i64> %vc, %vd28 ret <vscale x 1 x i64> %ve29}30 31define <vscale x 1 x i64> @vwsub_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {32; CHECK-LABEL: vwsub_vx_nxv1i64_nxv1i32:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma35; CHECK-NEXT: vwsub.vx v9, v8, a036; CHECK-NEXT: vmv1r.v v8, v937; CHECK-NEXT: ret38 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 039 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer40 %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>41 %vd = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>42 %ve = sub <vscale x 1 x i64> %vc, %vd43 ret <vscale x 1 x i64> %ve44}45 46define <vscale x 1 x i64> @vwsubu_vx_nxv1i64_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {47; CHECK-LABEL: vwsubu_vx_nxv1i64_nxv1i32:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma50; CHECK-NEXT: vwsubu.vx v9, v8, a051; CHECK-NEXT: vmv1r.v v8, v952; CHECK-NEXT: ret53 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 054 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer55 %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>56 %vd = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>57 %ve = sub <vscale x 1 x i64> %vc, %vd58 ret <vscale x 1 x i64> %ve59}60 61define <vscale x 1 x i64> @vwsub_wv_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {62; CHECK-LABEL: vwsub_wv_nxv1i64_nxv1i32:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma65; CHECK-NEXT: vwsub.wv v8, v8, v966; CHECK-NEXT: ret67 %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>68 %vd = sub <vscale x 1 x i64> %va, %vc69 ret <vscale x 1 x i64> %vd70}71 72define <vscale x 1 x i64> @vwsubu_wv_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {73; CHECK-LABEL: vwsubu_wv_nxv1i64_nxv1i32:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma76; CHECK-NEXT: vwsubu.wv v8, v8, v977; CHECK-NEXT: ret78 %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>79 %vd = sub <vscale x 1 x i64> %va, %vc80 ret <vscale x 1 x i64> %vd81}82 83define <vscale x 1 x i64> @vwsub_wx_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, i32 %b) {84; CHECK-LABEL: vwsub_wx_nxv1i64_nxv1i32:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma87; CHECK-NEXT: vwsub.wx v8, v8, a088; CHECK-NEXT: ret89 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 090 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer91 %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>92 %vc = sub <vscale x 1 x i64> %va, %vb93 ret <vscale x 1 x i64> %vc94}95 96define <vscale x 1 x i64> @vwsubu_wx_nxv1i64_nxv1i32(<vscale x 1 x i64> %va, i32 %b) {97; CHECK-LABEL: vwsubu_wx_nxv1i64_nxv1i32:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma100; CHECK-NEXT: vwsubu.wx v8, v8, a0101; CHECK-NEXT: ret102 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0103 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer104 %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>105 %vc = sub <vscale x 1 x i64> %va, %vb106 ret <vscale x 1 x i64> %vc107}108 109define <vscale x 2 x i64> @vwsub_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {110; CHECK-LABEL: vwsub_vv_nxv2i64_nxv2i32:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma113; CHECK-NEXT: vmv1r.v v10, v9114; CHECK-NEXT: vmv1r.v v11, v8115; CHECK-NEXT: vwsub.vv v8, v11, v10116; CHECK-NEXT: ret117 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>118 %vd = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>119 %ve = sub <vscale x 2 x i64> %vc, %vd120 ret <vscale x 2 x i64> %ve121}122 123define <vscale x 2 x i64> @vwsubu_vv_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {124; CHECK-LABEL: vwsubu_vv_nxv2i64_nxv2i32:125; CHECK: # %bb.0:126; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma127; CHECK-NEXT: vmv1r.v v10, v9128; CHECK-NEXT: vmv1r.v v11, v8129; CHECK-NEXT: vwsubu.vv v8, v11, v10130; CHECK-NEXT: ret131 %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>132 %vd = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>133 %ve = sub <vscale x 2 x i64> %vc, %vd134 ret <vscale x 2 x i64> %ve135}136 137define <vscale x 2 x i64> @vwsub_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {138; CHECK-LABEL: vwsub_vx_nxv2i64_nxv2i32:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma141; CHECK-NEXT: vmv1r.v v10, v8142; CHECK-NEXT: vwsub.vx v8, v10, a0143; CHECK-NEXT: ret144 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0145 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer146 %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>147 %vd = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>148 %ve = sub <vscale x 2 x i64> %vc, %vd149 ret <vscale x 2 x i64> %ve150}151 152define <vscale x 2 x i64> @vwsubu_vx_nxv2i64_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {153; CHECK-LABEL: vwsubu_vx_nxv2i64_nxv2i32:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma156; CHECK-NEXT: vmv1r.v v10, v8157; CHECK-NEXT: vwsubu.vx v8, v10, a0158; CHECK-NEXT: ret159 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0160 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer161 %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>162 %vd = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>163 %ve = sub <vscale x 2 x i64> %vc, %vd164 ret <vscale x 2 x i64> %ve165}166 167define <vscale x 2 x i64> @vwsub_wv_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {168; CHECK-LABEL: vwsub_wv_nxv2i64_nxv2i32:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma171; CHECK-NEXT: vwsub.wv v8, v8, v10172; CHECK-NEXT: ret173 %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>174 %vd = sub <vscale x 2 x i64> %va, %vc175 ret <vscale x 2 x i64> %vd176}177 178define <vscale x 2 x i64> @vwsubu_wv_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {179; CHECK-LABEL: vwsubu_wv_nxv2i64_nxv2i32:180; CHECK: # %bb.0:181; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma182; CHECK-NEXT: vwsubu.wv v8, v8, v10183; CHECK-NEXT: ret184 %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>185 %vd = sub <vscale x 2 x i64> %va, %vc186 ret <vscale x 2 x i64> %vd187}188 189define <vscale x 2 x i64> @vwsub_wx_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, i32 %b) {190; CHECK-LABEL: vwsub_wx_nxv2i64_nxv2i32:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma193; CHECK-NEXT: vwsub.wx v8, v8, a0194; CHECK-NEXT: ret195 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0196 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer197 %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>198 %vc = sub <vscale x 2 x i64> %va, %vb199 ret <vscale x 2 x i64> %vc200}201 202define <vscale x 2 x i64> @vwsubu_wx_nxv2i64_nxv2i32(<vscale x 2 x i64> %va, i32 %b) {203; CHECK-LABEL: vwsubu_wx_nxv2i64_nxv2i32:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma206; CHECK-NEXT: vwsubu.wx v8, v8, a0207; CHECK-NEXT: ret208 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0209 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer210 %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>211 %vc = sub <vscale x 2 x i64> %va, %vb212 ret <vscale x 2 x i64> %vc213}214 215define <vscale x 4 x i64> @vwsub_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {216; CHECK-LABEL: vwsub_vv_nxv4i64_nxv4i32:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma219; CHECK-NEXT: vmv2r.v v12, v10220; CHECK-NEXT: vmv2r.v v14, v8221; CHECK-NEXT: vwsub.vv v8, v14, v12222; CHECK-NEXT: ret223 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>224 %vd = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>225 %ve = sub <vscale x 4 x i64> %vc, %vd226 ret <vscale x 4 x i64> %ve227}228 229define <vscale x 4 x i64> @vwsubu_vv_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {230; CHECK-LABEL: vwsubu_vv_nxv4i64_nxv4i32:231; CHECK: # %bb.0:232; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma233; CHECK-NEXT: vmv2r.v v12, v10234; CHECK-NEXT: vmv2r.v v14, v8235; CHECK-NEXT: vwsubu.vv v8, v14, v12236; CHECK-NEXT: ret237 %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>238 %vd = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>239 %ve = sub <vscale x 4 x i64> %vc, %vd240 ret <vscale x 4 x i64> %ve241}242 243define <vscale x 4 x i64> @vwsub_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {244; CHECK-LABEL: vwsub_vx_nxv4i64_nxv4i32:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma247; CHECK-NEXT: vmv2r.v v12, v8248; CHECK-NEXT: vwsub.vx v8, v12, a0249; CHECK-NEXT: ret250 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0251 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer252 %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>253 %vd = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>254 %ve = sub <vscale x 4 x i64> %vc, %vd255 ret <vscale x 4 x i64> %ve256}257 258define <vscale x 4 x i64> @vwsubu_vx_nxv4i64_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {259; CHECK-LABEL: vwsubu_vx_nxv4i64_nxv4i32:260; CHECK: # %bb.0:261; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma262; CHECK-NEXT: vmv2r.v v12, v8263; CHECK-NEXT: vwsubu.vx v8, v12, a0264; CHECK-NEXT: ret265 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0266 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer267 %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>268 %vd = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>269 %ve = sub <vscale x 4 x i64> %vc, %vd270 ret <vscale x 4 x i64> %ve271}272 273define <vscale x 4 x i64> @vwsub_wv_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {274; CHECK-LABEL: vwsub_wv_nxv4i64_nxv4i32:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma277; CHECK-NEXT: vwsub.wv v8, v8, v12278; CHECK-NEXT: ret279 %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>280 %vd = sub <vscale x 4 x i64> %va, %vc281 ret <vscale x 4 x i64> %vd282}283 284define <vscale x 4 x i64> @vwsubu_wv_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {285; CHECK-LABEL: vwsubu_wv_nxv4i64_nxv4i32:286; CHECK: # %bb.0:287; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma288; CHECK-NEXT: vwsubu.wv v8, v8, v12289; CHECK-NEXT: ret290 %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>291 %vd = sub <vscale x 4 x i64> %va, %vc292 ret <vscale x 4 x i64> %vd293}294 295define <vscale x 4 x i64> @vwsub_wx_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, i32 %b) {296; CHECK-LABEL: vwsub_wx_nxv4i64_nxv4i32:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma299; CHECK-NEXT: vwsub.wx v8, v8, a0300; CHECK-NEXT: ret301 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0302 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer303 %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>304 %vc = sub <vscale x 4 x i64> %va, %vb305 ret <vscale x 4 x i64> %vc306}307 308define <vscale x 4 x i64> @vwsubu_wx_nxv4i64_nxv4i32(<vscale x 4 x i64> %va, i32 %b) {309; CHECK-LABEL: vwsubu_wx_nxv4i64_nxv4i32:310; CHECK: # %bb.0:311; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma312; CHECK-NEXT: vwsubu.wx v8, v8, a0313; CHECK-NEXT: ret314 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0315 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer316 %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>317 %vc = sub <vscale x 4 x i64> %va, %vb318 ret <vscale x 4 x i64> %vc319}320 321define <vscale x 8 x i64> @vwsub_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {322; CHECK-LABEL: vwsub_vv_nxv8i64_nxv8i32:323; CHECK: # %bb.0:324; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma325; CHECK-NEXT: vmv4r.v v16, v12326; CHECK-NEXT: vmv4r.v v20, v8327; CHECK-NEXT: vwsub.vv v8, v20, v16328; CHECK-NEXT: ret329 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>330 %vd = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>331 %ve = sub <vscale x 8 x i64> %vc, %vd332 ret <vscale x 8 x i64> %ve333}334 335define <vscale x 8 x i64> @vwsubu_vv_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {336; CHECK-LABEL: vwsubu_vv_nxv8i64_nxv8i32:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma339; CHECK-NEXT: vmv4r.v v16, v12340; CHECK-NEXT: vmv4r.v v20, v8341; CHECK-NEXT: vwsubu.vv v8, v20, v16342; CHECK-NEXT: ret343 %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>344 %vd = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>345 %ve = sub <vscale x 8 x i64> %vc, %vd346 ret <vscale x 8 x i64> %ve347}348 349define <vscale x 8 x i64> @vwsub_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {350; CHECK-LABEL: vwsub_vx_nxv8i64_nxv8i32:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma353; CHECK-NEXT: vmv4r.v v16, v8354; CHECK-NEXT: vwsub.vx v8, v16, a0355; CHECK-NEXT: ret356 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0357 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer358 %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>359 %vd = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>360 %ve = sub <vscale x 8 x i64> %vc, %vd361 ret <vscale x 8 x i64> %ve362}363 364define <vscale x 8 x i64> @vwsubu_vx_nxv8i64_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {365; CHECK-LABEL: vwsubu_vx_nxv8i64_nxv8i32:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma368; CHECK-NEXT: vmv4r.v v16, v8369; CHECK-NEXT: vwsubu.vx v8, v16, a0370; CHECK-NEXT: ret371 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0372 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer373 %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>374 %vd = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>375 %ve = sub <vscale x 8 x i64> %vc, %vd376 ret <vscale x 8 x i64> %ve377}378 379define <vscale x 8 x i64> @vwsub_wv_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {380; CHECK-LABEL: vwsub_wv_nxv8i64_nxv8i32:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma383; CHECK-NEXT: vwsub.wv v8, v8, v16384; CHECK-NEXT: ret385 %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>386 %vd = sub <vscale x 8 x i64> %va, %vc387 ret <vscale x 8 x i64> %vd388}389 390define <vscale x 8 x i64> @vwsubu_wv_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {391; CHECK-LABEL: vwsubu_wv_nxv8i64_nxv8i32:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma394; CHECK-NEXT: vwsubu.wv v8, v8, v16395; CHECK-NEXT: ret396 %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>397 %vd = sub <vscale x 8 x i64> %va, %vc398 ret <vscale x 8 x i64> %vd399}400 401define <vscale x 8 x i64> @vwsub_wx_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, i32 %b) {402; CHECK-LABEL: vwsub_wx_nxv8i64_nxv8i32:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma405; CHECK-NEXT: vwsub.wx v8, v8, a0406; CHECK-NEXT: ret407 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0408 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer409 %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>410 %vc = sub <vscale x 8 x i64> %va, %vb411 ret <vscale x 8 x i64> %vc412}413 414define <vscale x 8 x i64> @vwsubu_wx_nxv8i64_nxv8i32(<vscale x 8 x i64> %va, i32 %b) {415; CHECK-LABEL: vwsubu_wx_nxv8i64_nxv8i32:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma418; CHECK-NEXT: vwsubu.wx v8, v8, a0419; CHECK-NEXT: ret420 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0421 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer422 %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>423 %vc = sub <vscale x 8 x i64> %va, %vb424 ret <vscale x 8 x i64> %vc425}426 427define <vscale x 1 x i64> @vwsub_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {428; CHECK-LABEL: vwsub_vv_nxv1i64_nxv1i16:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma431; CHECK-NEXT: vsext.vf2 v10, v8432; CHECK-NEXT: vsext.vf2 v11, v9433; CHECK-NEXT: vwsub.vv v8, v10, v11434; CHECK-NEXT: ret435 %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>436 %vd = sext <vscale x 1 x i16> %vb to <vscale x 1 x i64>437 %ve = sub <vscale x 1 x i64> %vc, %vd438 ret <vscale x 1 x i64> %ve439}440 441define <vscale x 1 x i64> @vwsubu_vv_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {442; CHECK-LABEL: vwsubu_vv_nxv1i64_nxv1i16:443; CHECK: # %bb.0:444; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma445; CHECK-NEXT: vwsubu.vv v10, v8, v9446; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma447; CHECK-NEXT: vsext.vf2 v8, v10448; CHECK-NEXT: ret449 %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>450 %vd = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>451 %ve = sub <vscale x 1 x i64> %vc, %vd452 ret <vscale x 1 x i64> %ve453}454 455define <vscale x 1 x i64> @vwsub_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {456; CHECK-LABEL: vwsub_vx_nxv1i64_nxv1i16:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma459; CHECK-NEXT: vmv.v.x v9, a0460; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma461; CHECK-NEXT: vsext.vf2 v10, v8462; CHECK-NEXT: vsext.vf2 v11, v9463; CHECK-NEXT: vwsub.vv v8, v10, v11464; CHECK-NEXT: ret465 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0466 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer467 %vc = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>468 %vd = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>469 %ve = sub <vscale x 1 x i64> %vc, %vd470 ret <vscale x 1 x i64> %ve471}472 473define <vscale x 1 x i64> @vwsubu_vx_nxv1i64_nxv1i16(<vscale x 1 x i16> %va, i16 %b) {474; CHECK-LABEL: vwsubu_vx_nxv1i64_nxv1i16:475; CHECK: # %bb.0:476; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma477; CHECK-NEXT: vwsubu.vx v9, v8, a0478; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma479; CHECK-NEXT: vsext.vf2 v8, v9480; CHECK-NEXT: ret481 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0482 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer483 %vc = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>484 %vd = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>485 %ve = sub <vscale x 1 x i64> %vc, %vd486 ret <vscale x 1 x i64> %ve487}488 489define <vscale x 1 x i64> @vwsub_wv_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, <vscale x 1 x i16> %vb) {490; CHECK-LABEL: vwsub_wv_nxv1i64_nxv1i16:491; CHECK: # %bb.0:492; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma493; CHECK-NEXT: vsext.vf2 v10, v9494; CHECK-NEXT: vwsub.wv v8, v8, v10495; CHECK-NEXT: ret496 %vc = sext <vscale x 1 x i16> %vb to <vscale x 1 x i64>497 %vd = sub <vscale x 1 x i64> %va, %vc498 ret <vscale x 1 x i64> %vd499}500 501define <vscale x 1 x i64> @vwsubu_wv_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, <vscale x 1 x i16> %vb) {502; CHECK-LABEL: vwsubu_wv_nxv1i64_nxv1i16:503; CHECK: # %bb.0:504; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma505; CHECK-NEXT: vzext.vf2 v10, v9506; CHECK-NEXT: vwsubu.wv v8, v8, v10507; CHECK-NEXT: ret508 %vc = zext <vscale x 1 x i16> %vb to <vscale x 1 x i64>509 %vd = sub <vscale x 1 x i64> %va, %vc510 ret <vscale x 1 x i64> %vd511}512 513define <vscale x 1 x i64> @vwsub_wx_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, i16 %b) {514; CHECK-LABEL: vwsub_wx_nxv1i64_nxv1i16:515; CHECK: # %bb.0:516; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma517; CHECK-NEXT: vmv.v.x v9, a0518; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma519; CHECK-NEXT: vsext.vf2 v10, v9520; CHECK-NEXT: vwsub.wv v8, v8, v10521; CHECK-NEXT: ret522 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0523 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer524 %vb = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>525 %vc = sub <vscale x 1 x i64> %va, %vb526 ret <vscale x 1 x i64> %vc527}528 529define <vscale x 1 x i64> @vwsubu_wx_nxv1i64_nxv1i16(<vscale x 1 x i64> %va, i16 %b) {530; CHECK-LABEL: vwsubu_wx_nxv1i64_nxv1i16:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma533; CHECK-NEXT: vmv.v.x v9, a0534; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma535; CHECK-NEXT: vzext.vf2 v10, v9536; CHECK-NEXT: vwsubu.wv v8, v8, v10537; CHECK-NEXT: ret538 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i16 0539 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer540 %vb = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>541 %vc = sub <vscale x 1 x i64> %va, %vb542 ret <vscale x 1 x i64> %vc543}544 545define <vscale x 2 x i64> @vwsub_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {546; CHECK-LABEL: vwsub_vv_nxv2i64_nxv2i16:547; CHECK: # %bb.0:548; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma549; CHECK-NEXT: vsext.vf2 v10, v8550; CHECK-NEXT: vsext.vf2 v11, v9551; CHECK-NEXT: vwsub.vv v8, v10, v11552; CHECK-NEXT: ret553 %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>554 %vd = sext <vscale x 2 x i16> %vb to <vscale x 2 x i64>555 %ve = sub <vscale x 2 x i64> %vc, %vd556 ret <vscale x 2 x i64> %ve557}558 559define <vscale x 2 x i64> @vwsubu_vv_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {560; CHECK-LABEL: vwsubu_vv_nxv2i64_nxv2i16:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma563; CHECK-NEXT: vwsubu.vv v10, v8, v9564; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma565; CHECK-NEXT: vsext.vf2 v8, v10566; CHECK-NEXT: ret567 %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>568 %vd = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>569 %ve = sub <vscale x 2 x i64> %vc, %vd570 ret <vscale x 2 x i64> %ve571}572 573define <vscale x 2 x i64> @vwsub_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {574; CHECK-LABEL: vwsub_vx_nxv2i64_nxv2i16:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma577; CHECK-NEXT: vmv.v.x v9, a0578; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma579; CHECK-NEXT: vsext.vf2 v10, v8580; CHECK-NEXT: vsext.vf2 v11, v9581; CHECK-NEXT: vwsub.vv v8, v10, v11582; CHECK-NEXT: ret583 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0584 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer585 %vc = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>586 %vd = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>587 %ve = sub <vscale x 2 x i64> %vc, %vd588 ret <vscale x 2 x i64> %ve589}590 591define <vscale x 2 x i64> @vwsubu_vx_nxv2i64_nxv2i16(<vscale x 2 x i16> %va, i16 %b) {592; CHECK-LABEL: vwsubu_vx_nxv2i64_nxv2i16:593; CHECK: # %bb.0:594; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma595; CHECK-NEXT: vwsubu.vx v10, v8, a0596; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma597; CHECK-NEXT: vsext.vf2 v8, v10598; CHECK-NEXT: ret599 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0600 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer601 %vc = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>602 %vd = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>603 %ve = sub <vscale x 2 x i64> %vc, %vd604 ret <vscale x 2 x i64> %ve605}606 607define <vscale x 2 x i64> @vwsub_wv_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, <vscale x 2 x i16> %vb) {608; CHECK-LABEL: vwsub_wv_nxv2i64_nxv2i16:609; CHECK: # %bb.0:610; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma611; CHECK-NEXT: vsext.vf2 v11, v10612; CHECK-NEXT: vwsub.wv v8, v8, v11613; CHECK-NEXT: ret614 %vc = sext <vscale x 2 x i16> %vb to <vscale x 2 x i64>615 %vd = sub <vscale x 2 x i64> %va, %vc616 ret <vscale x 2 x i64> %vd617}618 619define <vscale x 2 x i64> @vwsubu_wv_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, <vscale x 2 x i16> %vb) {620; CHECK-LABEL: vwsubu_wv_nxv2i64_nxv2i16:621; CHECK: # %bb.0:622; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma623; CHECK-NEXT: vzext.vf2 v11, v10624; CHECK-NEXT: vwsubu.wv v8, v8, v11625; CHECK-NEXT: ret626 %vc = zext <vscale x 2 x i16> %vb to <vscale x 2 x i64>627 %vd = sub <vscale x 2 x i64> %va, %vc628 ret <vscale x 2 x i64> %vd629}630 631define <vscale x 2 x i64> @vwsub_wx_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, i16 %b) {632; CHECK-LABEL: vwsub_wx_nxv2i64_nxv2i16:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma635; CHECK-NEXT: vmv.v.x v10, a0636; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma637; CHECK-NEXT: vsext.vf2 v11, v10638; CHECK-NEXT: vwsub.wv v8, v8, v11639; CHECK-NEXT: ret640 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0641 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer642 %vb = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>643 %vc = sub <vscale x 2 x i64> %va, %vb644 ret <vscale x 2 x i64> %vc645}646 647define <vscale x 2 x i64> @vwsubu_wx_nxv2i64_nxv2i16(<vscale x 2 x i64> %va, i16 %b) {648; CHECK-LABEL: vwsubu_wx_nxv2i64_nxv2i16:649; CHECK: # %bb.0:650; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma651; CHECK-NEXT: vmv.v.x v10, a0652; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma653; CHECK-NEXT: vzext.vf2 v11, v10654; CHECK-NEXT: vwsubu.wv v8, v8, v11655; CHECK-NEXT: ret656 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i16 0657 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer658 %vb = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>659 %vc = sub <vscale x 2 x i64> %va, %vb660 ret <vscale x 2 x i64> %vc661}662 663define <vscale x 4 x i64> @vwsub_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {664; CHECK-LABEL: vwsub_vv_nxv4i64_nxv4i16:665; CHECK: # %bb.0:666; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma667; CHECK-NEXT: vsext.vf2 v12, v8668; CHECK-NEXT: vsext.vf2 v14, v9669; CHECK-NEXT: vwsub.vv v8, v12, v14670; CHECK-NEXT: ret671 %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>672 %vd = sext <vscale x 4 x i16> %vb to <vscale x 4 x i64>673 %ve = sub <vscale x 4 x i64> %vc, %vd674 ret <vscale x 4 x i64> %ve675}676 677define <vscale x 4 x i64> @vwsubu_vv_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {678; CHECK-LABEL: vwsubu_vv_nxv4i64_nxv4i16:679; CHECK: # %bb.0:680; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma681; CHECK-NEXT: vwsubu.vv v12, v8, v9682; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma683; CHECK-NEXT: vsext.vf2 v8, v12684; CHECK-NEXT: ret685 %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>686 %vd = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>687 %ve = sub <vscale x 4 x i64> %vc, %vd688 ret <vscale x 4 x i64> %ve689}690 691define <vscale x 4 x i64> @vwsub_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {692; CHECK-LABEL: vwsub_vx_nxv4i64_nxv4i16:693; CHECK: # %bb.0:694; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma695; CHECK-NEXT: vmv.v.x v9, a0696; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma697; CHECK-NEXT: vsext.vf2 v12, v8698; CHECK-NEXT: vsext.vf2 v14, v9699; CHECK-NEXT: vwsub.vv v8, v12, v14700; CHECK-NEXT: ret701 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0702 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer703 %vc = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>704 %vd = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>705 %ve = sub <vscale x 4 x i64> %vc, %vd706 ret <vscale x 4 x i64> %ve707}708 709define <vscale x 4 x i64> @vwsubu_vx_nxv4i64_nxv4i16(<vscale x 4 x i16> %va, i16 %b) {710; CHECK-LABEL: vwsubu_vx_nxv4i64_nxv4i16:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma713; CHECK-NEXT: vwsubu.vx v12, v8, a0714; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma715; CHECK-NEXT: vsext.vf2 v8, v12716; CHECK-NEXT: ret717 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0718 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer719 %vc = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>720 %vd = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>721 %ve = sub <vscale x 4 x i64> %vc, %vd722 ret <vscale x 4 x i64> %ve723}724 725define <vscale x 4 x i64> @vwsub_wv_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, <vscale x 4 x i16> %vb) {726; CHECK-LABEL: vwsub_wv_nxv4i64_nxv4i16:727; CHECK: # %bb.0:728; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma729; CHECK-NEXT: vsext.vf2 v14, v12730; CHECK-NEXT: vwsub.wv v8, v8, v14731; CHECK-NEXT: ret732 %vc = sext <vscale x 4 x i16> %vb to <vscale x 4 x i64>733 %vd = sub <vscale x 4 x i64> %va, %vc734 ret <vscale x 4 x i64> %vd735}736 737define <vscale x 4 x i64> @vwsubu_wv_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, <vscale x 4 x i16> %vb) {738; CHECK-LABEL: vwsubu_wv_nxv4i64_nxv4i16:739; CHECK: # %bb.0:740; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma741; CHECK-NEXT: vzext.vf2 v14, v12742; CHECK-NEXT: vwsubu.wv v8, v8, v14743; CHECK-NEXT: ret744 %vc = zext <vscale x 4 x i16> %vb to <vscale x 4 x i64>745 %vd = sub <vscale x 4 x i64> %va, %vc746 ret <vscale x 4 x i64> %vd747}748 749define <vscale x 4 x i64> @vwsub_wx_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, i16 %b) {750; CHECK-LABEL: vwsub_wx_nxv4i64_nxv4i16:751; CHECK: # %bb.0:752; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma753; CHECK-NEXT: vmv.v.x v14, a0754; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma755; CHECK-NEXT: vsext.vf2 v12, v14756; CHECK-NEXT: vwsub.wv v8, v8, v12757; CHECK-NEXT: ret758 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0759 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer760 %vb = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>761 %vc = sub <vscale x 4 x i64> %va, %vb762 ret <vscale x 4 x i64> %vc763}764 765define <vscale x 4 x i64> @vwsubu_wx_nxv4i64_nxv4i16(<vscale x 4 x i64> %va, i16 %b) {766; CHECK-LABEL: vwsubu_wx_nxv4i64_nxv4i16:767; CHECK: # %bb.0:768; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma769; CHECK-NEXT: vmv.v.x v14, a0770; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma771; CHECK-NEXT: vzext.vf2 v12, v14772; CHECK-NEXT: vwsubu.wv v8, v8, v12773; CHECK-NEXT: ret774 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i16 0775 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer776 %vb = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>777 %vc = sub <vscale x 4 x i64> %va, %vb778 ret <vscale x 4 x i64> %vc779}780 781define <vscale x 8 x i64> @vwsub_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {782; CHECK-LABEL: vwsub_vv_nxv8i64_nxv8i16:783; CHECK: # %bb.0:784; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma785; CHECK-NEXT: vsext.vf2 v16, v8786; CHECK-NEXT: vsext.vf2 v20, v10787; CHECK-NEXT: vwsub.vv v8, v16, v20788; CHECK-NEXT: ret789 %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>790 %vd = sext <vscale x 8 x i16> %vb to <vscale x 8 x i64>791 %ve = sub <vscale x 8 x i64> %vc, %vd792 ret <vscale x 8 x i64> %ve793}794 795define <vscale x 8 x i64> @vwsubu_vv_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {796; CHECK-LABEL: vwsubu_vv_nxv8i64_nxv8i16:797; CHECK: # %bb.0:798; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma799; CHECK-NEXT: vwsubu.vv v16, v8, v10800; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma801; CHECK-NEXT: vsext.vf2 v8, v16802; CHECK-NEXT: ret803 %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>804 %vd = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>805 %ve = sub <vscale x 8 x i64> %vc, %vd806 ret <vscale x 8 x i64> %ve807}808 809define <vscale x 8 x i64> @vwsub_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {810; CHECK-LABEL: vwsub_vx_nxv8i64_nxv8i16:811; CHECK: # %bb.0:812; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma813; CHECK-NEXT: vmv.v.x v10, a0814; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma815; CHECK-NEXT: vsext.vf2 v16, v8816; CHECK-NEXT: vsext.vf2 v20, v10817; CHECK-NEXT: vwsub.vv v8, v16, v20818; CHECK-NEXT: ret819 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0820 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer821 %vc = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>822 %vd = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>823 %ve = sub <vscale x 8 x i64> %vc, %vd824 ret <vscale x 8 x i64> %ve825}826 827define <vscale x 8 x i64> @vwsubu_vx_nxv8i64_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {828; CHECK-LABEL: vwsubu_vx_nxv8i64_nxv8i16:829; CHECK: # %bb.0:830; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma831; CHECK-NEXT: vwsubu.vx v16, v8, a0832; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma833; CHECK-NEXT: vsext.vf2 v8, v16834; CHECK-NEXT: ret835 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0836 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer837 %vc = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>838 %vd = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>839 %ve = sub <vscale x 8 x i64> %vc, %vd840 ret <vscale x 8 x i64> %ve841}842 843define <vscale x 8 x i64> @vwsub_wv_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, <vscale x 8 x i16> %vb) {844; CHECK-LABEL: vwsub_wv_nxv8i64_nxv8i16:845; CHECK: # %bb.0:846; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma847; CHECK-NEXT: vsext.vf2 v20, v16848; CHECK-NEXT: vwsub.wv v8, v8, v20849; CHECK-NEXT: ret850 %vc = sext <vscale x 8 x i16> %vb to <vscale x 8 x i64>851 %vd = sub <vscale x 8 x i64> %va, %vc852 ret <vscale x 8 x i64> %vd853}854 855define <vscale x 8 x i64> @vwsubu_wv_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, <vscale x 8 x i16> %vb) {856; CHECK-LABEL: vwsubu_wv_nxv8i64_nxv8i16:857; CHECK: # %bb.0:858; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma859; CHECK-NEXT: vzext.vf2 v20, v16860; CHECK-NEXT: vwsubu.wv v8, v8, v20861; CHECK-NEXT: ret862 %vc = zext <vscale x 8 x i16> %vb to <vscale x 8 x i64>863 %vd = sub <vscale x 8 x i64> %va, %vc864 ret <vscale x 8 x i64> %vd865}866 867define <vscale x 8 x i64> @vwsub_wx_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, i16 %b) {868; CHECK-LABEL: vwsub_wx_nxv8i64_nxv8i16:869; CHECK: # %bb.0:870; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma871; CHECK-NEXT: vmv.v.x v20, a0872; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma873; CHECK-NEXT: vsext.vf2 v16, v20874; CHECK-NEXT: vwsub.wv v8, v8, v16875; CHECK-NEXT: ret876 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0877 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer878 %vb = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>879 %vc = sub <vscale x 8 x i64> %va, %vb880 ret <vscale x 8 x i64> %vc881}882 883define <vscale x 8 x i64> @vwsubu_wx_nxv8i64_nxv8i16(<vscale x 8 x i64> %va, i16 %b) {884; CHECK-LABEL: vwsubu_wx_nxv8i64_nxv8i16:885; CHECK: # %bb.0:886; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma887; CHECK-NEXT: vmv.v.x v20, a0888; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma889; CHECK-NEXT: vzext.vf2 v16, v20890; CHECK-NEXT: vwsubu.wv v8, v8, v16891; CHECK-NEXT: ret892 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i16 0893 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer894 %vb = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>895 %vc = sub <vscale x 8 x i64> %va, %vb896 ret <vscale x 8 x i64> %vc897}898 899define <vscale x 1 x i64> @vwsub_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {900; CHECK-LABEL: vwsub_vv_nxv1i64_nxv1i8:901; CHECK: # %bb.0:902; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma903; CHECK-NEXT: vsext.vf4 v10, v8904; CHECK-NEXT: vsext.vf4 v11, v9905; CHECK-NEXT: vwsub.vv v8, v10, v11906; CHECK-NEXT: ret907 %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>908 %vd = sext <vscale x 1 x i8> %vb to <vscale x 1 x i64>909 %ve = sub <vscale x 1 x i64> %vc, %vd910 ret <vscale x 1 x i64> %ve911}912 913define <vscale x 1 x i64> @vwsubu_vv_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {914; CHECK-LABEL: vwsubu_vv_nxv1i64_nxv1i8:915; CHECK: # %bb.0:916; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma917; CHECK-NEXT: vwsubu.vv v10, v8, v9918; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma919; CHECK-NEXT: vsext.vf4 v8, v10920; CHECK-NEXT: ret921 %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>922 %vd = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>923 %ve = sub <vscale x 1 x i64> %vc, %vd924 ret <vscale x 1 x i64> %ve925}926 927define <vscale x 1 x i64> @vwsub_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {928; CHECK-LABEL: vwsub_vx_nxv1i64_nxv1i8:929; CHECK: # %bb.0:930; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma931; CHECK-NEXT: vmv.v.x v9, a0932; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma933; CHECK-NEXT: vsext.vf4 v10, v8934; CHECK-NEXT: vsext.vf4 v11, v9935; CHECK-NEXT: vwsub.vv v8, v10, v11936; CHECK-NEXT: ret937 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0938 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer939 %vc = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>940 %vd = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>941 %ve = sub <vscale x 1 x i64> %vc, %vd942 ret <vscale x 1 x i64> %ve943}944 945define <vscale x 1 x i64> @vwsubu_vx_nxv1i64_nxv1i8(<vscale x 1 x i8> %va, i8 %b) {946; CHECK-LABEL: vwsubu_vx_nxv1i64_nxv1i8:947; CHECK: # %bb.0:948; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma949; CHECK-NEXT: vwsubu.vx v9, v8, a0950; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma951; CHECK-NEXT: vsext.vf4 v8, v9952; CHECK-NEXT: ret953 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0954 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer955 %vc = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>956 %vd = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>957 %ve = sub <vscale x 1 x i64> %vc, %vd958 ret <vscale x 1 x i64> %ve959}960 961define <vscale x 1 x i64> @vwsub_wv_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, <vscale x 1 x i8> %vb) {962; CHECK-LABEL: vwsub_wv_nxv1i64_nxv1i8:963; CHECK: # %bb.0:964; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma965; CHECK-NEXT: vsext.vf4 v10, v9966; CHECK-NEXT: vwsub.wv v8, v8, v10967; CHECK-NEXT: ret968 %vc = sext <vscale x 1 x i8> %vb to <vscale x 1 x i64>969 %vd = sub <vscale x 1 x i64> %va, %vc970 ret <vscale x 1 x i64> %vd971}972 973define <vscale x 1 x i64> @vwsubu_wv_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, <vscale x 1 x i8> %vb) {974; CHECK-LABEL: vwsubu_wv_nxv1i64_nxv1i8:975; CHECK: # %bb.0:976; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma977; CHECK-NEXT: vzext.vf4 v10, v9978; CHECK-NEXT: vwsubu.wv v8, v8, v10979; CHECK-NEXT: ret980 %vc = zext <vscale x 1 x i8> %vb to <vscale x 1 x i64>981 %vd = sub <vscale x 1 x i64> %va, %vc982 ret <vscale x 1 x i64> %vd983}984 985define <vscale x 1 x i64> @vwsub_wx_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, i8 %b) {986; CHECK-LABEL: vwsub_wx_nxv1i64_nxv1i8:987; CHECK: # %bb.0:988; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma989; CHECK-NEXT: vmv.v.x v9, a0990; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma991; CHECK-NEXT: vsext.vf4 v10, v9992; CHECK-NEXT: vwsub.wv v8, v8, v10993; CHECK-NEXT: ret994 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 0995 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer996 %vb = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>997 %vc = sub <vscale x 1 x i64> %va, %vb998 ret <vscale x 1 x i64> %vc999}1000 1001define <vscale x 1 x i64> @vwsubu_wx_nxv1i64_nxv1i8(<vscale x 1 x i64> %va, i8 %b) {1002; CHECK-LABEL: vwsubu_wx_nxv1i64_nxv1i8:1003; CHECK: # %bb.0:1004; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma1005; CHECK-NEXT: vmv.v.x v9, a01006; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1007; CHECK-NEXT: vzext.vf4 v10, v91008; CHECK-NEXT: vwsubu.wv v8, v8, v101009; CHECK-NEXT: ret1010 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i8 01011 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer1012 %vb = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>1013 %vc = sub <vscale x 1 x i64> %va, %vb1014 ret <vscale x 1 x i64> %vc1015}1016 1017define <vscale x 2 x i64> @vwsub_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {1018; CHECK-LABEL: vwsub_vv_nxv2i64_nxv2i8:1019; CHECK: # %bb.0:1020; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1021; CHECK-NEXT: vsext.vf4 v10, v81022; CHECK-NEXT: vsext.vf4 v11, v91023; CHECK-NEXT: vwsub.vv v8, v10, v111024; CHECK-NEXT: ret1025 %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>1026 %vd = sext <vscale x 2 x i8> %vb to <vscale x 2 x i64>1027 %ve = sub <vscale x 2 x i64> %vc, %vd1028 ret <vscale x 2 x i64> %ve1029}1030 1031define <vscale x 2 x i64> @vwsubu_vv_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {1032; CHECK-LABEL: vwsubu_vv_nxv2i64_nxv2i8:1033; CHECK: # %bb.0:1034; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma1035; CHECK-NEXT: vwsubu.vv v10, v8, v91036; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma1037; CHECK-NEXT: vsext.vf4 v8, v101038; CHECK-NEXT: ret1039 %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>1040 %vd = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>1041 %ve = sub <vscale x 2 x i64> %vc, %vd1042 ret <vscale x 2 x i64> %ve1043}1044 1045define <vscale x 2 x i64> @vwsub_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {1046; CHECK-LABEL: vwsub_vx_nxv2i64_nxv2i8:1047; CHECK: # %bb.0:1048; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1049; CHECK-NEXT: vmv.v.x v9, a01050; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma1051; CHECK-NEXT: vsext.vf4 v10, v81052; CHECK-NEXT: vsext.vf4 v11, v91053; CHECK-NEXT: vwsub.vv v8, v10, v111054; CHECK-NEXT: ret1055 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 01056 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer1057 %vc = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>1058 %vd = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>1059 %ve = sub <vscale x 2 x i64> %vc, %vd1060 ret <vscale x 2 x i64> %ve1061}1062 1063define <vscale x 2 x i64> @vwsubu_vx_nxv2i64_nxv2i8(<vscale x 2 x i8> %va, i8 %b) {1064; CHECK-LABEL: vwsubu_vx_nxv2i64_nxv2i8:1065; CHECK: # %bb.0:1066; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1067; CHECK-NEXT: vwsubu.vx v10, v8, a01068; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma1069; CHECK-NEXT: vsext.vf4 v8, v101070; CHECK-NEXT: ret1071 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 01072 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer1073 %vc = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>1074 %vd = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>1075 %ve = sub <vscale x 2 x i64> %vc, %vd1076 ret <vscale x 2 x i64> %ve1077}1078 1079define <vscale x 2 x i64> @vwsub_wv_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, <vscale x 2 x i8> %vb) {1080; CHECK-LABEL: vwsub_wv_nxv2i64_nxv2i8:1081; CHECK: # %bb.0:1082; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1083; CHECK-NEXT: vsext.vf4 v11, v101084; CHECK-NEXT: vwsub.wv v8, v8, v111085; CHECK-NEXT: ret1086 %vc = sext <vscale x 2 x i8> %vb to <vscale x 2 x i64>1087 %vd = sub <vscale x 2 x i64> %va, %vc1088 ret <vscale x 2 x i64> %vd1089}1090 1091define <vscale x 2 x i64> @vwsubu_wv_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, <vscale x 2 x i8> %vb) {1092; CHECK-LABEL: vwsubu_wv_nxv2i64_nxv2i8:1093; CHECK: # %bb.0:1094; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1095; CHECK-NEXT: vzext.vf4 v11, v101096; CHECK-NEXT: vwsubu.wv v8, v8, v111097; CHECK-NEXT: ret1098 %vc = zext <vscale x 2 x i8> %vb to <vscale x 2 x i64>1099 %vd = sub <vscale x 2 x i64> %va, %vc1100 ret <vscale x 2 x i64> %vd1101}1102 1103define <vscale x 2 x i64> @vwsub_wx_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, i8 %b) {1104; CHECK-LABEL: vwsub_wx_nxv2i64_nxv2i8:1105; CHECK: # %bb.0:1106; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1107; CHECK-NEXT: vmv.v.x v10, a01108; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma1109; CHECK-NEXT: vsext.vf4 v11, v101110; CHECK-NEXT: vwsub.wv v8, v8, v111111; CHECK-NEXT: ret1112 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 01113 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer1114 %vb = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>1115 %vc = sub <vscale x 2 x i64> %va, %vb1116 ret <vscale x 2 x i64> %vc1117}1118 1119define <vscale x 2 x i64> @vwsubu_wx_nxv2i64_nxv2i8(<vscale x 2 x i64> %va, i8 %b) {1120; CHECK-LABEL: vwsubu_wx_nxv2i64_nxv2i8:1121; CHECK: # %bb.0:1122; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma1123; CHECK-NEXT: vmv.v.x v10, a01124; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma1125; CHECK-NEXT: vzext.vf4 v11, v101126; CHECK-NEXT: vwsubu.wv v8, v8, v111127; CHECK-NEXT: ret1128 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i8 01129 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer1130 %vb = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>1131 %vc = sub <vscale x 2 x i64> %va, %vb1132 ret <vscale x 2 x i64> %vc1133}1134 1135define <vscale x 4 x i64> @vwsub_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {1136; CHECK-LABEL: vwsub_vv_nxv4i64_nxv4i8:1137; CHECK: # %bb.0:1138; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1139; CHECK-NEXT: vsext.vf4 v12, v81140; CHECK-NEXT: vsext.vf4 v14, v91141; CHECK-NEXT: vwsub.vv v8, v12, v141142; CHECK-NEXT: ret1143 %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>1144 %vd = sext <vscale x 4 x i8> %vb to <vscale x 4 x i64>1145 %ve = sub <vscale x 4 x i64> %vc, %vd1146 ret <vscale x 4 x i64> %ve1147}1148 1149define <vscale x 4 x i64> @vwsubu_vv_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {1150; CHECK-LABEL: vwsubu_vv_nxv4i64_nxv4i8:1151; CHECK: # %bb.0:1152; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma1153; CHECK-NEXT: vwsubu.vv v12, v8, v91154; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma1155; CHECK-NEXT: vsext.vf4 v8, v121156; CHECK-NEXT: ret1157 %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>1158 %vd = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>1159 %ve = sub <vscale x 4 x i64> %vc, %vd1160 ret <vscale x 4 x i64> %ve1161}1162 1163define <vscale x 4 x i64> @vwsub_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {1164; CHECK-LABEL: vwsub_vx_nxv4i64_nxv4i8:1165; CHECK: # %bb.0:1166; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma1167; CHECK-NEXT: vmv.v.x v9, a01168; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1169; CHECK-NEXT: vsext.vf4 v12, v81170; CHECK-NEXT: vsext.vf4 v14, v91171; CHECK-NEXT: vwsub.vv v8, v12, v141172; CHECK-NEXT: ret1173 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 01174 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer1175 %vc = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>1176 %vd = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>1177 %ve = sub <vscale x 4 x i64> %vc, %vd1178 ret <vscale x 4 x i64> %ve1179}1180 1181define <vscale x 4 x i64> @vwsubu_vx_nxv4i64_nxv4i8(<vscale x 4 x i8> %va, i8 %b) {1182; CHECK-LABEL: vwsubu_vx_nxv4i64_nxv4i8:1183; CHECK: # %bb.0:1184; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma1185; CHECK-NEXT: vwsubu.vx v12, v8, a01186; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma1187; CHECK-NEXT: vsext.vf4 v8, v121188; CHECK-NEXT: ret1189 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 01190 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer1191 %vc = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>1192 %vd = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>1193 %ve = sub <vscale x 4 x i64> %vc, %vd1194 ret <vscale x 4 x i64> %ve1195}1196 1197define <vscale x 4 x i64> @vwsub_wv_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, <vscale x 4 x i8> %vb) {1198; CHECK-LABEL: vwsub_wv_nxv4i64_nxv4i8:1199; CHECK: # %bb.0:1200; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1201; CHECK-NEXT: vsext.vf4 v14, v121202; CHECK-NEXT: vwsub.wv v8, v8, v141203; CHECK-NEXT: ret1204 %vc = sext <vscale x 4 x i8> %vb to <vscale x 4 x i64>1205 %vd = sub <vscale x 4 x i64> %va, %vc1206 ret <vscale x 4 x i64> %vd1207}1208 1209define <vscale x 4 x i64> @vwsubu_wv_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, <vscale x 4 x i8> %vb) {1210; CHECK-LABEL: vwsubu_wv_nxv4i64_nxv4i8:1211; CHECK: # %bb.0:1212; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1213; CHECK-NEXT: vzext.vf4 v14, v121214; CHECK-NEXT: vwsubu.wv v8, v8, v141215; CHECK-NEXT: ret1216 %vc = zext <vscale x 4 x i8> %vb to <vscale x 4 x i64>1217 %vd = sub <vscale x 4 x i64> %va, %vc1218 ret <vscale x 4 x i64> %vd1219}1220 1221define <vscale x 4 x i64> @vwsub_wx_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, i8 %b) {1222; CHECK-LABEL: vwsub_wx_nxv4i64_nxv4i8:1223; CHECK: # %bb.0:1224; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma1225; CHECK-NEXT: vmv.v.x v14, a01226; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1227; CHECK-NEXT: vsext.vf4 v12, v141228; CHECK-NEXT: vwsub.wv v8, v8, v121229; CHECK-NEXT: ret1230 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 01231 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer1232 %vb = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>1233 %vc = sub <vscale x 4 x i64> %va, %vb1234 ret <vscale x 4 x i64> %vc1235}1236 1237define <vscale x 4 x i64> @vwsubu_wx_nxv4i64_nxv4i8(<vscale x 4 x i64> %va, i8 %b) {1238; CHECK-LABEL: vwsubu_wx_nxv4i64_nxv4i8:1239; CHECK: # %bb.0:1240; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma1241; CHECK-NEXT: vmv.v.x v14, a01242; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma1243; CHECK-NEXT: vzext.vf4 v12, v141244; CHECK-NEXT: vwsubu.wv v8, v8, v121245; CHECK-NEXT: ret1246 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i8 01247 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer1248 %vb = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>1249 %vc = sub <vscale x 4 x i64> %va, %vb1250 ret <vscale x 4 x i64> %vc1251}1252 1253define <vscale x 8 x i64> @vwsub_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {1254; CHECK-LABEL: vwsub_vv_nxv8i64_nxv8i8:1255; CHECK: # %bb.0:1256; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1257; CHECK-NEXT: vsext.vf4 v16, v81258; CHECK-NEXT: vsext.vf4 v20, v91259; CHECK-NEXT: vwsub.vv v8, v16, v201260; CHECK-NEXT: ret1261 %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>1262 %vd = sext <vscale x 8 x i8> %vb to <vscale x 8 x i64>1263 %ve = sub <vscale x 8 x i64> %vc, %vd1264 ret <vscale x 8 x i64> %ve1265}1266 1267define <vscale x 8 x i64> @vwsubu_vv_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {1268; CHECK-LABEL: vwsubu_vv_nxv8i64_nxv8i8:1269; CHECK: # %bb.0:1270; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma1271; CHECK-NEXT: vwsubu.vv v16, v8, v91272; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1273; CHECK-NEXT: vsext.vf4 v8, v161274; CHECK-NEXT: ret1275 %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>1276 %vd = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>1277 %ve = sub <vscale x 8 x i64> %vc, %vd1278 ret <vscale x 8 x i64> %ve1279}1280 1281define <vscale x 8 x i64> @vwsub_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {1282; CHECK-LABEL: vwsub_vx_nxv8i64_nxv8i8:1283; CHECK: # %bb.0:1284; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1285; CHECK-NEXT: vmv.v.x v9, a01286; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1287; CHECK-NEXT: vsext.vf4 v16, v81288; CHECK-NEXT: vsext.vf4 v20, v91289; CHECK-NEXT: vwsub.vv v8, v16, v201290; CHECK-NEXT: ret1291 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 01292 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer1293 %vc = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>1294 %vd = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>1295 %ve = sub <vscale x 8 x i64> %vc, %vd1296 ret <vscale x 8 x i64> %ve1297}1298 1299define <vscale x 8 x i64> @vwsubu_vx_nxv8i64_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {1300; CHECK-LABEL: vwsubu_vx_nxv8i64_nxv8i8:1301; CHECK: # %bb.0:1302; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1303; CHECK-NEXT: vwsubu.vx v16, v8, a01304; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma1305; CHECK-NEXT: vsext.vf4 v8, v161306; CHECK-NEXT: ret1307 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 01308 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer1309 %vc = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>1310 %vd = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>1311 %ve = sub <vscale x 8 x i64> %vc, %vd1312 ret <vscale x 8 x i64> %ve1313}1314 1315define <vscale x 8 x i64> @vwsub_wv_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, <vscale x 8 x i8> %vb) {1316; CHECK-LABEL: vwsub_wv_nxv8i64_nxv8i8:1317; CHECK: # %bb.0:1318; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1319; CHECK-NEXT: vsext.vf4 v20, v161320; CHECK-NEXT: vwsub.wv v8, v8, v201321; CHECK-NEXT: ret1322 %vc = sext <vscale x 8 x i8> %vb to <vscale x 8 x i64>1323 %vd = sub <vscale x 8 x i64> %va, %vc1324 ret <vscale x 8 x i64> %vd1325}1326 1327define <vscale x 8 x i64> @vwsubu_wv_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, <vscale x 8 x i8> %vb) {1328; CHECK-LABEL: vwsubu_wv_nxv8i64_nxv8i8:1329; CHECK: # %bb.0:1330; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1331; CHECK-NEXT: vzext.vf4 v20, v161332; CHECK-NEXT: vwsubu.wv v8, v8, v201333; CHECK-NEXT: ret1334 %vc = zext <vscale x 8 x i8> %vb to <vscale x 8 x i64>1335 %vd = sub <vscale x 8 x i64> %va, %vc1336 ret <vscale x 8 x i64> %vd1337}1338 1339define <vscale x 8 x i64> @vwsub_wx_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, i8 %b) {1340; CHECK-LABEL: vwsub_wx_nxv8i64_nxv8i8:1341; CHECK: # %bb.0:1342; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1343; CHECK-NEXT: vmv.v.x v20, a01344; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1345; CHECK-NEXT: vsext.vf4 v16, v201346; CHECK-NEXT: vwsub.wv v8, v8, v161347; CHECK-NEXT: ret1348 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 01349 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer1350 %vb = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>1351 %vc = sub <vscale x 8 x i64> %va, %vb1352 ret <vscale x 8 x i64> %vc1353}1354 1355define <vscale x 8 x i64> @vwsubu_wx_nxv8i64_nxv8i8(<vscale x 8 x i64> %va, i8 %b) {1356; CHECK-LABEL: vwsubu_wx_nxv8i64_nxv8i8:1357; CHECK: # %bb.0:1358; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma1359; CHECK-NEXT: vmv.v.x v20, a01360; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma1361; CHECK-NEXT: vzext.vf4 v16, v201362; CHECK-NEXT: vwsubu.wv v8, v8, v161363; CHECK-NEXT: ret1364 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i8 01365 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer1366 %vb = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>1367 %vc = sub <vscale x 8 x i64> %va, %vb1368 ret <vscale x 8 x i64> %vc1369}1370