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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vwsubu.wv v8, v8, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(15 <vscale x 1 x i16> poison,16 <vscale x 1 x i16> %0,17 <vscale x 1 x i8> %1,18 iXLen %2)19 20 ret <vscale x 1 x i16> %a21}22 23define <vscale x 1 x i16> @intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i16_nxv1i16_nxv1i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu27; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.mask.nxv1i16.nxv1i8(31 <vscale x 1 x i16> %0,32 <vscale x 1 x i16> %1,33 <vscale x 1 x i8> %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x i16> %a38}39 40define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma44; CHECK-NEXT: vwsubu.wv v8, v8, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(48 <vscale x 2 x i16> poison,49 <vscale x 2 x i16> %0,50 <vscale x 2 x i8> %1,51 iXLen %2)52 53 ret <vscale x 2 x i16> %a54}55 56define <vscale x 2 x i16> @intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i16_nxv2i16_nxv2i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu60; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.mask.nxv2i16.nxv2i8(64 <vscale x 2 x i16> %0,65 <vscale x 2 x i16> %1,66 <vscale x 2 x i8> %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x i16> %a71}72 73define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma77; CHECK-NEXT: vwsubu.wv v8, v8, v978; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(81 <vscale x 4 x i16> poison,82 <vscale x 4 x i16> %0,83 <vscale x 4 x i8> %1,84 iXLen %2)85 86 ret <vscale x 4 x i16> %a87}88 89define <vscale x 4 x i16> @intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i16_nxv4i16_nxv4i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu93; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.mask.nxv4i16.nxv4i8(97 <vscale x 4 x i16> %0,98 <vscale x 4 x i16> %1,99 <vscale x 4 x i8> %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x i16> %a104}105 106define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma110; CHECK-NEXT: vwsubu.wv v8, v8, v10111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(114 <vscale x 8 x i16> poison,115 <vscale x 8 x i16> %0,116 <vscale x 8 x i8> %1,117 iXLen %2)118 119 ret <vscale x 8 x i16> %a120}121 122define <vscale x 8 x i16> @intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i16_nxv8i16_nxv8i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu126; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.mask.nxv8i16.nxv8i8(130 <vscale x 8 x i16> %0,131 <vscale x 8 x i16> %1,132 <vscale x 8 x i8> %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 1)135 136 ret <vscale x 8 x i16> %a137}138 139define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma143; CHECK-NEXT: vwsubu.wv v8, v8, v12144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(147 <vscale x 16 x i16> poison,148 <vscale x 16 x i16> %0,149 <vscale x 16 x i8> %1,150 iXLen %2)151 152 ret <vscale x 16 x i16> %a153}154 155define <vscale x 16 x i16> @intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i16_nxv16i16_nxv16i8:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu159; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.mask.nxv16i16.nxv16i8(163 <vscale x 16 x i16> %0,164 <vscale x 16 x i16> %1,165 <vscale x 16 x i8> %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 1)168 169 ret <vscale x 16 x i16> %a170}171 172define <vscale x 32 x i16> @intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma176; CHECK-NEXT: vwsubu.wv v8, v8, v16177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8(180 <vscale x 32 x i16> poison,181 <vscale x 32 x i16> %0,182 <vscale x 32 x i8> %1,183 iXLen %2)184 185 ret <vscale x 32 x i16> %a186}187 188define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv32i16_nxv32i16_nxv32i8:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vl4r.v v24, (a0)192; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu193; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t194; CHECK-NEXT: ret195entry:196 %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(197 <vscale x 32 x i16> %0,198 <vscale x 32 x i16> %1,199 <vscale x 32 x i8> %2,200 <vscale x 32 x i1> %3,201 iXLen %4, iXLen 1)202 203 ret <vscale x 32 x i16> %a204}205 206define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {207; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16:208; CHECK: # %bb.0: # %entry209; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma210; CHECK-NEXT: vwsubu.wv v8, v8, v9211; CHECK-NEXT: ret212entry:213 %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(214 <vscale x 1 x i32> poison,215 <vscale x 1 x i32> %0,216 <vscale x 1 x i16> %1,217 iXLen %2)218 219 ret <vscale x 1 x i32> %a220}221 222define <vscale x 1 x i32> @intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {223; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i32_nxv1i32_nxv1i16:224; CHECK: # %bb.0: # %entry225; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu226; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t227; CHECK-NEXT: ret228entry:229 %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.mask.nxv1i32.nxv1i16(230 <vscale x 1 x i32> %0,231 <vscale x 1 x i32> %1,232 <vscale x 1 x i16> %2,233 <vscale x 1 x i1> %3,234 iXLen %4, iXLen 1)235 236 ret <vscale x 1 x i32> %a237}238 239define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {240; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma243; CHECK-NEXT: vwsubu.wv v8, v8, v9244; CHECK-NEXT: ret245entry:246 %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(247 <vscale x 2 x i32> poison,248 <vscale x 2 x i32> %0,249 <vscale x 2 x i16> %1,250 iXLen %2)251 252 ret <vscale x 2 x i32> %a253}254 255define <vscale x 2 x i32> @intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {256; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i32_nxv2i32_nxv2i16:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu259; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t260; CHECK-NEXT: ret261entry:262 %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.mask.nxv2i32.nxv2i16(263 <vscale x 2 x i32> %0,264 <vscale x 2 x i32> %1,265 <vscale x 2 x i16> %2,266 <vscale x 2 x i1> %3,267 iXLen %4, iXLen 1)268 269 ret <vscale x 2 x i32> %a270}271 272define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {273; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16:274; CHECK: # %bb.0: # %entry275; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma276; CHECK-NEXT: vwsubu.wv v8, v8, v10277; CHECK-NEXT: ret278entry:279 %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(280 <vscale x 4 x i32> poison,281 <vscale x 4 x i32> %0,282 <vscale x 4 x i16> %1,283 iXLen %2)284 285 ret <vscale x 4 x i32> %a286}287 288define <vscale x 4 x i32> @intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {289; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i32_nxv4i32_nxv4i16:290; CHECK: # %bb.0: # %entry291; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu292; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t293; CHECK-NEXT: ret294entry:295 %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.mask.nxv4i32.nxv4i16(296 <vscale x 4 x i32> %0,297 <vscale x 4 x i32> %1,298 <vscale x 4 x i16> %2,299 <vscale x 4 x i1> %3,300 iXLen %4, iXLen 1)301 302 ret <vscale x 4 x i32> %a303}304 305define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {306; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16:307; CHECK: # %bb.0: # %entry308; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma309; CHECK-NEXT: vwsubu.wv v8, v8, v12310; CHECK-NEXT: ret311entry:312 %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(313 <vscale x 8 x i32> poison,314 <vscale x 8 x i32> %0,315 <vscale x 8 x i16> %1,316 iXLen %2)317 318 ret <vscale x 8 x i32> %a319}320 321define <vscale x 8 x i32> @intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {322; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i32_nxv8i32_nxv8i16:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu325; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t326; CHECK-NEXT: ret327entry:328 %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.mask.nxv8i32.nxv8i16(329 <vscale x 8 x i32> %0,330 <vscale x 8 x i32> %1,331 <vscale x 8 x i16> %2,332 <vscale x 8 x i1> %3,333 iXLen %4, iXLen 1)334 335 ret <vscale x 8 x i32> %a336}337 338define <vscale x 16 x i32> @intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {339; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16:340; CHECK: # %bb.0: # %entry341; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma342; CHECK-NEXT: vwsubu.wv v8, v8, v16343; CHECK-NEXT: ret344entry:345 %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.nxv16i16(346 <vscale x 16 x i32> poison,347 <vscale x 16 x i32> %0,348 <vscale x 16 x i16> %1,349 iXLen %2)350 351 ret <vscale x 16 x i32> %a352}353 354define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {355; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv16i32_nxv16i32_nxv16i16:356; CHECK: # %bb.0: # %entry357; CHECK-NEXT: vl4re16.v v24, (a0)358; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu359; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t360; CHECK-NEXT: ret361entry:362 %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(363 <vscale x 16 x i32> %0,364 <vscale x 16 x i32> %1,365 <vscale x 16 x i16> %2,366 <vscale x 16 x i1> %3,367 iXLen %4, iXLen 1)368 369 ret <vscale x 16 x i32> %a370}371 372define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {373; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32:374; CHECK: # %bb.0: # %entry375; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma376; CHECK-NEXT: vwsubu.wv v8, v8, v9377; CHECK-NEXT: ret378entry:379 %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(380 <vscale x 1 x i64> poison,381 <vscale x 1 x i64> %0,382 <vscale x 1 x i32> %1,383 iXLen %2)384 385 ret <vscale x 1 x i64> %a386}387 388define <vscale x 1 x i64> @intrinsic_vwsubu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {389; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv1i64_nxv1i64_nxv1i32:390; CHECK: # %bb.0: # %entry391; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu392; CHECK-NEXT: vwsubu.wv v8, v9, v10, v0.t393; CHECK-NEXT: ret394entry:395 %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.mask.nxv1i64.nxv1i32(396 <vscale x 1 x i64> %0,397 <vscale x 1 x i64> %1,398 <vscale x 1 x i32> %2,399 <vscale x 1 x i1> %3,400 iXLen %4, iXLen 1)401 402 ret <vscale x 1 x i64> %a403}404 405define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {406; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32:407; CHECK: # %bb.0: # %entry408; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma409; CHECK-NEXT: vwsubu.wv v8, v8, v10410; CHECK-NEXT: ret411entry:412 %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(413 <vscale x 2 x i64> poison,414 <vscale x 2 x i64> %0,415 <vscale x 2 x i32> %1,416 iXLen %2)417 418 ret <vscale x 2 x i64> %a419}420 421define <vscale x 2 x i64> @intrinsic_vwsubu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {422; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv2i64_nxv2i64_nxv2i32:423; CHECK: # %bb.0: # %entry424; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu425; CHECK-NEXT: vwsubu.wv v8, v10, v12, v0.t426; CHECK-NEXT: ret427entry:428 %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.mask.nxv2i64.nxv2i32(429 <vscale x 2 x i64> %0,430 <vscale x 2 x i64> %1,431 <vscale x 2 x i32> %2,432 <vscale x 2 x i1> %3,433 iXLen %4, iXLen 1)434 435 ret <vscale x 2 x i64> %a436}437 438define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {439; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32:440; CHECK: # %bb.0: # %entry441; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma442; CHECK-NEXT: vwsubu.wv v8, v8, v12443; CHECK-NEXT: ret444entry:445 %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(446 <vscale x 4 x i64> poison,447 <vscale x 4 x i64> %0,448 <vscale x 4 x i32> %1,449 iXLen %2)450 451 ret <vscale x 4 x i64> %a452}453 454define <vscale x 4 x i64> @intrinsic_vwsubu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {455; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv4i64_nxv4i64_nxv4i32:456; CHECK: # %bb.0: # %entry457; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu458; CHECK-NEXT: vwsubu.wv v8, v12, v16, v0.t459; CHECK-NEXT: ret460entry:461 %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.mask.nxv4i64.nxv4i32(462 <vscale x 4 x i64> %0,463 <vscale x 4 x i64> %1,464 <vscale x 4 x i32> %2,465 <vscale x 4 x i1> %3,466 iXLen %4, iXLen 1)467 468 ret <vscale x 4 x i64> %a469}470 471define <vscale x 8 x i64> @intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {472; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma475; CHECK-NEXT: vwsubu.wv v8, v8, v16476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32(479 <vscale x 8 x i64> poison,480 <vscale x 8 x i64> %0,481 <vscale x 8 x i32> %1,482 iXLen %2)483 484 ret <vscale x 8 x i64> %a485}486 487define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {488; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_nxv8i64_nxv8i64_nxv8i32:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vl4re32.v v24, (a0)491; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu492; CHECK-NEXT: vwsubu.wv v8, v16, v24, v0.t493; CHECK-NEXT: ret494entry:495 %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(496 <vscale x 8 x i64> %0,497 <vscale x 8 x i64> %1,498 <vscale x 8 x i32> %2,499 <vscale x 8 x i1> %3,500 iXLen %4, iXLen 1)501 502 ret <vscale x 8 x i64> %a503}504 505define <vscale x 1 x i16> @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, iXLen %2) nounwind {506; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8:507; CHECK: # %bb.0: # %entry508; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma509; CHECK-NEXT: vwsubu.wx v8, v8, a0510; CHECK-NEXT: ret511entry:512 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8(513 <vscale x 1 x i16> poison,514 <vscale x 1 x i16> %0,515 i8 %1,516 iXLen %2)517 518 ret <vscale x 1 x i16> %a519}520 521define <vscale x 1 x i16> @intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {522; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i16_nxv1i16_i8:523; CHECK: # %bb.0: # %entry524; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu525; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t526; CHECK-NEXT: ret527entry:528 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.mask.nxv1i16.i8(529 <vscale x 1 x i16> %0,530 <vscale x 1 x i16> %1,531 i8 %2,532 <vscale x 1 x i1> %3,533 iXLen %4, iXLen 1)534 535 ret <vscale x 1 x i16> %a536}537 538define <vscale x 2 x i16> @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, iXLen %2) nounwind {539; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8:540; CHECK: # %bb.0: # %entry541; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma542; CHECK-NEXT: vwsubu.wx v8, v8, a0543; CHECK-NEXT: ret544entry:545 %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8(546 <vscale x 2 x i16> poison,547 <vscale x 2 x i16> %0,548 i8 %1,549 iXLen %2)550 551 ret <vscale x 2 x i16> %a552}553 554define <vscale x 2 x i16> @intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {555; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i16_nxv2i16_i8:556; CHECK: # %bb.0: # %entry557; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu558; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t559; CHECK-NEXT: ret560entry:561 %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.mask.nxv2i16.i8(562 <vscale x 2 x i16> %0,563 <vscale x 2 x i16> %1,564 i8 %2,565 <vscale x 2 x i1> %3,566 iXLen %4, iXLen 1)567 568 ret <vscale x 2 x i16> %a569}570 571define <vscale x 4 x i16> @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, iXLen %2) nounwind {572; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8:573; CHECK: # %bb.0: # %entry574; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma575; CHECK-NEXT: vwsubu.wx v8, v8, a0576; CHECK-NEXT: ret577entry:578 %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8(579 <vscale x 4 x i16> poison,580 <vscale x 4 x i16> %0,581 i8 %1,582 iXLen %2)583 584 ret <vscale x 4 x i16> %a585}586 587define <vscale x 4 x i16> @intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {588; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i16_nxv4i16_i8:589; CHECK: # %bb.0: # %entry590; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu591; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t592; CHECK-NEXT: ret593entry:594 %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.mask.nxv4i16.i8(595 <vscale x 4 x i16> %0,596 <vscale x 4 x i16> %1,597 i8 %2,598 <vscale x 4 x i1> %3,599 iXLen %4, iXLen 1)600 601 ret <vscale x 4 x i16> %a602}603 604define <vscale x 8 x i16> @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, iXLen %2) nounwind {605; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8:606; CHECK: # %bb.0: # %entry607; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma608; CHECK-NEXT: vwsubu.wx v8, v8, a0609; CHECK-NEXT: ret610entry:611 %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8(612 <vscale x 8 x i16> poison,613 <vscale x 8 x i16> %0,614 i8 %1,615 iXLen %2)616 617 ret <vscale x 8 x i16> %a618}619 620define <vscale x 8 x i16> @intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {621; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i16_nxv8i16_i8:622; CHECK: # %bb.0: # %entry623; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu624; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t625; CHECK-NEXT: ret626entry:627 %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.mask.nxv8i16.i8(628 <vscale x 8 x i16> %0,629 <vscale x 8 x i16> %1,630 i8 %2,631 <vscale x 8 x i1> %3,632 iXLen %4, iXLen 1)633 634 ret <vscale x 8 x i16> %a635}636 637define <vscale x 16 x i16> @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, iXLen %2) nounwind {638; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8:639; CHECK: # %bb.0: # %entry640; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma641; CHECK-NEXT: vwsubu.wx v8, v8, a0642; CHECK-NEXT: ret643entry:644 %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8(645 <vscale x 16 x i16> poison,646 <vscale x 16 x i16> %0,647 i8 %1,648 iXLen %2)649 650 ret <vscale x 16 x i16> %a651}652 653define <vscale x 16 x i16> @intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {654; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i16_nxv16i16_i8:655; CHECK: # %bb.0: # %entry656; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu657; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t658; CHECK-NEXT: ret659entry:660 %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.mask.nxv16i16.i8(661 <vscale x 16 x i16> %0,662 <vscale x 16 x i16> %1,663 i8 %2,664 <vscale x 16 x i1> %3,665 iXLen %4, iXLen 1)666 667 ret <vscale x 16 x i16> %a668}669 670define <vscale x 32 x i16> @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, iXLen %2) nounwind {671; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8:672; CHECK: # %bb.0: # %entry673; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma674; CHECK-NEXT: vwsubu.wx v8, v8, a0675; CHECK-NEXT: ret676entry:677 %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8(678 <vscale x 32 x i16> poison,679 <vscale x 32 x i16> %0,680 i8 %1,681 iXLen %2)682 683 ret <vscale x 32 x i16> %a684}685 686define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {687; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv32i16_nxv32i16_i8:688; CHECK: # %bb.0: # %entry689; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu690; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t691; CHECK-NEXT: ret692entry:693 %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.i8(694 <vscale x 32 x i16> %0,695 <vscale x 32 x i16> %1,696 i8 %2,697 <vscale x 32 x i1> %3,698 iXLen %4, iXLen 1)699 700 ret <vscale x 32 x i16> %a701}702 703define <vscale x 1 x i32> @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, iXLen %2) nounwind {704; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16:705; CHECK: # %bb.0: # %entry706; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma707; CHECK-NEXT: vwsubu.wx v8, v8, a0708; CHECK-NEXT: ret709entry:710 %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16(711 <vscale x 1 x i32> poison,712 <vscale x 1 x i32> %0,713 i16 %1,714 iXLen %2)715 716 ret <vscale x 1 x i32> %a717}718 719define <vscale x 1 x i32> @intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {720; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i32_nxv1i32_i16:721; CHECK: # %bb.0: # %entry722; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu723; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t724; CHECK-NEXT: ret725entry:726 %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.mask.nxv1i32.i16(727 <vscale x 1 x i32> %0,728 <vscale x 1 x i32> %1,729 i16 %2,730 <vscale x 1 x i1> %3,731 iXLen %4, iXLen 1)732 733 ret <vscale x 1 x i32> %a734}735 736define <vscale x 2 x i32> @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, iXLen %2) nounwind {737; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16:738; CHECK: # %bb.0: # %entry739; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma740; CHECK-NEXT: vwsubu.wx v8, v8, a0741; CHECK-NEXT: ret742entry:743 %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16(744 <vscale x 2 x i32> poison,745 <vscale x 2 x i32> %0,746 i16 %1,747 iXLen %2)748 749 ret <vscale x 2 x i32> %a750}751 752define <vscale x 2 x i32> @intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {753; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i32_nxv2i32_i16:754; CHECK: # %bb.0: # %entry755; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu756; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t757; CHECK-NEXT: ret758entry:759 %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.mask.nxv2i32.i16(760 <vscale x 2 x i32> %0,761 <vscale x 2 x i32> %1,762 i16 %2,763 <vscale x 2 x i1> %3,764 iXLen %4, iXLen 1)765 766 ret <vscale x 2 x i32> %a767}768 769define <vscale x 4 x i32> @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, iXLen %2) nounwind {770; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16:771; CHECK: # %bb.0: # %entry772; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma773; CHECK-NEXT: vwsubu.wx v8, v8, a0774; CHECK-NEXT: ret775entry:776 %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16(777 <vscale x 4 x i32> poison,778 <vscale x 4 x i32> %0,779 i16 %1,780 iXLen %2)781 782 ret <vscale x 4 x i32> %a783}784 785define <vscale x 4 x i32> @intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {786; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i32_nxv4i32_i16:787; CHECK: # %bb.0: # %entry788; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu789; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t790; CHECK-NEXT: ret791entry:792 %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.mask.nxv4i32.i16(793 <vscale x 4 x i32> %0,794 <vscale x 4 x i32> %1,795 i16 %2,796 <vscale x 4 x i1> %3,797 iXLen %4, iXLen 1)798 799 ret <vscale x 4 x i32> %a800}801 802define <vscale x 8 x i32> @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, iXLen %2) nounwind {803; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16:804; CHECK: # %bb.0: # %entry805; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma806; CHECK-NEXT: vwsubu.wx v8, v8, a0807; CHECK-NEXT: ret808entry:809 %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16(810 <vscale x 8 x i32> poison,811 <vscale x 8 x i32> %0,812 i16 %1,813 iXLen %2)814 815 ret <vscale x 8 x i32> %a816}817 818define <vscale x 8 x i32> @intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {819; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i32_nxv8i32_i16:820; CHECK: # %bb.0: # %entry821; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu822; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t823; CHECK-NEXT: ret824entry:825 %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.mask.nxv8i32.i16(826 <vscale x 8 x i32> %0,827 <vscale x 8 x i32> %1,828 i16 %2,829 <vscale x 8 x i1> %3,830 iXLen %4, iXLen 1)831 832 ret <vscale x 8 x i32> %a833}834 835define <vscale x 16 x i32> @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, iXLen %2) nounwind {836; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16:837; CHECK: # %bb.0: # %entry838; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma839; CHECK-NEXT: vwsubu.wx v8, v8, a0840; CHECK-NEXT: ret841entry:842 %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16(843 <vscale x 16 x i32> poison,844 <vscale x 16 x i32> %0,845 i16 %1,846 iXLen %2)847 848 ret <vscale x 16 x i32> %a849}850 851define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {852; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv16i32_nxv16i32_i16:853; CHECK: # %bb.0: # %entry854; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu855; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t856; CHECK-NEXT: ret857entry:858 %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.i16(859 <vscale x 16 x i32> %0,860 <vscale x 16 x i32> %1,861 i16 %2,862 <vscale x 16 x i1> %3,863 iXLen %4, iXLen 1)864 865 ret <vscale x 16 x i32> %a866}867 868define <vscale x 1 x i64> @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, iXLen %2) nounwind {869; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32:870; CHECK: # %bb.0: # %entry871; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma872; CHECK-NEXT: vwsubu.wx v8, v8, a0873; CHECK-NEXT: ret874entry:875 %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32(876 <vscale x 1 x i64> poison,877 <vscale x 1 x i64> %0,878 i32 %1,879 iXLen %2)880 881 ret <vscale x 1 x i64> %a882}883 884define <vscale x 1 x i64> @intrinsic_vwsubu.w_mask_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {885; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv1i64_nxv1i64_i32:886; CHECK: # %bb.0: # %entry887; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu888; CHECK-NEXT: vwsubu.wx v8, v9, a0, v0.t889; CHECK-NEXT: ret890entry:891 %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.mask.nxv1i64.i32(892 <vscale x 1 x i64> %0,893 <vscale x 1 x i64> %1,894 i32 %2,895 <vscale x 1 x i1> %3,896 iXLen %4, iXLen 1)897 898 ret <vscale x 1 x i64> %a899}900 901define <vscale x 2 x i64> @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, iXLen %2) nounwind {902; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32:903; CHECK: # %bb.0: # %entry904; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma905; CHECK-NEXT: vwsubu.wx v8, v8, a0906; CHECK-NEXT: ret907entry:908 %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32(909 <vscale x 2 x i64> poison,910 <vscale x 2 x i64> %0,911 i32 %1,912 iXLen %2)913 914 ret <vscale x 2 x i64> %a915}916 917define <vscale x 2 x i64> @intrinsic_vwsubu.w_mask_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {918; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv2i64_nxv2i64_i32:919; CHECK: # %bb.0: # %entry920; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu921; CHECK-NEXT: vwsubu.wx v8, v10, a0, v0.t922; CHECK-NEXT: ret923entry:924 %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.mask.nxv2i64.i32(925 <vscale x 2 x i64> %0,926 <vscale x 2 x i64> %1,927 i32 %2,928 <vscale x 2 x i1> %3,929 iXLen %4, iXLen 1)930 931 ret <vscale x 2 x i64> %a932}933 934define <vscale x 4 x i64> @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, iXLen %2) nounwind {935; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32:936; CHECK: # %bb.0: # %entry937; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma938; CHECK-NEXT: vwsubu.wx v8, v8, a0939; CHECK-NEXT: ret940entry:941 %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32(942 <vscale x 4 x i64> poison,943 <vscale x 4 x i64> %0,944 i32 %1,945 iXLen %2)946 947 ret <vscale x 4 x i64> %a948}949 950define <vscale x 4 x i64> @intrinsic_vwsubu.w_mask_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {951; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv4i64_nxv4i64_i32:952; CHECK: # %bb.0: # %entry953; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu954; CHECK-NEXT: vwsubu.wx v8, v12, a0, v0.t955; CHECK-NEXT: ret956entry:957 %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.mask.nxv4i64.i32(958 <vscale x 4 x i64> %0,959 <vscale x 4 x i64> %1,960 i32 %2,961 <vscale x 4 x i1> %3,962 iXLen %4, iXLen 1)963 964 ret <vscale x 4 x i64> %a965}966 967define <vscale x 8 x i64> @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, iXLen %2) nounwind {968; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32:969; CHECK: # %bb.0: # %entry970; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma971; CHECK-NEXT: vwsubu.wx v8, v8, a0972; CHECK-NEXT: ret973entry:974 %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32(975 <vscale x 8 x i64> poison,976 <vscale x 8 x i64> %0,977 i32 %1,978 iXLen %2)979 980 ret <vscale x 8 x i64> %a981}982 983define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {984; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_nxv8i64_nxv8i64_i32:985; CHECK: # %bb.0: # %entry986; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu987; CHECK-NEXT: vwsubu.wx v8, v16, a0, v0.t988; CHECK-NEXT: ret989entry:990 %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.i32(991 <vscale x 8 x i64> %0,992 <vscale x 8 x i64> %1,993 i32 %2,994 <vscale x 8 x i1> %3,995 iXLen %4, iXLen 1)996 997 ret <vscale x 8 x i64> %a998}999 1000define <vscale x 1 x i16> @intrinsic_vwsubu.w_mask_wv_tie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1001; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv1i16_nxv1i16_nxv1i8:1002; CHECK: # %bb.0: # %entry1003; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu1004; CHECK-NEXT: vwsubu.wv v8, v8, v9, v0.t1005; CHECK-NEXT: ret1006entry:1007 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.mask.nxv1i16.nxv1i8(1008 <vscale x 1 x i16> %0,1009 <vscale x 1 x i16> %0,1010 <vscale x 1 x i8> %1,1011 <vscale x 1 x i1> %2,1012 iXLen %3, iXLen 1)1013 1014 ret <vscale x 1 x i16> %a1015}1016 1017define <vscale x 2 x i16> @intrinsic_vwsubu.w_mask_wv_tie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1018; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv2i16_nxv2i16_nxv2i8:1019; CHECK: # %bb.0: # %entry1020; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu1021; CHECK-NEXT: vwsubu.wv v8, v8, v9, v0.t1022; CHECK-NEXT: ret1023entry:1024 %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.mask.nxv2i16.nxv2i8(1025 <vscale x 2 x i16> %0,1026 <vscale x 2 x i16> %0,1027 <vscale x 2 x i8> %1,1028 <vscale x 2 x i1> %2,1029 iXLen %3, iXLen 1)1030 1031 ret <vscale x 2 x i16> %a1032}1033 1034define <vscale x 4 x i16> @intrinsic_vwsubu.w_mask_wv_tie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1035; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv4i16_nxv4i16_nxv4i8:1036; CHECK: # %bb.0: # %entry1037; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu1038; CHECK-NEXT: vwsubu.wv v8, v8, v9, v0.t1039; CHECK-NEXT: ret1040entry:1041 %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.mask.nxv4i16.nxv4i8(1042 <vscale x 4 x i16> %0,1043 <vscale x 4 x i16> %0,1044 <vscale x 4 x i8> %1,1045 <vscale x 4 x i1> %2,1046 iXLen %3, iXLen 1)1047 1048 ret <vscale x 4 x i16> %a1049}1050 1051define <vscale x 8 x i16> @intrinsic_vwsubu.w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1052; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv8i16_nxv8i16_nxv8i8:1053; CHECK: # %bb.0: # %entry1054; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu1055; CHECK-NEXT: vwsubu.wv v8, v8, v10, v0.t1056; CHECK-NEXT: ret1057entry:1058 %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.mask.nxv8i16.nxv8i8(1059 <vscale x 8 x i16> %0,1060 <vscale x 8 x i16> %0,1061 <vscale x 8 x i8> %1,1062 <vscale x 8 x i1> %2,1063 iXLen %3, iXLen 1)1064 1065 ret <vscale x 8 x i16> %a1066}1067 1068define <vscale x 16 x i16> @intrinsic_vwsubu.w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1069; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv16i16_nxv16i16_nxv16i8:1070; CHECK: # %bb.0: # %entry1071; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu1072; CHECK-NEXT: vwsubu.wv v8, v8, v12, v0.t1073; CHECK-NEXT: ret1074entry:1075 %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.mask.nxv16i16.nxv16i8(1076 <vscale x 16 x i16> %0,1077 <vscale x 16 x i16> %0,1078 <vscale x 16 x i8> %1,1079 <vscale x 16 x i1> %2,1080 iXLen %3, iXLen 1)1081 1082 ret <vscale x 16 x i16> %a1083}1084 1085define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1086; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv32i16_nxv32i16_nxv32i8:1087; CHECK: # %bb.0: # %entry1088; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu1089; CHECK-NEXT: vwsubu.wv v8, v8, v16, v0.t1090; CHECK-NEXT: ret1091entry:1092 %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.nxv32i8(1093 <vscale x 32 x i16> %0,1094 <vscale x 32 x i16> %0,1095 <vscale x 32 x i8> %1,1096 <vscale x 32 x i1> %2,1097 iXLen %3, iXLen 1)1098 1099 ret <vscale x 32 x i16> %a1100}1101 1102define <vscale x 1 x i32> @intrinsic_vwsubu.w_mask_wv_tie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1103; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv1i32_nxv1i32_nxv1i16:1104; CHECK: # %bb.0: # %entry1105; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1106; CHECK-NEXT: vwsubu.wv v8, v8, v9, v0.t1107; CHECK-NEXT: ret1108entry:1109 %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.mask.nxv1i32.nxv1i16(1110 <vscale x 1 x i32> %0,1111 <vscale x 1 x i32> %0,1112 <vscale x 1 x i16> %1,1113 <vscale x 1 x i1> %2,1114 iXLen %3, iXLen 1)1115 1116 ret <vscale x 1 x i32> %a1117}1118 1119define <vscale x 2 x i32> @intrinsic_vwsubu.w_mask_wv_tie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1120; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv2i32_nxv2i32_nxv2i16:1121; CHECK: # %bb.0: # %entry1122; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1123; CHECK-NEXT: vwsubu.wv v8, v8, v9, v0.t1124; CHECK-NEXT: ret1125entry:1126 %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.mask.nxv2i32.nxv2i16(1127 <vscale x 2 x i32> %0,1128 <vscale x 2 x i32> %0,1129 <vscale x 2 x i16> %1,1130 <vscale x 2 x i1> %2,1131 iXLen %3, iXLen 1)1132 1133 ret <vscale x 2 x i32> %a1134}1135 1136define <vscale x 4 x i32> @intrinsic_vwsubu.w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1137; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv4i32_nxv4i32_nxv4i16:1138; CHECK: # %bb.0: # %entry1139; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1140; CHECK-NEXT: vwsubu.wv v8, v8, v10, v0.t1141; CHECK-NEXT: ret1142entry:1143 %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.mask.nxv4i32.nxv4i16(1144 <vscale x 4 x i32> %0,1145 <vscale x 4 x i32> %0,1146 <vscale x 4 x i16> %1,1147 <vscale x 4 x i1> %2,1148 iXLen %3, iXLen 1)1149 1150 ret <vscale x 4 x i32> %a1151}1152 1153define <vscale x 8 x i32> @intrinsic_vwsubu.w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1154; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv8i32_nxv8i32_nxv8i16:1155; CHECK: # %bb.0: # %entry1156; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1157; CHECK-NEXT: vwsubu.wv v8, v8, v12, v0.t1158; CHECK-NEXT: ret1159entry:1160 %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.mask.nxv8i32.nxv8i16(1161 <vscale x 8 x i32> %0,1162 <vscale x 8 x i32> %0,1163 <vscale x 8 x i16> %1,1164 <vscale x 8 x i1> %2,1165 iXLen %3, iXLen 1)1166 1167 ret <vscale x 8 x i32> %a1168}1169 1170define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1171; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv16i32_nxv16i32_nxv16i16:1172; CHECK: # %bb.0: # %entry1173; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1174; CHECK-NEXT: vwsubu.wv v8, v8, v16, v0.t1175; CHECK-NEXT: ret1176entry:1177 %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.nxv16i16(1178 <vscale x 16 x i32> %0,1179 <vscale x 16 x i32> %0,1180 <vscale x 16 x i16> %1,1181 <vscale x 16 x i1> %2,1182 iXLen %3, iXLen 1)1183 1184 ret <vscale x 16 x i32> %a1185}1186 1187define <vscale x 1 x i64> @intrinsic_vwsubu.w_mask_wv_tie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1188; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv1i64_nxv1i64_nxv1i32:1189; CHECK: # %bb.0: # %entry1190; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu1191; CHECK-NEXT: vwsubu.wv v8, v8, v9, v0.t1192; CHECK-NEXT: ret1193entry:1194 %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.mask.nxv1i64.nxv1i32(1195 <vscale x 1 x i64> %0,1196 <vscale x 1 x i64> %0,1197 <vscale x 1 x i32> %1,1198 <vscale x 1 x i1> %2,1199 iXLen %3, iXLen 1)1200 1201 ret <vscale x 1 x i64> %a1202}1203 1204define <vscale x 2 x i64> @intrinsic_vwsubu.w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1205; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv2i64_nxv2i64_nxv2i32:1206; CHECK: # %bb.0: # %entry1207; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu1208; CHECK-NEXT: vwsubu.wv v8, v8, v10, v0.t1209; CHECK-NEXT: ret1210entry:1211 %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.mask.nxv2i64.nxv2i32(1212 <vscale x 2 x i64> %0,1213 <vscale x 2 x i64> %0,1214 <vscale x 2 x i32> %1,1215 <vscale x 2 x i1> %2,1216 iXLen %3, iXLen 1)1217 1218 ret <vscale x 2 x i64> %a1219}1220 1221define <vscale x 4 x i64> @intrinsic_vwsubu.w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1222; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv4i64_nxv4i64_nxv4i32:1223; CHECK: # %bb.0: # %entry1224; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu1225; CHECK-NEXT: vwsubu.wv v8, v8, v12, v0.t1226; CHECK-NEXT: ret1227entry:1228 %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.mask.nxv4i64.nxv4i32(1229 <vscale x 4 x i64> %0,1230 <vscale x 4 x i64> %0,1231 <vscale x 4 x i32> %1,1232 <vscale x 4 x i1> %2,1233 iXLen %3, iXLen 1)1234 1235 ret <vscale x 4 x i64> %a1236}1237 1238define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1239; CHECK-LABEL: intrinsic_vwsubu.w_mask_wv_tie_nxv8i64_nxv8i64_nxv8i32:1240; CHECK: # %bb.0: # %entry1241; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu1242; CHECK-NEXT: vwsubu.wv v8, v8, v16, v0.t1243; CHECK-NEXT: ret1244entry:1245 %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.nxv8i32(1246 <vscale x 8 x i64> %0,1247 <vscale x 8 x i64> %0,1248 <vscale x 8 x i32> %1,1249 <vscale x 8 x i1> %2,1250 iXLen %3, iXLen 1)1251 1252 ret <vscale x 8 x i64> %a1253}1254 1255define <vscale x 1 x i16> @intrinsic_vwsubu.w_mask_wx_tie_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1256; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv1i16_nxv1i16_i8:1257; CHECK: # %bb.0: # %entry1258; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu1259; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1260; CHECK-NEXT: ret1261entry:1262 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.mask.nxv1i16.i8(1263 <vscale x 1 x i16> %0,1264 <vscale x 1 x i16> %0,1265 i8 %1,1266 <vscale x 1 x i1> %2,1267 iXLen %3, iXLen 1)1268 1269 ret <vscale x 1 x i16> %a1270}1271 1272define <vscale x 2 x i16> @intrinsic_vwsubu.w_mask_wx_tie_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1273; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv2i16_nxv2i16_i8:1274; CHECK: # %bb.0: # %entry1275; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu1276; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1277; CHECK-NEXT: ret1278entry:1279 %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.mask.nxv2i16.i8(1280 <vscale x 2 x i16> %0,1281 <vscale x 2 x i16> %0,1282 i8 %1,1283 <vscale x 2 x i1> %2,1284 iXLen %3, iXLen 1)1285 1286 ret <vscale x 2 x i16> %a1287}1288 1289define <vscale x 4 x i16> @intrinsic_vwsubu.w_mask_wx_tie_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1290; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv4i16_nxv4i16_i8:1291; CHECK: # %bb.0: # %entry1292; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu1293; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1294; CHECK-NEXT: ret1295entry:1296 %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.mask.nxv4i16.i8(1297 <vscale x 4 x i16> %0,1298 <vscale x 4 x i16> %0,1299 i8 %1,1300 <vscale x 4 x i1> %2,1301 iXLen %3, iXLen 1)1302 1303 ret <vscale x 4 x i16> %a1304}1305 1306define <vscale x 8 x i16> @intrinsic_vwsubu.w_mask_wx_tie_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1307; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv8i16_nxv8i16_i8:1308; CHECK: # %bb.0: # %entry1309; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu1310; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1311; CHECK-NEXT: ret1312entry:1313 %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.mask.nxv8i16.i8(1314 <vscale x 8 x i16> %0,1315 <vscale x 8 x i16> %0,1316 i8 %1,1317 <vscale x 8 x i1> %2,1318 iXLen %3, iXLen 1)1319 1320 ret <vscale x 8 x i16> %a1321}1322 1323define <vscale x 16 x i16> @intrinsic_vwsubu.w_mask_wx_tie_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1324; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv16i16_nxv16i16_i8:1325; CHECK: # %bb.0: # %entry1326; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu1327; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1328; CHECK-NEXT: ret1329entry:1330 %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.mask.nxv16i16.i8(1331 <vscale x 16 x i16> %0,1332 <vscale x 16 x i16> %0,1333 i8 %1,1334 <vscale x 16 x i1> %2,1335 iXLen %3, iXLen 1)1336 1337 ret <vscale x 16 x i16> %a1338}1339 1340define <vscale x 32 x i16> @intrinsic_vwsubu.w_mask_wx_tie_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1341; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv32i16_nxv32i16_i8:1342; CHECK: # %bb.0: # %entry1343; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu1344; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1345; CHECK-NEXT: ret1346entry:1347 %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.mask.nxv32i16.i8(1348 <vscale x 32 x i16> %0,1349 <vscale x 32 x i16> %0,1350 i8 %1,1351 <vscale x 32 x i1> %2,1352 iXLen %3, iXLen 1)1353 1354 ret <vscale x 32 x i16> %a1355}1356 1357define <vscale x 1 x i32> @intrinsic_vwsubu.w_mask_wx_tie_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1358; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv1i32_nxv1i32_i16:1359; CHECK: # %bb.0: # %entry1360; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1361; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1362; CHECK-NEXT: ret1363entry:1364 %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.mask.nxv1i32.i16(1365 <vscale x 1 x i32> %0,1366 <vscale x 1 x i32> %0,1367 i16 %1,1368 <vscale x 1 x i1> %2,1369 iXLen %3, iXLen 1)1370 1371 ret <vscale x 1 x i32> %a1372}1373 1374define <vscale x 2 x i32> @intrinsic_vwsubu.w_mask_wx_tie_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1375; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv2i32_nxv2i32_i16:1376; CHECK: # %bb.0: # %entry1377; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1378; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1379; CHECK-NEXT: ret1380entry:1381 %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.mask.nxv2i32.i16(1382 <vscale x 2 x i32> %0,1383 <vscale x 2 x i32> %0,1384 i16 %1,1385 <vscale x 2 x i1> %2,1386 iXLen %3, iXLen 1)1387 1388 ret <vscale x 2 x i32> %a1389}1390 1391define <vscale x 4 x i32> @intrinsic_vwsubu.w_mask_wx_tie_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1392; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv4i32_nxv4i32_i16:1393; CHECK: # %bb.0: # %entry1394; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1395; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1396; CHECK-NEXT: ret1397entry:1398 %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.mask.nxv4i32.i16(1399 <vscale x 4 x i32> %0,1400 <vscale x 4 x i32> %0,1401 i16 %1,1402 <vscale x 4 x i1> %2,1403 iXLen %3, iXLen 1)1404 1405 ret <vscale x 4 x i32> %a1406}1407 1408define <vscale x 8 x i32> @intrinsic_vwsubu.w_mask_wx_tie_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1409; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv8i32_nxv8i32_i16:1410; CHECK: # %bb.0: # %entry1411; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1412; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1413; CHECK-NEXT: ret1414entry:1415 %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.mask.nxv8i32.i16(1416 <vscale x 8 x i32> %0,1417 <vscale x 8 x i32> %0,1418 i16 %1,1419 <vscale x 8 x i1> %2,1420 iXLen %3, iXLen 1)1421 1422 ret <vscale x 8 x i32> %a1423}1424 1425define <vscale x 16 x i32> @intrinsic_vwsubu.w_mask_wx_tie_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1426; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv16i32_nxv16i32_i16:1427; CHECK: # %bb.0: # %entry1428; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1429; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1430; CHECK-NEXT: ret1431entry:1432 %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.mask.nxv16i32.i16(1433 <vscale x 16 x i32> %0,1434 <vscale x 16 x i32> %0,1435 i16 %1,1436 <vscale x 16 x i1> %2,1437 iXLen %3, iXLen 1)1438 1439 ret <vscale x 16 x i32> %a1440}1441 1442define <vscale x 1 x i64> @intrinsic_vwsubu.w_mask_wx_tie_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1443; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv1i64_nxv1i64_i32:1444; CHECK: # %bb.0: # %entry1445; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1446; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1447; CHECK-NEXT: ret1448entry:1449 %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.mask.nxv1i64.i32(1450 <vscale x 1 x i64> %0,1451 <vscale x 1 x i64> %0,1452 i32 %1,1453 <vscale x 1 x i1> %2,1454 iXLen %3, iXLen 1)1455 1456 ret <vscale x 1 x i64> %a1457}1458 1459define <vscale x 2 x i64> @intrinsic_vwsubu.w_mask_wx_tie_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1460; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv2i64_nxv2i64_i32:1461; CHECK: # %bb.0: # %entry1462; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1463; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1464; CHECK-NEXT: ret1465entry:1466 %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.mask.nxv2i64.i32(1467 <vscale x 2 x i64> %0,1468 <vscale x 2 x i64> %0,1469 i32 %1,1470 <vscale x 2 x i1> %2,1471 iXLen %3, iXLen 1)1472 1473 ret <vscale x 2 x i64> %a1474}1475 1476define <vscale x 4 x i64> @intrinsic_vwsubu.w_mask_wx_tie_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1477; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv4i64_nxv4i64_i32:1478; CHECK: # %bb.0: # %entry1479; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1480; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1481; CHECK-NEXT: ret1482entry:1483 %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.mask.nxv4i64.i32(1484 <vscale x 4 x i64> %0,1485 <vscale x 4 x i64> %0,1486 i32 %1,1487 <vscale x 4 x i1> %2,1488 iXLen %3, iXLen 1)1489 1490 ret <vscale x 4 x i64> %a1491}1492 1493define <vscale x 8 x i64> @intrinsic_vwsubu.w_mask_wx_tie_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1494; CHECK-LABEL: intrinsic_vwsubu.w_mask_wx_tie_nxv8i64_nxv8i64_i32:1495; CHECK: # %bb.0: # %entry1496; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1497; CHECK-NEXT: vwsubu.wx v8, v8, a0, v0.t1498; CHECK-NEXT: ret1499entry:1500 %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.mask.nxv8i64.i32(1501 <vscale x 8 x i64> %0,1502 <vscale x 8 x i64> %0,1503 i32 %1,1504 <vscale x 8 x i1> %2,1505 iXLen %3, iXLen 1)1506 1507 ret <vscale x 8 x i64> %a1508}1509 1510define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1511; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:1512; CHECK: # %bb.0: # %entry1513; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1514; CHECK-NEXT: vwsubu.wv v10, v9, v81515; CHECK-NEXT: vmv1r.v v8, v101516; CHECK-NEXT: ret1517entry:1518 %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(1519 <vscale x 1 x i16> poison,1520 <vscale x 1 x i16> %1,1521 <vscale x 1 x i8> %0,1522 iXLen %2)1523 1524 ret <vscale x 1 x i16> %a1525}1526 1527define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1528; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:1529; CHECK: # %bb.0: # %entry1530; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1531; CHECK-NEXT: vwsubu.wv v10, v9, v81532; CHECK-NEXT: vmv1r.v v8, v101533; CHECK-NEXT: ret1534entry:1535 %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(1536 <vscale x 2 x i16> poison,1537 <vscale x 2 x i16> %1,1538 <vscale x 2 x i8> %0,1539 iXLen %2)1540 1541 ret <vscale x 2 x i16> %a1542}1543 1544define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1545; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:1546; CHECK: # %bb.0: # %entry1547; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma1548; CHECK-NEXT: vwsubu.wv v10, v9, v81549; CHECK-NEXT: vmv1r.v v8, v101550; CHECK-NEXT: ret1551entry:1552 %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(1553 <vscale x 4 x i16> poison,1554 <vscale x 4 x i16> %1,1555 <vscale x 4 x i8> %0,1556 iXLen %2)1557 1558 ret <vscale x 4 x i16> %a1559}1560 1561define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1562; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:1563; CHECK: # %bb.0: # %entry1564; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma1565; CHECK-NEXT: vmv1r.v v12, v81566; CHECK-NEXT: vwsubu.wv v8, v10, v121567; CHECK-NEXT: ret1568entry:1569 %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(1570 <vscale x 8 x i16> poison,1571 <vscale x 8 x i16> %1,1572 <vscale x 8 x i8> %0,1573 iXLen %2)1574 1575 ret <vscale x 8 x i16> %a1576}1577 1578define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1579; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:1580; CHECK: # %bb.0: # %entry1581; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1582; CHECK-NEXT: vmv2r.v v16, v81583; CHECK-NEXT: vwsubu.wv v8, v12, v161584; CHECK-NEXT: ret1585entry:1586 %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(1587 <vscale x 16 x i16> poison,1588 <vscale x 16 x i16> %1,1589 <vscale x 16 x i8> %0,1590 iXLen %2)1591 1592 ret <vscale x 16 x i16> %a1593}1594 1595define <vscale x 32 x i16> @intrinsic_vwsubu.w_wv_untie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1596; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv32i16_nxv32i16_nxv32i8:1597; CHECK: # %bb.0: # %entry1598; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma1599; CHECK-NEXT: vmv4r.v v24, v81600; CHECK-NEXT: vwsubu.wv v8, v16, v241601; CHECK-NEXT: ret1602entry:1603 %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8(1604 <vscale x 32 x i16> poison,1605 <vscale x 32 x i16> %1,1606 <vscale x 32 x i8> %0,1607 iXLen %2)1608 1609 ret <vscale x 32 x i16> %a1610}1611 1612define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {1613; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:1614; CHECK: # %bb.0: # %entry1615; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1616; CHECK-NEXT: vwsubu.wv v10, v9, v81617; CHECK-NEXT: vmv1r.v v8, v101618; CHECK-NEXT: ret1619entry:1620 %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(1621 <vscale x 1 x i32> poison,1622 <vscale x 1 x i32> %1,1623 <vscale x 1 x i16> %0,1624 iXLen %2)1625 1626 ret <vscale x 1 x i32> %a1627}1628 1629define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {1630; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:1631; CHECK: # %bb.0: # %entry1632; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1633; CHECK-NEXT: vwsubu.wv v10, v9, v81634; CHECK-NEXT: vmv1r.v v8, v101635; CHECK-NEXT: ret1636entry:1637 %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(1638 <vscale x 2 x i32> poison,1639 <vscale x 2 x i32> %1,1640 <vscale x 2 x i16> %0,1641 iXLen %2)1642 1643 ret <vscale x 2 x i32> %a1644}1645 1646define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {1647; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:1648; CHECK: # %bb.0: # %entry1649; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1650; CHECK-NEXT: vmv1r.v v12, v81651; CHECK-NEXT: vwsubu.wv v8, v10, v121652; CHECK-NEXT: ret1653entry:1654 %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(1655 <vscale x 4 x i32> poison,1656 <vscale x 4 x i32> %1,1657 <vscale x 4 x i16> %0,1658 iXLen %2)1659 1660 ret <vscale x 4 x i32> %a1661}1662 1663define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {1664; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:1665; CHECK: # %bb.0: # %entry1666; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1667; CHECK-NEXT: vmv2r.v v16, v81668; CHECK-NEXT: vwsubu.wv v8, v12, v161669; CHECK-NEXT: ret1670entry:1671 %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(1672 <vscale x 8 x i32> poison,1673 <vscale x 8 x i32> %1,1674 <vscale x 8 x i16> %0,1675 iXLen %2)1676 1677 ret <vscale x 8 x i32> %a1678}1679 1680define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {1681; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:1682; CHECK: # %bb.0: # %entry1683; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1684; CHECK-NEXT: vwsubu.wv v10, v9, v81685; CHECK-NEXT: vmv1r.v v8, v101686; CHECK-NEXT: ret1687entry:1688 %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(1689 <vscale x 1 x i64> poison,1690 <vscale x 1 x i64> %1,1691 <vscale x 1 x i32> %0,1692 iXLen %2)1693 1694 ret <vscale x 1 x i64> %a1695}1696 1697define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {1698; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:1699; CHECK: # %bb.0: # %entry1700; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1701; CHECK-NEXT: vmv1r.v v12, v81702; CHECK-NEXT: vwsubu.wv v8, v10, v121703; CHECK-NEXT: ret1704entry:1705 %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(1706 <vscale x 2 x i64> poison,1707 <vscale x 2 x i64> %1,1708 <vscale x 2 x i32> %0,1709 iXLen %2)1710 1711 ret <vscale x 2 x i64> %a1712}1713 1714define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {1715; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:1716; CHECK: # %bb.0: # %entry1717; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1718; CHECK-NEXT: vmv2r.v v16, v81719; CHECK-NEXT: vwsubu.wv v8, v12, v161720; CHECK-NEXT: ret1721entry:1722 %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(1723 <vscale x 4 x i64> poison,1724 <vscale x 4 x i64> %1,1725 <vscale x 4 x i32> %0,1726 iXLen %2)1727 1728 ret <vscale x 4 x i64> %a1729}1730 1731define <vscale x 8 x i64> @intrinsic_vwsubu.w_wv_untie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {1732; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i64_nxv8i64_nxv8i32:1733; CHECK: # %bb.0: # %entry1734; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1735; CHECK-NEXT: vmv4r.v v24, v81736; CHECK-NEXT: vwsubu.wv v8, v16, v241737; CHECK-NEXT: ret1738entry:1739 %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32(1740 <vscale x 8 x i64> poison,1741 <vscale x 8 x i64> %1,1742 <vscale x 8 x i32> %0,1743 iXLen %2)1744 1745 ret <vscale x 8 x i64> %a1746}1747