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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 8 x i7> @vxor_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: vxor_vx_nxv8i7:9; CHECK:       # %bb.0:10; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma11; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t12; CHECK-NEXT:    ret13  %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 014  %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer15  %v = call <vscale x 8 x i7> @llvm.vp.xor.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)16  ret <vscale x 8 x i7> %v17}18 19define <vscale x 1 x i8> @vxor_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {20; CHECK-LABEL: vxor_vv_nxv1i8:21; CHECK:       # %bb.0:22; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma23; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t24; CHECK-NEXT:    ret25  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)26  ret <vscale x 1 x i8> %v27}28 29define <vscale x 1 x i8> @vxor_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {30; CHECK-LABEL: vxor_vv_nxv1i8_unmasked:31; CHECK:       # %bb.0:32; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma33; CHECK-NEXT:    vxor.vv v8, v8, v934; CHECK-NEXT:    ret35  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)36  ret <vscale x 1 x i8> %v37}38 39define <vscale x 1 x i8> @vxor_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {40; CHECK-LABEL: vxor_vx_nxv1i8:41; CHECK:       # %bb.0:42; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma43; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t44; CHECK-NEXT:    ret45  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 046  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer47  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)48  ret <vscale x 1 x i8> %v49}50 51define <vscale x 1 x i8> @vxor_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {52; CHECK-LABEL: vxor_vx_nxv1i8_unmasked:53; CHECK:       # %bb.0:54; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma55; CHECK-NEXT:    vxor.vx v8, v8, a056; CHECK-NEXT:    ret57  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 058  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer59  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)60  ret <vscale x 1 x i8> %v61}62 63define <vscale x 1 x i8> @vxor_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {64; CHECK-LABEL: vxor_vi_nxv1i8:65; CHECK:       # %bb.0:66; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma67; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t68; CHECK-NEXT:    ret69  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 7), <vscale x 1 x i1> %m, i32 %evl)70  ret <vscale x 1 x i8> %v71}72 73define <vscale x 1 x i8> @vxor_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {74; CHECK-LABEL: vxor_vi_nxv1i8_unmasked:75; CHECK:       # %bb.0:76; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma77; CHECK-NEXT:    vxor.vi v8, v8, 778; CHECK-NEXT:    ret79  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 7), <vscale x 1 x i1> splat (i1 true), i32 %evl)80  ret <vscale x 1 x i8> %v81}82 83define <vscale x 1 x i8> @vxor_vi_nxv1i8_1(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {84; CHECK-LABEL: vxor_vi_nxv1i8_1:85; CHECK:       # %bb.0:86; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma87; CHECK-NEXT:    vnot.v v8, v8, v0.t88; CHECK-NEXT:    ret89  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)90  ret <vscale x 1 x i8> %v91}92 93define <vscale x 1 x i8> @vxor_vi_nxv1i8_unmasked_1(<vscale x 1 x i8> %va, i32 zeroext %evl) {94; CHECK-LABEL: vxor_vi_nxv1i8_unmasked_1:95; CHECK:       # %bb.0:96; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma97; CHECK-NEXT:    vnot.v v8, v898; CHECK-NEXT:    ret99  %v = call <vscale x 1 x i8> @llvm.vp.xor.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)100  ret <vscale x 1 x i8> %v101}102 103define <vscale x 2 x i8> @vxor_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {104; CHECK-LABEL: vxor_vv_nxv2i8:105; CHECK:       # %bb.0:106; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma107; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t108; CHECK-NEXT:    ret109  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)110  ret <vscale x 2 x i8> %v111}112 113define <vscale x 2 x i8> @vxor_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {114; CHECK-LABEL: vxor_vv_nxv2i8_unmasked:115; CHECK:       # %bb.0:116; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma117; CHECK-NEXT:    vxor.vv v8, v8, v9118; CHECK-NEXT:    ret119  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)120  ret <vscale x 2 x i8> %v121}122 123define <vscale x 2 x i8> @vxor_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {124; CHECK-LABEL: vxor_vx_nxv2i8:125; CHECK:       # %bb.0:126; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma127; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t128; CHECK-NEXT:    ret129  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0130  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer131  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)132  ret <vscale x 2 x i8> %v133}134 135define <vscale x 2 x i8> @vxor_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {136; CHECK-LABEL: vxor_vx_nxv2i8_unmasked:137; CHECK:       # %bb.0:138; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma139; CHECK-NEXT:    vxor.vx v8, v8, a0140; CHECK-NEXT:    ret141  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0142  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer143  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)144  ret <vscale x 2 x i8> %v145}146 147define <vscale x 2 x i8> @vxor_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {148; CHECK-LABEL: vxor_vi_nxv2i8:149; CHECK:       # %bb.0:150; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma151; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t152; CHECK-NEXT:    ret153  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 7), <vscale x 2 x i1> %m, i32 %evl)154  ret <vscale x 2 x i8> %v155}156 157define <vscale x 2 x i8> @vxor_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {158; CHECK-LABEL: vxor_vi_nxv2i8_unmasked:159; CHECK:       # %bb.0:160; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma161; CHECK-NEXT:    vxor.vi v8, v8, 7162; CHECK-NEXT:    ret163  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 7), <vscale x 2 x i1> splat (i1 true), i32 %evl)164  ret <vscale x 2 x i8> %v165}166 167define <vscale x 2 x i8> @vxor_vi_nxv2i8_1(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {168; CHECK-LABEL: vxor_vi_nxv2i8_1:169; CHECK:       # %bb.0:170; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma171; CHECK-NEXT:    vnot.v v8, v8, v0.t172; CHECK-NEXT:    ret173  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)174  ret <vscale x 2 x i8> %v175}176 177define <vscale x 2 x i8> @vxor_vi_nxv2i8_unmasked_1(<vscale x 2 x i8> %va, i32 zeroext %evl) {178; CHECK-LABEL: vxor_vi_nxv2i8_unmasked_1:179; CHECK:       # %bb.0:180; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma181; CHECK-NEXT:    vnot.v v8, v8182; CHECK-NEXT:    ret183  %v = call <vscale x 2 x i8> @llvm.vp.xor.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)184  ret <vscale x 2 x i8> %v185}186 187define <vscale x 4 x i8> @vxor_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {188; CHECK-LABEL: vxor_vv_nxv4i8:189; CHECK:       # %bb.0:190; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma191; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t192; CHECK-NEXT:    ret193  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)194  ret <vscale x 4 x i8> %v195}196 197define <vscale x 4 x i8> @vxor_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {198; CHECK-LABEL: vxor_vv_nxv4i8_unmasked:199; CHECK:       # %bb.0:200; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma201; CHECK-NEXT:    vxor.vv v8, v8, v9202; CHECK-NEXT:    ret203  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)204  ret <vscale x 4 x i8> %v205}206 207define <vscale x 4 x i8> @vxor_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {208; CHECK-LABEL: vxor_vx_nxv4i8:209; CHECK:       # %bb.0:210; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma211; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t212; CHECK-NEXT:    ret213  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0214  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer215  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)216  ret <vscale x 4 x i8> %v217}218 219define <vscale x 4 x i8> @vxor_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {220; CHECK-LABEL: vxor_vx_nxv4i8_unmasked:221; CHECK:       # %bb.0:222; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma223; CHECK-NEXT:    vxor.vx v8, v8, a0224; CHECK-NEXT:    ret225  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0226  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer227  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)228  ret <vscale x 4 x i8> %v229}230 231define <vscale x 4 x i8> @vxor_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {232; CHECK-LABEL: vxor_vi_nxv4i8:233; CHECK:       # %bb.0:234; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma235; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t236; CHECK-NEXT:    ret237  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 7), <vscale x 4 x i1> %m, i32 %evl)238  ret <vscale x 4 x i8> %v239}240 241define <vscale x 4 x i8> @vxor_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {242; CHECK-LABEL: vxor_vi_nxv4i8_unmasked:243; CHECK:       # %bb.0:244; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma245; CHECK-NEXT:    vxor.vi v8, v8, 7246; CHECK-NEXT:    ret247  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 7), <vscale x 4 x i1> splat (i1 true), i32 %evl)248  ret <vscale x 4 x i8> %v249}250 251define <vscale x 4 x i8> @vxor_vi_nxv4i8_1(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {252; CHECK-LABEL: vxor_vi_nxv4i8_1:253; CHECK:       # %bb.0:254; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma255; CHECK-NEXT:    vnot.v v8, v8, v0.t256; CHECK-NEXT:    ret257  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)258  ret <vscale x 4 x i8> %v259}260 261define <vscale x 4 x i8> @vxor_vi_nxv4i8_unmasked_1(<vscale x 4 x i8> %va, i32 zeroext %evl) {262; CHECK-LABEL: vxor_vi_nxv4i8_unmasked_1:263; CHECK:       # %bb.0:264; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma265; CHECK-NEXT:    vnot.v v8, v8266; CHECK-NEXT:    ret267  %v = call <vscale x 4 x i8> @llvm.vp.xor.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)268  ret <vscale x 4 x i8> %v269}270 271define <vscale x 8 x i8> @vxor_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vxor_vv_nxv8i8:273; CHECK:       # %bb.0:274; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma275; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t276; CHECK-NEXT:    ret277  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)278  ret <vscale x 8 x i8> %v279}280 281define <vscale x 8 x i8> @vxor_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {282; CHECK-LABEL: vxor_vv_nxv8i8_unmasked:283; CHECK:       # %bb.0:284; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma285; CHECK-NEXT:    vxor.vv v8, v8, v9286; CHECK-NEXT:    ret287  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)288  ret <vscale x 8 x i8> %v289}290 291define <vscale x 8 x i8> @vxor_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {292; CHECK-LABEL: vxor_vx_nxv8i8:293; CHECK:       # %bb.0:294; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma295; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t296; CHECK-NEXT:    ret297  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0298  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer299  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)300  ret <vscale x 8 x i8> %v301}302 303define <vscale x 8 x i8> @vxor_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {304; CHECK-LABEL: vxor_vx_nxv8i8_unmasked:305; CHECK:       # %bb.0:306; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma307; CHECK-NEXT:    vxor.vx v8, v8, a0308; CHECK-NEXT:    ret309  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0310  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer311  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)312  ret <vscale x 8 x i8> %v313}314 315define <vscale x 8 x i8> @vxor_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {316; CHECK-LABEL: vxor_vi_nxv8i8:317; CHECK:       # %bb.0:318; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma319; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t320; CHECK-NEXT:    ret321  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 7), <vscale x 8 x i1> %m, i32 %evl)322  ret <vscale x 8 x i8> %v323}324 325define <vscale x 8 x i8> @vxor_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {326; CHECK-LABEL: vxor_vi_nxv8i8_unmasked:327; CHECK:       # %bb.0:328; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma329; CHECK-NEXT:    vxor.vi v8, v8, 7330; CHECK-NEXT:    ret331  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 7), <vscale x 8 x i1> splat (i1 true), i32 %evl)332  ret <vscale x 8 x i8> %v333}334 335define <vscale x 8 x i8> @vxor_vi_nxv8i8_1(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {336; CHECK-LABEL: vxor_vi_nxv8i8_1:337; CHECK:       # %bb.0:338; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma339; CHECK-NEXT:    vnot.v v8, v8, v0.t340; CHECK-NEXT:    ret341  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)342  ret <vscale x 8 x i8> %v343}344 345define <vscale x 8 x i8> @vxor_vi_nxv8i8_unmasked_1(<vscale x 8 x i8> %va, i32 zeroext %evl) {346; CHECK-LABEL: vxor_vi_nxv8i8_unmasked_1:347; CHECK:       # %bb.0:348; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma349; CHECK-NEXT:    vnot.v v8, v8350; CHECK-NEXT:    ret351  %v = call <vscale x 8 x i8> @llvm.vp.xor.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)352  ret <vscale x 8 x i8> %v353}354 355define <vscale x 15 x i8> @vxor_vv_nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> %b, <vscale x 15 x i1> %m, i32 zeroext %evl) {356; CHECK-LABEL: vxor_vv_nxv15i8:357; CHECK:       # %bb.0:358; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma359; CHECK-NEXT:    vxor.vv v8, v8, v10, v0.t360; CHECK-NEXT:    ret361  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> %b, <vscale x 15 x i1> %m, i32 %evl)362  ret <vscale x 15 x i8> %v363}364 365define <vscale x 15 x i8> @vxor_vv_nxv15i8_unmasked(<vscale x 15 x i8> %va, <vscale x 15 x i8> %b, i32 zeroext %evl) {366; CHECK-LABEL: vxor_vv_nxv15i8_unmasked:367; CHECK:       # %bb.0:368; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma369; CHECK-NEXT:    vxor.vv v8, v8, v10370; CHECK-NEXT:    ret371  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> %b, <vscale x 15 x i1> splat (i1 true), i32 %evl)372  ret <vscale x 15 x i8> %v373}374 375define <vscale x 15 x i8> @vxor_vx_nxv15i8(<vscale x 15 x i8> %va, i8 %b, <vscale x 15 x i1> %m, i32 zeroext %evl) {376; CHECK-LABEL: vxor_vx_nxv15i8:377; CHECK:       # %bb.0:378; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma379; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t380; CHECK-NEXT:    ret381  %elt.head = insertelement <vscale x 15 x i8> poison, i8 %b, i32 0382  %vb = shufflevector <vscale x 15 x i8> %elt.head, <vscale x 15 x i8> poison, <vscale x 15 x i32> zeroinitializer383  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> %vb, <vscale x 15 x i1> %m, i32 %evl)384  ret <vscale x 15 x i8> %v385}386 387define <vscale x 15 x i8> @vxor_vx_nxv15i8_unmasked(<vscale x 15 x i8> %va, i8 %b, i32 zeroext %evl) {388; CHECK-LABEL: vxor_vx_nxv15i8_unmasked:389; CHECK:       # %bb.0:390; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma391; CHECK-NEXT:    vxor.vx v8, v8, a0392; CHECK-NEXT:    ret393  %elt.head = insertelement <vscale x 15 x i8> poison, i8 %b, i32 0394  %vb = shufflevector <vscale x 15 x i8> %elt.head, <vscale x 15 x i8> poison, <vscale x 15 x i32> zeroinitializer395  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> %vb, <vscale x 15 x i1> splat (i1 true), i32 %evl)396  ret <vscale x 15 x i8> %v397}398 399define <vscale x 15 x i8> @vxor_vi_nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i1> %m, i32 zeroext %evl) {400; CHECK-LABEL: vxor_vi_nxv15i8:401; CHECK:       # %bb.0:402; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma403; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t404; CHECK-NEXT:    ret405  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> splat (i8 7), <vscale x 15 x i1> %m, i32 %evl)406  ret <vscale x 15 x i8> %v407}408 409define <vscale x 15 x i8> @vxor_vi_nxv15i8_unmasked(<vscale x 15 x i8> %va, i32 zeroext %evl) {410; CHECK-LABEL: vxor_vi_nxv15i8_unmasked:411; CHECK:       # %bb.0:412; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma413; CHECK-NEXT:    vxor.vi v8, v8, 7414; CHECK-NEXT:    ret415  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> splat (i8 7), <vscale x 15 x i1> splat (i1 true), i32 %evl)416  ret <vscale x 15 x i8> %v417}418 419define <vscale x 15 x i8> @vxor_vi_nxv15i8_1(<vscale x 15 x i8> %va, <vscale x 15 x i1> %m, i32 zeroext %evl) {420; CHECK-LABEL: vxor_vi_nxv15i8_1:421; CHECK:       # %bb.0:422; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma423; CHECK-NEXT:    vnot.v v8, v8, v0.t424; CHECK-NEXT:    ret425  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> splat (i8 -1), <vscale x 15 x i1> %m, i32 %evl)426  ret <vscale x 15 x i8> %v427}428 429define <vscale x 15 x i8> @vxor_vi_nxv15i8_unmasked_1(<vscale x 15 x i8> %va, i32 zeroext %evl) {430; CHECK-LABEL: vxor_vi_nxv15i8_unmasked_1:431; CHECK:       # %bb.0:432; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma433; CHECK-NEXT:    vnot.v v8, v8434; CHECK-NEXT:    ret435  %v = call <vscale x 15 x i8> @llvm.vp.xor.nxv15i8(<vscale x 15 x i8> %va, <vscale x 15 x i8> splat (i8 -1), <vscale x 15 x i1> splat (i1 true), i32 %evl)436  ret <vscale x 15 x i8> %v437}438 439define <vscale x 16 x i8> @vxor_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {440; CHECK-LABEL: vxor_vv_nxv16i8:441; CHECK:       # %bb.0:442; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma443; CHECK-NEXT:    vxor.vv v8, v8, v10, v0.t444; CHECK-NEXT:    ret445  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)446  ret <vscale x 16 x i8> %v447}448 449define <vscale x 16 x i8> @vxor_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {450; CHECK-LABEL: vxor_vv_nxv16i8_unmasked:451; CHECK:       # %bb.0:452; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma453; CHECK-NEXT:    vxor.vv v8, v8, v10454; CHECK-NEXT:    ret455  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)456  ret <vscale x 16 x i8> %v457}458 459define <vscale x 16 x i8> @vxor_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {460; CHECK-LABEL: vxor_vx_nxv16i8:461; CHECK:       # %bb.0:462; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma463; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t464; CHECK-NEXT:    ret465  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0466  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer467  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)468  ret <vscale x 16 x i8> %v469}470 471define <vscale x 16 x i8> @vxor_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {472; CHECK-LABEL: vxor_vx_nxv16i8_unmasked:473; CHECK:       # %bb.0:474; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma475; CHECK-NEXT:    vxor.vx v8, v8, a0476; CHECK-NEXT:    ret477  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0478  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer479  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)480  ret <vscale x 16 x i8> %v481}482 483define <vscale x 16 x i8> @vxor_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {484; CHECK-LABEL: vxor_vi_nxv16i8:485; CHECK:       # %bb.0:486; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma487; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t488; CHECK-NEXT:    ret489  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i1> %m, i32 %evl)490  ret <vscale x 16 x i8> %v491}492 493define <vscale x 16 x i8> @vxor_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {494; CHECK-LABEL: vxor_vi_nxv16i8_unmasked:495; CHECK:       # %bb.0:496; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma497; CHECK-NEXT:    vxor.vi v8, v8, 7498; CHECK-NEXT:    ret499  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 7), <vscale x 16 x i1> splat (i1 true), i32 %evl)500  ret <vscale x 16 x i8> %v501}502 503define <vscale x 16 x i8> @vxor_vi_nxv16i8_1(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {504; CHECK-LABEL: vxor_vi_nxv16i8_1:505; CHECK:       # %bb.0:506; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma507; CHECK-NEXT:    vnot.v v8, v8, v0.t508; CHECK-NEXT:    ret509  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)510  ret <vscale x 16 x i8> %v511}512 513define <vscale x 16 x i8> @vxor_vi_nxv16i8_unmasked_1(<vscale x 16 x i8> %va, i32 zeroext %evl) {514; CHECK-LABEL: vxor_vi_nxv16i8_unmasked_1:515; CHECK:       # %bb.0:516; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma517; CHECK-NEXT:    vnot.v v8, v8518; CHECK-NEXT:    ret519  %v = call <vscale x 16 x i8> @llvm.vp.xor.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)520  ret <vscale x 16 x i8> %v521}522 523define <vscale x 32 x i8> @vxor_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {524; CHECK-LABEL: vxor_vv_nxv32i8:525; CHECK:       # %bb.0:526; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma527; CHECK-NEXT:    vxor.vv v8, v8, v12, v0.t528; CHECK-NEXT:    ret529  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)530  ret <vscale x 32 x i8> %v531}532 533define <vscale x 32 x i8> @vxor_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {534; CHECK-LABEL: vxor_vv_nxv32i8_unmasked:535; CHECK:       # %bb.0:536; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma537; CHECK-NEXT:    vxor.vv v8, v8, v12538; CHECK-NEXT:    ret539  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)540  ret <vscale x 32 x i8> %v541}542 543define <vscale x 32 x i8> @vxor_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {544; CHECK-LABEL: vxor_vx_nxv32i8:545; CHECK:       # %bb.0:546; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma547; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t548; CHECK-NEXT:    ret549  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0550  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer551  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)552  ret <vscale x 32 x i8> %v553}554 555define <vscale x 32 x i8> @vxor_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {556; CHECK-LABEL: vxor_vx_nxv32i8_unmasked:557; CHECK:       # %bb.0:558; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma559; CHECK-NEXT:    vxor.vx v8, v8, a0560; CHECK-NEXT:    ret561  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0562  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer563  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)564  ret <vscale x 32 x i8> %v565}566 567define <vscale x 32 x i8> @vxor_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {568; CHECK-LABEL: vxor_vi_nxv32i8:569; CHECK:       # %bb.0:570; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma571; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t572; CHECK-NEXT:    ret573  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 7), <vscale x 32 x i1> %m, i32 %evl)574  ret <vscale x 32 x i8> %v575}576 577define <vscale x 32 x i8> @vxor_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {578; CHECK-LABEL: vxor_vi_nxv32i8_unmasked:579; CHECK:       # %bb.0:580; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma581; CHECK-NEXT:    vxor.vi v8, v8, 7582; CHECK-NEXT:    ret583  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 7), <vscale x 32 x i1> splat (i1 true), i32 %evl)584  ret <vscale x 32 x i8> %v585}586 587define <vscale x 32 x i8> @vxor_vi_nxv32i8_1(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {588; CHECK-LABEL: vxor_vi_nxv32i8_1:589; CHECK:       # %bb.0:590; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma591; CHECK-NEXT:    vnot.v v8, v8, v0.t592; CHECK-NEXT:    ret593  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)594  ret <vscale x 32 x i8> %v595}596 597define <vscale x 32 x i8> @vxor_vi_nxv32i8_unmasked_1(<vscale x 32 x i8> %va, i32 zeroext %evl) {598; CHECK-LABEL: vxor_vi_nxv32i8_unmasked_1:599; CHECK:       # %bb.0:600; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma601; CHECK-NEXT:    vnot.v v8, v8602; CHECK-NEXT:    ret603  %v = call <vscale x 32 x i8> @llvm.vp.xor.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)604  ret <vscale x 32 x i8> %v605}606 607define <vscale x 64 x i8> @vxor_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {608; CHECK-LABEL: vxor_vv_nxv64i8:609; CHECK:       # %bb.0:610; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma611; CHECK-NEXT:    vxor.vv v8, v8, v16, v0.t612; CHECK-NEXT:    ret613  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)614  ret <vscale x 64 x i8> %v615}616 617define <vscale x 64 x i8> @vxor_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {618; CHECK-LABEL: vxor_vv_nxv64i8_unmasked:619; CHECK:       # %bb.0:620; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma621; CHECK-NEXT:    vxor.vv v8, v8, v16622; CHECK-NEXT:    ret623  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)624  ret <vscale x 64 x i8> %v625}626 627define <vscale x 64 x i8> @vxor_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {628; CHECK-LABEL: vxor_vx_nxv64i8:629; CHECK:       # %bb.0:630; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma631; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t632; CHECK-NEXT:    ret633  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0634  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer635  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)636  ret <vscale x 64 x i8> %v637}638 639define <vscale x 64 x i8> @vxor_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {640; CHECK-LABEL: vxor_vx_nxv64i8_unmasked:641; CHECK:       # %bb.0:642; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma643; CHECK-NEXT:    vxor.vx v8, v8, a0644; CHECK-NEXT:    ret645  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0646  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer647  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)648  ret <vscale x 64 x i8> %v649}650 651define <vscale x 64 x i8> @vxor_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {652; CHECK-LABEL: vxor_vi_nxv64i8:653; CHECK:       # %bb.0:654; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma655; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t656; CHECK-NEXT:    ret657  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 7), <vscale x 64 x i1> %m, i32 %evl)658  ret <vscale x 64 x i8> %v659}660 661define <vscale x 64 x i8> @vxor_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {662; CHECK-LABEL: vxor_vi_nxv64i8_unmasked:663; CHECK:       # %bb.0:664; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma665; CHECK-NEXT:    vxor.vi v8, v8, 7666; CHECK-NEXT:    ret667  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 7), <vscale x 64 x i1> splat (i1 true), i32 %evl)668  ret <vscale x 64 x i8> %v669}670 671define <vscale x 64 x i8> @vxor_vi_nxv64i8_1(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {672; CHECK-LABEL: vxor_vi_nxv64i8_1:673; CHECK:       # %bb.0:674; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma675; CHECK-NEXT:    vnot.v v8, v8, v0.t676; CHECK-NEXT:    ret677  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)678  ret <vscale x 64 x i8> %v679}680 681define <vscale x 64 x i8> @vxor_vi_nxv64i8_unmasked_1(<vscale x 64 x i8> %va, i32 zeroext %evl) {682; CHECK-LABEL: vxor_vi_nxv64i8_unmasked_1:683; CHECK:       # %bb.0:684; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma685; CHECK-NEXT:    vnot.v v8, v8686; CHECK-NEXT:    ret687  %v = call <vscale x 64 x i8> @llvm.vp.xor.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)688  ret <vscale x 64 x i8> %v689}690 691define <vscale x 1 x i16> @vxor_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {692; CHECK-LABEL: vxor_vv_nxv1i16:693; CHECK:       # %bb.0:694; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma695; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t696; CHECK-NEXT:    ret697  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)698  ret <vscale x 1 x i16> %v699}700 701define <vscale x 1 x i16> @vxor_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {702; CHECK-LABEL: vxor_vv_nxv1i16_unmasked:703; CHECK:       # %bb.0:704; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma705; CHECK-NEXT:    vxor.vv v8, v8, v9706; CHECK-NEXT:    ret707  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)708  ret <vscale x 1 x i16> %v709}710 711define <vscale x 1 x i16> @vxor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {712; CHECK-LABEL: vxor_vx_nxv1i16:713; CHECK:       # %bb.0:714; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma715; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t716; CHECK-NEXT:    ret717  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0718  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer719  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)720  ret <vscale x 1 x i16> %v721}722 723define <vscale x 1 x i16> @vxor_vx_nxv1i16_commute(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {724; CHECK-LABEL: vxor_vx_nxv1i16_commute:725; CHECK:       # %bb.0:726; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma727; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t728; CHECK-NEXT:    ret729  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0730  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer731  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %vb, <vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 %evl)732  ret <vscale x 1 x i16> %v733}734 735define <vscale x 1 x i16> @vxor_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {736; CHECK-LABEL: vxor_vx_nxv1i16_unmasked:737; CHECK:       # %bb.0:738; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma739; CHECK-NEXT:    vxor.vx v8, v8, a0740; CHECK-NEXT:    ret741  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0742  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer743  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)744  ret <vscale x 1 x i16> %v745}746 747define <vscale x 1 x i16> @vxor_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {748; CHECK-LABEL: vxor_vi_nxv1i16:749; CHECK:       # %bb.0:750; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma751; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t752; CHECK-NEXT:    ret753  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 7), <vscale x 1 x i1> %m, i32 %evl)754  ret <vscale x 1 x i16> %v755}756 757define <vscale x 1 x i16> @vxor_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {758; CHECK-LABEL: vxor_vi_nxv1i16_unmasked:759; CHECK:       # %bb.0:760; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma761; CHECK-NEXT:    vxor.vi v8, v8, 7762; CHECK-NEXT:    ret763  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 7), <vscale x 1 x i1> splat (i1 true), i32 %evl)764  ret <vscale x 1 x i16> %v765}766 767define <vscale x 1 x i16> @vxor_vi_nxv1i16_1(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {768; CHECK-LABEL: vxor_vi_nxv1i16_1:769; CHECK:       # %bb.0:770; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma771; CHECK-NEXT:    vnot.v v8, v8, v0.t772; CHECK-NEXT:    ret773  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)774  ret <vscale x 1 x i16> %v775}776 777define <vscale x 1 x i16> @vxor_vi_nxv1i16_unmasked_1(<vscale x 1 x i16> %va, i32 zeroext %evl) {778; CHECK-LABEL: vxor_vi_nxv1i16_unmasked_1:779; CHECK:       # %bb.0:780; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma781; CHECK-NEXT:    vnot.v v8, v8782; CHECK-NEXT:    ret783  %v = call <vscale x 1 x i16> @llvm.vp.xor.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)784  ret <vscale x 1 x i16> %v785}786 787define <vscale x 2 x i16> @vxor_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {788; CHECK-LABEL: vxor_vv_nxv2i16:789; CHECK:       # %bb.0:790; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma791; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t792; CHECK-NEXT:    ret793  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)794  ret <vscale x 2 x i16> %v795}796 797define <vscale x 2 x i16> @vxor_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {798; CHECK-LABEL: vxor_vv_nxv2i16_unmasked:799; CHECK:       # %bb.0:800; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma801; CHECK-NEXT:    vxor.vv v8, v8, v9802; CHECK-NEXT:    ret803  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)804  ret <vscale x 2 x i16> %v805}806 807define <vscale x 2 x i16> @vxor_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {808; CHECK-LABEL: vxor_vx_nxv2i16:809; CHECK:       # %bb.0:810; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma811; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t812; CHECK-NEXT:    ret813  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0814  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer815  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)816  ret <vscale x 2 x i16> %v817}818 819define <vscale x 2 x i16> @vxor_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {820; CHECK-LABEL: vxor_vx_nxv2i16_unmasked:821; CHECK:       # %bb.0:822; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma823; CHECK-NEXT:    vxor.vx v8, v8, a0824; CHECK-NEXT:    ret825  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0826  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer827  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)828  ret <vscale x 2 x i16> %v829}830 831define <vscale x 2 x i16> @vxor_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {832; CHECK-LABEL: vxor_vi_nxv2i16:833; CHECK:       # %bb.0:834; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma835; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t836; CHECK-NEXT:    ret837  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 7), <vscale x 2 x i1> %m, i32 %evl)838  ret <vscale x 2 x i16> %v839}840 841define <vscale x 2 x i16> @vxor_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {842; CHECK-LABEL: vxor_vi_nxv2i16_unmasked:843; CHECK:       # %bb.0:844; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma845; CHECK-NEXT:    vxor.vi v8, v8, 7846; CHECK-NEXT:    ret847  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 7), <vscale x 2 x i1> splat (i1 true), i32 %evl)848  ret <vscale x 2 x i16> %v849}850 851define <vscale x 2 x i16> @vxor_vi_nxv2i16_1(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {852; CHECK-LABEL: vxor_vi_nxv2i16_1:853; CHECK:       # %bb.0:854; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma855; CHECK-NEXT:    vnot.v v8, v8, v0.t856; CHECK-NEXT:    ret857  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)858  ret <vscale x 2 x i16> %v859}860 861define <vscale x 2 x i16> @vxor_vi_nxv2i16_unmasked_1(<vscale x 2 x i16> %va, i32 zeroext %evl) {862; CHECK-LABEL: vxor_vi_nxv2i16_unmasked_1:863; CHECK:       # %bb.0:864; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma865; CHECK-NEXT:    vnot.v v8, v8866; CHECK-NEXT:    ret867  %v = call <vscale x 2 x i16> @llvm.vp.xor.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)868  ret <vscale x 2 x i16> %v869}870 871define <vscale x 4 x i16> @vxor_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {872; CHECK-LABEL: vxor_vv_nxv4i16:873; CHECK:       # %bb.0:874; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma875; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t876; CHECK-NEXT:    ret877  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)878  ret <vscale x 4 x i16> %v879}880 881define <vscale x 4 x i16> @vxor_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {882; CHECK-LABEL: vxor_vv_nxv4i16_unmasked:883; CHECK:       # %bb.0:884; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma885; CHECK-NEXT:    vxor.vv v8, v8, v9886; CHECK-NEXT:    ret887  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)888  ret <vscale x 4 x i16> %v889}890 891define <vscale x 4 x i16> @vxor_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {892; CHECK-LABEL: vxor_vx_nxv4i16:893; CHECK:       # %bb.0:894; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma895; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t896; CHECK-NEXT:    ret897  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0898  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer899  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)900  ret <vscale x 4 x i16> %v901}902 903define <vscale x 4 x i16> @vxor_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {904; CHECK-LABEL: vxor_vx_nxv4i16_unmasked:905; CHECK:       # %bb.0:906; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma907; CHECK-NEXT:    vxor.vx v8, v8, a0908; CHECK-NEXT:    ret909  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0910  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer911  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)912  ret <vscale x 4 x i16> %v913}914 915define <vscale x 4 x i16> @vxor_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {916; CHECK-LABEL: vxor_vi_nxv4i16:917; CHECK:       # %bb.0:918; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma919; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t920; CHECK-NEXT:    ret921  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 7), <vscale x 4 x i1> %m, i32 %evl)922  ret <vscale x 4 x i16> %v923}924 925define <vscale x 4 x i16> @vxor_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {926; CHECK-LABEL: vxor_vi_nxv4i16_unmasked:927; CHECK:       # %bb.0:928; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma929; CHECK-NEXT:    vxor.vi v8, v8, 7930; CHECK-NEXT:    ret931  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 7), <vscale x 4 x i1> splat (i1 true), i32 %evl)932  ret <vscale x 4 x i16> %v933}934 935define <vscale x 4 x i16> @vxor_vi_nxv4i16_1(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {936; CHECK-LABEL: vxor_vi_nxv4i16_1:937; CHECK:       # %bb.0:938; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma939; CHECK-NEXT:    vnot.v v8, v8, v0.t940; CHECK-NEXT:    ret941  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)942  ret <vscale x 4 x i16> %v943}944 945define <vscale x 4 x i16> @vxor_vi_nxv4i16_unmasked_1(<vscale x 4 x i16> %va, i32 zeroext %evl) {946; CHECK-LABEL: vxor_vi_nxv4i16_unmasked_1:947; CHECK:       # %bb.0:948; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma949; CHECK-NEXT:    vnot.v v8, v8950; CHECK-NEXT:    ret951  %v = call <vscale x 4 x i16> @llvm.vp.xor.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)952  ret <vscale x 4 x i16> %v953}954 955define <vscale x 8 x i16> @vxor_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {956; CHECK-LABEL: vxor_vv_nxv8i16:957; CHECK:       # %bb.0:958; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma959; CHECK-NEXT:    vxor.vv v8, v8, v10, v0.t960; CHECK-NEXT:    ret961  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)962  ret <vscale x 8 x i16> %v963}964 965define <vscale x 8 x i16> @vxor_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {966; CHECK-LABEL: vxor_vv_nxv8i16_unmasked:967; CHECK:       # %bb.0:968; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma969; CHECK-NEXT:    vxor.vv v8, v8, v10970; CHECK-NEXT:    ret971  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)972  ret <vscale x 8 x i16> %v973}974 975define <vscale x 8 x i16> @vxor_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {976; CHECK-LABEL: vxor_vx_nxv8i16:977; CHECK:       # %bb.0:978; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma979; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t980; CHECK-NEXT:    ret981  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0982  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer983  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)984  ret <vscale x 8 x i16> %v985}986 987define <vscale x 8 x i16> @vxor_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {988; CHECK-LABEL: vxor_vx_nxv8i16_unmasked:989; CHECK:       # %bb.0:990; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma991; CHECK-NEXT:    vxor.vx v8, v8, a0992; CHECK-NEXT:    ret993  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0994  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer995  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)996  ret <vscale x 8 x i16> %v997}998 999define <vscale x 8 x i16> @vxor_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1000; CHECK-LABEL: vxor_vi_nxv8i16:1001; CHECK:       # %bb.0:1002; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1003; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1004; CHECK-NEXT:    ret1005  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 7), <vscale x 8 x i1> %m, i32 %evl)1006  ret <vscale x 8 x i16> %v1007}1008 1009define <vscale x 8 x i16> @vxor_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {1010; CHECK-LABEL: vxor_vi_nxv8i16_unmasked:1011; CHECK:       # %bb.0:1012; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1013; CHECK-NEXT:    vxor.vi v8, v8, 71014; CHECK-NEXT:    ret1015  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 7), <vscale x 8 x i1> splat (i1 true), i32 %evl)1016  ret <vscale x 8 x i16> %v1017}1018 1019define <vscale x 8 x i16> @vxor_vi_nxv8i16_1(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1020; CHECK-LABEL: vxor_vi_nxv8i16_1:1021; CHECK:       # %bb.0:1022; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1023; CHECK-NEXT:    vnot.v v8, v8, v0.t1024; CHECK-NEXT:    ret1025  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)1026  ret <vscale x 8 x i16> %v1027}1028 1029define <vscale x 8 x i16> @vxor_vi_nxv8i16_unmasked_1(<vscale x 8 x i16> %va, i32 zeroext %evl) {1030; CHECK-LABEL: vxor_vi_nxv8i16_unmasked_1:1031; CHECK:       # %bb.0:1032; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1033; CHECK-NEXT:    vnot.v v8, v81034; CHECK-NEXT:    ret1035  %v = call <vscale x 8 x i16> @llvm.vp.xor.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1036  ret <vscale x 8 x i16> %v1037}1038 1039define <vscale x 16 x i16> @vxor_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1040; CHECK-LABEL: vxor_vv_nxv16i16:1041; CHECK:       # %bb.0:1042; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1043; CHECK-NEXT:    vxor.vv v8, v8, v12, v0.t1044; CHECK-NEXT:    ret1045  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)1046  ret <vscale x 16 x i16> %v1047}1048 1049define <vscale x 16 x i16> @vxor_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {1050; CHECK-LABEL: vxor_vv_nxv16i16_unmasked:1051; CHECK:       # %bb.0:1052; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1053; CHECK-NEXT:    vxor.vv v8, v8, v121054; CHECK-NEXT:    ret1055  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1056  ret <vscale x 16 x i16> %v1057}1058 1059define <vscale x 16 x i16> @vxor_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1060; CHECK-LABEL: vxor_vx_nxv16i16:1061; CHECK:       # %bb.0:1062; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1063; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t1064; CHECK-NEXT:    ret1065  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 01066  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer1067  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)1068  ret <vscale x 16 x i16> %v1069}1070 1071define <vscale x 16 x i16> @vxor_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {1072; CHECK-LABEL: vxor_vx_nxv16i16_unmasked:1073; CHECK:       # %bb.0:1074; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1075; CHECK-NEXT:    vxor.vx v8, v8, a01076; CHECK-NEXT:    ret1077  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 01078  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer1079  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1080  ret <vscale x 16 x i16> %v1081}1082 1083define <vscale x 16 x i16> @vxor_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1084; CHECK-LABEL: vxor_vi_nxv16i16:1085; CHECK:       # %bb.0:1086; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1087; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1088; CHECK-NEXT:    ret1089  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 7), <vscale x 16 x i1> %m, i32 %evl)1090  ret <vscale x 16 x i16> %v1091}1092 1093define <vscale x 16 x i16> @vxor_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {1094; CHECK-LABEL: vxor_vi_nxv16i16_unmasked:1095; CHECK:       # %bb.0:1096; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1097; CHECK-NEXT:    vxor.vi v8, v8, 71098; CHECK-NEXT:    ret1099  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 7), <vscale x 16 x i1> splat (i1 true), i32 %evl)1100  ret <vscale x 16 x i16> %v1101}1102 1103define <vscale x 16 x i16> @vxor_vi_nxv16i16_1(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1104; CHECK-LABEL: vxor_vi_nxv16i16_1:1105; CHECK:       # %bb.0:1106; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1107; CHECK-NEXT:    vnot.v v8, v8, v0.t1108; CHECK-NEXT:    ret1109  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)1110  ret <vscale x 16 x i16> %v1111}1112 1113define <vscale x 16 x i16> @vxor_vi_nxv16i16_unmasked_1(<vscale x 16 x i16> %va, i32 zeroext %evl) {1114; CHECK-LABEL: vxor_vi_nxv16i16_unmasked_1:1115; CHECK:       # %bb.0:1116; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1117; CHECK-NEXT:    vnot.v v8, v81118; CHECK-NEXT:    ret1119  %v = call <vscale x 16 x i16> @llvm.vp.xor.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)1120  ret <vscale x 16 x i16> %v1121}1122 1123define <vscale x 32 x i16> @vxor_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {1124; CHECK-LABEL: vxor_vv_nxv32i16:1125; CHECK:       # %bb.0:1126; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1127; CHECK-NEXT:    vxor.vv v8, v8, v16, v0.t1128; CHECK-NEXT:    ret1129  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)1130  ret <vscale x 32 x i16> %v1131}1132 1133define <vscale x 32 x i16> @vxor_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {1134; CHECK-LABEL: vxor_vv_nxv32i16_unmasked:1135; CHECK:       # %bb.0:1136; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1137; CHECK-NEXT:    vxor.vv v8, v8, v161138; CHECK-NEXT:    ret1139  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)1140  ret <vscale x 32 x i16> %v1141}1142 1143define <vscale x 32 x i16> @vxor_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {1144; CHECK-LABEL: vxor_vx_nxv32i16:1145; CHECK:       # %bb.0:1146; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1147; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t1148; CHECK-NEXT:    ret1149  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 01150  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer1151  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)1152  ret <vscale x 32 x i16> %v1153}1154 1155define <vscale x 32 x i16> @vxor_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {1156; CHECK-LABEL: vxor_vx_nxv32i16_unmasked:1157; CHECK:       # %bb.0:1158; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1159; CHECK-NEXT:    vxor.vx v8, v8, a01160; CHECK-NEXT:    ret1161  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 01162  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer1163  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)1164  ret <vscale x 32 x i16> %v1165}1166 1167define <vscale x 32 x i16> @vxor_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {1168; CHECK-LABEL: vxor_vi_nxv32i16:1169; CHECK:       # %bb.0:1170; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1171; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1172; CHECK-NEXT:    ret1173  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 7), <vscale x 32 x i1> %m, i32 %evl)1174  ret <vscale x 32 x i16> %v1175}1176 1177define <vscale x 32 x i16> @vxor_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {1178; CHECK-LABEL: vxor_vi_nxv32i16_unmasked:1179; CHECK:       # %bb.0:1180; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1181; CHECK-NEXT:    vxor.vi v8, v8, 71182; CHECK-NEXT:    ret1183  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 7), <vscale x 32 x i1> splat (i1 true), i32 %evl)1184  ret <vscale x 32 x i16> %v1185}1186 1187define <vscale x 32 x i16> @vxor_vi_nxv32i16_1(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {1188; CHECK-LABEL: vxor_vi_nxv32i16_1:1189; CHECK:       # %bb.0:1190; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1191; CHECK-NEXT:    vnot.v v8, v8, v0.t1192; CHECK-NEXT:    ret1193  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)1194  ret <vscale x 32 x i16> %v1195}1196 1197define <vscale x 32 x i16> @vxor_vi_nxv32i16_unmasked_1(<vscale x 32 x i16> %va, i32 zeroext %evl) {1198; CHECK-LABEL: vxor_vi_nxv32i16_unmasked_1:1199; CHECK:       # %bb.0:1200; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1201; CHECK-NEXT:    vnot.v v8, v81202; CHECK-NEXT:    ret1203  %v = call <vscale x 32 x i16> @llvm.vp.xor.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1204  ret <vscale x 32 x i16> %v1205}1206 1207define <vscale x 1 x i32> @vxor_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1208; CHECK-LABEL: vxor_vv_nxv1i32:1209; CHECK:       # %bb.0:1210; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1211; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t1212; CHECK-NEXT:    ret1213  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)1214  ret <vscale x 1 x i32> %v1215}1216 1217define <vscale x 1 x i32> @vxor_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {1218; CHECK-LABEL: vxor_vv_nxv1i32_unmasked:1219; CHECK:       # %bb.0:1220; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1221; CHECK-NEXT:    vxor.vv v8, v8, v91222; CHECK-NEXT:    ret1223  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1224  ret <vscale x 1 x i32> %v1225}1226 1227define <vscale x 1 x i32> @vxor_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1228; CHECK-LABEL: vxor_vx_nxv1i32:1229; CHECK:       # %bb.0:1230; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1231; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t1232; CHECK-NEXT:    ret1233  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01234  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1235  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)1236  ret <vscale x 1 x i32> %v1237}1238 1239define <vscale x 1 x i32> @vxor_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {1240; CHECK-LABEL: vxor_vx_nxv1i32_unmasked:1241; CHECK:       # %bb.0:1242; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1243; CHECK-NEXT:    vxor.vx v8, v8, a01244; CHECK-NEXT:    ret1245  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01246  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1247  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1248  ret <vscale x 1 x i32> %v1249}1250 1251define <vscale x 1 x i32> @vxor_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1252; CHECK-LABEL: vxor_vi_nxv1i32:1253; CHECK:       # %bb.0:1254; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1255; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1256; CHECK-NEXT:    ret1257  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 7), <vscale x 1 x i1> %m, i32 %evl)1258  ret <vscale x 1 x i32> %v1259}1260 1261define <vscale x 1 x i32> @vxor_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {1262; CHECK-LABEL: vxor_vi_nxv1i32_unmasked:1263; CHECK:       # %bb.0:1264; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1265; CHECK-NEXT:    vxor.vi v8, v8, 71266; CHECK-NEXT:    ret1267  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 7), <vscale x 1 x i1> splat (i1 true), i32 %evl)1268  ret <vscale x 1 x i32> %v1269}1270 1271define <vscale x 1 x i32> @vxor_vi_nxv1i32_1(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1272; CHECK-LABEL: vxor_vi_nxv1i32_1:1273; CHECK:       # %bb.0:1274; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1275; CHECK-NEXT:    vnot.v v8, v8, v0.t1276; CHECK-NEXT:    ret1277  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)1278  ret <vscale x 1 x i32> %v1279}1280 1281define <vscale x 1 x i32> @vxor_vi_nxv1i32_unmasked_1(<vscale x 1 x i32> %va, i32 zeroext %evl) {1282; CHECK-LABEL: vxor_vi_nxv1i32_unmasked_1:1283; CHECK:       # %bb.0:1284; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1285; CHECK-NEXT:    vnot.v v8, v81286; CHECK-NEXT:    ret1287  %v = call <vscale x 1 x i32> @llvm.vp.xor.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1288  ret <vscale x 1 x i32> %v1289}1290 1291define <vscale x 2 x i32> @vxor_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1292; CHECK-LABEL: vxor_vv_nxv2i32:1293; CHECK:       # %bb.0:1294; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1295; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t1296; CHECK-NEXT:    ret1297  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)1298  ret <vscale x 2 x i32> %v1299}1300 1301define <vscale x 2 x i32> @vxor_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {1302; CHECK-LABEL: vxor_vv_nxv2i32_unmasked:1303; CHECK:       # %bb.0:1304; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1305; CHECK-NEXT:    vxor.vv v8, v8, v91306; CHECK-NEXT:    ret1307  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1308  ret <vscale x 2 x i32> %v1309}1310 1311define <vscale x 2 x i32> @vxor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1312; CHECK-LABEL: vxor_vx_nxv2i32:1313; CHECK:       # %bb.0:1314; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1315; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t1316; CHECK-NEXT:    ret1317  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01318  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1319  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)1320  ret <vscale x 2 x i32> %v1321}1322 1323define <vscale x 2 x i32> @vxor_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {1324; CHECK-LABEL: vxor_vx_nxv2i32_unmasked:1325; CHECK:       # %bb.0:1326; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1327; CHECK-NEXT:    vxor.vx v8, v8, a01328; CHECK-NEXT:    ret1329  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01330  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1331  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1332  ret <vscale x 2 x i32> %v1333}1334 1335define <vscale x 2 x i32> @vxor_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1336; CHECK-LABEL: vxor_vi_nxv2i32:1337; CHECK:       # %bb.0:1338; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1339; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1340; CHECK-NEXT:    ret1341  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 7), <vscale x 2 x i1> %m, i32 %evl)1342  ret <vscale x 2 x i32> %v1343}1344 1345define <vscale x 2 x i32> @vxor_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {1346; CHECK-LABEL: vxor_vi_nxv2i32_unmasked:1347; CHECK:       # %bb.0:1348; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1349; CHECK-NEXT:    vxor.vi v8, v8, 71350; CHECK-NEXT:    ret1351  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 7), <vscale x 2 x i1> splat (i1 true), i32 %evl)1352  ret <vscale x 2 x i32> %v1353}1354 1355define <vscale x 2 x i32> @vxor_vi_nxv2i32_1(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1356; CHECK-LABEL: vxor_vi_nxv2i32_1:1357; CHECK:       # %bb.0:1358; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1359; CHECK-NEXT:    vnot.v v8, v8, v0.t1360; CHECK-NEXT:    ret1361  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)1362  ret <vscale x 2 x i32> %v1363}1364 1365define <vscale x 2 x i32> @vxor_vi_nxv2i32_unmasked_1(<vscale x 2 x i32> %va, i32 zeroext %evl) {1366; CHECK-LABEL: vxor_vi_nxv2i32_unmasked_1:1367; CHECK:       # %bb.0:1368; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1369; CHECK-NEXT:    vnot.v v8, v81370; CHECK-NEXT:    ret1371  %v = call <vscale x 2 x i32> @llvm.vp.xor.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1372  ret <vscale x 2 x i32> %v1373}1374 1375define <vscale x 4 x i32> @vxor_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1376; CHECK-LABEL: vxor_vv_nxv4i32:1377; CHECK:       # %bb.0:1378; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1379; CHECK-NEXT:    vxor.vv v8, v8, v10, v0.t1380; CHECK-NEXT:    ret1381  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)1382  ret <vscale x 4 x i32> %v1383}1384 1385define <vscale x 4 x i32> @vxor_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {1386; CHECK-LABEL: vxor_vv_nxv4i32_unmasked:1387; CHECK:       # %bb.0:1388; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1389; CHECK-NEXT:    vxor.vv v8, v8, v101390; CHECK-NEXT:    ret1391  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1392  ret <vscale x 4 x i32> %v1393}1394 1395define <vscale x 4 x i32> @vxor_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1396; CHECK-LABEL: vxor_vx_nxv4i32:1397; CHECK:       # %bb.0:1398; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1399; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t1400; CHECK-NEXT:    ret1401  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01402  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1403  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)1404  ret <vscale x 4 x i32> %v1405}1406 1407define <vscale x 4 x i32> @vxor_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {1408; CHECK-LABEL: vxor_vx_nxv4i32_unmasked:1409; CHECK:       # %bb.0:1410; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1411; CHECK-NEXT:    vxor.vx v8, v8, a01412; CHECK-NEXT:    ret1413  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01414  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1415  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1416  ret <vscale x 4 x i32> %v1417}1418 1419define <vscale x 4 x i32> @vxor_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1420; CHECK-LABEL: vxor_vi_nxv4i32:1421; CHECK:       # %bb.0:1422; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1423; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1424; CHECK-NEXT:    ret1425  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i1> %m, i32 %evl)1426  ret <vscale x 4 x i32> %v1427}1428 1429define <vscale x 4 x i32> @vxor_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1430; CHECK-LABEL: vxor_vi_nxv4i32_unmasked:1431; CHECK:       # %bb.0:1432; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1433; CHECK-NEXT:    vxor.vi v8, v8, 71434; CHECK-NEXT:    ret1435  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i1> splat (i1 true), i32 %evl)1436  ret <vscale x 4 x i32> %v1437}1438 1439define <vscale x 4 x i32> @vxor_vi_nxv4i32_1(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1440; CHECK-LABEL: vxor_vi_nxv4i32_1:1441; CHECK:       # %bb.0:1442; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1443; CHECK-NEXT:    vnot.v v8, v8, v0.t1444; CHECK-NEXT:    ret1445  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)1446  ret <vscale x 4 x i32> %v1447}1448 1449define <vscale x 4 x i32> @vxor_vi_nxv4i32_unmasked_1(<vscale x 4 x i32> %va, i32 zeroext %evl) {1450; CHECK-LABEL: vxor_vi_nxv4i32_unmasked_1:1451; CHECK:       # %bb.0:1452; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1453; CHECK-NEXT:    vnot.v v8, v81454; CHECK-NEXT:    ret1455  %v = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1456  ret <vscale x 4 x i32> %v1457}1458 1459define <vscale x 8 x i32> @vxor_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1460; CHECK-LABEL: vxor_vv_nxv8i32:1461; CHECK:       # %bb.0:1462; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1463; CHECK-NEXT:    vxor.vv v8, v8, v12, v0.t1464; CHECK-NEXT:    ret1465  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)1466  ret <vscale x 8 x i32> %v1467}1468 1469define <vscale x 8 x i32> @vxor_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {1470; CHECK-LABEL: vxor_vv_nxv8i32_unmasked:1471; CHECK:       # %bb.0:1472; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1473; CHECK-NEXT:    vxor.vv v8, v8, v121474; CHECK-NEXT:    ret1475  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1476  ret <vscale x 8 x i32> %v1477}1478 1479define <vscale x 8 x i32> @vxor_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1480; CHECK-LABEL: vxor_vx_nxv8i32:1481; CHECK:       # %bb.0:1482; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1483; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t1484; CHECK-NEXT:    ret1485  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01486  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1487  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)1488  ret <vscale x 8 x i32> %v1489}1490 1491define <vscale x 8 x i32> @vxor_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {1492; CHECK-LABEL: vxor_vx_nxv8i32_unmasked:1493; CHECK:       # %bb.0:1494; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1495; CHECK-NEXT:    vxor.vx v8, v8, a01496; CHECK-NEXT:    ret1497  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01498  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1499  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1500  ret <vscale x 8 x i32> %v1501}1502 1503define <vscale x 8 x i32> @vxor_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1504; CHECK-LABEL: vxor_vi_nxv8i32:1505; CHECK:       # %bb.0:1506; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1507; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1508; CHECK-NEXT:    ret1509  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i1> %m, i32 %evl)1510  ret <vscale x 8 x i32> %v1511}1512 1513define <vscale x 8 x i32> @vxor_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1514; CHECK-LABEL: vxor_vi_nxv8i32_unmasked:1515; CHECK:       # %bb.0:1516; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1517; CHECK-NEXT:    vxor.vi v8, v8, 71518; CHECK-NEXT:    ret1519  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i1> splat (i1 true), i32 %evl)1520  ret <vscale x 8 x i32> %v1521}1522 1523define <vscale x 8 x i32> @vxor_vi_nxv8i32_1(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1524; CHECK-LABEL: vxor_vi_nxv8i32_1:1525; CHECK:       # %bb.0:1526; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1527; CHECK-NEXT:    vnot.v v8, v8, v0.t1528; CHECK-NEXT:    ret1529  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)1530  ret <vscale x 8 x i32> %v1531}1532 1533define <vscale x 8 x i32> @vxor_vi_nxv8i32_unmasked_1(<vscale x 8 x i32> %va, i32 zeroext %evl) {1534; CHECK-LABEL: vxor_vi_nxv8i32_unmasked_1:1535; CHECK:       # %bb.0:1536; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1537; CHECK-NEXT:    vnot.v v8, v81538; CHECK-NEXT:    ret1539  %v = call <vscale x 8 x i32> @llvm.vp.xor.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1540  ret <vscale x 8 x i32> %v1541}1542 1543define <vscale x 16 x i32> @vxor_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1544; CHECK-LABEL: vxor_vv_nxv16i32:1545; CHECK:       # %bb.0:1546; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1547; CHECK-NEXT:    vxor.vv v8, v8, v16, v0.t1548; CHECK-NEXT:    ret1549  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)1550  ret <vscale x 16 x i32> %v1551}1552 1553define <vscale x 16 x i32> @vxor_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {1554; CHECK-LABEL: vxor_vv_nxv16i32_unmasked:1555; CHECK:       # %bb.0:1556; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1557; CHECK-NEXT:    vxor.vv v8, v8, v161558; CHECK-NEXT:    ret1559  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1560  ret <vscale x 16 x i32> %v1561}1562 1563define <vscale x 16 x i32> @vxor_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1564; CHECK-LABEL: vxor_vx_nxv16i32:1565; CHECK:       # %bb.0:1566; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1567; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t1568; CHECK-NEXT:    ret1569  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01570  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1571  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)1572  ret <vscale x 16 x i32> %v1573}1574 1575define <vscale x 16 x i32> @vxor_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {1576; CHECK-LABEL: vxor_vx_nxv16i32_unmasked:1577; CHECK:       # %bb.0:1578; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1579; CHECK-NEXT:    vxor.vx v8, v8, a01580; CHECK-NEXT:    ret1581  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01582  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1583  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1584  ret <vscale x 16 x i32> %v1585}1586 1587define <vscale x 16 x i32> @vxor_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1588; CHECK-LABEL: vxor_vi_nxv16i32:1589; CHECK:       # %bb.0:1590; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1591; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1592; CHECK-NEXT:    ret1593  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 7), <vscale x 16 x i1> %m, i32 %evl)1594  ret <vscale x 16 x i32> %v1595}1596 1597define <vscale x 16 x i32> @vxor_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1598; CHECK-LABEL: vxor_vi_nxv16i32_unmasked:1599; CHECK:       # %bb.0:1600; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1601; CHECK-NEXT:    vxor.vi v8, v8, 71602; CHECK-NEXT:    ret1603  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 7), <vscale x 16 x i1> splat (i1 true), i32 %evl)1604  ret <vscale x 16 x i32> %v1605}1606 1607define <vscale x 16 x i32> @vxor_vi_nxv16i32_1(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1608; CHECK-LABEL: vxor_vi_nxv16i32_1:1609; CHECK:       # %bb.0:1610; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1611; CHECK-NEXT:    vnot.v v8, v8, v0.t1612; CHECK-NEXT:    ret1613  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)1614  ret <vscale x 16 x i32> %v1615}1616 1617define <vscale x 16 x i32> @vxor_vi_nxv16i32_unmasked_1(<vscale x 16 x i32> %va, i32 zeroext %evl) {1618; CHECK-LABEL: vxor_vi_nxv16i32_unmasked_1:1619; CHECK:       # %bb.0:1620; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1621; CHECK-NEXT:    vnot.v v8, v81622; CHECK-NEXT:    ret1623  %v = call <vscale x 16 x i32> @llvm.vp.xor.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)1624  ret <vscale x 16 x i32> %v1625}1626 1627define <vscale x 1 x i64> @vxor_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1628; CHECK-LABEL: vxor_vv_nxv1i64:1629; CHECK:       # %bb.0:1630; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1631; CHECK-NEXT:    vxor.vv v8, v8, v9, v0.t1632; CHECK-NEXT:    ret1633  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)1634  ret <vscale x 1 x i64> %v1635}1636 1637define <vscale x 1 x i64> @vxor_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {1638; CHECK-LABEL: vxor_vv_nxv1i64_unmasked:1639; CHECK:       # %bb.0:1640; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1641; CHECK-NEXT:    vxor.vv v8, v8, v91642; CHECK-NEXT:    ret1643  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1644  ret <vscale x 1 x i64> %v1645}1646 1647define <vscale x 1 x i64> @vxor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1648; RV32-LABEL: vxor_vx_nxv1i64:1649; RV32:       # %bb.0:1650; RV32-NEXT:    addi sp, sp, -161651; RV32-NEXT:    .cfi_def_cfa_offset 161652; RV32-NEXT:    sw a0, 8(sp)1653; RV32-NEXT:    sw a1, 12(sp)1654; RV32-NEXT:    addi a0, sp, 81655; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1656; RV32-NEXT:    vlse64.v v9, (a0), zero1657; RV32-NEXT:    vxor.vv v8, v8, v9, v0.t1658; RV32-NEXT:    addi sp, sp, 161659; RV32-NEXT:    .cfi_def_cfa_offset 01660; RV32-NEXT:    ret1661;1662; RV64-LABEL: vxor_vx_nxv1i64:1663; RV64:       # %bb.0:1664; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1665; RV64-NEXT:    vxor.vx v8, v8, a0, v0.t1666; RV64-NEXT:    ret1667  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01668  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1669  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)1670  ret <vscale x 1 x i64> %v1671}1672 1673define <vscale x 1 x i64> @vxor_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {1674; RV32-LABEL: vxor_vx_nxv1i64_unmasked:1675; RV32:       # %bb.0:1676; RV32-NEXT:    addi sp, sp, -161677; RV32-NEXT:    .cfi_def_cfa_offset 161678; RV32-NEXT:    sw a0, 8(sp)1679; RV32-NEXT:    sw a1, 12(sp)1680; RV32-NEXT:    addi a0, sp, 81681; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1682; RV32-NEXT:    vlse64.v v9, (a0), zero1683; RV32-NEXT:    vxor.vv v8, v8, v91684; RV32-NEXT:    addi sp, sp, 161685; RV32-NEXT:    .cfi_def_cfa_offset 01686; RV32-NEXT:    ret1687;1688; RV64-LABEL: vxor_vx_nxv1i64_unmasked:1689; RV64:       # %bb.0:1690; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1691; RV64-NEXT:    vxor.vx v8, v8, a01692; RV64-NEXT:    ret1693  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01694  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1695  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1696  ret <vscale x 1 x i64> %v1697}1698 1699define <vscale x 1 x i64> @vxor_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1700; CHECK-LABEL: vxor_vi_nxv1i64:1701; CHECK:       # %bb.0:1702; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1703; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1704; CHECK-NEXT:    ret1705  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 7), <vscale x 1 x i1> %m, i32 %evl)1706  ret <vscale x 1 x i64> %v1707}1708 1709define <vscale x 1 x i64> @vxor_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1710; CHECK-LABEL: vxor_vi_nxv1i64_unmasked:1711; CHECK:       # %bb.0:1712; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1713; CHECK-NEXT:    vxor.vi v8, v8, 71714; CHECK-NEXT:    ret1715  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 7), <vscale x 1 x i1> splat (i1 true), i32 %evl)1716  ret <vscale x 1 x i64> %v1717}1718 1719define <vscale x 1 x i64> @vxor_vi_nxv1i64_1(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1720; CHECK-LABEL: vxor_vi_nxv1i64_1:1721; CHECK:       # %bb.0:1722; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1723; CHECK-NEXT:    vnot.v v8, v8, v0.t1724; CHECK-NEXT:    ret1725  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)1726  ret <vscale x 1 x i64> %v1727}1728 1729define <vscale x 1 x i64> @vxor_vi_nxv1i64_unmasked_1(<vscale x 1 x i64> %va, i32 zeroext %evl) {1730; CHECK-LABEL: vxor_vi_nxv1i64_unmasked_1:1731; CHECK:       # %bb.0:1732; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1733; CHECK-NEXT:    vnot.v v8, v81734; CHECK-NEXT:    ret1735  %v = call <vscale x 1 x i64> @llvm.vp.xor.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1736  ret <vscale x 1 x i64> %v1737}1738 1739define <vscale x 2 x i64> @vxor_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1740; CHECK-LABEL: vxor_vv_nxv2i64:1741; CHECK:       # %bb.0:1742; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1743; CHECK-NEXT:    vxor.vv v8, v8, v10, v0.t1744; CHECK-NEXT:    ret1745  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)1746  ret <vscale x 2 x i64> %v1747}1748 1749define <vscale x 2 x i64> @vxor_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {1750; CHECK-LABEL: vxor_vv_nxv2i64_unmasked:1751; CHECK:       # %bb.0:1752; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1753; CHECK-NEXT:    vxor.vv v8, v8, v101754; CHECK-NEXT:    ret1755  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1756  ret <vscale x 2 x i64> %v1757}1758 1759define <vscale x 2 x i64> @vxor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1760; RV32-LABEL: vxor_vx_nxv2i64:1761; RV32:       # %bb.0:1762; RV32-NEXT:    addi sp, sp, -161763; RV32-NEXT:    .cfi_def_cfa_offset 161764; RV32-NEXT:    sw a0, 8(sp)1765; RV32-NEXT:    sw a1, 12(sp)1766; RV32-NEXT:    addi a0, sp, 81767; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1768; RV32-NEXT:    vlse64.v v10, (a0), zero1769; RV32-NEXT:    vxor.vv v8, v8, v10, v0.t1770; RV32-NEXT:    addi sp, sp, 161771; RV32-NEXT:    .cfi_def_cfa_offset 01772; RV32-NEXT:    ret1773;1774; RV64-LABEL: vxor_vx_nxv2i64:1775; RV64:       # %bb.0:1776; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1777; RV64-NEXT:    vxor.vx v8, v8, a0, v0.t1778; RV64-NEXT:    ret1779  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01780  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1781  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)1782  ret <vscale x 2 x i64> %v1783}1784 1785define <vscale x 2 x i64> @vxor_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {1786; RV32-LABEL: vxor_vx_nxv2i64_unmasked:1787; RV32:       # %bb.0:1788; RV32-NEXT:    addi sp, sp, -161789; RV32-NEXT:    .cfi_def_cfa_offset 161790; RV32-NEXT:    sw a0, 8(sp)1791; RV32-NEXT:    sw a1, 12(sp)1792; RV32-NEXT:    addi a0, sp, 81793; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1794; RV32-NEXT:    vlse64.v v10, (a0), zero1795; RV32-NEXT:    vxor.vv v8, v8, v101796; RV32-NEXT:    addi sp, sp, 161797; RV32-NEXT:    .cfi_def_cfa_offset 01798; RV32-NEXT:    ret1799;1800; RV64-LABEL: vxor_vx_nxv2i64_unmasked:1801; RV64:       # %bb.0:1802; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1803; RV64-NEXT:    vxor.vx v8, v8, a01804; RV64-NEXT:    ret1805  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01806  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1807  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1808  ret <vscale x 2 x i64> %v1809}1810 1811define <vscale x 2 x i64> @vxor_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1812; CHECK-LABEL: vxor_vi_nxv2i64:1813; CHECK:       # %bb.0:1814; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1815; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1816; CHECK-NEXT:    ret1817  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 7), <vscale x 2 x i1> %m, i32 %evl)1818  ret <vscale x 2 x i64> %v1819}1820 1821define <vscale x 2 x i64> @vxor_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1822; CHECK-LABEL: vxor_vi_nxv2i64_unmasked:1823; CHECK:       # %bb.0:1824; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1825; CHECK-NEXT:    vxor.vi v8, v8, 71826; CHECK-NEXT:    ret1827  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 7), <vscale x 2 x i1> splat (i1 true), i32 %evl)1828  ret <vscale x 2 x i64> %v1829}1830 1831define <vscale x 2 x i64> @vxor_vi_nxv2i64_1(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1832; CHECK-LABEL: vxor_vi_nxv2i64_1:1833; CHECK:       # %bb.0:1834; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1835; CHECK-NEXT:    vnot.v v8, v8, v0.t1836; CHECK-NEXT:    ret1837  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)1838  ret <vscale x 2 x i64> %v1839}1840 1841define <vscale x 2 x i64> @vxor_vi_nxv2i64_unmasked_1(<vscale x 2 x i64> %va, i32 zeroext %evl) {1842; CHECK-LABEL: vxor_vi_nxv2i64_unmasked_1:1843; CHECK:       # %bb.0:1844; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1845; CHECK-NEXT:    vnot.v v8, v81846; CHECK-NEXT:    ret1847  %v = call <vscale x 2 x i64> @llvm.vp.xor.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1848  ret <vscale x 2 x i64> %v1849}1850 1851define <vscale x 4 x i64> @vxor_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1852; CHECK-LABEL: vxor_vv_nxv4i64:1853; CHECK:       # %bb.0:1854; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1855; CHECK-NEXT:    vxor.vv v8, v8, v12, v0.t1856; CHECK-NEXT:    ret1857  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)1858  ret <vscale x 4 x i64> %v1859}1860 1861define <vscale x 4 x i64> @vxor_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {1862; CHECK-LABEL: vxor_vv_nxv4i64_unmasked:1863; CHECK:       # %bb.0:1864; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1865; CHECK-NEXT:    vxor.vv v8, v8, v121866; CHECK-NEXT:    ret1867  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1868  ret <vscale x 4 x i64> %v1869}1870 1871define <vscale x 4 x i64> @vxor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1872; RV32-LABEL: vxor_vx_nxv4i64:1873; RV32:       # %bb.0:1874; RV32-NEXT:    addi sp, sp, -161875; RV32-NEXT:    .cfi_def_cfa_offset 161876; RV32-NEXT:    sw a0, 8(sp)1877; RV32-NEXT:    sw a1, 12(sp)1878; RV32-NEXT:    addi a0, sp, 81879; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1880; RV32-NEXT:    vlse64.v v12, (a0), zero1881; RV32-NEXT:    vxor.vv v8, v8, v12, v0.t1882; RV32-NEXT:    addi sp, sp, 161883; RV32-NEXT:    .cfi_def_cfa_offset 01884; RV32-NEXT:    ret1885;1886; RV64-LABEL: vxor_vx_nxv4i64:1887; RV64:       # %bb.0:1888; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1889; RV64-NEXT:    vxor.vx v8, v8, a0, v0.t1890; RV64-NEXT:    ret1891  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01892  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1893  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)1894  ret <vscale x 4 x i64> %v1895}1896 1897define <vscale x 4 x i64> @vxor_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {1898; RV32-LABEL: vxor_vx_nxv4i64_unmasked:1899; RV32:       # %bb.0:1900; RV32-NEXT:    addi sp, sp, -161901; RV32-NEXT:    .cfi_def_cfa_offset 161902; RV32-NEXT:    sw a0, 8(sp)1903; RV32-NEXT:    sw a1, 12(sp)1904; RV32-NEXT:    addi a0, sp, 81905; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1906; RV32-NEXT:    vlse64.v v12, (a0), zero1907; RV32-NEXT:    vxor.vv v8, v8, v121908; RV32-NEXT:    addi sp, sp, 161909; RV32-NEXT:    .cfi_def_cfa_offset 01910; RV32-NEXT:    ret1911;1912; RV64-LABEL: vxor_vx_nxv4i64_unmasked:1913; RV64:       # %bb.0:1914; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1915; RV64-NEXT:    vxor.vx v8, v8, a01916; RV64-NEXT:    ret1917  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01918  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1919  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1920  ret <vscale x 4 x i64> %v1921}1922 1923define <vscale x 4 x i64> @vxor_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1924; CHECK-LABEL: vxor_vi_nxv4i64:1925; CHECK:       # %bb.0:1926; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1927; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t1928; CHECK-NEXT:    ret1929  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 7), <vscale x 4 x i1> %m, i32 %evl)1930  ret <vscale x 4 x i64> %v1931}1932 1933define <vscale x 4 x i64> @vxor_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1934; CHECK-LABEL: vxor_vi_nxv4i64_unmasked:1935; CHECK:       # %bb.0:1936; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1937; CHECK-NEXT:    vxor.vi v8, v8, 71938; CHECK-NEXT:    ret1939  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 7), <vscale x 4 x i1> splat (i1 true), i32 %evl)1940  ret <vscale x 4 x i64> %v1941}1942 1943define <vscale x 4 x i64> @vxor_vi_nxv4i64_1(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1944; CHECK-LABEL: vxor_vi_nxv4i64_1:1945; CHECK:       # %bb.0:1946; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1947; CHECK-NEXT:    vnot.v v8, v8, v0.t1948; CHECK-NEXT:    ret1949  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)1950  ret <vscale x 4 x i64> %v1951}1952 1953define <vscale x 4 x i64> @vxor_vi_nxv4i64_unmasked_1(<vscale x 4 x i64> %va, i32 zeroext %evl) {1954; CHECK-LABEL: vxor_vi_nxv4i64_unmasked_1:1955; CHECK:       # %bb.0:1956; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1957; CHECK-NEXT:    vnot.v v8, v81958; CHECK-NEXT:    ret1959  %v = call <vscale x 4 x i64> @llvm.vp.xor.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1960  ret <vscale x 4 x i64> %v1961}1962 1963define <vscale x 8 x i64> @vxor_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1964; CHECK-LABEL: vxor_vv_nxv8i64:1965; CHECK:       # %bb.0:1966; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1967; CHECK-NEXT:    vxor.vv v8, v8, v16, v0.t1968; CHECK-NEXT:    ret1969  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)1970  ret <vscale x 8 x i64> %v1971}1972 1973define <vscale x 8 x i64> @vxor_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {1974; CHECK-LABEL: vxor_vv_nxv8i64_unmasked:1975; CHECK:       # %bb.0:1976; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1977; CHECK-NEXT:    vxor.vv v8, v8, v161978; CHECK-NEXT:    ret1979  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1980  ret <vscale x 8 x i64> %v1981}1982 1983define <vscale x 8 x i64> @vxor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1984; RV32-LABEL: vxor_vx_nxv8i64:1985; RV32:       # %bb.0:1986; RV32-NEXT:    addi sp, sp, -161987; RV32-NEXT:    .cfi_def_cfa_offset 161988; RV32-NEXT:    sw a0, 8(sp)1989; RV32-NEXT:    sw a1, 12(sp)1990; RV32-NEXT:    addi a0, sp, 81991; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1992; RV32-NEXT:    vlse64.v v16, (a0), zero1993; RV32-NEXT:    vxor.vv v8, v8, v16, v0.t1994; RV32-NEXT:    addi sp, sp, 161995; RV32-NEXT:    .cfi_def_cfa_offset 01996; RV32-NEXT:    ret1997;1998; RV64-LABEL: vxor_vx_nxv8i64:1999; RV64:       # %bb.0:2000; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma2001; RV64-NEXT:    vxor.vx v8, v8, a0, v0.t2002; RV64-NEXT:    ret2003  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02004  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2005  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)2006  ret <vscale x 8 x i64> %v2007}2008 2009define <vscale x 8 x i64> @vxor_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {2010; RV32-LABEL: vxor_vx_nxv8i64_unmasked:2011; RV32:       # %bb.0:2012; RV32-NEXT:    addi sp, sp, -162013; RV32-NEXT:    .cfi_def_cfa_offset 162014; RV32-NEXT:    sw a0, 8(sp)2015; RV32-NEXT:    sw a1, 12(sp)2016; RV32-NEXT:    addi a0, sp, 82017; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma2018; RV32-NEXT:    vlse64.v v16, (a0), zero2019; RV32-NEXT:    vxor.vv v8, v8, v162020; RV32-NEXT:    addi sp, sp, 162021; RV32-NEXT:    .cfi_def_cfa_offset 02022; RV32-NEXT:    ret2023;2024; RV64-LABEL: vxor_vx_nxv8i64_unmasked:2025; RV64:       # %bb.0:2026; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma2027; RV64-NEXT:    vxor.vx v8, v8, a02028; RV64-NEXT:    ret2029  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 02030  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer2031  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)2032  ret <vscale x 8 x i64> %v2033}2034 2035define <vscale x 8 x i64> @vxor_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {2036; CHECK-LABEL: vxor_vi_nxv8i64:2037; CHECK:       # %bb.0:2038; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2039; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t2040; CHECK-NEXT:    ret2041  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 7), <vscale x 8 x i1> %m, i32 %evl)2042  ret <vscale x 8 x i64> %v2043}2044 2045define <vscale x 8 x i64> @vxor_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {2046; CHECK-LABEL: vxor_vi_nxv8i64_unmasked:2047; CHECK:       # %bb.0:2048; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2049; CHECK-NEXT:    vxor.vi v8, v8, 72050; CHECK-NEXT:    ret2051  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 7), <vscale x 8 x i1> splat (i1 true), i32 %evl)2052  ret <vscale x 8 x i64> %v2053}2054 2055define <vscale x 8 x i64> @vxor_vi_nxv8i64_1(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {2056; CHECK-LABEL: vxor_vi_nxv8i64_1:2057; CHECK:       # %bb.0:2058; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2059; CHECK-NEXT:    vnot.v v8, v8, v0.t2060; CHECK-NEXT:    ret2061  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)2062  ret <vscale x 8 x i64> %v2063}2064 2065define <vscale x 8 x i64> @vxor_vi_nxv8i64_unmasked_1(<vscale x 8 x i64> %va, i32 zeroext %evl) {2066; CHECK-LABEL: vxor_vi_nxv8i64_unmasked_1:2067; CHECK:       # %bb.0:2068; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2069; CHECK-NEXT:    vnot.v v8, v82070; CHECK-NEXT:    ret2071  %v = call <vscale x 8 x i64> @llvm.vp.xor.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)2072  ret <vscale x 8 x i64> %v2073}2074