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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22 3; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \4; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV325; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \6; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV647 8; Test same rounding mode in one block.9define <vscale x 1 x i8> @test1(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {10; CHECK-LABEL: test1:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: csrwi vxrm, 013; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma14; CHECK-NEXT: vaadd.vv v8, v8, v915; CHECK-NEXT: vaadd.vv v8, v8, v1016; CHECK-NEXT: ret17entry:18 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(19 <vscale x 1 x i8> poison,20 <vscale x 1 x i8> %0,21 <vscale x 1 x i8> %1,22 iXLen 0, iXLen %3)23 %b = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(24 <vscale x 1 x i8> poison,25 <vscale x 1 x i8> %a,26 <vscale x 1 x i8> %2,27 iXLen 0, iXLen %3)28 29 ret <vscale x 1 x i8> %b30}31 32; Test different rounding mode.33define <vscale x 1 x i8> @test2(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {34; CHECK-LABEL: test2:35; CHECK: # %bb.0: # %entry36; CHECK-NEXT: csrwi vxrm, 237; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma38; CHECK-NEXT: vaadd.vv v8, v8, v939; CHECK-NEXT: csrwi vxrm, 040; CHECK-NEXT: vaadd.vv v8, v8, v1041; CHECK-NEXT: ret42entry:43 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(44 <vscale x 1 x i8> poison,45 <vscale x 1 x i8> %0,46 <vscale x 1 x i8> %1,47 iXLen 2, iXLen %3)48 %b = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(49 <vscale x 1 x i8> poison,50 <vscale x 1 x i8> %a,51 <vscale x 1 x i8> %2,52 iXLen 0, iXLen %3)53 54 ret <vscale x 1 x i8> %b55}56 57declare <vscale x 1 x i8> @foo(<vscale x 1 x i8>)58 59; Test same vxrm with call in between which may invalidate vxrm.60define <vscale x 1 x i8> @test3(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {61; RV32-LABEL: test3:62; RV32: # %bb.0: # %entry63; RV32-NEXT: addi sp, sp, -3264; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill65; RV32-NEXT: sw s0, 24(sp) # 4-byte Folded Spill66; RV32-NEXT: csrr a1, vlenb67; RV32-NEXT: sub sp, sp, a168; RV32-NEXT: mv s0, a069; RV32-NEXT: addi a1, sp, 1670; RV32-NEXT: vs1r.v v10, (a1) # vscale x 8-byte Folded Spill71; RV32-NEXT: csrwi vxrm, 072; RV32-NEXT: vsetvli zero, a0, e8, mf8, ta, ma73; RV32-NEXT: vaadd.vv v8, v8, v974; RV32-NEXT: call foo75; RV32-NEXT: csrwi vxrm, 076; RV32-NEXT: addi a0, sp, 1677; RV32-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload78; RV32-NEXT: vsetvli zero, s0, e8, mf8, ta, ma79; RV32-NEXT: vaadd.vv v8, v8, v980; RV32-NEXT: csrr a0, vlenb81; RV32-NEXT: add sp, sp, a082; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload83; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload84; RV32-NEXT: addi sp, sp, 3285; RV32-NEXT: ret86;87; RV64-LABEL: test3:88; RV64: # %bb.0: # %entry89; RV64-NEXT: addi sp, sp, -3290; RV64-NEXT: sd ra, 24(sp) # 8-byte Folded Spill91; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill92; RV64-NEXT: csrr a1, vlenb93; RV64-NEXT: sub sp, sp, a194; RV64-NEXT: mv s0, a095; RV64-NEXT: addi a1, sp, 1696; RV64-NEXT: vs1r.v v10, (a1) # vscale x 8-byte Folded Spill97; RV64-NEXT: csrwi vxrm, 098; RV64-NEXT: vsetvli zero, a0, e8, mf8, ta, ma99; RV64-NEXT: vaadd.vv v8, v8, v9100; RV64-NEXT: call foo101; RV64-NEXT: csrwi vxrm, 0102; RV64-NEXT: addi a0, sp, 16103; RV64-NEXT: vl1r.v v9, (a0) # vscale x 8-byte Folded Reload104; RV64-NEXT: vsetvli zero, s0, e8, mf8, ta, ma105; RV64-NEXT: vaadd.vv v8, v8, v9106; RV64-NEXT: csrr a0, vlenb107; RV64-NEXT: add sp, sp, a0108; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload109; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload110; RV64-NEXT: addi sp, sp, 32111; RV64-NEXT: ret112entry:113 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(114 <vscale x 1 x i8> poison,115 <vscale x 1 x i8> %0,116 <vscale x 1 x i8> %1,117 iXLen 0, iXLen %3)118 %b = call <vscale x 1 x i8> @foo(<vscale x 1 x i8> %a)119 %c = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(120 <vscale x 1 x i8> poison,121 <vscale x 1 x i8> %b,122 <vscale x 1 x i8> %2,123 iXLen 0, iXLen %3)124 125 ret <vscale x 1 x i8> %c126}127 128; Test same vxrm with asm in between which may invalidate vxrm.129define <vscale x 1 x i8> @test4(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {130; CHECK-LABEL: test4:131; CHECK: # %bb.0: # %entry132; CHECK-NEXT: csrwi vxrm, 0133; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma134; CHECK-NEXT: vaadd.vv v8, v8, v9135; CHECK-NEXT: #APP136; CHECK-NEXT: #NO_APP137; CHECK-NEXT: csrwi vxrm, 0138; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma139; CHECK-NEXT: vaadd.vv v8, v8, v10140; CHECK-NEXT: ret141entry:142 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(143 <vscale x 1 x i8> poison,144 <vscale x 1 x i8> %0,145 <vscale x 1 x i8> %1,146 iXLen 0, iXLen %3)147 %b = call <vscale x 1 x i8> asm "", "=^vr,0"(<vscale x 1 x i8> %a)148 %c = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(149 <vscale x 1 x i8> poison,150 <vscale x 1 x i8> %b,151 <vscale x 1 x i8> %2,152 iXLen 0, iXLen %3)153 154 ret <vscale x 1 x i8> %c155}156 157; Test same rounding mode in triangle.158define <vscale x 1 x i8> @test5(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3, i1 %cond) nounwind {159; CHECK-LABEL: test5:160; CHECK: # %bb.0: # %entry161; CHECK-NEXT: andi a1, a1, 1162; CHECK-NEXT: csrwi vxrm, 0163; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma164; CHECK-NEXT: vaadd.vv v8, v8, v9165; CHECK-NEXT: beqz a1, .LBB4_2166; CHECK-NEXT: # %bb.1: # %condblock167; CHECK-NEXT: vaadd.vv v8, v8, v10168; CHECK-NEXT: .LBB4_2: # %mergeblock169; CHECK-NEXT: ret170entry:171 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(172 <vscale x 1 x i8> poison,173 <vscale x 1 x i8> %0,174 <vscale x 1 x i8> %1,175 iXLen 0, iXLen %3)176 br i1 %cond, label %condblock, label %mergeblock177 178condblock:179 %b = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(180 <vscale x 1 x i8> poison,181 <vscale x 1 x i8> %a,182 <vscale x 1 x i8> %2,183 iXLen 0, iXLen %3)184 br label %mergeblock185 186mergeblock:187 %c = phi <vscale x 1 x i8> [%a, %entry], [%b, %condblock]188 189 ret <vscale x 1 x i8> %c190}191 192; Test same rounding mode in diamond with no dominating vxrm.193define <vscale x 1 x i8> @test6(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3, i1 %cond) nounwind {194; CHECK-LABEL: test6:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: andi a1, a1, 1197; CHECK-NEXT: csrwi vxrm, 0198; CHECK-NEXT: beqz a1, .LBB5_2199; CHECK-NEXT: # %bb.1: # %trueblock200; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma201; CHECK-NEXT: vaadd.vv v8, v8, v9202; CHECK-NEXT: ret203; CHECK-NEXT: .LBB5_2: # %falseblock204; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma205; CHECK-NEXT: vaadd.vv v8, v8, v10206; CHECK-NEXT: ret207entry:208 br i1 %cond, label %trueblock, label %falseblock209 210trueblock:211 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(212 <vscale x 1 x i8> poison,213 <vscale x 1 x i8> %0,214 <vscale x 1 x i8> %1,215 iXLen 0, iXLen %3)216 br label %mergeblock217 218falseblock:219 %b = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(220 <vscale x 1 x i8> poison,221 <vscale x 1 x i8> %0,222 <vscale x 1 x i8> %2,223 iXLen 0, iXLen %3)224 br label %mergeblock225 226mergeblock:227 %c = phi <vscale x 1 x i8> [%a, %trueblock], [%b, %falseblock]228 229 ret <vscale x 1 x i8> %c230}231 232; Test same rounding mode in diamond with same dominating vxrm.233define <vscale x 1 x i8> @test7(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3, i1 %cond) nounwind {234; CHECK-LABEL: test7:235; CHECK: # %bb.0: # %entry236; CHECK-NEXT: andi a1, a1, 1237; CHECK-NEXT: csrwi vxrm, 0238; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma239; CHECK-NEXT: vaadd.vv v8, v8, v9240; CHECK-NEXT: beqz a1, .LBB6_2241; CHECK-NEXT: # %bb.1: # %trueblock242; CHECK-NEXT: vaadd.vv v8, v8, v10243; CHECK-NEXT: ret244; CHECK-NEXT: .LBB6_2: # %falseblock245; CHECK-NEXT: vasub.vv v8, v8, v10246; CHECK-NEXT: ret247entry:248 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(249 <vscale x 1 x i8> poison,250 <vscale x 1 x i8> %0,251 <vscale x 1 x i8> %1,252 iXLen 0, iXLen %3)253 br i1 %cond, label %trueblock, label %falseblock254 255trueblock:256 %b = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(257 <vscale x 1 x i8> poison,258 <vscale x 1 x i8> %a,259 <vscale x 1 x i8> %2,260 iXLen 0, iXLen %3)261 br label %mergeblock262 263falseblock:264 %c = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8(265 <vscale x 1 x i8> poison,266 <vscale x 1 x i8> %a,267 <vscale x 1 x i8> %2,268 iXLen 0, iXLen %3)269 br label %mergeblock270 271mergeblock:272 %d = phi <vscale x 1 x i8> [%b, %trueblock], [%c, %falseblock]273 274 ret <vscale x 1 x i8> %d275}276 277; Test same rounding mode in diamond with same vxrm at merge.278define <vscale x 1 x i8> @test8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3, i1 %cond) nounwind {279; CHECK-LABEL: test8:280; CHECK: # %bb.0: # %entry281; CHECK-NEXT: andi a1, a1, 1282; CHECK-NEXT: csrwi vxrm, 0283; CHECK-NEXT: beqz a1, .LBB7_2284; CHECK-NEXT: # %bb.1: # %trueblock285; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma286; CHECK-NEXT: vaadd.vv v8, v8, v9287; CHECK-NEXT: vaadd.vv v8, v8, v10288; CHECK-NEXT: ret289; CHECK-NEXT: .LBB7_2: # %falseblock290; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma291; CHECK-NEXT: vasub.vv v8, v8, v9292; CHECK-NEXT: vaadd.vv v8, v8, v10293; CHECK-NEXT: ret294entry:295 br i1 %cond, label %trueblock, label %falseblock296 297trueblock:298 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(299 <vscale x 1 x i8> poison,300 <vscale x 1 x i8> %0,301 <vscale x 1 x i8> %1,302 iXLen 0, iXLen %3)303 br label %mergeblock304 305falseblock:306 %b = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8(307 <vscale x 1 x i8> poison,308 <vscale x 1 x i8> %0,309 <vscale x 1 x i8> %1,310 iXLen 0, iXLen %3)311 br label %mergeblock312 313mergeblock:314 %c = phi <vscale x 1 x i8> [%a, %trueblock], [%b, %falseblock]315 %d = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(316 <vscale x 1 x i8> poison,317 <vscale x 1 x i8> %c,318 <vscale x 1 x i8> %2,319 iXLen 0, iXLen %3)320 321 ret <vscale x 1 x i8> %d322}323 324; Test same rounding mode in diamond with different vxrm at merge.325define <vscale x 1 x i8> @test9(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3, i1 %cond) nounwind {326; CHECK-LABEL: test9:327; CHECK: # %bb.0: # %entry328; CHECK-NEXT: andi a1, a1, 1329; CHECK-NEXT: csrwi vxrm, 0330; CHECK-NEXT: beqz a1, .LBB8_2331; CHECK-NEXT: # %bb.1: # %trueblock332; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma333; CHECK-NEXT: vaadd.vv v8, v8, v9334; CHECK-NEXT: j .LBB8_3335; CHECK-NEXT: .LBB8_2: # %falseblock336; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma337; CHECK-NEXT: vasub.vv v8, v8, v9338; CHECK-NEXT: .LBB8_3: # %mergeblock339; CHECK-NEXT: csrwi vxrm, 2340; CHECK-NEXT: vaadd.vv v8, v8, v10341; CHECK-NEXT: ret342entry:343 br i1 %cond, label %trueblock, label %falseblock344 345trueblock:346 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(347 <vscale x 1 x i8> poison,348 <vscale x 1 x i8> %0,349 <vscale x 1 x i8> %1,350 iXLen 0, iXLen %3)351 br label %mergeblock352 353falseblock:354 %b = call <vscale x 1 x i8> @llvm.riscv.vasub.nxv1i8.nxv1i8(355 <vscale x 1 x i8> poison,356 <vscale x 1 x i8> %0,357 <vscale x 1 x i8> %1,358 iXLen 0, iXLen %3)359 br label %mergeblock360 361mergeblock:362 %c = phi <vscale x 1 x i8> [%a, %trueblock], [%b, %falseblock]363 %d = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(364 <vscale x 1 x i8> poison,365 <vscale x 1 x i8> %c,366 <vscale x 1 x i8> %2,367 iXLen 2, iXLen %3)368 369 ret <vscale x 1 x i8> %d370}371 372; Test loop with no dominating vxrm write.373define void @test10(ptr nocapture %ptr_dest, ptr nocapture readonly %ptr_op1, ptr nocapture readonly %ptr_op2, iXLen %n) {374; CHECK-LABEL: test10:375; CHECK: # %bb.0: # %entry376; CHECK-NEXT: beqz a3, .LBB9_3377; CHECK-NEXT: # %bb.1: # %for.body.preheader378; CHECK-NEXT: csrwi vxrm, 2379; CHECK-NEXT: .LBB9_2: # %for.body380; CHECK-NEXT: # =>This Inner Loop Header: Depth=1381; CHECK-NEXT: vsetvli a4, a3, e8, mf8, ta, ma382; CHECK-NEXT: vle8.v v8, (a1)383; CHECK-NEXT: vle8.v v9, (a2)384; CHECK-NEXT: vaadd.vv v8, v8, v9385; CHECK-NEXT: sub a3, a3, a4386; CHECK-NEXT: vse8.v v8, (a0)387; CHECK-NEXT: bnez a3, .LBB9_2388; CHECK-NEXT: .LBB9_3: # %for.end389; CHECK-NEXT: ret390entry:391 %tobool.not9 = icmp eq iXLen %n, 0392 br i1 %tobool.not9, label %for.end, label %for.body393 394for.body:395 %n.addr.011 = phi iXLen [ %n, %entry ], [ %sub, %for.body ]396 %vl = tail call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %n.addr.011, iXLen 0, iXLen 5)397 %load1 = tail call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.iXLen(<vscale x 1 x i8> poison, ptr %ptr_op1, iXLen %vl)398 %load2 = tail call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.iXLen(<vscale x 1 x i8> poison, ptr %ptr_op2, iXLen %vl)399 %vadd = tail call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %load1, <vscale x 1 x i8> %load2, iXLen 2, iXLen %vl)400 tail call void @llvm.riscv.vse.nxv1i8.iXLen(<vscale x 1 x i8> %vadd, ptr %ptr_dest, iXLen %vl)401 %sub = sub iXLen %n.addr.011, %vl402 %tobool.not = icmp eq iXLen %sub, 0403 br i1 %tobool.not, label %for.end, label %for.body404 405for.end:406 ret void407}408 409; Test loop with dominating vxrm write. Make sure there is no write in the loop.410define void @test11(ptr nocapture %ptr_dest, ptr nocapture readonly %ptr_op1, ptr nocapture readonly %ptr_op2, iXLen %n) {411; CHECK-LABEL: test11:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: vsetvli a4, a3, e8, mf8, ta, ma414; CHECK-NEXT: vle8.v v8, (a1)415; CHECK-NEXT: vle8.v v9, (a2)416; CHECK-NEXT: csrwi vxrm, 2417; CHECK-NEXT: .LBB10_1: # %for.body418; CHECK-NEXT: # =>This Inner Loop Header: Depth=1419; CHECK-NEXT: vaadd.vv v8, v8, v9420; CHECK-NEXT: sub a3, a3, a4421; CHECK-NEXT: vse8.v v8, (a0)422; CHECK-NEXT: beqz a3, .LBB10_3423; CHECK-NEXT: # %bb.2: # %for.body424; CHECK-NEXT: # in Loop: Header=BB10_1 Depth=1425; CHECK-NEXT: vsetvli a4, a3, e8, mf8, ta, ma426; CHECK-NEXT: vle8.v v8, (a1)427; CHECK-NEXT: vle8.v v9, (a2)428; CHECK-NEXT: j .LBB10_1429; CHECK-NEXT: .LBB10_3: # %for.end430; CHECK-NEXT: ret431entry:432 %vl = tail call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %n, iXLen 0, iXLen 5)433 %load1a = tail call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.iXLen(<vscale x 1 x i8> poison, ptr %ptr_op1, iXLen %vl)434 %load2a = tail call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.iXLen(<vscale x 1 x i8> poison, ptr %ptr_op2, iXLen %vl)435 %vadda = tail call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %load1a, <vscale x 1 x i8> %load2a, iXLen 2, iXLen %vl)436 tail call void @llvm.riscv.vse.nxv1i8.iXLen(<vscale x 1 x i8> %vadda, ptr %ptr_dest, iXLen %vl)437 %suba = sub iXLen %n, %vl438 %tobool.not9 = icmp eq iXLen %suba, 0439 br i1 %tobool.not9, label %for.end, label %for.body440 441for.body:442 %n.addr.011 = phi iXLen [ %suba, %entry ], [ %sub, %for.body ]443 %vl2 = tail call iXLen @llvm.riscv.vsetvli.iXLen(iXLen %n.addr.011, iXLen 0, iXLen 5)444 %load1 = tail call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.iXLen(<vscale x 1 x i8> poison, ptr %ptr_op1, iXLen %vl2)445 %load2 = tail call <vscale x 1 x i8> @llvm.riscv.vle.nxv1i8.iXLen(<vscale x 1 x i8> poison, ptr %ptr_op2, iXLen %vl2)446 %vadd = tail call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %load1, <vscale x 1 x i8> %load2, iXLen 2, iXLen %vl2)447 tail call void @llvm.riscv.vse.nxv1i8.iXLen(<vscale x 1 x i8> %vadd, ptr %ptr_dest, iXLen %vl2)448 %sub = sub iXLen %n.addr.011, %vl2449 %tobool.not = icmp eq iXLen %sub, 0450 br i1 %tobool.not, label %for.end, label %for.body451 452for.end:453 ret void454}455 456; The edge from entry to block2 is a critical edge. The vxrm write in block2457; is redundant when coming from block1, but is needed when coming from entry.458; FIXME: We could remove the write from the end of block1 without splitting the459; critical edge.460define <vscale x 1 x i8> @test12(i1 %c1, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %vl) {461; CHECK-LABEL: test12:462; CHECK: # %bb.0: # %entry463; CHECK-NEXT: andi a0, a0, 1464; CHECK-NEXT: csrwi vxrm, 0465; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma466; CHECK-NEXT: vaadd.vv v9, v8, v9467; CHECK-NEXT: beqz a0, .LBB11_2468; CHECK-NEXT: # %bb.1: # %block1469; CHECK-NEXT: csrwi vxrm, 1470; CHECK-NEXT: vaadd.vv v9, v8, v9471; CHECK-NEXT: csrwi vxrm, 2472; CHECK-NEXT: .LBB11_2: # %block2473; CHECK-NEXT: csrwi vxrm, 2474; CHECK-NEXT: vaadd.vv v8, v8, v9475; CHECK-NEXT: ret476entry:477 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen 0, iXLen %vl)478 br i1 %c1, label %block1, label %block2479 480block1:481 %b = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %a, iXLen 1, iXLen %vl)482 br label %block2483 484block2:485 %c = phi <vscale x 1 x i8> [ %a, %entry ], [ %b, %block1]486 %d = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %c, iXLen 2, iXLen %vl)487 ret <vscale x 1 x i8> %d488}489 490; Similar to test12, but introduces a second critical edge from block1 to491; block3. Now the write to vxrm at the end of block1, can't be removed because492; it is needed by block3.493define <vscale x 1 x i8> @test13(i1 %c1, i1 %c2, i1 %c3, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %vl) {494; CHECK-LABEL: test13:495; CHECK: # %bb.0: # %entry496; CHECK-NEXT: andi a0, a0, 1497; CHECK-NEXT: csrwi vxrm, 0498; CHECK-NEXT: vsetvli zero, a3, e8, mf8, ta, ma499; CHECK-NEXT: vaadd.vv v10, v8, v9500; CHECK-NEXT: beqz a0, .LBB12_2501; CHECK-NEXT: # %bb.1: # %block1502; CHECK-NEXT: csrwi vxrm, 1503; CHECK-NEXT: vaadd.vv v10, v8, v10504; CHECK-NEXT: andi a1, a1, 1505; CHECK-NEXT: csrwi vxrm, 2506; CHECK-NEXT: beqz a1, .LBB12_3507; CHECK-NEXT: .LBB12_2: # %block2508; CHECK-NEXT: csrwi vxrm, 2509; CHECK-NEXT: vaadd.vv v8, v8, v10510; CHECK-NEXT: ret511; CHECK-NEXT: .LBB12_3: # %block3512; CHECK-NEXT: vaadd.vv v8, v9, v10513; CHECK-NEXT: ret514entry:515 %a = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen 0, iXLen %vl)516 br i1 %c1, label %block1, label %block2517 518block1:519 %b = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %a, iXLen 1, iXLen %vl)520 br i1 %c2, label %block2, label %block3521 522block2:523 %c = phi <vscale x 1 x i8> [ %a, %entry ], [ %b, %block1]524 %d = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %0, <vscale x 1 x i8> %c, iXLen 2, iXLen %vl)525 ret <vscale x 1 x i8> %d526 527block3:528 %e = call <vscale x 1 x i8> @llvm.riscv.vaadd.nxv1i8.nxv1i8(<vscale x 1 x i8> poison, <vscale x 1 x i8> %1, <vscale x 1 x i8> %b, iXLen 2, iXLen %vl)529 ret <vscale x 1 x i8> %e530}531