95 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+m,+v -o - %s \3# RUN: -start-before=prologepilog | FileCheck %s4#5# These tests check that we are assigning the right stack slot to GPRs and to6# vector registers (VRs). If this test changes, make sure there is no overlap7# between slots for GPRs and VRs.8--- |9 define void @foo() #0 {10 ; CHECK-LABEL: foo:11 ; CHECK: # %bb.0: # %entry12 ; CHECK-NEXT: addi sp, sp, -3213 ; CHECK-NEXT: sw s9, 28(sp) # 4-byte Folded Spill14 ; CHECK-NEXT: csrr a1, vlenb15 ; CHECK-NEXT: slli a1, a1, 116 ; CHECK-NEXT: sub sp, sp, a117 ; CHECK-NEXT: sw a0, 8(sp) # 4-byte Folded Spill18 ; CHECK-NEXT: addi a0, sp, 1619 ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill20 ; CHECK-NEXT: csrr a0, vlenb21 ; CHECK-NEXT: slli a0, a0, 122 ; CHECK-NEXT: add sp, sp, a023 ; CHECK-NEXT: lw s9, 28(sp) # 4-byte Folded Reload24 ; CHECK-NEXT: addi sp, sp, 3225 ; CHECK-NEXT: ret26 entry:27 ret void28 }29 30 define void @rvv_clobbers_callee_save() #0 {31 ; CHECK-LABEL: rvv_clobbers_callee_save:32 ; CHECK: # %bb.0: # %entry33 ; CHECK-NEXT: addi sp, sp, -8034 ; CHECK-NEXT: sw ra, 76(sp) # 4-byte Folded Spill35 ; CHECK-NEXT: sw s0, 72(sp) # 4-byte Folded Spill36 ; CHECK-NEXT: sw s9, 68(sp) # 4-byte Folded Spill37 ; CHECK-NEXT: addi s0, sp, 8038 ; CHECK-NEXT: csrr a1, vlenb39 ; CHECK-NEXT: slli a1, a1, 140 ; CHECK-NEXT: sub sp, sp, a141 ; CHECK-NEXT: andi sp, sp, -3242 ; CHECK-NEXT: sw a0, 32(sp) # 4-byte Folded Spill43 ; CHECK-NEXT: addi a0, sp, 6444 ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill45 ; CHECK-NEXT: addi sp, s0, -8046 ; CHECK-NEXT: lw ra, 76(sp) # 4-byte Folded Reload47 ; CHECK-NEXT: lw s0, 72(sp) # 4-byte Folded Reload48 ; CHECK-NEXT: lw s9, 68(sp) # 4-byte Folded Reload49 ; CHECK-NEXT: addi sp, sp, 8050 ; CHECK-NEXT: ret51 entry:52 ret void53 }54 55 attributes #0 = { nounwind }56...57---58name: foo59alignment: 260frameInfo:61 maxAlignment: 862stack:63 - { id: 0, type: spill-slot, size: 4, alignment: 4 }64 - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }65machineFunctionInfo: {}66body: |67 bb.0.entry:68 liveins: $x10, $v30m269 70 $x25 = COPY $x1071 SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)72 VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)73 PseudoRET74 75...76---77name: rvv_clobbers_callee_save78alignment: 279frameInfo:80 maxAlignment: 881stack:82 - { id: 0, type: spill-slot, size: 4, alignment: 32 }83 - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }84machineFunctionInfo: {}85body: |86 bb.0.entry:87 liveins: $x10, $v30m288 89 $x25 = COPY $x1090 SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)91 VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)92 PseudoRET93 94...95