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1# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2# RUN: llc -mtriple=riscv64 -mattr=+m,+v -o - %s \3# RUN: -start-before=prologepilog | FileCheck %s4#5# This test checks that we are assigning the right stack slot to GPRs and to6# vector registers (VRs). If this test changes, make sure there is no overlap7# between slots for GPRs and VRs.8--- |9 define void @foo() #0 {10 ; CHECK-LABEL: foo:11 ; CHECK: # %bb.0: # %entry12 ; CHECK-NEXT: addi sp, sp, -4813 ; CHECK-NEXT: sd s9, 40(sp) # 8-byte Folded Spill14 ; CHECK-NEXT: csrr a1, vlenb15 ; CHECK-NEXT: slli a1, a1, 116 ; CHECK-NEXT: sub sp, sp, a117 ; CHECK-NEXT: sd a0, 16(sp) # 8-byte Folded Spill18 ; CHECK-NEXT: addi a0, sp, 3219 ; CHECK-NEXT: vs2r.v v30, (a0) # vscale x 16-byte Folded Spill20 ; CHECK-NEXT: csrr a0, vlenb21 ; CHECK-NEXT: slli a0, a0, 122 ; CHECK-NEXT: add sp, sp, a023 ; CHECK-NEXT: ld s9, 40(sp) # 8-byte Folded Reload24 ; CHECK-NEXT: addi sp, sp, 4825 ; CHECK-NEXT: ret26 entry:27 ret void28 }29 30 attributes #0 = { nounwind }31...32---33name: foo34alignment: 235tracksRegLiveness: true36frameInfo:37 maxAlignment: 838stack:39 - { id: 0, type: spill-slot, size: 8, alignment: 8 }40 - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }41machineFunctionInfo: {}42body: |43 bb.0.entry:44 liveins: $x10, $v30m245 46 $x25 = COPY $x1047 SD renamable $x25, %stack.0, 0 :: (store (s64) into %stack.0)48 VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)49 PseudoRET50 51...52