86 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xandesvbfhcvt \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xandesvbfhcvt \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x float> @intrinsic_vfwcvt_s.bf16_nxv1f32_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vfwcvt_s.bf16_nxv1f32_nxv1bf16:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: nds.vfwcvt.s.bf16 v9, v812; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv1f32.nxv1bf16(16 <vscale x 1 x float> poison,17 <vscale x 1 x bfloat> %0,18 iXLen %1)19 20 ret <vscale x 1 x float> %a21}22 23define <vscale x 2 x float> @intrinsic_vfwcvt_s.bf16_nxv2f32_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {24; CHECK-LABEL: intrinsic_vfwcvt_s.bf16_nxv2f32_nxv2bf16:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma27; CHECK-NEXT: nds.vfwcvt.s.bf16 v9, v828; CHECK-NEXT: vmv1r.v v8, v929; CHECK-NEXT: ret30entry:31 %a = call <vscale x 2 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv2f32.nxv2bf16(32 <vscale x 2 x float> poison,33 <vscale x 2 x bfloat> %0,34 iXLen %1)35 36 ret <vscale x 2 x float> %a37}38 39define <vscale x 4 x float> @intrinsic_vfwcvt_s.bf16_nxv4f32_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {40; CHECK-LABEL: intrinsic_vfwcvt_s.bf16_nxv4f32_nxv4bf16:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma43; CHECK-NEXT: vmv1r.v v10, v844; CHECK-NEXT: nds.vfwcvt.s.bf16 v8, v1045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 4 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv4f32.nxv4bf16(48 <vscale x 4 x float> poison,49 <vscale x 4 x bfloat> %0,50 iXLen %1)51 52 ret <vscale x 4 x float> %a53}54 55define <vscale x 8 x float> @intrinsic_vfwcvt_s.bf16_nxv8f32_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {56; CHECK-LABEL: intrinsic_vfwcvt_s.bf16_nxv8f32_nxv8bf16:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma59; CHECK-NEXT: vmv2r.v v12, v860; CHECK-NEXT: nds.vfwcvt.s.bf16 v8, v1261; CHECK-NEXT: ret62entry:63 %a = call <vscale x 8 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv8f32.nxv8bf16(64 <vscale x 8 x float> poison,65 <vscale x 8 x bfloat> %0,66 iXLen %1)67 68 ret <vscale x 8 x float> %a69}70 71define <vscale x 16 x float> @intrinsic_vfwcvt_s.bf16_nxv16f32_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {72; CHECK-LABEL: intrinsic_vfwcvt_s.bf16_nxv16f32_nxv16bf16:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma75; CHECK-NEXT: vmv4r.v v16, v876; CHECK-NEXT: nds.vfwcvt.s.bf16 v8, v1677; CHECK-NEXT: ret78entry:79 %a = call <vscale x 16 x float> @llvm.riscv.nds.vfwcvt.s.bf16.nxv16f32.nxv16bf16(80 <vscale x 16 x float> poison,81 <vscale x 16 x bfloat> %0,82 iXLen %1)83 84 ret <vscale x 16 x float> %a85}86