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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+xandesvdot \3; RUN: -verify-machineinstrs -target-abi=ilp32 | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvdot \5; RUN: -verify-machineinstrs -target-abi=lp64 | FileCheck %s6 7define <vscale x 1 x i32> @intrinsic_vd4dotsu_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv1i32_nxv4i8_nxv4i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma11; CHECK-NEXT: nds.vd4dotsu.vv v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = tail call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.nxv1i32.nxv4i8.nxv4i8(15 <vscale x 1 x i32> %0,16 <vscale x 4 x i8> %1,17 <vscale x 4 x i8> %2,18 iXLen %3, iXLen 2)19 ret <vscale x 1 x i32> %a20}21 22define <vscale x 1 x i32> @intrinsic_vd4dotsu_mask_vv_nxv1i32_nxv4i8_nxv4i8(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 1 x i1>%3, iXLen %4) nounwind {23; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv1i32_nxv4i8_nxv4i8:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma26; CHECK-NEXT: nds.vd4dotsu.vv v8, v9, v10, v0.t27; CHECK-NEXT: ret28entry:29 %a = tail call <vscale x 1 x i32> @llvm.riscv.nds.vd4dotsu.mask.nxv1i32.nxv4i8.nxv4i8(30 <vscale x 1 x i32> %0,31 <vscale x 4 x i8> %1,32 <vscale x 4 x i8> %2,33 <vscale x 1 x i1> %3,34 iXLen %4, iXLen 2)35 ret <vscale x 1 x i32> %a36}37 38define <vscale x 2 x i32> @intrinsic_vd4dotsu_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {39; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv2i32_nxv8i8_nxv8i8:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma42; CHECK-NEXT: nds.vd4dotsu.vv v8, v9, v1043; CHECK-NEXT: ret44entry:45 %a = tail call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.nxv2i32.nxv8i8.nxv8i8(46 <vscale x 2 x i32> %0,47 <vscale x 8 x i8> %1,48 <vscale x 8 x i8> %2,49 iXLen %3, iXLen 2)50 ret <vscale x 2 x i32> %a51}52 53define <vscale x 2 x i32> @intrinsic_vd4dotsu_mask_vv_nxv2i32_nxv8i8_nxv8i8(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {54; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv2i32_nxv8i8_nxv8i8:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma57; CHECK-NEXT: nds.vd4dotsu.vv v8, v9, v10, v0.t58; CHECK-NEXT: ret59entry:60 %a = tail call <vscale x 2 x i32> @llvm.riscv.nds.vd4dotsu.mask.nxv2i32.nxv8i8.nxv8i8(61 <vscale x 2 x i32> %0,62 <vscale x 8 x i8> %1,63 <vscale x 8 x i8> %2,64 <vscale x 2 x i1> %3,65 iXLen %4, iXLen 2)66 ret <vscale x 2 x i32> %a67}68 69define <vscale x 4 x i32> @intrinsic_vd4dotsu_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {70; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv4i32_nxv16i8_nxv16i8:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma73; CHECK-NEXT: nds.vd4dotsu.vv v8, v10, v1274; CHECK-NEXT: ret75entry:76 %a = tail call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.nxv4i32.nxv16i8.nxv16i8(77 <vscale x 4 x i32> %0,78 <vscale x 16 x i8> %1,79 <vscale x 16 x i8> %2,80 iXLen %3, iXLen 2)81 ret <vscale x 4 x i32> %a82}83 84define <vscale x 4 x i32> @intrinsic_vd4dotsu_mask_vv_nxv4i32_nxv16i8_nxv16i8(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {85; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv4i32_nxv16i8_nxv16i8:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma88; CHECK-NEXT: nds.vd4dotsu.vv v8, v10, v12, v0.t89; CHECK-NEXT: ret90entry:91 %a = tail call <vscale x 4 x i32> @llvm.riscv.nds.vd4dotsu.mask.nxv4i32.nxv16i8.nxv16i8(92 <vscale x 4 x i32> %0,93 <vscale x 16 x i8> %1,94 <vscale x 16 x i8> %2,95 <vscale x 4 x i1> %3,96 iXLen %4, iXLen 2)97 ret <vscale x 4 x i32> %a98}99 100define <vscale x 8 x i32> @intrinsic_vd4dotsu_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {101; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv8i32_nxv32i8_nxv32i8:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma104; CHECK-NEXT: nds.vd4dotsu.vv v8, v12, v16105; CHECK-NEXT: ret106entry:107 %a = tail call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.nxv8i32.nxv32i8.nxv32i8(108 <vscale x 8 x i32> %0,109 <vscale x 32 x i8> %1,110 <vscale x 32 x i8> %2,111 iXLen %3, iXLen 2)112 ret <vscale x 8 x i32> %a113}114 115define <vscale x 8 x i32> @intrinsic_vd4dotsu_mask_vv_nxv8i32_nxv32i8_nxv32i8(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {116; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv8i32_nxv32i8_nxv32i8:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma119; CHECK-NEXT: nds.vd4dotsu.vv v8, v12, v16, v0.t120; CHECK-NEXT: ret121entry:122 %a = tail call <vscale x 8 x i32> @llvm.riscv.nds.vd4dotsu.mask.nxv8i32.nxv32i8.nxv32i8(123 <vscale x 8 x i32> %0,124 <vscale x 32 x i8> %1,125 <vscale x 32 x i8> %2,126 <vscale x 8 x i1> %3,127 iXLen %4, iXLen 2)128 ret <vscale x 8 x i32> %a129}130 131define <vscale x 16 x i32> @intrinsic_vd4dotsu_vv_nxv16i32_nxv64i8_nxv64i8(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, iXLen %3) nounwind {132; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv16i32_nxv64i8_nxv64i8:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vl8r.v v24, (a0)135; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma136; CHECK-NEXT: nds.vd4dotsu.vv v8, v16, v24137; CHECK-NEXT: ret138entry:139 %a = tail call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.nxv16i32.nxv64i8.nxv64i8(140 <vscale x 16 x i32> %0,141 <vscale x 64 x i8> %1,142 <vscale x 64 x i8> %2,143 iXLen %3, iXLen 2)144 ret <vscale x 16 x i32> %a145}146 147define <vscale x 16 x i32> @intrinsic_vd4dotsu_mask_vv_nxv16i32_nxv64i8_nxv64i8(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {148; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv16i32_nxv64i8_nxv64i8:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: vl8r.v v24, (a0)151; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma152; CHECK-NEXT: nds.vd4dotsu.vv v8, v16, v24, v0.t153; CHECK-NEXT: ret154entry:155 %a = tail call <vscale x 16 x i32> @llvm.riscv.nds.vd4dotsu.mask.nxv16i32.nxv64i8.nxv64i8(156 <vscale x 16 x i32> %0,157 <vscale x 64 x i8> %1,158 <vscale x 64 x i8> %2,159 <vscale x 16 x i1> %3,160 iXLen %4, iXLen 2)161 ret <vscale x 16 x i32> %a162}163 164define <vscale x 1 x i64> @intrinsic_vd4dotsu_vv_nxv1i64_nxv4i16_nxv4i16(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {165; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv1i64_nxv4i16_nxv4i16:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma168; CHECK-NEXT: nds.vd4dotsu.vv v8, v9, v10169; CHECK-NEXT: ret170entry:171 %a = tail call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.nxv1i64.nxv4i16.nxv4i16(172 <vscale x 1 x i64> %0,173 <vscale x 4 x i16> %1,174 <vscale x 4 x i16> %2,175 iXLen %3, iXLen 2)176 ret <vscale x 1 x i64> %a177}178 179define <vscale x 1 x i64> @intrinsic_vd4dotsu_mask_vv_nxv1i64_nxv4i16_nxv4i16(<vscale x 1 x i64> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {180; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv1i64_nxv4i16_nxv4i16:181; CHECK: # %bb.0: # %entry182; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma183; CHECK-NEXT: nds.vd4dotsu.vv v8, v9, v10, v0.t184; CHECK-NEXT: ret185entry:186 %a = tail call <vscale x 1 x i64> @llvm.riscv.nds.vd4dotsu.mask.nxv1i64.nxv4i16.nxv4i16(187 <vscale x 1 x i64> %0,188 <vscale x 4 x i16> %1,189 <vscale x 4 x i16> %2,190 <vscale x 1 x i1> %3,191 iXLen %4, iXLen 2)192 ret <vscale x 1 x i64> %a193}194 195define <vscale x 2 x i64> @intrinsic_vd4dotsu_vv_nxv2i64_nxv8i16_nxv8i16(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {196; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv2i64_nxv8i16_nxv8i16:197; CHECK: # %bb.0: # %entry198; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma199; CHECK-NEXT: nds.vd4dotsu.vv v8, v10, v12200; CHECK-NEXT: ret201entry:202 %a = tail call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.nxv2i64.nxv8i16.nxv8i16(203 <vscale x 2 x i64> %0,204 <vscale x 8 x i16> %1,205 <vscale x 8 x i16> %2,206 iXLen %3, iXLen 2)207 ret <vscale x 2 x i64> %a208}209 210define <vscale x 2 x i64> @intrinsic_vd4dotsu_mask_vv_nxv2i64_nxv8i16_nxv8i16(<vscale x 2 x i64> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 2 x i1>%3, iXLen %4) nounwind {211; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv2i64_nxv8i16_nxv8i16:212; CHECK: # %bb.0: # %entry213; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma214; CHECK-NEXT: nds.vd4dotsu.vv v8, v10, v12, v0.t215; CHECK-NEXT: ret216entry:217 %a = tail call <vscale x 2 x i64> @llvm.riscv.nds.vd4dotsu.mask.nxv2i64.nxv8i16.nxv8i16(218 <vscale x 2 x i64> %0,219 <vscale x 8 x i16> %1,220 <vscale x 8 x i16> %2,221 <vscale x 2 x i1> %3,222 iXLen %4, iXLen 2)223 ret <vscale x 2 x i64> %a224}225 226define <vscale x 4 x i64> @intrinsic_vd4dotsu_vv_nxv4i64_nxv16i16_nxv16i16(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {227; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv4i64_nxv16i16_nxv16i16:228; CHECK: # %bb.0: # %entry229; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma230; CHECK-NEXT: nds.vd4dotsu.vv v8, v12, v16231; CHECK-NEXT: ret232entry:233 %a = tail call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.nxv4i64.nxv16i16.nxv16i16(234 <vscale x 4 x i64> %0,235 <vscale x 16 x i16> %1,236 <vscale x 16 x i16> %2,237 iXLen %3, iXLen 2)238 ret <vscale x 4 x i64> %a239}240 241define <vscale x 4 x i64> @intrinsic_vd4dotsu_mask_vv_nxv4i64_nxv16i16_nxv16i16(<vscale x 4 x i64> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {242; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv4i64_nxv16i16_nxv16i16:243; CHECK: # %bb.0: # %entry244; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma245; CHECK-NEXT: nds.vd4dotsu.vv v8, v12, v16, v0.t246; CHECK-NEXT: ret247entry:248 %a = tail call <vscale x 4 x i64> @llvm.riscv.nds.vd4dotsu.mask.nxv4i64.nxv16i16.nxv16i16(249 <vscale x 4 x i64> %0,250 <vscale x 16 x i16> %1,251 <vscale x 16 x i16> %2,252 <vscale x 4 x i1> %3,253 iXLen %4, iXLen 2)254 ret <vscale x 4 x i64> %a255}256 257define <vscale x 8 x i64> @intrinsic_vd4dotsu_vv_nxv8i64_nxv32i16_nxv32i16(<vscale x 8 x i64> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, iXLen %3) nounwind {258; CHECK-LABEL: intrinsic_vd4dotsu_vv_nxv8i64_nxv32i16_nxv32i16:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: vl8re16.v v24, (a0)261; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma262; CHECK-NEXT: nds.vd4dotsu.vv v8, v16, v24263; CHECK-NEXT: ret264entry:265 %a = tail call <vscale x 8 x i64> @llvm.riscv.nds.vd4dotsu.nxv8i64.nxv32i16.nxv32i16(266 <vscale x 8 x i64> %0,267 <vscale x 32 x i16> %1,268 <vscale x 32 x i16> %2,269 iXLen %3, iXLen 2)270 ret <vscale x 8 x i64> %a271}272 273define <vscale x 8 x i64> @intrinsic_vd4dotsu_mask_vv_nxv8i64_nxv32i16_nxv32i16(<vscale x 8 x i64> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {274; CHECK-LABEL: intrinsic_vd4dotsu_mask_vv_nxv8i64_nxv32i16_nxv32i16:275; CHECK: # %bb.0: # %entry276; CHECK-NEXT: vl8re16.v v24, (a0)277; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma278; CHECK-NEXT: nds.vd4dotsu.vv v8, v16, v24, v0.t279; CHECK-NEXT: ret280entry:281 %a = tail call <vscale x 8 x i64> @llvm.riscv.nds.vd4dotsu.mask.nxv8i64.nxv32i16.nxv32i16(282 <vscale x 8 x i64> %0,283 <vscale x 32 x i16> %1,284 <vscale x 32 x i16> %2,285 <vscale x 8 x i1> %3,286 iXLen %4, iXLen 2)287 ret <vscale x 8 x i64> %a288}289