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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+xandesvpackfph \3; RUN: -verify-machineinstrs -target-abi=ilp32f | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvpackfph \5; RUN: -verify-machineinstrs -target-abi=lp64f | FileCheck %s6 7define <vscale x 1 x half> @intrinsic_vfpmadb_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, float %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv1f16_nxv1f16_f32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: fsrmi a1, 011; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma12; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v813; CHECK-NEXT: fsrm a114; CHECK-NEXT: ret15entry:16 %a = tail call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32(17 <vscale x 1 x half> poison,18 <vscale x 1 x half> %0,19 float %1, iXLen 0, iXLen %2)20 21 ret <vscale x 1 x half> %a22}23 24define <vscale x 1 x half> @intrinsic_vfpmadb_mask_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv1f16_nxv1f16_f32:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: fsrmi a1, 028; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu29; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v9, v0.t30; CHECK-NEXT: fsrm a131; CHECK-NEXT: ret32entry:33 %a = tail call <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32(34 <vscale x 1 x half> %0,35 <vscale x 1 x half> %1,36 float %2,37 <vscale x 1 x i1> %3,38 iXLen 0, iXLen %4, iXLen 1)39 40 ret <vscale x 1 x half> %a41}42 43define <vscale x 2 x half> @intrinsic_vfpmadb_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, float %1, iXLen %2) nounwind {44; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv2f16_nxv2f16_f32:45; CHECK: # %bb.0: # %entry46; CHECK-NEXT: fsrmi a1, 047; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma48; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v849; CHECK-NEXT: fsrm a150; CHECK-NEXT: ret51entry:52 %a = tail call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32(53 <vscale x 2 x half> poison,54 <vscale x 2 x half> %0,55 float %1, iXLen 0, iXLen %2)56 57 ret <vscale x 2 x half> %a58}59 60define <vscale x 2 x half> @intrinsic_vfpmadb_mask_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {61; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv2f16_nxv2f16_f32:62; CHECK: # %bb.0: # %entry63; CHECK-NEXT: fsrmi a1, 064; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu65; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v9, v0.t66; CHECK-NEXT: fsrm a167; CHECK-NEXT: ret68entry:69 %a = tail call <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32(70 <vscale x 2 x half> %0,71 <vscale x 2 x half> %1,72 float %2,73 <vscale x 2 x i1> %3,74 iXLen 0, iXLen %4, iXLen 1)75 76 ret <vscale x 2 x half> %a77}78 79define <vscale x 4 x half> @intrinsic_vfpmadb_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, float %1, iXLen %2) nounwind {80; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv4f16_nxv4f16_f32:81; CHECK: # %bb.0: # %entry82; CHECK-NEXT: fsrmi a1, 083; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma84; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v885; CHECK-NEXT: fsrm a186; CHECK-NEXT: ret87entry:88 %a = tail call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32(89 <vscale x 4 x half> poison,90 <vscale x 4 x half> %0,91 float %1, iXLen 0, iXLen %2)92 93 ret <vscale x 4 x half> %a94}95 96define <vscale x 4 x half> @intrinsic_vfpmadb_mask_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {97; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv4f16_nxv4f16_f32:98; CHECK: # %bb.0: # %entry99; CHECK-NEXT: fsrmi a1, 0100; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu101; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v9, v0.t102; CHECK-NEXT: fsrm a1103; CHECK-NEXT: ret104entry:105 %a = tail call <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32(106 <vscale x 4 x half> %0,107 <vscale x 4 x half> %1,108 float %2,109 <vscale x 4 x i1> %3,110 iXLen 0, iXLen %4, iXLen 1)111 112 ret <vscale x 4 x half> %a113}114 115define <vscale x 8 x half> @intrinsic_vfpmadb_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, float %1, iXLen %2) nounwind {116; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv8f16_nxv8f16_f32:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: fsrmi a1, 0119; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma120; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v8121; CHECK-NEXT: fsrm a1122; CHECK-NEXT: ret123entry:124 %a = tail call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32(125 <vscale x 8 x half> poison,126 <vscale x 8 x half> %0,127 float %1, iXLen 0, iXLen %2)128 129 ret <vscale x 8 x half> %a130}131 132define <vscale x 8 x half> @intrinsic_vfpmadb_mask_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {133; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv8f16_nxv8f16_f32:134; CHECK: # %bb.0: # %entry135; CHECK-NEXT: fsrmi a1, 0136; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu137; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v10, v0.t138; CHECK-NEXT: fsrm a1139; CHECK-NEXT: ret140entry:141 %a = tail call <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.mask.nxv8f16.f32(142 <vscale x 8 x half> %0,143 <vscale x 8 x half> %1,144 float %2,145 <vscale x 8 x i1> %3,146 iXLen 0, iXLen %4, iXLen 1)147 148 ret <vscale x 8 x half> %a149}150 151define <vscale x 16 x half> @intrinsic_vfpmadb_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, float %1, iXLen %2) nounwind {152; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv16f16_nxv16f16_f32:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: fsrmi a1, 0155; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma156; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v8157; CHECK-NEXT: fsrm a1158; CHECK-NEXT: ret159entry:160 %a = tail call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32(161 <vscale x 16 x half> poison,162 <vscale x 16 x half> %0,163 float %1, iXLen 0, iXLen %2)164 165 ret <vscale x 16 x half> %a166}167 168define <vscale x 16 x half> @intrinsic_vfpmadb_mask_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {169; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv16f16_nxv16f16_f32:170; CHECK: # %bb.0: # %entry171; CHECK-NEXT: fsrmi a1, 0172; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu173; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v12, v0.t174; CHECK-NEXT: fsrm a1175; CHECK-NEXT: ret176entry:177 %a = tail call <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.mask.nxv16f16.f32(178 <vscale x 16 x half> %0,179 <vscale x 16 x half> %1,180 float %2,181 <vscale x 16 x i1> %3,182 iXLen 0, iXLen %4, iXLen 1)183 184 ret <vscale x 16 x half> %a185}186 187define <vscale x 32 x half> @intrinsic_vfpmadb_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, float %1, iXLen %2) nounwind {188; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv32f16_nxv32f16_f32:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: fsrmi a1, 0191; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma192; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v8193; CHECK-NEXT: fsrm a1194; CHECK-NEXT: ret195entry:196 %a = tail call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32(197 <vscale x 32 x half> poison,198 <vscale x 32 x half> %0,199 float %1, iXLen 0, iXLen %2)200 201 ret <vscale x 32 x half> %a202}203 204define <vscale x 32 x half> @intrinsic_vfpmadb_mask_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {205; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv32f16_nxv32f16_f32:206; CHECK: # %bb.0: # %entry207; CHECK-NEXT: fsrmi a1, 0208; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu209; CHECK-NEXT: nds.vfpmadb.vf v8, fa0, v16, v0.t210; CHECK-NEXT: fsrm a1211; CHECK-NEXT: ret212entry:213 %a = tail call <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.mask.nxv32f16.f32(214 <vscale x 32 x half> %0,215 <vscale x 32 x half> %1,216 float %2,217 <vscale x 32 x i1> %3,218 iXLen 0, iXLen %4, iXLen 1)219 220 ret <vscale x 32 x half> %a221}222