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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+xandesvsintload \3; RUN: -verify-machineinstrs -target-abi=ilp32 | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvsintload \5; RUN: -verify-machineinstrs -target-abi=lp64 | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_nds_vln_v_nxv1i8_nxv1i8(ptr %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_nds_vln_v_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: nds.vln8.v v8, (a0)12; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8(15 <vscale x 1 x i8> poison,16 ptr %0,17 iXLen %1)18 19 ret <vscale x 1 x i8> %a20}21 22define <vscale x 1 x i8> @intrinsic_nds_vln_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {23; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv1i8_nxv1i8:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu26; CHECK-NEXT: nds.vln8.v v8, (a0), v0.t27; CHECK-NEXT: ret28entry:29 %a = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8(30 <vscale x 1 x i8> %0,31 ptr %1,32 <vscale x 1 x i1> %2,33 iXLen %3, iXLen 1)34 35 ret <vscale x 1 x i8> %a36}37 38define <vscale x 2 x i8> @intrinsic_nds_vln_v_nxv2i8_nxv2i8(ptr %0, iXLen %1) nounwind {39; CHECK-LABEL: intrinsic_nds_vln_v_nxv2i8_nxv2i8:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma42; CHECK-NEXT: nds.vln8.v v8, (a0)43; CHECK-NEXT: ret44entry:45 %a = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8(46 <vscale x 2 x i8> poison,47 ptr %0,48 iXLen %1)49 50 ret <vscale x 2 x i8> %a51}52 53define <vscale x 2 x i8> @intrinsic_nds_vln_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {54; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv2i8_nxv2i8:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu57; CHECK-NEXT: nds.vln8.v v8, (a0), v0.t58; CHECK-NEXT: ret59entry:60 %a = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8(61 <vscale x 2 x i8> %0,62 ptr %1,63 <vscale x 2 x i1> %2,64 iXLen %3, iXLen 1)65 66 ret <vscale x 2 x i8> %a67}68 69define <vscale x 4 x i8> @intrinsic_nds_vln_v_nxv4i8_nxv4i8(ptr %0, iXLen %1) nounwind {70; CHECK-LABEL: intrinsic_nds_vln_v_nxv4i8_nxv4i8:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma73; CHECK-NEXT: nds.vln8.v v8, (a0)74; CHECK-NEXT: ret75entry:76 %a = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8(77 <vscale x 4 x i8> poison,78 ptr %0,79 iXLen %1)80 81 ret <vscale x 4 x i8> %a82}83 84define <vscale x 4 x i8> @intrinsic_nds_vln_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {85; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv4i8_nxv4i8:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu88; CHECK-NEXT: nds.vln8.v v8, (a0), v0.t89; CHECK-NEXT: ret90entry:91 %a = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8(92 <vscale x 4 x i8> %0,93 ptr %1,94 <vscale x 4 x i1> %2,95 iXLen %3, iXLen 1)96 97 ret <vscale x 4 x i8> %a98}99 100define <vscale x 8 x i8> @intrinsic_nds_vln_v_nxv8i8_nxv8i8(ptr %0, iXLen %1) nounwind {101; CHECK-LABEL: intrinsic_nds_vln_v_nxv8i8_nxv8i8:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma104; CHECK-NEXT: nds.vln8.v v8, (a0)105; CHECK-NEXT: ret106entry:107 %a = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8(108 <vscale x 8 x i8> poison,109 ptr %0,110 iXLen %1)111 112 ret <vscale x 8 x i8> %a113}114 115define <vscale x 8 x i8> @intrinsic_nds_vln_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {116; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv8i8_nxv8i8:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu119; CHECK-NEXT: nds.vln8.v v8, (a0), v0.t120; CHECK-NEXT: ret121entry:122 %a = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8(123 <vscale x 8 x i8> %0,124 ptr %1,125 <vscale x 8 x i1> %2,126 iXLen %3, iXLen 1)127 128 ret <vscale x 8 x i8> %a129}130 131define <vscale x 16 x i8> @intrinsic_nds_vln_v_nxv16i8_nxv16i8(ptr %0, iXLen %1) nounwind {132; CHECK-LABEL: intrinsic_nds_vln_v_nxv16i8_nxv16i8:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma135; CHECK-NEXT: nds.vln8.v v8, (a0)136; CHECK-NEXT: ret137entry:138 %a = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8(139 <vscale x 16 x i8> poison,140 ptr %0,141 iXLen %1)142 143 ret <vscale x 16 x i8> %a144}145 146define <vscale x 16 x i8> @intrinsic_nds_vln_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {147; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv16i8_nxv16i8:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu150; CHECK-NEXT: nds.vln8.v v8, (a0), v0.t151; CHECK-NEXT: ret152entry:153 %a = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8(154 <vscale x 16 x i8> %0,155 ptr %1,156 <vscale x 16 x i1> %2,157 iXLen %3, iXLen 1)158 159 ret <vscale x 16 x i8> %a160}161 162define <vscale x 32 x i8> @intrinsic_nds_vln_v_nxv32i8_nxv32i8(ptr %0, iXLen %1) nounwind {163; CHECK-LABEL: intrinsic_nds_vln_v_nxv32i8_nxv32i8:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma166; CHECK-NEXT: nds.vln8.v v8, (a0)167; CHECK-NEXT: ret168entry:169 %a = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8(170 <vscale x 32 x i8> poison,171 ptr %0,172 iXLen %1)173 174 ret <vscale x 32 x i8> %a175}176 177define <vscale x 32 x i8> @intrinsic_nds_vln_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {178; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv32i8_nxv32i8:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu181; CHECK-NEXT: nds.vln8.v v8, (a0), v0.t182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8(185 <vscale x 32 x i8> %0,186 ptr %1,187 <vscale x 32 x i1> %2,188 iXLen %3, iXLen 1)189 190 ret <vscale x 32 x i8> %a191}192 193define <vscale x 64 x i8> @intrinsic_nds_vln_v_nxv64i8_nxv64i8(ptr %0, iXLen %1) nounwind {194; CHECK-LABEL: intrinsic_nds_vln_v_nxv64i8_nxv64i8:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma197; CHECK-NEXT: nds.vln8.v v8, (a0)198; CHECK-NEXT: ret199entry:200 %a = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8(201 <vscale x 64 x i8> poison,202 ptr %0,203 iXLen %1)204 205 ret <vscale x 64 x i8> %a206}207 208define <vscale x 64 x i8> @intrinsic_nds_vln_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {209; CHECK-LABEL: intrinsic_nds_vln_mask_v_nxv64i8_nxv64i8:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu212; CHECK-NEXT: nds.vln8.v v8, (a0), v0.t213; CHECK-NEXT: ret214entry:215 %a = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8(216 <vscale x 64 x i8> %0,217 ptr %1,218 <vscale x 64 x i1> %2,219 iXLen %3, iXLen 1)220 221 ret <vscale x 64 x i8> %a222}223