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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp,+zvfh \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp,+zvfh \5; RUN: -verify-machineinstrs | FileCheck %s6 7define void @test_sf_vc_x_se_e8mf8(i8 zeroext %rs1, iXLen %vl) {8; CHECK-LABEL: test_sf_vc_x_se_e8mf8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: sf.vc.x 3, 31, 31, a012; CHECK-NEXT: ret13entry:14 tail call void @llvm.riscv.sf.vc.x.se.e8mf8.iXLen.i8.iXLen(iXLen 3, iXLen 31, iXLen 31, i8 %rs1, iXLen 8, iXLen 5, iXLen %vl)15 ret void16}17 18define void @test_sf_vc_x_se_e8mf4(i8 zeroext %rs1, iXLen %vl) {19; CHECK-LABEL: test_sf_vc_x_se_e8mf4:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma22; CHECK-NEXT: sf.vc.x 3, 31, 31, a023; CHECK-NEXT: ret24entry:25 tail call void @llvm.riscv.sf.vc.x.se.e8mf4.iXLen.i8.iXLen(iXLen 3, iXLen 31, iXLen 31, i8 %rs1, iXLen 8, iXLen 6, iXLen %vl)26 ret void27}28 29define void @test_sf_vc_x_se_e8mf2(i8 zeroext %rs1, iXLen %vl) {30; CHECK-LABEL: test_sf_vc_x_se_e8mf2:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma33; CHECK-NEXT: sf.vc.x 3, 31, 31, a034; CHECK-NEXT: ret35entry:36 tail call void @llvm.riscv.sf.vc.x.se.e8mf2.iXLen.i8.iXLen(iXLen 3, iXLen 31, iXLen 31, i8 %rs1, iXLen 8, iXLen 7, iXLen %vl)37 ret void38}39 40define void @test_sf_vc_x_se_e8m1(i8 zeroext %rs1, iXLen %vl) {41; CHECK-LABEL: test_sf_vc_x_se_e8m1:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma44; CHECK-NEXT: sf.vc.x 3, 31, 31, a045; CHECK-NEXT: ret46entry:47 tail call void @llvm.riscv.sf.vc.x.se.e8m1.iXLen.i8.iXLen(iXLen 3, iXLen 31, iXLen 31, i8 %rs1, iXLen 8, iXLen 0, iXLen %vl)48 ret void49}50 51define void @test_sf_vc_x_se_e8m2(i8 zeroext %rs1, iXLen %vl) {52; CHECK-LABEL: test_sf_vc_x_se_e8m2:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma55; CHECK-NEXT: sf.vc.x 3, 31, 31, a056; CHECK-NEXT: ret57entry:58 tail call void @llvm.riscv.sf.vc.x.se.e8m2.iXLen.i8.iXLen(iXLen 3, iXLen 31, iXLen 31, i8 %rs1, iXLen 8, iXLen 1, iXLen %vl)59 ret void60}61 62define void @test_sf_vc_x_se_e8m4(i8 zeroext %rs1, iXLen %vl) {63; CHECK-LABEL: test_sf_vc_x_se_e8m4:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma66; CHECK-NEXT: sf.vc.x 3, 31, 31, a067; CHECK-NEXT: ret68entry:69 tail call void @llvm.riscv.sf.vc.x.se.e8m4.iXLen.i8.iXLen(iXLen 3, iXLen 31, iXLen 31, i8 %rs1, iXLen 8, iXLen 2, iXLen %vl)70 ret void71}72 73define void @test_sf_vc_x_se_e8m8(i8 zeroext %rs1, iXLen %vl) {74; CHECK-LABEL: test_sf_vc_x_se_e8m8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma77; CHECK-NEXT: sf.vc.x 3, 31, 31, a078; CHECK-NEXT: ret79entry:80 tail call void @llvm.riscv.sf.vc.x.se.e8m8.iXLen.i8.iXLen(iXLen 3, iXLen 31, iXLen 31, i8 %rs1, iXLen 8, iXLen 3, iXLen %vl)81 ret void82}83 84define void @test_sf_vc_x_se_e16mf4(i16 zeroext %rs1, iXLen %vl) {85; CHECK-LABEL: test_sf_vc_x_se_e16mf4:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma88; CHECK-NEXT: sf.vc.x 3, 31, 31, a089; CHECK-NEXT: ret90entry:91 tail call void @llvm.riscv.sf.vc.x.se.e16mf4.iXLen.i16.iXLen(iXLen 3, iXLen 31, iXLen 31, i16 %rs1, iXLen 16, iXLen 6, iXLen %vl)92 ret void93}94 95define void @test_sf_vc_x_se_e16mf2(i16 zeroext %rs1, iXLen %vl) {96; CHECK-LABEL: test_sf_vc_x_se_e16mf2:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma99; CHECK-NEXT: sf.vc.x 3, 31, 31, a0100; CHECK-NEXT: ret101entry:102 tail call void @llvm.riscv.sf.vc.x.se.e16mf2.iXLen.i16.iXLen(iXLen 3, iXLen 31, iXLen 31, i16 %rs1, iXLen 16, iXLen 7, iXLen %vl)103 ret void104}105 106define void @test_sf_vc_x_se_e16m1(i16 zeroext %rs1, iXLen %vl) {107; CHECK-LABEL: test_sf_vc_x_se_e16m1:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma110; CHECK-NEXT: sf.vc.x 3, 31, 31, a0111; CHECK-NEXT: ret112entry:113 tail call void @llvm.riscv.sf.vc.x.se.e16m1.iXLen.i16.iXLen(iXLen 3, iXLen 31, iXLen 31, i16 %rs1, iXLen 16, iXLen 0, iXLen %vl)114 ret void115}116 117define void @test_sf_vc_x_se_e16m2(i16 zeroext %rs1, iXLen %vl) {118; CHECK-LABEL: test_sf_vc_x_se_e16m2:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma121; CHECK-NEXT: sf.vc.x 3, 31, 31, a0122; CHECK-NEXT: ret123entry:124 tail call void @llvm.riscv.sf.vc.x.se.e16m2.iXLen.i16.iXLen(iXLen 3, iXLen 31, iXLen 31, i16 %rs1, iXLen 16, iXLen 1, iXLen %vl)125 ret void126}127 128define void @test_sf_vc_x_se_e16m4(i16 zeroext %rs1, iXLen %vl) {129; CHECK-LABEL: test_sf_vc_x_se_e16m4:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma132; CHECK-NEXT: sf.vc.x 3, 31, 31, a0133; CHECK-NEXT: ret134entry:135 tail call void @llvm.riscv.sf.vc.x.se.e16m4.iXLen.i16.iXLen(iXLen 3, iXLen 31, iXLen 31, i16 %rs1, iXLen 16, iXLen 2, iXLen %vl)136 ret void137}138 139define void @test_sf_vc_x_se_e16m8(i16 zeroext %rs1, iXLen %vl) {140; CHECK-LABEL: test_sf_vc_x_se_e16m8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma143; CHECK-NEXT: sf.vc.x 3, 31, 31, a0144; CHECK-NEXT: ret145entry:146 tail call void @llvm.riscv.sf.vc.x.se.e16m8.iXLen.i16.iXLen(iXLen 3, iXLen 31, iXLen 31, i16 %rs1, iXLen 16, iXLen 3, iXLen %vl)147 ret void148}149 150define void @test_sf_vc_x_se_e32mf2(i32 signext %rs1, iXLen %vl) {151; CHECK-LABEL: test_sf_vc_x_se_e32mf2:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma154; CHECK-NEXT: sf.vc.x 3, 31, 31, a0155; CHECK-NEXT: ret156entry:157 tail call void @llvm.riscv.sf.vc.x.se.e32mf2.iXLen.i32.iXLen(iXLen 3, iXLen 31, iXLen 31, i32 %rs1, iXLen 32, iXLen 7, iXLen %vl)158 ret void159}160 161define void @test_sf_vc_x_se_e32m1(i32 signext %rs1, iXLen %vl) {162; CHECK-LABEL: test_sf_vc_x_se_e32m1:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma165; CHECK-NEXT: sf.vc.x 3, 31, 31, a0166; CHECK-NEXT: ret167entry:168 tail call void @llvm.riscv.sf.vc.x.se.e32m1.iXLen.i32.iXLen(iXLen 3, iXLen 31, iXLen 31, i32 %rs1, iXLen 32, iXLen 0, iXLen %vl)169 ret void170}171 172define void @test_sf_vc_x_se_e32m2(i32 signext %rs1, iXLen %vl) {173; CHECK-LABEL: test_sf_vc_x_se_e32m2:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma176; CHECK-NEXT: sf.vc.x 3, 31, 31, a0177; CHECK-NEXT: ret178entry:179 tail call void @llvm.riscv.sf.vc.x.se.e32m2.iXLen.i32.iXLen(iXLen 3, iXLen 31, iXLen 31, i32 %rs1, iXLen 32, iXLen 1, iXLen %vl)180 ret void181}182 183define void @test_sf_vc_x_se_e32m4(i32 signext %rs1, iXLen %vl) {184; CHECK-LABEL: test_sf_vc_x_se_e32m4:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma187; CHECK-NEXT: sf.vc.x 3, 31, 31, a0188; CHECK-NEXT: ret189entry:190 tail call void @llvm.riscv.sf.vc.x.se.e32m4.iXLen.i32.iXLen(iXLen 3, iXLen 31, iXLen 31, i32 %rs1, iXLen 32, iXLen 2, iXLen %vl)191 ret void192}193 194define void @test_sf_vc_x_se_e32m8(i32 signext %rs1, iXLen %vl) {195; CHECK-LABEL: test_sf_vc_x_se_e32m8:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma198; CHECK-NEXT: sf.vc.x 3, 31, 31, a0199; CHECK-NEXT: ret200entry:201 tail call void @llvm.riscv.sf.vc.x.se.e32m8.iXLen.i32.iXLen(iXLen 3, iXLen 31, iXLen 31, i32 %rs1, iXLen 32, iXLen 3, iXLen %vl)202 ret void203}204 205define <vscale x 1 x i8> @test_sf_vc_v_x_se_e8mf8(i8 zeroext %rs1, iXLen %vl) {206; CHECK-LABEL: test_sf_vc_v_x_se_e8mf8:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma209; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0210; CHECK-NEXT: ret211entry:212 %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.x.se.nxv1i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)213 ret <vscale x 1 x i8> %0214}215 216define <vscale x 2 x i8> @test_sf_vc_v_x_se_e8mf4(i8 zeroext %rs1, iXLen %vl) {217; CHECK-LABEL: test_sf_vc_v_x_se_e8mf4:218; CHECK: # %bb.0: # %entry219; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma220; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0221; CHECK-NEXT: ret222entry:223 %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.x.se.nxv2i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)224 ret <vscale x 2 x i8> %0225}226 227define <vscale x 4 x i8> @test_sf_vc_v_x_se_e8mf2(i8 zeroext %rs1, iXLen %vl) {228; CHECK-LABEL: test_sf_vc_v_x_se_e8mf2:229; CHECK: # %bb.0: # %entry230; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma231; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0232; CHECK-NEXT: ret233entry:234 %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.x.se.nxv4i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)235 ret <vscale x 4 x i8> %0236}237 238define <vscale x 8 x i8> @test_sf_vc_v_x_se_e8m1(i8 zeroext %rs1, iXLen %vl) {239; CHECK-LABEL: test_sf_vc_v_x_se_e8m1:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma242; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0243; CHECK-NEXT: ret244entry:245 %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.x.se.nxv8i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)246 ret <vscale x 8 x i8> %0247}248 249define <vscale x 16 x i8> @test_sf_vc_v_x_se_e8m2(i8 zeroext %rs1, iXLen %vl) {250; CHECK-LABEL: test_sf_vc_v_x_se_e8m2:251; CHECK: # %bb.0: # %entry252; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma253; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0254; CHECK-NEXT: ret255entry:256 %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.x.se.nxv16i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)257 ret <vscale x 16 x i8> %0258}259 260define <vscale x 32 x i8> @test_sf_vc_v_x_se_e8m4(i8 zeroext %rs1, iXLen %vl) {261; CHECK-LABEL: test_sf_vc_v_x_se_e8m4:262; CHECK: # %bb.0: # %entry263; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma264; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0265; CHECK-NEXT: ret266entry:267 %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.x.se.nxv32i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)268 ret <vscale x 32 x i8> %0269}270 271define <vscale x 64 x i8> @test_sf_vc_v_x_se_e8m8(i8 zeroext %rs1, iXLen %vl) {272; CHECK-LABEL: test_sf_vc_v_x_se_e8m8:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma275; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0276; CHECK-NEXT: ret277entry:278 %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.x.se.nxv64i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)279 ret <vscale x 64 x i8> %0280}281 282define <vscale x 1 x i16> @test_sf_vc_v_x_se_e16mf4(i16 zeroext %rs1, iXLen %vl) {283; CHECK-LABEL: test_sf_vc_v_x_se_e16mf4:284; CHECK: # %bb.0: # %entry285; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma286; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0287; CHECK-NEXT: ret288entry:289 %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.x.se.nxv1i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)290 ret <vscale x 1 x i16> %0291}292 293define <vscale x 2 x i16> @test_sf_vc_v_x_se_e16mf2(i16 zeroext %rs1, iXLen %vl) {294; CHECK-LABEL: test_sf_vc_v_x_se_e16mf2:295; CHECK: # %bb.0: # %entry296; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma297; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0298; CHECK-NEXT: ret299entry:300 %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.x.se.nxv2i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)301 ret <vscale x 2 x i16> %0302}303 304define <vscale x 4 x i16> @test_sf_vc_v_x_se_e16m1(i16 zeroext %rs1, iXLen %vl) {305; CHECK-LABEL: test_sf_vc_v_x_se_e16m1:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma308; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0309; CHECK-NEXT: ret310entry:311 %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.x.se.nxv4i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)312 ret <vscale x 4 x i16> %0313}314 315define <vscale x 8 x i16> @test_sf_vc_v_x_se_e16m2(i16 zeroext %rs1, iXLen %vl) {316; CHECK-LABEL: test_sf_vc_v_x_se_e16m2:317; CHECK: # %bb.0: # %entry318; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma319; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0320; CHECK-NEXT: ret321entry:322 %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.x.se.nxv8i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)323 ret <vscale x 8 x i16> %0324}325 326define <vscale x 16 x i16> @test_sf_vc_v_x_se_e16m4(i16 zeroext %rs1, iXLen %vl) {327; CHECK-LABEL: test_sf_vc_v_x_se_e16m4:328; CHECK: # %bb.0: # %entry329; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma330; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0331; CHECK-NEXT: ret332entry:333 %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.x.se.nxv16i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)334 ret <vscale x 16 x i16> %0335}336 337define <vscale x 32 x i16> @test_sf_vc_v_x_se_e16m8(i16 zeroext %rs1, iXLen %vl) {338; CHECK-LABEL: test_sf_vc_v_x_se_e16m8:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma341; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0342; CHECK-NEXT: ret343entry:344 %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.x.se.nxv32i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)345 ret <vscale x 32 x i16> %0346}347 348define <vscale x 1 x i32> @test_sf_vc_v_x_se_e32mf2(i32 signext %rs1, iXLen %vl) {349; CHECK-LABEL: test_sf_vc_v_x_se_e32mf2:350; CHECK: # %bb.0: # %entry351; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma352; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0353; CHECK-NEXT: ret354entry:355 %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.x.se.nxv1i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)356 ret <vscale x 1 x i32> %0357}358 359define <vscale x 2 x i32> @test_sf_vc_v_x_se_e32m1(i32 signext %rs1, iXLen %vl) {360; CHECK-LABEL: test_sf_vc_v_x_se_e32m1:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma363; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0364; CHECK-NEXT: ret365entry:366 %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.x.se.nxv2i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)367 ret <vscale x 2 x i32> %0368}369 370define <vscale x 4 x i32> @test_sf_vc_v_x_se_e32m2(i32 signext %rs1, iXLen %vl) {371; CHECK-LABEL: test_sf_vc_v_x_se_e32m2:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma374; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0375; CHECK-NEXT: ret376entry:377 %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.x.se.nxv4i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)378 ret <vscale x 4 x i32> %0379}380 381define <vscale x 8 x i32> @test_sf_vc_v_x_se_e32m4(i32 signext %rs1, iXLen %vl) {382; CHECK-LABEL: test_sf_vc_v_x_se_e32m4:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma385; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0386; CHECK-NEXT: ret387entry:388 %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.x.se.nxv8i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)389 ret <vscale x 8 x i32> %0390}391 392define <vscale x 16 x i32> @test_sf_vc_v_x_se_e32m8(i32 signext %rs1, iXLen %vl) {393; CHECK-LABEL: test_sf_vc_v_x_se_e32m8:394; CHECK: # %bb.0: # %entry395; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma396; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0397; CHECK-NEXT: ret398entry:399 %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.x.se.nxv16i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)400 ret <vscale x 16 x i32> %0401}402 403define <vscale x 1 x i8> @test_sf_vc_v_x_e8mf8(i8 zeroext %rs1, iXLen %vl) {404; CHECK-LABEL: test_sf_vc_v_x_e8mf8:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma407; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0408; CHECK-NEXT: ret409entry:410 %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.x.nxv1i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)411 ret <vscale x 1 x i8> %0412}413 414define <vscale x 2 x i8> @test_sf_vc_v_x_e8mf4(i8 zeroext %rs1, iXLen %vl) {415; CHECK-LABEL: test_sf_vc_v_x_e8mf4:416; CHECK: # %bb.0: # %entry417; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma418; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0419; CHECK-NEXT: ret420entry:421 %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.x.nxv2i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)422 ret <vscale x 2 x i8> %0423}424 425define <vscale x 4 x i8> @test_sf_vc_v_x_e8mf2(i8 zeroext %rs1, iXLen %vl) {426; CHECK-LABEL: test_sf_vc_v_x_e8mf2:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma429; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0430; CHECK-NEXT: ret431entry:432 %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.x.nxv4i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)433 ret <vscale x 4 x i8> %0434}435 436define <vscale x 8 x i8> @test_sf_vc_v_x_e8m1(i8 zeroext %rs1, iXLen %vl) {437; CHECK-LABEL: test_sf_vc_v_x_e8m1:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma440; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0441; CHECK-NEXT: ret442entry:443 %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.x.nxv8i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)444 ret <vscale x 8 x i8> %0445}446 447define <vscale x 16 x i8> @test_sf_vc_v_x_e8m2(i8 zeroext %rs1, iXLen %vl) {448; CHECK-LABEL: test_sf_vc_v_x_e8m2:449; CHECK: # %bb.0: # %entry450; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma451; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0452; CHECK-NEXT: ret453entry:454 %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.x.nxv16i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)455 ret <vscale x 16 x i8> %0456}457 458define <vscale x 32 x i8> @test_sf_vc_v_x_e8m4(i8 zeroext %rs1, iXLen %vl) {459; CHECK-LABEL: test_sf_vc_v_x_e8m4:460; CHECK: # %bb.0: # %entry461; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma462; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0463; CHECK-NEXT: ret464entry:465 %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.x.nxv32i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)466 ret <vscale x 32 x i8> %0467}468 469define <vscale x 64 x i8> @test_sf_vc_v_x_e8m8(i8 zeroext %rs1, iXLen %vl) {470; CHECK-LABEL: test_sf_vc_v_x_e8m8:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma473; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0474; CHECK-NEXT: ret475entry:476 %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.x.nxv64i8.iXLen.i8.iXLen(iXLen 3, iXLen 31, i8 %rs1, iXLen %vl)477 ret <vscale x 64 x i8> %0478}479 480define <vscale x 1 x i16> @test_sf_vc_v_x_e16mf4(i16 zeroext %rs1, iXLen %vl) {481; CHECK-LABEL: test_sf_vc_v_x_e16mf4:482; CHECK: # %bb.0: # %entry483; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma484; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0485; CHECK-NEXT: ret486entry:487 %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.x.nxv1i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)488 ret <vscale x 1 x i16> %0489}490 491define <vscale x 2 x i16> @test_sf_vc_v_x_e16mf2(i16 zeroext %rs1, iXLen %vl) {492; CHECK-LABEL: test_sf_vc_v_x_e16mf2:493; CHECK: # %bb.0: # %entry494; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma495; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0496; CHECK-NEXT: ret497entry:498 %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.x.nxv2i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)499 ret <vscale x 2 x i16> %0500}501 502define <vscale x 4 x i16> @test_sf_vc_v_x_e16m1(i16 zeroext %rs1, iXLen %vl) {503; CHECK-LABEL: test_sf_vc_v_x_e16m1:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma506; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0507; CHECK-NEXT: ret508entry:509 %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.x.nxv4i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)510 ret <vscale x 4 x i16> %0511}512 513define <vscale x 8 x i16> @test_sf_vc_v_x_e16m2(i16 zeroext %rs1, iXLen %vl) {514; CHECK-LABEL: test_sf_vc_v_x_e16m2:515; CHECK: # %bb.0: # %entry516; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma517; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0518; CHECK-NEXT: ret519entry:520 %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.x.nxv8i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)521 ret <vscale x 8 x i16> %0522}523 524define <vscale x 16 x i16> @test_sf_vc_v_x_e16m4(i16 zeroext %rs1, iXLen %vl) {525; CHECK-LABEL: test_sf_vc_v_x_e16m4:526; CHECK: # %bb.0: # %entry527; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma528; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0529; CHECK-NEXT: ret530entry:531 %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.x.nxv16i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)532 ret <vscale x 16 x i16> %0533}534 535define <vscale x 32 x i16> @test_sf_vc_v_x_e16m8(i16 zeroext %rs1, iXLen %vl) {536; CHECK-LABEL: test_sf_vc_v_x_e16m8:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma539; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0540; CHECK-NEXT: ret541entry:542 %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.x.nxv32i16.iXLen.i16.iXLen(iXLen 3, iXLen 31, i16 %rs1, iXLen %vl)543 ret <vscale x 32 x i16> %0544}545 546define <vscale x 1 x i32> @test_sf_vc_v_x_e32mf2(i32 signext %rs1, iXLen %vl) {547; CHECK-LABEL: test_sf_vc_v_x_e32mf2:548; CHECK: # %bb.0: # %entry549; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma550; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0551; CHECK-NEXT: ret552entry:553 %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.x.nxv1i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)554 ret <vscale x 1 x i32> %0555}556 557define <vscale x 2 x i32> @test_sf_vc_v_x_e32m1(i32 signext %rs1, iXLen %vl) {558; CHECK-LABEL: test_sf_vc_v_x_e32m1:559; CHECK: # %bb.0: # %entry560; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma561; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0562; CHECK-NEXT: ret563entry:564 %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.x.nxv2i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)565 ret <vscale x 2 x i32> %0566}567 568define <vscale x 4 x i32> @test_sf_vc_v_x_e32m2(i32 signext %rs1, iXLen %vl) {569; CHECK-LABEL: test_sf_vc_v_x_e32m2:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma572; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0573; CHECK-NEXT: ret574entry:575 %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.x.nxv4i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)576 ret <vscale x 4 x i32> %0577}578 579define <vscale x 8 x i32> @test_sf_vc_v_x_e32m4(i32 signext %rs1, iXLen %vl) {580; CHECK-LABEL: test_sf_vc_v_x_e32m4:581; CHECK: # %bb.0: # %entry582; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma583; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0584; CHECK-NEXT: ret585entry:586 %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.x.nxv8i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)587 ret <vscale x 8 x i32> %0588}589 590define <vscale x 16 x i32> @test_sf_vc_v_x_e32m8(i32 signext %rs1, iXLen %vl) {591; CHECK-LABEL: test_sf_vc_v_x_e32m8:592; CHECK: # %bb.0: # %entry593; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma594; CHECK-NEXT: sf.vc.v.x 3, 31, v8, a0595; CHECK-NEXT: ret596entry:597 %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.x.nxv16i32.iXLen.i32.iXLen(iXLen 3, iXLen 31, i32 %rs1, iXLen %vl)598 ret <vscale x 16 x i32> %0599}600 601define void @test_sf_vc_i_se_e8mf8(iXLen %vl) {602; CHECK-LABEL: test_sf_vc_i_se_e8mf8:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma605; CHECK-NEXT: sf.vc.i 3, 31, 31, 10606; CHECK-NEXT: ret607entry:608 tail call void @llvm.riscv.sf.vc.i.se.e8mf8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 8, iXLen 5, iXLen %vl)609 ret void610}611 612define void @test_sf_vc_i_se_e8mf4(iXLen %vl) {613; CHECK-LABEL: test_sf_vc_i_se_e8mf4:614; CHECK: # %bb.0: # %entry615; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma616; CHECK-NEXT: sf.vc.i 3, 31, 31, 10617; CHECK-NEXT: ret618entry:619 tail call void @llvm.riscv.sf.vc.i.se.e8mf4.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 8, iXLen 6, iXLen %vl)620 ret void621}622 623define void @test_sf_vc_i_se_e8mf2(iXLen %vl) {624; CHECK-LABEL: test_sf_vc_i_se_e8mf2:625; CHECK: # %bb.0: # %entry626; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma627; CHECK-NEXT: sf.vc.i 3, 31, 31, 10628; CHECK-NEXT: ret629entry:630 tail call void @llvm.riscv.sf.vc.i.se.e8mf2.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 8, iXLen 7, iXLen %vl)631 ret void632}633 634define void @test_sf_vc_i_se_e8m1(iXLen %vl) {635; CHECK-LABEL: test_sf_vc_i_se_e8m1:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma638; CHECK-NEXT: sf.vc.i 3, 31, 31, 10639; CHECK-NEXT: ret640entry:641 tail call void @llvm.riscv.sf.vc.i.se.e8m1.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 8, iXLen 0, iXLen %vl)642 ret void643}644 645define void @test_sf_vc_i_se_e8m2(iXLen %vl) {646; CHECK-LABEL: test_sf_vc_i_se_e8m2:647; CHECK: # %bb.0: # %entry648; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma649; CHECK-NEXT: sf.vc.i 3, 31, 31, 10650; CHECK-NEXT: ret651entry:652 tail call void @llvm.riscv.sf.vc.i.se.e8m2.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 8, iXLen 1, iXLen %vl)653 ret void654}655 656define void @test_sf_vc_i_se_e8m4(iXLen %vl) {657; CHECK-LABEL: test_sf_vc_i_se_e8m4:658; CHECK: # %bb.0: # %entry659; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma660; CHECK-NEXT: sf.vc.i 3, 31, 31, 10661; CHECK-NEXT: ret662entry:663 tail call void @llvm.riscv.sf.vc.i.se.e8m4.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 8, iXLen 2, iXLen %vl)664 ret void665}666 667define void @test_sf_vc_i_se_e8m8(iXLen %vl) {668; CHECK-LABEL: test_sf_vc_i_se_e8m8:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma671; CHECK-NEXT: sf.vc.i 3, 31, 31, 10672; CHECK-NEXT: ret673entry:674 tail call void @llvm.riscv.sf.vc.i.se.e8m8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 8, iXLen 3, iXLen %vl)675 ret void676}677 678define void @test_sf_vc_i_se_e16mf4(iXLen %vl) {679; CHECK-LABEL: test_sf_vc_i_se_e16mf4:680; CHECK: # %bb.0: # %entry681; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma682; CHECK-NEXT: sf.vc.i 3, 31, 31, 10683; CHECK-NEXT: ret684entry:685 tail call void @llvm.riscv.sf.vc.i.se.e16mf4.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 16, iXLen 6, iXLen %vl)686 ret void687}688 689define void @test_sf_vc_i_se_e16mf2(iXLen %vl) {690; CHECK-LABEL: test_sf_vc_i_se_e16mf2:691; CHECK: # %bb.0: # %entry692; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma693; CHECK-NEXT: sf.vc.i 3, 31, 31, 10694; CHECK-NEXT: ret695entry:696 tail call void @llvm.riscv.sf.vc.i.se.e16mf2.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 16, iXLen 7, iXLen %vl)697 ret void698}699 700define void @test_sf_vc_i_se_e16m1(iXLen %vl) {701; CHECK-LABEL: test_sf_vc_i_se_e16m1:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma704; CHECK-NEXT: sf.vc.i 3, 31, 31, 10705; CHECK-NEXT: ret706entry:707 tail call void @llvm.riscv.sf.vc.i.se.e16m1.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 16, iXLen 0, iXLen %vl)708 ret void709}710 711define void @test_sf_vc_i_se_e16m2(iXLen %vl) {712; CHECK-LABEL: test_sf_vc_i_se_e16m2:713; CHECK: # %bb.0: # %entry714; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma715; CHECK-NEXT: sf.vc.i 3, 31, 31, 10716; CHECK-NEXT: ret717entry:718 tail call void @llvm.riscv.sf.vc.i.se.e16m2.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 16, iXLen 1, iXLen %vl)719 ret void720}721 722define void @test_sf_vc_i_se_e16m4(iXLen %vl) {723; CHECK-LABEL: test_sf_vc_i_se_e16m4:724; CHECK: # %bb.0: # %entry725; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma726; CHECK-NEXT: sf.vc.i 3, 31, 31, 10727; CHECK-NEXT: ret728entry:729 tail call void @llvm.riscv.sf.vc.i.se.e16m4.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 16, iXLen 2, iXLen %vl)730 ret void731}732 733define void @test_sf_vc_i_se_e16m8(iXLen %vl) {734; CHECK-LABEL: test_sf_vc_i_se_e16m8:735; CHECK: # %bb.0: # %entry736; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma737; CHECK-NEXT: sf.vc.i 3, 31, 31, 10738; CHECK-NEXT: ret739entry:740 tail call void @llvm.riscv.sf.vc.i.se.e16m8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 16, iXLen 3, iXLen %vl)741 ret void742}743 744define void @test_sf_vc_i_se_e32mf2(iXLen %vl) {745; CHECK-LABEL: test_sf_vc_i_se_e32mf2:746; CHECK: # %bb.0: # %entry747; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma748; CHECK-NEXT: sf.vc.i 3, 31, 31, 10749; CHECK-NEXT: ret750entry:751 tail call void @llvm.riscv.sf.vc.i.se.e32mf2.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 32, iXLen 7, iXLen %vl)752 ret void753}754 755define void @test_sf_vc_i_se_e32m1(iXLen %vl) {756; CHECK-LABEL: test_sf_vc_i_se_e32m1:757; CHECK: # %bb.0: # %entry758; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma759; CHECK-NEXT: sf.vc.i 3, 31, 31, 10760; CHECK-NEXT: ret761entry:762 tail call void @llvm.riscv.sf.vc.i.se.e32m1.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 32, iXLen 0, iXLen %vl)763 ret void764}765 766define void @test_sf_vc_i_se_e32m2(iXLen %vl) {767; CHECK-LABEL: test_sf_vc_i_se_e32m2:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma770; CHECK-NEXT: sf.vc.i 3, 31, 31, 10771; CHECK-NEXT: ret772entry:773 tail call void @llvm.riscv.sf.vc.i.se.e32m2.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 32, iXLen 1, iXLen %vl)774 ret void775}776 777define void @test_sf_vc_i_se_e32m4(iXLen %vl) {778; CHECK-LABEL: test_sf_vc_i_se_e32m4:779; CHECK: # %bb.0: # %entry780; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma781; CHECK-NEXT: sf.vc.i 3, 31, 31, 10782; CHECK-NEXT: ret783entry:784 tail call void @llvm.riscv.sf.vc.i.se.e32m4.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 32, iXLen 2, iXLen %vl)785 ret void786}787 788define void @test_sf_vc_i_se_e32m8(iXLen %vl) {789; CHECK-LABEL: test_sf_vc_i_se_e32m8:790; CHECK: # %bb.0: # %entry791; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma792; CHECK-NEXT: sf.vc.i 3, 31, 31, 10793; CHECK-NEXT: ret794entry:795 tail call void @llvm.riscv.sf.vc.i.se.e32m8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 32, iXLen 3, iXLen %vl)796 ret void797}798 799define void @test_sf_vc_i_se_e64m1(iXLen %vl) {800; CHECK-LABEL: test_sf_vc_i_se_e64m1:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma803; CHECK-NEXT: sf.vc.i 3, 31, 31, 10804; CHECK-NEXT: ret805entry:806 tail call void @llvm.riscv.sf.vc.i.se.e64m1.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 64, iXLen 0, iXLen %vl)807 ret void808}809 810define void @test_sf_vc_i_se_e64m2(iXLen %vl) {811; CHECK-LABEL: test_sf_vc_i_se_e64m2:812; CHECK: # %bb.0: # %entry813; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma814; CHECK-NEXT: sf.vc.i 3, 31, 31, 10815; CHECK-NEXT: ret816entry:817 tail call void @llvm.riscv.sf.vc.i.se.e64m2.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 64, iXLen 1, iXLen %vl)818 ret void819}820 821define void @test_sf_vc_i_se_e64m4(iXLen %vl) {822; CHECK-LABEL: test_sf_vc_i_se_e64m4:823; CHECK: # %bb.0: # %entry824; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma825; CHECK-NEXT: sf.vc.i 3, 31, 31, 10826; CHECK-NEXT: ret827entry:828 tail call void @llvm.riscv.sf.vc.i.se.e64m4.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 64, iXLen 2, iXLen %vl)829 ret void830}831 832define void @test_sf_vc_i_se_e64m8(iXLen %vl) {833; CHECK-LABEL: test_sf_vc_i_se_e64m8:834; CHECK: # %bb.0: # %entry835; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma836; CHECK-NEXT: sf.vc.i 3, 31, 31, 10837; CHECK-NEXT: ret838entry:839 tail call void @llvm.riscv.sf.vc.i.se.e64m8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 31, iXLen 10, iXLen 64, iXLen 3, iXLen %vl)840 ret void841}842 843define <vscale x 1 x i8> @test_sf_vc_v_i_se_e8mf8(iXLen %vl) {844; CHECK-LABEL: test_sf_vc_v_i_se_e8mf8:845; CHECK: # %bb.0: # %entry846; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma847; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10848; CHECK-NEXT: ret849entry:850 %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.i.se.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)851 ret <vscale x 1 x i8> %0852}853 854define <vscale x 2 x i8> @test_sf_vc_v_i_se_e8mf4(iXLen %vl) {855; CHECK-LABEL: test_sf_vc_v_i_se_e8mf4:856; CHECK: # %bb.0: # %entry857; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma858; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10859; CHECK-NEXT: ret860entry:861 %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.i.se.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)862 ret <vscale x 2 x i8> %0863}864 865define <vscale x 4 x i8> @test_sf_vc_v_i_se_e8mf2(iXLen %vl) {866; CHECK-LABEL: test_sf_vc_v_i_se_e8mf2:867; CHECK: # %bb.0: # %entry868; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma869; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10870; CHECK-NEXT: ret871entry:872 %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.i.se.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)873 ret <vscale x 4 x i8> %0874}875 876define <vscale x 8 x i8> @test_sf_vc_v_i_se_e8m1(iXLen %vl) {877; CHECK-LABEL: test_sf_vc_v_i_se_e8m1:878; CHECK: # %bb.0: # %entry879; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma880; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10881; CHECK-NEXT: ret882entry:883 %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.i.se.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)884 ret <vscale x 8 x i8> %0885}886 887define <vscale x 16 x i8> @test_sf_vc_v_i_se_e8m2(iXLen %vl) {888; CHECK-LABEL: test_sf_vc_v_i_se_e8m2:889; CHECK: # %bb.0: # %entry890; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma891; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10892; CHECK-NEXT: ret893entry:894 %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.i.se.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)895 ret <vscale x 16 x i8> %0896}897 898define <vscale x 32 x i8> @test_sf_vc_v_i_se_e8m4(iXLen %vl) {899; CHECK-LABEL: test_sf_vc_v_i_se_e8m4:900; CHECK: # %bb.0: # %entry901; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma902; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10903; CHECK-NEXT: ret904entry:905 %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.i.se.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)906 ret <vscale x 32 x i8> %0907}908 909define <vscale x 64 x i8> @test_sf_vc_v_i_se_e8m8(iXLen %vl) {910; CHECK-LABEL: test_sf_vc_v_i_se_e8m8:911; CHECK: # %bb.0: # %entry912; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma913; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10914; CHECK-NEXT: ret915entry:916 %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.i.se.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)917 ret <vscale x 64 x i8> %0918}919 920define <vscale x 1 x i16> @test_sf_vc_v_i_se_e16mf4(iXLen %vl) {921; CHECK-LABEL: test_sf_vc_v_i_se_e16mf4:922; CHECK: # %bb.0: # %entry923; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma924; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10925; CHECK-NEXT: ret926entry:927 %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.i.se.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)928 ret <vscale x 1 x i16> %0929}930 931define <vscale x 2 x i16> @test_sf_vc_v_i_se_e16mf2(iXLen %vl) {932; CHECK-LABEL: test_sf_vc_v_i_se_e16mf2:933; CHECK: # %bb.0: # %entry934; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma935; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10936; CHECK-NEXT: ret937entry:938 %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.i.se.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)939 ret <vscale x 2 x i16> %0940}941 942define <vscale x 4 x i16> @test_sf_vc_v_i_se_e16m1(iXLen %vl) {943; CHECK-LABEL: test_sf_vc_v_i_se_e16m1:944; CHECK: # %bb.0: # %entry945; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma946; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10947; CHECK-NEXT: ret948entry:949 %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.i.se.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)950 ret <vscale x 4 x i16> %0951}952 953define <vscale x 8 x i16> @test_sf_vc_v_i_se_e16m2(iXLen %vl) {954; CHECK-LABEL: test_sf_vc_v_i_se_e16m2:955; CHECK: # %bb.0: # %entry956; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma957; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10958; CHECK-NEXT: ret959entry:960 %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.i.se.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)961 ret <vscale x 8 x i16> %0962}963 964define <vscale x 16 x i16> @test_sf_vc_v_i_se_e16m4(iXLen %vl) {965; CHECK-LABEL: test_sf_vc_v_i_se_e16m4:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma968; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10969; CHECK-NEXT: ret970entry:971 %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.i.se.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)972 ret <vscale x 16 x i16> %0973}974 975define <vscale x 32 x i16> @test_sf_vc_v_i_se_e16m8(iXLen %vl) {976; CHECK-LABEL: test_sf_vc_v_i_se_e16m8:977; CHECK: # %bb.0: # %entry978; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma979; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10980; CHECK-NEXT: ret981entry:982 %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.i.se.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)983 ret <vscale x 32 x i16> %0984}985 986define <vscale x 1 x i32> @test_sf_vc_v_i_se_e32mf2(iXLen %vl) {987; CHECK-LABEL: test_sf_vc_v_i_se_e32mf2:988; CHECK: # %bb.0: # %entry989; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma990; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 10991; CHECK-NEXT: ret992entry:993 %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.i.se.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)994 ret <vscale x 1 x i32> %0995}996 997define <vscale x 2 x i32> @test_sf_vc_v_i_se_e32m1(iXLen %vl) {998; CHECK-LABEL: test_sf_vc_v_i_se_e32m1:999; CHECK: # %bb.0: # %entry1000; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1001; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101002; CHECK-NEXT: ret1003entry:1004 %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.i.se.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1005 ret <vscale x 2 x i32> %01006}1007 1008define <vscale x 4 x i32> @test_sf_vc_v_i_se_e32m2(iXLen %vl) {1009; CHECK-LABEL: test_sf_vc_v_i_se_e32m2:1010; CHECK: # %bb.0: # %entry1011; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1012; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101013; CHECK-NEXT: ret1014entry:1015 %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.i.se.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1016 ret <vscale x 4 x i32> %01017}1018 1019define <vscale x 8 x i32> @test_sf_vc_v_i_se_e32m4(iXLen %vl) {1020; CHECK-LABEL: test_sf_vc_v_i_se_e32m4:1021; CHECK: # %bb.0: # %entry1022; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1023; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101024; CHECK-NEXT: ret1025entry:1026 %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.i.se.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1027 ret <vscale x 8 x i32> %01028}1029 1030define <vscale x 16 x i32> @test_sf_vc_v_i_se_e32m8(iXLen %vl) {1031; CHECK-LABEL: test_sf_vc_v_i_se_e32m8:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1034; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101035; CHECK-NEXT: ret1036entry:1037 %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.i.se.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1038 ret <vscale x 16 x i32> %01039}1040 1041define <vscale x 1 x i64> @test_sf_vc_v_i_se_e64m1(iXLen %vl) {1042; CHECK-LABEL: test_sf_vc_v_i_se_e64m1:1043; CHECK: # %bb.0: # %entry1044; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1045; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101046; CHECK-NEXT: ret1047entry:1048 %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.i.se.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1049 ret <vscale x 1 x i64> %01050}1051 1052define <vscale x 2 x i64> @test_sf_vc_v_i_se_e64m2(iXLen %vl) {1053; CHECK-LABEL: test_sf_vc_v_i_se_e64m2:1054; CHECK: # %bb.0: # %entry1055; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1056; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101057; CHECK-NEXT: ret1058entry:1059 %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.i.se.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1060 ret <vscale x 2 x i64> %01061}1062 1063define <vscale x 4 x i64> @test_sf_vc_v_i_se_e64m4(iXLen %vl) {1064; CHECK-LABEL: test_sf_vc_v_i_se_e64m4:1065; CHECK: # %bb.0: # %entry1066; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1067; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101068; CHECK-NEXT: ret1069entry:1070 %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.i.se.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1071 ret <vscale x 4 x i64> %01072}1073 1074define <vscale x 8 x i64> @test_sf_vc_v_i_se_e64m8(iXLen %vl) {1075; CHECK-LABEL: test_sf_vc_v_i_se_e64m8:1076; CHECK: # %bb.0: # %entry1077; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1078; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101079; CHECK-NEXT: ret1080entry:1081 %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.i.se.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1082 ret <vscale x 8 x i64> %01083}1084 1085define <vscale x 1 x i8> @test_sf_vc_v_i_e8mf8(iXLen %vl) {1086; CHECK-LABEL: test_sf_vc_v_i_e8mf8:1087; CHECK: # %bb.0: # %entry1088; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma1089; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101090; CHECK-NEXT: ret1091entry:1092 %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.i.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1093 ret <vscale x 1 x i8> %01094}1095 1096define <vscale x 2 x i8> @test_sf_vc_v_i_e8mf4(iXLen %vl) {1097; CHECK-LABEL: test_sf_vc_v_i_e8mf4:1098; CHECK: # %bb.0: # %entry1099; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma1100; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101101; CHECK-NEXT: ret1102entry:1103 %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.i.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1104 ret <vscale x 2 x i8> %01105}1106 1107define <vscale x 4 x i8> @test_sf_vc_v_i_e8mf2(iXLen %vl) {1108; CHECK-LABEL: test_sf_vc_v_i_e8mf2:1109; CHECK: # %bb.0: # %entry1110; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma1111; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101112; CHECK-NEXT: ret1113entry:1114 %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.i.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1115 ret <vscale x 4 x i8> %01116}1117 1118define <vscale x 8 x i8> @test_sf_vc_v_i_e8m1(iXLen %vl) {1119; CHECK-LABEL: test_sf_vc_v_i_e8m1:1120; CHECK: # %bb.0: # %entry1121; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma1122; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101123; CHECK-NEXT: ret1124entry:1125 %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.i.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1126 ret <vscale x 8 x i8> %01127}1128 1129define <vscale x 16 x i8> @test_sf_vc_v_i_e8m2(iXLen %vl) {1130; CHECK-LABEL: test_sf_vc_v_i_e8m2:1131; CHECK: # %bb.0: # %entry1132; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma1133; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101134; CHECK-NEXT: ret1135entry:1136 %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.i.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1137 ret <vscale x 16 x i8> %01138}1139 1140define <vscale x 32 x i8> @test_sf_vc_v_i_e8m4(iXLen %vl) {1141; CHECK-LABEL: test_sf_vc_v_i_e8m4:1142; CHECK: # %bb.0: # %entry1143; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma1144; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101145; CHECK-NEXT: ret1146entry:1147 %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.i.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1148 ret <vscale x 32 x i8> %01149}1150 1151define <vscale x 64 x i8> @test_sf_vc_v_i_e8m8(iXLen %vl) {1152; CHECK-LABEL: test_sf_vc_v_i_e8m8:1153; CHECK: # %bb.0: # %entry1154; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1155; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101156; CHECK-NEXT: ret1157entry:1158 %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.i.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1159 ret <vscale x 64 x i8> %01160}1161 1162define <vscale x 1 x i16> @test_sf_vc_v_i_e16mf4(iXLen %vl) {1163; CHECK-LABEL: test_sf_vc_v_i_e16mf4:1164; CHECK: # %bb.0: # %entry1165; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1166; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101167; CHECK-NEXT: ret1168entry:1169 %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.i.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1170 ret <vscale x 1 x i16> %01171}1172 1173define <vscale x 2 x i16> @test_sf_vc_v_i_e16mf2(iXLen %vl) {1174; CHECK-LABEL: test_sf_vc_v_i_e16mf2:1175; CHECK: # %bb.0: # %entry1176; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1177; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101178; CHECK-NEXT: ret1179entry:1180 %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.i.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1181 ret <vscale x 2 x i16> %01182}1183 1184define <vscale x 4 x i16> @test_sf_vc_v_i_e16m1(iXLen %vl) {1185; CHECK-LABEL: test_sf_vc_v_i_e16m1:1186; CHECK: # %bb.0: # %entry1187; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1188; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101189; CHECK-NEXT: ret1190entry:1191 %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.i.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1192 ret <vscale x 4 x i16> %01193}1194 1195define <vscale x 8 x i16> @test_sf_vc_v_i_e16m2(iXLen %vl) {1196; CHECK-LABEL: test_sf_vc_v_i_e16m2:1197; CHECK: # %bb.0: # %entry1198; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1199; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101200; CHECK-NEXT: ret1201entry:1202 %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.i.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1203 ret <vscale x 8 x i16> %01204}1205 1206define <vscale x 16 x i16> @test_sf_vc_v_i_e16m4(iXLen %vl) {1207; CHECK-LABEL: test_sf_vc_v_i_e16m4:1208; CHECK: # %bb.0: # %entry1209; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1210; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101211; CHECK-NEXT: ret1212entry:1213 %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.i.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1214 ret <vscale x 16 x i16> %01215}1216 1217define <vscale x 32 x i16> @test_sf_vc_v_i_e16m8(iXLen %vl) {1218; CHECK-LABEL: test_sf_vc_v_i_e16m8:1219; CHECK: # %bb.0: # %entry1220; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1221; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101222; CHECK-NEXT: ret1223entry:1224 %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.i.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1225 ret <vscale x 32 x i16> %01226}1227 1228define <vscale x 1 x i32> @test_sf_vc_v_i_e32mf2(iXLen %vl) {1229; CHECK-LABEL: test_sf_vc_v_i_e32mf2:1230; CHECK: # %bb.0: # %entry1231; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1232; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101233; CHECK-NEXT: ret1234entry:1235 %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.i.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1236 ret <vscale x 1 x i32> %01237}1238 1239define <vscale x 2 x i32> @test_sf_vc_v_i_e32m1(iXLen %vl) {1240; CHECK-LABEL: test_sf_vc_v_i_e32m1:1241; CHECK: # %bb.0: # %entry1242; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1243; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101244; CHECK-NEXT: ret1245entry:1246 %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.i.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1247 ret <vscale x 2 x i32> %01248}1249 1250define <vscale x 4 x i32> @test_sf_vc_v_i_e32m2(iXLen %vl) {1251; CHECK-LABEL: test_sf_vc_v_i_e32m2:1252; CHECK: # %bb.0: # %entry1253; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1254; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101255; CHECK-NEXT: ret1256entry:1257 %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.i.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1258 ret <vscale x 4 x i32> %01259}1260 1261define <vscale x 8 x i32> @test_sf_vc_v_i_e32m4(iXLen %vl) {1262; CHECK-LABEL: test_sf_vc_v_i_e32m4:1263; CHECK: # %bb.0: # %entry1264; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1265; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101266; CHECK-NEXT: ret1267entry:1268 %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.i.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1269 ret <vscale x 8 x i32> %01270}1271 1272define <vscale x 16 x i32> @test_sf_vc_v_i_e32m8(iXLen %vl) {1273; CHECK-LABEL: test_sf_vc_v_i_e32m8:1274; CHECK: # %bb.0: # %entry1275; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1276; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101277; CHECK-NEXT: ret1278entry:1279 %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.i.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1280 ret <vscale x 16 x i32> %01281}1282 1283define <vscale x 1 x i64> @test_sf_vc_v_i_e64m1(iXLen %vl) {1284; CHECK-LABEL: test_sf_vc_v_i_e64m1:1285; CHECK: # %bb.0: # %entry1286; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1287; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101288; CHECK-NEXT: ret1289entry:1290 %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.i.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1291 ret <vscale x 1 x i64> %01292}1293 1294define <vscale x 2 x i64> @test_sf_vc_v_i_e64m2(iXLen %vl) {1295; CHECK-LABEL: test_sf_vc_v_i_e64m2:1296; CHECK: # %bb.0: # %entry1297; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1298; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101299; CHECK-NEXT: ret1300entry:1301 %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.i.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1302 ret <vscale x 2 x i64> %01303}1304 1305define <vscale x 4 x i64> @test_sf_vc_v_i_e64m4(iXLen %vl) {1306; CHECK-LABEL: test_sf_vc_v_i_e64m4:1307; CHECK: # %bb.0: # %entry1308; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1309; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101310; CHECK-NEXT: ret1311entry:1312 %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.i.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1313 ret <vscale x 4 x i64> %01314}1315 1316define <vscale x 8 x i64> @test_sf_vc_v_i_e64m8(iXLen %vl) {1317; CHECK-LABEL: test_sf_vc_v_i_e64m8:1318; CHECK: # %bb.0: # %entry1319; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1320; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101321; CHECK-NEXT: ret1322entry:1323 %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.i.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1324 ret <vscale x 8 x i64> %01325}1326 1327define <vscale x 1 x half> @test_f_sf_vc_v_i_se_e16mf4(iXLen %vl) {1328; CHECK-LABEL: test_f_sf_vc_v_i_se_e16mf4:1329; CHECK: # %bb.0: # %entry1330; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1331; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101332; CHECK-NEXT: ret1333entry:1334 %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.i.se.nxv1f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1335 ret <vscale x 1 x half> %01336}1337 1338define <vscale x 2 x half> @test_f_sf_vc_v_i_se_e16mf2(iXLen %vl) {1339; CHECK-LABEL: test_f_sf_vc_v_i_se_e16mf2:1340; CHECK: # %bb.0: # %entry1341; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1342; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101343; CHECK-NEXT: ret1344entry:1345 %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.i.se.nxv2f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1346 ret <vscale x 2 x half> %01347}1348 1349define <vscale x 4 x half> @test_f_sf_vc_v_i_se_e16m1(iXLen %vl) {1350; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m1:1351; CHECK: # %bb.0: # %entry1352; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1353; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101354; CHECK-NEXT: ret1355entry:1356 %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.i.se.nxv4f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1357 ret <vscale x 4 x half> %01358}1359 1360define <vscale x 8 x half> @test_f_sf_vc_v_i_se_e16m2(iXLen %vl) {1361; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m2:1362; CHECK: # %bb.0: # %entry1363; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1364; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101365; CHECK-NEXT: ret1366entry:1367 %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.i.se.nxv8f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1368 ret <vscale x 8 x half> %01369}1370 1371define <vscale x 16 x half> @test_f_sf_vc_v_i_se_e16m4(iXLen %vl) {1372; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m4:1373; CHECK: # %bb.0: # %entry1374; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1375; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101376; CHECK-NEXT: ret1377entry:1378 %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.i.se.nxv16f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1379 ret <vscale x 16 x half> %01380}1381 1382define <vscale x 32 x half> @test_f_sf_vc_v_i_se_e16m8(iXLen %vl) {1383; CHECK-LABEL: test_f_sf_vc_v_i_se_e16m8:1384; CHECK: # %bb.0: # %entry1385; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1386; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101387; CHECK-NEXT: ret1388entry:1389 %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.i.se.nxv32f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1390 ret <vscale x 32 x half> %01391}1392 1393define <vscale x 1 x float> @test_f_sf_vc_v_i_se_e32mf2(iXLen %vl) {1394; CHECK-LABEL: test_f_sf_vc_v_i_se_e32mf2:1395; CHECK: # %bb.0: # %entry1396; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1397; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101398; CHECK-NEXT: ret1399entry:1400 %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.i.se.nxv1f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1401 ret <vscale x 1 x float> %01402}1403 1404define <vscale x 2 x float> @test_f_sf_vc_v_i_se_e32m1(iXLen %vl) {1405; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m1:1406; CHECK: # %bb.0: # %entry1407; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1408; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101409; CHECK-NEXT: ret1410entry:1411 %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.i.se.nxv2f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1412 ret <vscale x 2 x float> %01413}1414 1415define <vscale x 4 x float> @test_f_sf_vc_v_i_se_e32m2(iXLen %vl) {1416; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m2:1417; CHECK: # %bb.0: # %entry1418; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1419; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101420; CHECK-NEXT: ret1421entry:1422 %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.i.se.nxv4f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1423 ret <vscale x 4 x float> %01424}1425 1426define <vscale x 8 x float> @test_f_sf_vc_v_i_se_e32m4(iXLen %vl) {1427; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m4:1428; CHECK: # %bb.0: # %entry1429; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1430; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101431; CHECK-NEXT: ret1432entry:1433 %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.i.se.nxv8f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1434 ret <vscale x 8 x float> %01435}1436 1437define <vscale x 16 x float> @test_f_sf_vc_v_i_se_e32m8(iXLen %vl) {1438; CHECK-LABEL: test_f_sf_vc_v_i_se_e32m8:1439; CHECK: # %bb.0: # %entry1440; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1441; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101442; CHECK-NEXT: ret1443entry:1444 %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.i.se.nxv16f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1445 ret <vscale x 16 x float> %01446}1447 1448define <vscale x 1 x double> @test_f_sf_vc_v_i_se_e64m1(iXLen %vl) {1449; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m1:1450; CHECK: # %bb.0: # %entry1451; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1452; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101453; CHECK-NEXT: ret1454entry:1455 %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.i.se.nxv1f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1456 ret <vscale x 1 x double> %01457}1458 1459define <vscale x 2 x double> @test_f_sf_vc_v_i_se_e64m2(iXLen %vl) {1460; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m2:1461; CHECK: # %bb.0: # %entry1462; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1463; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101464; CHECK-NEXT: ret1465entry:1466 %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.i.se.nxv2f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1467 ret <vscale x 2 x double> %01468}1469 1470define <vscale x 4 x double> @test_f_sf_vc_v_i_se_e64m4(iXLen %vl) {1471; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m4:1472; CHECK: # %bb.0: # %entry1473; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1474; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101475; CHECK-NEXT: ret1476entry:1477 %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.i.se.nxv4f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1478 ret <vscale x 4 x double> %01479}1480 1481define <vscale x 8 x double> @test_f_sf_vc_v_i_se_e64m8(iXLen %vl) {1482; CHECK-LABEL: test_f_sf_vc_v_i_se_e64m8:1483; CHECK: # %bb.0: # %entry1484; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1485; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101486; CHECK-NEXT: ret1487entry:1488 %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.i.se.nxv8f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1489 ret <vscale x 8 x double> %01490}1491 1492define <vscale x 1 x half> @test_f_sf_vc_v_i_e16mf4(iXLen %vl) {1493; CHECK-LABEL: test_f_sf_vc_v_i_e16mf4:1494; CHECK: # %bb.0: # %entry1495; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1496; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101497; CHECK-NEXT: ret1498entry:1499 %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.i.nxv1f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1500 ret <vscale x 1 x half> %01501}1502 1503define <vscale x 2 x half> @test_f_sf_vc_v_i_e16mf2(iXLen %vl) {1504; CHECK-LABEL: test_f_sf_vc_v_i_e16mf2:1505; CHECK: # %bb.0: # %entry1506; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1507; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101508; CHECK-NEXT: ret1509entry:1510 %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.i.nxv2f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1511 ret <vscale x 2 x half> %01512}1513 1514define <vscale x 4 x half> @test_f_sf_vc_v_i_e16m1(iXLen %vl) {1515; CHECK-LABEL: test_f_sf_vc_v_i_e16m1:1516; CHECK: # %bb.0: # %entry1517; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1518; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101519; CHECK-NEXT: ret1520entry:1521 %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.i.nxv4f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1522 ret <vscale x 4 x half> %01523}1524 1525define <vscale x 8 x half> @test_f_sf_vc_v_i_e16m2(iXLen %vl) {1526; CHECK-LABEL: test_f_sf_vc_v_i_e16m2:1527; CHECK: # %bb.0: # %entry1528; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1529; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101530; CHECK-NEXT: ret1531entry:1532 %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.i.nxv8f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1533 ret <vscale x 8 x half> %01534}1535 1536define <vscale x 16 x half> @test_f_sf_vc_v_i_e16m4(iXLen %vl) {1537; CHECK-LABEL: test_f_sf_vc_v_i_e16m4:1538; CHECK: # %bb.0: # %entry1539; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1540; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101541; CHECK-NEXT: ret1542entry:1543 %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.i.nxv16f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1544 ret <vscale x 16 x half> %01545}1546 1547define <vscale x 32 x half> @test_f_sf_vc_v_i_e16m8(iXLen %vl) {1548; CHECK-LABEL: test_f_sf_vc_v_i_e16m8:1549; CHECK: # %bb.0: # %entry1550; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1551; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101552; CHECK-NEXT: ret1553entry:1554 %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.i.nxv32f16.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1555 ret <vscale x 32 x half> %01556}1557 1558define <vscale x 1 x float> @test_f_sf_vc_v_i_e32mf2(iXLen %vl) {1559; CHECK-LABEL: test_f_sf_vc_v_i_e32mf2:1560; CHECK: # %bb.0: # %entry1561; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1562; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101563; CHECK-NEXT: ret1564entry:1565 %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.i.nxv1f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1566 ret <vscale x 1 x float> %01567}1568 1569define <vscale x 2 x float> @test_f_sf_vc_v_i_e32m1(iXLen %vl) {1570; CHECK-LABEL: test_f_sf_vc_v_i_e32m1:1571; CHECK: # %bb.0: # %entry1572; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1573; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101574; CHECK-NEXT: ret1575entry:1576 %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.i.nxv2f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1577 ret <vscale x 2 x float> %01578}1579 1580define <vscale x 4 x float> @test_f_sf_vc_v_i_e32m2(iXLen %vl) {1581; CHECK-LABEL: test_f_sf_vc_v_i_e32m2:1582; CHECK: # %bb.0: # %entry1583; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1584; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101585; CHECK-NEXT: ret1586entry:1587 %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.i.nxv4f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1588 ret <vscale x 4 x float> %01589}1590 1591define <vscale x 8 x float> @test_f_sf_vc_v_i_e32m4(iXLen %vl) {1592; CHECK-LABEL: test_f_sf_vc_v_i_e32m4:1593; CHECK: # %bb.0: # %entry1594; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1595; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101596; CHECK-NEXT: ret1597entry:1598 %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.i.nxv8f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1599 ret <vscale x 8 x float> %01600}1601 1602define <vscale x 16 x float> @test_f_sf_vc_v_i_e32m8(iXLen %vl) {1603; CHECK-LABEL: test_f_sf_vc_v_i_e32m8:1604; CHECK: # %bb.0: # %entry1605; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1606; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101607; CHECK-NEXT: ret1608entry:1609 %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.i.nxv16f32.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1610 ret <vscale x 16 x float> %01611}1612 1613define <vscale x 1 x double> @test_f_sf_vc_v_i_e64m1(iXLen %vl) {1614; CHECK-LABEL: test_f_sf_vc_v_i_e64m1:1615; CHECK: # %bb.0: # %entry1616; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1617; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101618; CHECK-NEXT: ret1619entry:1620 %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.i.nxv1f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1621 ret <vscale x 1 x double> %01622}1623 1624define <vscale x 2 x double> @test_f_sf_vc_v_i_e64m2(iXLen %vl) {1625; CHECK-LABEL: test_f_sf_vc_v_i_e64m2:1626; CHECK: # %bb.0: # %entry1627; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1628; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101629; CHECK-NEXT: ret1630entry:1631 %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.i.nxv2f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1632 ret <vscale x 2 x double> %01633}1634 1635define <vscale x 4 x double> @test_f_sf_vc_v_i_e64m4(iXLen %vl) {1636; CHECK-LABEL: test_f_sf_vc_v_i_e64m4:1637; CHECK: # %bb.0: # %entry1638; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1639; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101640; CHECK-NEXT: ret1641entry:1642 %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.i.nxv4f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1643 ret <vscale x 4 x double> %01644}1645 1646define <vscale x 8 x double> @test_f_sf_vc_v_i_e64m8(iXLen %vl) {1647; CHECK-LABEL: test_f_sf_vc_v_i_e64m8:1648; CHECK: # %bb.0: # %entry1649; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1650; CHECK-NEXT: sf.vc.v.i 3, 31, v8, 101651; CHECK-NEXT: ret1652entry:1653 %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.i.nxv8f64.iXLen.iXLen.iXLen(iXLen 3, iXLen 31, iXLen 10, iXLen %vl)1654 ret <vscale x 8 x double> %01655}1656 1657define <vscale x 1 x half> @test_sf_vc_fv_x_se_e16mf4(i16 %rs1, iXLen %vl) {1658; CHECK-LABEL: test_sf_vc_fv_x_se_e16mf4:1659; CHECK: # %bb.0: # %entry1660; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1661; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01662; CHECK-NEXT: ret1663entry:1664 %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.x.se.nxv1f16.i16.iXLen(iXLen 3, iXLen 4, i16 %rs1, iXLen %vl)1665 ret <vscale x 1 x half> %01666}1667 1668define <vscale x 2 x half> @test_sf_vc_fv_x_se_e16mf2(i16 %rs1, iXLen %vl) {1669; CHECK-LABEL: test_sf_vc_fv_x_se_e16mf2:1670; CHECK: # %bb.0: # %entry1671; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1672; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01673; CHECK-NEXT: ret1674entry:1675 %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.x.se.nxv2f16.i16.iXLen(iXLen 3, iXLen 4, i16 %rs1, iXLen %vl)1676 ret <vscale x 2 x half> %01677}1678 1679define <vscale x 4 x half> @test_sf_vc_fv_x_se_e16m1(i16 %rs1, iXLen %vl) {1680; CHECK-LABEL: test_sf_vc_fv_x_se_e16m1:1681; CHECK: # %bb.0: # %entry1682; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1683; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01684; CHECK-NEXT: ret1685entry:1686 %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.x.se.nxv4f16.i16.iXLen(iXLen 3, iXLen 4, i16 %rs1, iXLen %vl)1687 ret <vscale x 4 x half> %01688}1689 1690define <vscale x 8 x half> @test_sf_vc_fv_x_se_e16m2(i16 %rs1, iXLen %vl) {1691; CHECK-LABEL: test_sf_vc_fv_x_se_e16m2:1692; CHECK: # %bb.0: # %entry1693; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1694; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01695; CHECK-NEXT: ret1696entry:1697 %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.x.se.nxv8f16.i16.iXLen(iXLen 3, iXLen 4, i16 %rs1, iXLen %vl)1698 ret <vscale x 8 x half> %01699}1700 1701define <vscale x 16 x half> @test_sf_vc_fv_x_se_e16m4(i16 %rs1, iXLen %vl) {1702; CHECK-LABEL: test_sf_vc_fv_x_se_e16m4:1703; CHECK: # %bb.0: # %entry1704; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1705; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01706; CHECK-NEXT: ret1707entry:1708 %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.x.se.nxv16f16.i16.iXLen(iXLen 3, iXLen 4, i16 %rs1, iXLen %vl)1709 ret <vscale x 16 x half> %01710}1711 1712define <vscale x 32 x half> @test_sf_vc_fv_x_se_e16m8(i16 %rs1, iXLen %vl) {1713; CHECK-LABEL: test_sf_vc_fv_x_se_e16m8:1714; CHECK: # %bb.0: # %entry1715; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1716; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01717; CHECK-NEXT: ret1718entry:1719 %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.x.se.nxv32f16.i16.iXLen(iXLen 3, iXLen 4, i16 %rs1, iXLen %vl)1720 ret <vscale x 32 x half> %01721}1722 1723define <vscale x 1 x float> @test_sf_vc_fv_x_se_e32mf2(i32 %rs1, iXLen %vl) {1724; CHECK-LABEL: test_sf_vc_fv_x_se_e32mf2:1725; CHECK: # %bb.0: # %entry1726; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1727; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01728; CHECK-NEXT: ret1729entry:1730 %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.x.se.nxv1f32.i32.iXLen(iXLen 3, iXLen 4, i32 %rs1, iXLen %vl)1731 ret <vscale x 1 x float> %01732}1733 1734define <vscale x 2 x float> @test_sf_vc_fv_x_se_e32m1(i32 %rs1, iXLen %vl) {1735; CHECK-LABEL: test_sf_vc_fv_x_se_e32m1:1736; CHECK: # %bb.0: # %entry1737; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1738; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01739; CHECK-NEXT: ret1740entry:1741 %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.x.se.nxv2f32.i32.iXLen(iXLen 3, iXLen 4, i32 %rs1, iXLen %vl)1742 ret <vscale x 2 x float> %01743}1744 1745define <vscale x 4 x float> @test_sf_vc_fv_x_se_e32m2(i32 %rs1, iXLen %vl) {1746; CHECK-LABEL: test_sf_vc_fv_x_se_e32m2:1747; CHECK: # %bb.0: # %entry1748; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1749; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01750; CHECK-NEXT: ret1751entry:1752 %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.x.se.nxv4f32.i32.iXLen(iXLen 3, iXLen 4, i32 %rs1, iXLen %vl)1753 ret <vscale x 4 x float> %01754}1755 1756define <vscale x 8 x float> @test_sf_vc_fv_x_se_e32m4(i32 %rs1, iXLen %vl) {1757; CHECK-LABEL: test_sf_vc_fv_x_se_e32m4:1758; CHECK: # %bb.0: # %entry1759; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1760; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01761; CHECK-NEXT: ret1762entry:1763 %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.x.se.nxv8f32.i32.iXLen(iXLen 3, iXLen 4, i32 %rs1, iXLen %vl)1764 ret <vscale x 8 x float> %01765}1766 1767define <vscale x 16 x float> @test_sf_vc_fv_x_se_e32m8(i32 %rs1, iXLen %vl) {1768; CHECK-LABEL: test_sf_vc_fv_x_se_e32m8:1769; CHECK: # %bb.0: # %entry1770; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1771; CHECK-NEXT: sf.vc.v.x 3, 4, v8, a01772; CHECK-NEXT: ret1773entry:1774 %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.x.se.nxv16f32.i32.iXLen(iXLen 3, iXLen 4, i32 %rs1, iXLen %vl)1775 ret <vscale x 16 x float> %01776}1777 1778define <vscale x 1 x half> @test_sf_vc_fv_i_se_e16mf4(iXLen %vl) {1779; CHECK-LABEL: test_sf_vc_fv_i_se_e16mf4:1780; CHECK: # %bb.0: # %entry1781; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1782; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41783; CHECK-NEXT: ret1784entry:1785 %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.i.se.nxv1f16.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1786 ret <vscale x 1 x half> %01787}1788 1789define <vscale x 2 x half> @test_sf_vc_fv_i_se_e16mf2(iXLen %vl) {1790; CHECK-LABEL: test_sf_vc_fv_i_se_e16mf2:1791; CHECK: # %bb.0: # %entry1792; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1793; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41794; CHECK-NEXT: ret1795entry:1796 %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.i.se.nxv2f16.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1797 ret <vscale x 2 x half> %01798}1799 1800define <vscale x 4 x half> @test_sf_vc_fv_i_se_e16m1(iXLen %vl) {1801; CHECK-LABEL: test_sf_vc_fv_i_se_e16m1:1802; CHECK: # %bb.0: # %entry1803; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1804; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41805; CHECK-NEXT: ret1806entry:1807 %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.i.se.nxv4f16.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1808 ret <vscale x 4 x half> %01809}1810 1811define <vscale x 8 x half> @test_sf_vc_fv_i_se_e16m2(iXLen %vl) {1812; CHECK-LABEL: test_sf_vc_fv_i_se_e16m2:1813; CHECK: # %bb.0: # %entry1814; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1815; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41816; CHECK-NEXT: ret1817entry:1818 %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.i.se.nxv8f16.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1819 ret <vscale x 8 x half> %01820}1821 1822define <vscale x 16 x half> @test_sf_vc_fv_i_se_e16m4(iXLen %vl) {1823; CHECK-LABEL: test_sf_vc_fv_i_se_e16m4:1824; CHECK: # %bb.0: # %entry1825; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1826; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41827; CHECK-NEXT: ret1828entry:1829 %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.i.se.nxv16f16.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1830 ret <vscale x 16 x half> %01831}1832 1833define <vscale x 32 x half> @test_sf_vc_fv_i_se_e16m8(iXLen %vl) {1834; CHECK-LABEL: test_sf_vc_fv_i_se_e16m8:1835; CHECK: # %bb.0: # %entry1836; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1837; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41838; CHECK-NEXT: ret1839entry:1840 %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.i.se.nxv32f16.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1841 ret <vscale x 32 x half> %01842}1843 1844define <vscale x 1 x float> @test_sf_vc_fv_i_se_e32mf2(iXLen %vl) {1845; CHECK-LABEL: test_sf_vc_fv_i_se_e32mf2:1846; CHECK: # %bb.0: # %entry1847; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1848; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41849; CHECK-NEXT: ret1850entry:1851 %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.i.se.nxv1f32.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1852 ret <vscale x 1 x float> %01853}1854 1855define <vscale x 2 x float> @test_sf_vc_fv_i_se_e32m1(iXLen %vl) {1856; CHECK-LABEL: test_sf_vc_fv_i_se_e32m1:1857; CHECK: # %bb.0: # %entry1858; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1859; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41860; CHECK-NEXT: ret1861entry:1862 %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.i.se.nxv2f32.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1863 ret <vscale x 2 x float> %01864}1865 1866define <vscale x 4 x float> @test_sf_vc_fv_i_se_e32m2(iXLen %vl) {1867; CHECK-LABEL: test_sf_vc_fv_i_se_e32m2:1868; CHECK: # %bb.0: # %entry1869; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1870; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41871; CHECK-NEXT: ret1872entry:1873 %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.i.se.nxv4f32.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1874 ret <vscale x 4 x float> %01875}1876 1877define <vscale x 8 x float> @test_sf_vc_fv_i_se_e32m4(iXLen %vl) {1878; CHECK-LABEL: test_sf_vc_fv_i_se_e32m4:1879; CHECK: # %bb.0: # %entry1880; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1881; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41882; CHECK-NEXT: ret1883entry:1884 %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.i.se.nxv8f32.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1885 ret <vscale x 8 x float> %01886}1887 1888define <vscale x 16 x float> @test_sf_vc_fv_i_se_e32m8(iXLen %vl) {1889; CHECK-LABEL: test_sf_vc_fv_i_se_e32m8:1890; CHECK: # %bb.0: # %entry1891; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1892; CHECK-NEXT: sf.vc.v.i 3, 8, v8, 41893; CHECK-NEXT: ret1894entry:1895 %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.i.se.nxv16f32.iXLen.iXLen(iXLen 3, iXLen 8, iXLen 4, iXLen %vl)1896 ret <vscale x 16 x float> %01897}1898 1899