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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN:  sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh,+xsfvcp \3; RUN:    -verify-machineinstrs | FileCheck %s4; RUN:  sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh,+xsfvcp \5; RUN:    -verify-machineinstrs | FileCheck %s6 7define void @test_sf_vc_vv_se_e8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {8; CHECK-LABEL: test_sf_vc_vv_se_e8mf8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v912; CHECK-NEXT:    ret13entry:14  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1i8.nxv1i8.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)15  ret void16}17 18define void @test_sf_vc_vv_se_e8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {19; CHECK-LABEL: test_sf_vc_vv_se_e8mf4:20; CHECK:       # %bb.0: # %entry21; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma22; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v923; CHECK-NEXT:    ret24entry:25  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2i8.nxv2i8.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)26  ret void27}28 29define void @test_sf_vc_vv_se_e8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {30; CHECK-LABEL: test_sf_vc_vv_se_e8mf2:31; CHECK:       # %bb.0: # %entry32; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma33; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v934; CHECK-NEXT:    ret35entry:36  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4i8.nxv4i8.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)37  ret void38}39 40define void @test_sf_vc_vv_se_e8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {41; CHECK-LABEL: test_sf_vc_vv_se_e8m1:42; CHECK:       # %bb.0: # %entry43; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma44; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v945; CHECK-NEXT:    ret46entry:47  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8i8.nxv8i8.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)48  ret void49}50 51define void @test_sf_vc_vv_se_e8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {52; CHECK-LABEL: test_sf_vc_vv_se_e8m2:53; CHECK:       # %bb.0: # %entry54; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma55; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v1056; CHECK-NEXT:    ret57entry:58  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16i8.nxv16i8.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)59  ret void60}61 62define void @test_sf_vc_vv_se_e8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {63; CHECK-LABEL: test_sf_vc_vv_se_e8m4:64; CHECK:       # %bb.0: # %entry65; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma66; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v1267; CHECK-NEXT:    ret68entry:69  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv32i8.nxv32i8.iXLen(iXLen 3, iXLen 31, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)70  ret void71}72 73define void @test_sf_vc_vv_se_e8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl) {74; CHECK-LABEL: test_sf_vc_vv_se_e8m8:75; CHECK:       # %bb.0: # %entry76; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma77; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v1678; CHECK-NEXT:    ret79entry:80  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv64i8.nxv64i8.iXLen(iXLen 3, iXLen 31, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl)81  ret void82}83 84define void @test_sf_vc_vv_se_e16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {85; CHECK-LABEL: test_sf_vc_vv_se_e16mf4:86; CHECK:       # %bb.0: # %entry87; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma88; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v989; CHECK-NEXT:    ret90entry:91  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1i16.nxv1i16.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)92  ret void93}94 95define void @test_sf_vc_vv_se_e16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {96; CHECK-LABEL: test_sf_vc_vv_se_e16mf2:97; CHECK:       # %bb.0: # %entry98; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma99; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v9100; CHECK-NEXT:    ret101entry:102  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2i16.nxv2i16.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)103  ret void104}105 106define void @test_sf_vc_vv_se_e16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {107; CHECK-LABEL: test_sf_vc_vv_se_e16m1:108; CHECK:       # %bb.0: # %entry109; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma110; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v9111; CHECK-NEXT:    ret112entry:113  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4i16.nxv4i16.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)114  ret void115}116 117define void @test_sf_vc_vv_se_e16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {118; CHECK-LABEL: test_sf_vc_vv_se_e16m2:119; CHECK:       # %bb.0: # %entry120; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma121; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v10122; CHECK-NEXT:    ret123entry:124  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8i16.nxv8i16.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)125  ret void126}127 128define void @test_sf_vc_vv_se_e16m4(<vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {129; CHECK-LABEL: test_sf_vc_vv_se_e16m4:130; CHECK:       # %bb.0: # %entry131; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma132; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v12133; CHECK-NEXT:    ret134entry:135  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16i16.nxv16i16.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)136  ret void137}138 139define void @test_sf_vc_vv_se_e16m8(<vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {140; CHECK-LABEL: test_sf_vc_vv_se_e16m8:141; CHECK:       # %bb.0: # %entry142; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma143; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v16144; CHECK-NEXT:    ret145entry:146  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv32i16.nxv32i16.iXLen(iXLen 3, iXLen 31, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)147  ret void148}149 150define void @test_sf_vc_vv_se_e32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {151; CHECK-LABEL: test_sf_vc_vv_se_e32mf2:152; CHECK:       # %bb.0: # %entry153; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma154; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v9155; CHECK-NEXT:    ret156entry:157  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1i32.nxv1i32.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)158  ret void159}160 161define void @test_sf_vc_vv_se_e32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {162; CHECK-LABEL: test_sf_vc_vv_se_e32m1:163; CHECK:       # %bb.0: # %entry164; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma165; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v9166; CHECK-NEXT:    ret167entry:168  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2i32.nxv2i32.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)169  ret void170}171 172define void @test_sf_vc_vv_se_e32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {173; CHECK-LABEL: test_sf_vc_vv_se_e32m2:174; CHECK:       # %bb.0: # %entry175; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma176; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v10177; CHECK-NEXT:    ret178entry:179  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4i32.nxv4i32.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)180  ret void181}182 183define void @test_sf_vc_vv_se_e32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {184; CHECK-LABEL: test_sf_vc_vv_se_e32m4:185; CHECK:       # %bb.0: # %entry186; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma187; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v12188; CHECK-NEXT:    ret189entry:190  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8i32.nxv8i32.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)191  ret void192}193 194define void @test_sf_vc_vv_se_e32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {195; CHECK-LABEL: test_sf_vc_vv_se_e32m8:196; CHECK:       # %bb.0: # %entry197; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma198; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v16199; CHECK-NEXT:    ret200entry:201  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16i32.nxv16i32.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)202  ret void203}204 205define void @test_sf_vc_vv_se_e64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {206; CHECK-LABEL: test_sf_vc_vv_se_e64m1:207; CHECK:       # %bb.0: # %entry208; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma209; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v9210; CHECK-NEXT:    ret211entry:212  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1i64.nxv1i64.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)213  ret void214}215 216define void @test_sf_vc_vv_se_e64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {217; CHECK-LABEL: test_sf_vc_vv_se_e64m2:218; CHECK:       # %bb.0: # %entry219; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma220; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v10221; CHECK-NEXT:    ret222entry:223  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2i64.nxv2i64.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)224  ret void225}226 227define void @test_sf_vc_vv_se_e64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {228; CHECK-LABEL: test_sf_vc_vv_se_e64m4:229; CHECK:       # %bb.0: # %entry230; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma231; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v12232; CHECK-NEXT:    ret233entry:234  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4i64.nxv4i64.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)235  ret void236}237 238define void @test_sf_vc_vv_se_e64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {239; CHECK-LABEL: test_sf_vc_vv_se_e64m8:240; CHECK:       # %bb.0: # %entry241; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma242; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v16243; CHECK-NEXT:    ret244entry:245  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8i64.nxv8i64.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)246  ret void247}248 249define <vscale x 1 x i8> @test_sf_vc_v_vv_se_e8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {250; CHECK-LABEL: test_sf_vc_v_vv_se_e8mf8:251; CHECK:       # %bb.0: # %entry252; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma253; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9254; CHECK-NEXT:    ret255entry:256  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv1i8.iXLen.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)257  ret <vscale x 1 x i8> %0258}259 260define <vscale x 2 x i8> @test_sf_vc_v_vv_se_e8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {261; CHECK-LABEL: test_sf_vc_v_vv_se_e8mf4:262; CHECK:       # %bb.0: # %entry263; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma264; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9265; CHECK-NEXT:    ret266entry:267  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv2i8.iXLen.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)268  ret <vscale x 2 x i8> %0269}270 271define <vscale x 4 x i8> @test_sf_vc_v_vv_se_e8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {272; CHECK-LABEL: test_sf_vc_v_vv_se_e8mf2:273; CHECK:       # %bb.0: # %entry274; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma275; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9276; CHECK-NEXT:    ret277entry:278  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv4i8.iXLen.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)279  ret <vscale x 4 x i8> %0280}281 282define <vscale x 8 x i8> @test_sf_vc_v_vv_se_e8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {283; CHECK-LABEL: test_sf_vc_v_vv_se_e8m1:284; CHECK:       # %bb.0: # %entry285; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma286; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9287; CHECK-NEXT:    ret288entry:289  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv8i8.iXLen.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)290  ret <vscale x 8 x i8> %0291}292 293define <vscale x 16 x i8> @test_sf_vc_v_vv_se_e8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {294; CHECK-LABEL: test_sf_vc_v_vv_se_e8m2:295; CHECK:       # %bb.0: # %entry296; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma297; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10298; CHECK-NEXT:    ret299entry:300  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv16i8.iXLen.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)301  ret <vscale x 16 x i8> %0302}303 304define <vscale x 32 x i8> @test_sf_vc_v_vv_se_e8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {305; CHECK-LABEL: test_sf_vc_v_vv_se_e8m4:306; CHECK:       # %bb.0: # %entry307; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma308; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12309; CHECK-NEXT:    ret310entry:311  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv32i8.iXLen.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)312  ret <vscale x 32 x i8> %0313}314 315define <vscale x 64 x i8> @test_sf_vc_v_vv_se_e8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl) {316; CHECK-LABEL: test_sf_vc_v_vv_se_e8m8:317; CHECK:       # %bb.0: # %entry318; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma319; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16320; CHECK-NEXT:    ret321entry:322  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vv.se.nxv64i8.iXLen.nxv64i8.iXLen(iXLen 3, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl)323  ret <vscale x 64 x i8> %0324}325 326define <vscale x 1 x i16> @test_sf_vc_v_vv_se_e16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {327; CHECK-LABEL: test_sf_vc_v_vv_se_e16mf4:328; CHECK:       # %bb.0: # %entry329; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma330; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9331; CHECK-NEXT:    ret332entry:333  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv1i16.iXLen.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)334  ret <vscale x 1 x i16> %0335}336 337define <vscale x 2 x i16> @test_sf_vc_v_vv_se_e16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {338; CHECK-LABEL: test_sf_vc_v_vv_se_e16mf2:339; CHECK:       # %bb.0: # %entry340; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma341; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9342; CHECK-NEXT:    ret343entry:344  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv2i16.iXLen.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)345  ret <vscale x 2 x i16> %0346}347 348define <vscale x 4 x i16> @test_sf_vc_v_vv_se_e16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {349; CHECK-LABEL: test_sf_vc_v_vv_se_e16m1:350; CHECK:       # %bb.0: # %entry351; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma352; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9353; CHECK-NEXT:    ret354entry:355  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv4i16.iXLen.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)356  ret <vscale x 4 x i16> %0357}358 359define <vscale x 8 x i16> @test_sf_vc_v_vv_se_e16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {360; CHECK-LABEL: test_sf_vc_v_vv_se_e16m2:361; CHECK:       # %bb.0: # %entry362; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma363; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10364; CHECK-NEXT:    ret365entry:366  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv8i16.iXLen.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)367  ret <vscale x 8 x i16> %0368}369 370define <vscale x 16 x i16> @test_sf_vc_v_vv_se_e16m4(<vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {371; CHECK-LABEL: test_sf_vc_v_vv_se_e16m4:372; CHECK:       # %bb.0: # %entry373; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma374; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12375; CHECK-NEXT:    ret376entry:377  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv16i16.iXLen.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)378  ret <vscale x 16 x i16> %0379}380 381define <vscale x 32 x i16> @test_sf_vc_v_vv_se_e16m8(<vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {382; CHECK-LABEL: test_sf_vc_v_vv_se_e16m8:383; CHECK:       # %bb.0: # %entry384; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma385; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16386; CHECK-NEXT:    ret387entry:388  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vv.se.nxv32i16.iXLen.nxv32i16.iXLen(iXLen 3, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)389  ret <vscale x 32 x i16> %0390}391 392define <vscale x 1 x i32> @test_sf_vc_v_vv_se_e32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {393; CHECK-LABEL: test_sf_vc_v_vv_se_e32mf2:394; CHECK:       # %bb.0: # %entry395; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma396; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9397; CHECK-NEXT:    ret398entry:399  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv1i32.iXLen.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)400  ret <vscale x 1 x i32> %0401}402 403define <vscale x 2 x i32> @test_sf_vc_v_vv_se_e32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {404; CHECK-LABEL: test_sf_vc_v_vv_se_e32m1:405; CHECK:       # %bb.0: # %entry406; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma407; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9408; CHECK-NEXT:    ret409entry:410  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv2i32.iXLen.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)411  ret <vscale x 2 x i32> %0412}413 414define <vscale x 4 x i32> @test_sf_vc_v_vv_se_e32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {415; CHECK-LABEL: test_sf_vc_v_vv_se_e32m2:416; CHECK:       # %bb.0: # %entry417; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma418; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10419; CHECK-NEXT:    ret420entry:421  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv4i32.iXLen.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)422  ret <vscale x 4 x i32> %0423}424 425define <vscale x 8 x i32> @test_sf_vc_v_vv_se_e32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {426; CHECK-LABEL: test_sf_vc_v_vv_se_e32m4:427; CHECK:       # %bb.0: # %entry428; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma429; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12430; CHECK-NEXT:    ret431entry:432  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv8i32.iXLen.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)433  ret <vscale x 8 x i32> %0434}435 436define <vscale x 16 x i32> @test_sf_vc_v_vv_se_e32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {437; CHECK-LABEL: test_sf_vc_v_vv_se_e32m8:438; CHECK:       # %bb.0: # %entry439; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma440; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16441; CHECK-NEXT:    ret442entry:443  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv16i32.iXLen.nxv16i32.iXLen(iXLen 3, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)444  ret <vscale x 16 x i32> %0445}446 447define <vscale x 1 x i64> @test_sf_vc_v_vv_se_e64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {448; CHECK-LABEL: test_sf_vc_v_vv_se_e64m1:449; CHECK:       # %bb.0: # %entry450; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma451; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9452; CHECK-NEXT:    ret453entry:454  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv1i64.iXLen.nxv1i64.iXLen(iXLen 3, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)455  ret <vscale x 1 x i64> %0456}457 458define <vscale x 2 x i64> @test_sf_vc_v_vv_se_e64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {459; CHECK-LABEL: test_sf_vc_v_vv_se_e64m2:460; CHECK:       # %bb.0: # %entry461; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma462; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10463; CHECK-NEXT:    ret464entry:465  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv2i64.iXLen.nxv2i64.iXLen(iXLen 3, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)466  ret <vscale x 2 x i64> %0467}468 469define <vscale x 4 x i64> @test_sf_vc_v_vv_se_e64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {470; CHECK-LABEL: test_sf_vc_v_vv_se_e64m4:471; CHECK:       # %bb.0: # %entry472; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma473; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12474; CHECK-NEXT:    ret475entry:476  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv4i64.iXLen.nxv4i64.iXLen(iXLen 3, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)477  ret <vscale x 4 x i64> %0478}479 480define <vscale x 8 x i64> @test_sf_vc_v_vv_se_e64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {481; CHECK-LABEL: test_sf_vc_v_vv_se_e64m8:482; CHECK:       # %bb.0: # %entry483; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma484; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16485; CHECK-NEXT:    ret486entry:487  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vv.se.nxv8i64.iXLen.nxv8i64.iXLen(iXLen 3, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)488  ret <vscale x 8 x i64> %0489}490 491define <vscale x 1 x i8> @test_sf_vc_v_vv_e8mf8(<vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {492; CHECK-LABEL: test_sf_vc_v_vv_e8mf8:493; CHECK:       # %bb.0: # %entry494; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma495; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9496; CHECK-NEXT:    ret497entry:498  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vv.nxv1i8.iXLen.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)499  ret <vscale x 1 x i8> %0500}501 502define <vscale x 2 x i8> @test_sf_vc_v_vv_e8mf4(<vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {503; CHECK-LABEL: test_sf_vc_v_vv_e8mf4:504; CHECK:       # %bb.0: # %entry505; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma506; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9507; CHECK-NEXT:    ret508entry:509  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vv.nxv2i8.iXLen.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)510  ret <vscale x 2 x i8> %0511}512 513define <vscale x 4 x i8> @test_sf_vc_v_vv_e8mf2(<vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {514; CHECK-LABEL: test_sf_vc_v_vv_e8mf2:515; CHECK:       # %bb.0: # %entry516; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma517; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9518; CHECK-NEXT:    ret519entry:520  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vv.nxv4i8.iXLen.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)521  ret <vscale x 4 x i8> %0522}523 524define <vscale x 8 x i8> @test_sf_vc_v_vv_e8m1(<vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {525; CHECK-LABEL: test_sf_vc_v_vv_e8m1:526; CHECK:       # %bb.0: # %entry527; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma528; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9529; CHECK-NEXT:    ret530entry:531  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vv.nxv8i8.iXLen.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)532  ret <vscale x 8 x i8> %0533}534 535define <vscale x 16 x i8> @test_sf_vc_v_vv_e8m2(<vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {536; CHECK-LABEL: test_sf_vc_v_vv_e8m2:537; CHECK:       # %bb.0: # %entry538; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma539; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10540; CHECK-NEXT:    ret541entry:542  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vv.nxv16i8.iXLen.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)543  ret <vscale x 16 x i8> %0544}545 546define <vscale x 32 x i8> @test_sf_vc_v_vv_e8m4(<vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {547; CHECK-LABEL: test_sf_vc_v_vv_e8m4:548; CHECK:       # %bb.0: # %entry549; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma550; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12551; CHECK-NEXT:    ret552entry:553  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vv.nxv32i8.iXLen.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)554  ret <vscale x 32 x i8> %0555}556 557define <vscale x 64 x i8> @test_sf_vc_v_vv_e8m8(<vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl) {558; CHECK-LABEL: test_sf_vc_v_vv_e8m8:559; CHECK:       # %bb.0: # %entry560; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma561; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16562; CHECK-NEXT:    ret563entry:564  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vv.nxv64i8.iXLen.nxv64i8.iXLen(iXLen 3, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl)565  ret <vscale x 64 x i8> %0566}567 568define <vscale x 1 x i16> @test_sf_vc_v_vv_e16mf4(<vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {569; CHECK-LABEL: test_sf_vc_v_vv_e16mf4:570; CHECK:       # %bb.0: # %entry571; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma572; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9573; CHECK-NEXT:    ret574entry:575  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vv.nxv1i16.iXLen.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)576  ret <vscale x 1 x i16> %0577}578 579define <vscale x 2 x i16> @test_sf_vc_v_vv_e16mf2(<vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {580; CHECK-LABEL: test_sf_vc_v_vv_e16mf2:581; CHECK:       # %bb.0: # %entry582; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma583; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9584; CHECK-NEXT:    ret585entry:586  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vv.nxv2i16.iXLen.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)587  ret <vscale x 2 x i16> %0588}589 590define <vscale x 4 x i16> @test_sf_vc_v_vv_e16m1(<vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {591; CHECK-LABEL: test_sf_vc_v_vv_e16m1:592; CHECK:       # %bb.0: # %entry593; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma594; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9595; CHECK-NEXT:    ret596entry:597  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vv.nxv4i16.iXLen.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)598  ret <vscale x 4 x i16> %0599}600 601define <vscale x 8 x i16> @test_sf_vc_v_vv_e16m2(<vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {602; CHECK-LABEL: test_sf_vc_v_vv_e16m2:603; CHECK:       # %bb.0: # %entry604; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma605; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10606; CHECK-NEXT:    ret607entry:608  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vv.nxv8i16.iXLen.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)609  ret <vscale x 8 x i16> %0610}611 612define <vscale x 16 x i16> @test_sf_vc_v_vv_e16m4(<vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {613; CHECK-LABEL: test_sf_vc_v_vv_e16m4:614; CHECK:       # %bb.0: # %entry615; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma616; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12617; CHECK-NEXT:    ret618entry:619  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vv.nxv16i16.iXLen.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)620  ret <vscale x 16 x i16> %0621}622 623define <vscale x 32 x i16> @test_sf_vc_v_vv_e16m8(<vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {624; CHECK-LABEL: test_sf_vc_v_vv_e16m8:625; CHECK:       # %bb.0: # %entry626; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma627; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16628; CHECK-NEXT:    ret629entry:630  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vv.nxv32i16.iXLen.nxv32i16.iXLen(iXLen 3, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)631  ret <vscale x 32 x i16> %0632}633 634define <vscale x 1 x i32> @test_sf_vc_v_vv_e32mf2(<vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {635; CHECK-LABEL: test_sf_vc_v_vv_e32mf2:636; CHECK:       # %bb.0: # %entry637; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma638; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9639; CHECK-NEXT:    ret640entry:641  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vv.nxv1i32.iXLen.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)642  ret <vscale x 1 x i32> %0643}644 645define <vscale x 2 x i32> @test_sf_vc_v_vv_e32m1(<vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {646; CHECK-LABEL: test_sf_vc_v_vv_e32m1:647; CHECK:       # %bb.0: # %entry648; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma649; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9650; CHECK-NEXT:    ret651entry:652  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vv.nxv2i32.iXLen.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)653  ret <vscale x 2 x i32> %0654}655 656define <vscale x 4 x i32> @test_sf_vc_v_vv_e32m2(<vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {657; CHECK-LABEL: test_sf_vc_v_vv_e32m2:658; CHECK:       # %bb.0: # %entry659; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma660; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10661; CHECK-NEXT:    ret662entry:663  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.nxv4i32.iXLen.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)664  ret <vscale x 4 x i32> %0665}666 667define <vscale x 8 x i32> @test_sf_vc_v_vv_e32m4(<vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {668; CHECK-LABEL: test_sf_vc_v_vv_e32m4:669; CHECK:       # %bb.0: # %entry670; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma671; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12672; CHECK-NEXT:    ret673entry:674  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vv.nxv8i32.iXLen.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)675  ret <vscale x 8 x i32> %0676}677 678define <vscale x 16 x i32> @test_sf_vc_v_vv_e32m8(<vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {679; CHECK-LABEL: test_sf_vc_v_vv_e32m8:680; CHECK:       # %bb.0: # %entry681; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma682; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16683; CHECK-NEXT:    ret684entry:685  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vv.nxv16i32.iXLen.nxv16i32.iXLen(iXLen 3, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)686  ret <vscale x 16 x i32> %0687}688 689define <vscale x 1 x i64> @test_sf_vc_v_vv_e64m1(<vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {690; CHECK-LABEL: test_sf_vc_v_vv_e64m1:691; CHECK:       # %bb.0: # %entry692; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma693; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v9694; CHECK-NEXT:    ret695entry:696  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vv.nxv1i64.iXLen.nxv1i64.iXLen(iXLen 3, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)697  ret <vscale x 1 x i64> %0698}699 700define <vscale x 2 x i64> @test_sf_vc_v_vv_e64m2(<vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {701; CHECK-LABEL: test_sf_vc_v_vv_e64m2:702; CHECK:       # %bb.0: # %entry703; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma704; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v10705; CHECK-NEXT:    ret706entry:707  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vv.nxv2i64.iXLen.nxv2i64.iXLen(iXLen 3, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)708  ret <vscale x 2 x i64> %0709}710 711define <vscale x 4 x i64> @test_sf_vc_v_vv_e64m4(<vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {712; CHECK-LABEL: test_sf_vc_v_vv_e64m4:713; CHECK:       # %bb.0: # %entry714; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma715; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v12716; CHECK-NEXT:    ret717entry:718  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vv.nxv4i64.iXLen.nxv4i64.iXLen(iXLen 3, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)719  ret <vscale x 4 x i64> %0720}721 722define <vscale x 8 x i64> @test_sf_vc_v_vv_e64m8(<vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {723; CHECK-LABEL: test_sf_vc_v_vv_e64m8:724; CHECK:       # %bb.0: # %entry725; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma726; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v16727; CHECK-NEXT:    ret728entry:729  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vv.nxv8i64.iXLen.nxv8i64.iXLen(iXLen 3, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)730  ret <vscale x 8 x i64> %0731}732 733define void @test_sf_vc_xv_se_e8mf8(<vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {734; CHECK-LABEL: test_sf_vc_xv_se_e8mf8:735; CHECK:       # %bb.0: # %entry736; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma737; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0738; CHECK-NEXT:    ret739entry:740  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv1i8.i8.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)741  ret void742}743 744define void @test_sf_vc_xv_se_e8mf4(<vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {745; CHECK-LABEL: test_sf_vc_xv_se_e8mf4:746; CHECK:       # %bb.0: # %entry747; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma748; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0749; CHECK-NEXT:    ret750entry:751  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv2i8.i8.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)752  ret void753}754 755define void @test_sf_vc_xv_se_e8mf2(<vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {756; CHECK-LABEL: test_sf_vc_xv_se_e8mf2:757; CHECK:       # %bb.0: # %entry758; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma759; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0760; CHECK-NEXT:    ret761entry:762  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv4i8.i8.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)763  ret void764}765 766define void @test_sf_vc_xv_se_e8m1(<vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {767; CHECK-LABEL: test_sf_vc_xv_se_e8m1:768; CHECK:       # %bb.0: # %entry769; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma770; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0771; CHECK-NEXT:    ret772entry:773  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv8i8.i8.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)774  ret void775}776 777define void @test_sf_vc_xv_se_e8m2(<vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {778; CHECK-LABEL: test_sf_vc_xv_se_e8m2:779; CHECK:       # %bb.0: # %entry780; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma781; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0782; CHECK-NEXT:    ret783entry:784  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv16i8.i8.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)785  ret void786}787 788define void @test_sf_vc_xv_se_e8m4(<vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {789; CHECK-LABEL: test_sf_vc_xv_se_e8m4:790; CHECK:       # %bb.0: # %entry791; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma792; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0793; CHECK-NEXT:    ret794entry:795  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv32i8.i8.iXLen(iXLen 3, iXLen 31, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)796  ret void797}798 799define void @test_sf_vc_xv_se_e8m8(<vscale x 64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {800; CHECK-LABEL: test_sf_vc_xv_se_e8m8:801; CHECK:       # %bb.0: # %entry802; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma803; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0804; CHECK-NEXT:    ret805entry:806  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv64i8.i8.iXLen(iXLen 3, iXLen 31, <vscale x 64 x i8> %vs2, i8 %rs1, iXLen %vl)807  ret void808}809 810define void @test_sf_vc_xv_se_e16mf4(<vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {811; CHECK-LABEL: test_sf_vc_xv_se_e16mf4:812; CHECK:       # %bb.0: # %entry813; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma814; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0815; CHECK-NEXT:    ret816entry:817  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv1i16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)818  ret void819}820 821define void @test_sf_vc_xv_se_e16mf2(<vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {822; CHECK-LABEL: test_sf_vc_xv_se_e16mf2:823; CHECK:       # %bb.0: # %entry824; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma825; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0826; CHECK-NEXT:    ret827entry:828  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv2i16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)829  ret void830}831 832define void @test_sf_vc_xv_se_e16m1(<vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {833; CHECK-LABEL: test_sf_vc_xv_se_e16m1:834; CHECK:       # %bb.0: # %entry835; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma836; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0837; CHECK-NEXT:    ret838entry:839  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv4i16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)840  ret void841}842 843define void @test_sf_vc_xv_se_e16m2(<vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {844; CHECK-LABEL: test_sf_vc_xv_se_e16m2:845; CHECK:       # %bb.0: # %entry846; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma847; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0848; CHECK-NEXT:    ret849entry:850  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv8i16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)851  ret void852}853 854define void @test_sf_vc_xv_se_e16m4(<vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {855; CHECK-LABEL: test_sf_vc_xv_se_e16m4:856; CHECK:       # %bb.0: # %entry857; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma858; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0859; CHECK-NEXT:    ret860entry:861  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv16i16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)862  ret void863}864 865define void @test_sf_vc_xv_se_e16m8(<vscale x 32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {866; CHECK-LABEL: test_sf_vc_xv_se_e16m8:867; CHECK:       # %bb.0: # %entry868; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma869; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0870; CHECK-NEXT:    ret871entry:872  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv32i16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)873  ret void874}875 876define void @test_sf_vc_xv_se_e32mf2(<vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {877; CHECK-LABEL: test_sf_vc_xv_se_e32mf2:878; CHECK:       # %bb.0: # %entry879; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma880; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0881; CHECK-NEXT:    ret882entry:883  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv1i32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)884  ret void885}886 887define void @test_sf_vc_xv_se_e32m1(<vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {888; CHECK-LABEL: test_sf_vc_xv_se_e32m1:889; CHECK:       # %bb.0: # %entry890; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma891; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0892; CHECK-NEXT:    ret893entry:894  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv2i32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)895  ret void896}897 898define void @test_sf_vc_xv_se_e32m2(<vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {899; CHECK-LABEL: test_sf_vc_xv_se_e32m2:900; CHECK:       # %bb.0: # %entry901; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma902; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0903; CHECK-NEXT:    ret904entry:905  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv4i32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)906  ret void907}908 909define void @test_sf_vc_xv_se_e32m4(<vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {910; CHECK-LABEL: test_sf_vc_xv_se_e32m4:911; CHECK:       # %bb.0: # %entry912; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma913; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0914; CHECK-NEXT:    ret915entry:916  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv8i32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)917  ret void918}919 920define void @test_sf_vc_xv_se_e32m8(<vscale x 16 x i32> %vs2, i32 signext %rs1, iXLen %vl) {921; CHECK-LABEL: test_sf_vc_xv_se_e32m8:922; CHECK:       # %bb.0: # %entry923; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma924; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a0925; CHECK-NEXT:    ret926entry:927  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv16i32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)928  ret void929}930 931define <vscale x 1 x i8> @test_sf_vc_v_xv_se_e8mf8(<vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {932; CHECK-LABEL: test_sf_vc_v_xv_se_e8mf8:933; CHECK:       # %bb.0: # %entry934; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma935; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a0936; CHECK-NEXT:    ret937entry:938  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv1i8.iXLen.i8.iXLen(iXLen 3, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)939  ret <vscale x 1 x i8> %0940}941 942define <vscale x 2 x i8> @test_sf_vc_v_xv_se_e8mf4(<vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {943; CHECK-LABEL: test_sf_vc_v_xv_se_e8mf4:944; CHECK:       # %bb.0: # %entry945; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma946; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a0947; CHECK-NEXT:    ret948entry:949  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv2i8.iXLen.i8.iXLen(iXLen 3, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)950  ret <vscale x 2 x i8> %0951}952 953define <vscale x 4 x i8> @test_sf_vc_v_xv_se_e8mf2(<vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {954; CHECK-LABEL: test_sf_vc_v_xv_se_e8mf2:955; CHECK:       # %bb.0: # %entry956; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma957; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a0958; CHECK-NEXT:    ret959entry:960  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv4i8.iXLen.i8.iXLen(iXLen 3, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)961  ret <vscale x 4 x i8> %0962}963 964define <vscale x 8 x i8> @test_sf_vc_v_xv_se_e8m1(<vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {965; CHECK-LABEL: test_sf_vc_v_xv_se_e8m1:966; CHECK:       # %bb.0: # %entry967; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma968; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a0969; CHECK-NEXT:    ret970entry:971  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv8i8.iXLen.i8.iXLen(iXLen 3, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)972  ret <vscale x 8 x i8> %0973}974 975define <vscale x 16 x i8> @test_sf_vc_v_xv_se_e8m2(<vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {976; CHECK-LABEL: test_sf_vc_v_xv_se_e8m2:977; CHECK:       # %bb.0: # %entry978; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma979; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a0980; CHECK-NEXT:    ret981entry:982  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv16i8.iXLen.i8.iXLen(iXLen 3, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)983  ret <vscale x 16 x i8> %0984}985 986define <vscale x 32 x i8> @test_sf_vc_v_xv_se_e8m4(<vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {987; CHECK-LABEL: test_sf_vc_v_xv_se_e8m4:988; CHECK:       # %bb.0: # %entry989; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma990; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a0991; CHECK-NEXT:    ret992entry:993  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv32i8.iXLen.i8.iXLen(iXLen 3, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)994  ret <vscale x 32 x i8> %0995}996 997define <vscale x 64 x i8> @test_sf_vc_v_xv_se_e8m8(<vscale x 64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {998; CHECK-LABEL: test_sf_vc_v_xv_se_e8m8:999; CHECK:       # %bb.0: # %entry1000; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma1001; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01002; CHECK-NEXT:    ret1003entry:1004  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xv.se.nxv64i8.iXLen.i8.iXLen(iXLen 3, <vscale x 64 x i8> %vs2, i8 %rs1, iXLen %vl)1005  ret <vscale x 64 x i8> %01006}1007 1008define <vscale x 1 x i16> @test_sf_vc_v_xv_se_e16mf4(<vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1009; CHECK-LABEL: test_sf_vc_v_xv_se_e16mf4:1010; CHECK:       # %bb.0: # %entry1011; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1012; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01013; CHECK-NEXT:    ret1014entry:1015  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv1i16.iXLen.i16.iXLen(iXLen 3, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)1016  ret <vscale x 1 x i16> %01017}1018 1019define <vscale x 2 x i16> @test_sf_vc_v_xv_se_e16mf2(<vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1020; CHECK-LABEL: test_sf_vc_v_xv_se_e16mf2:1021; CHECK:       # %bb.0: # %entry1022; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1023; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01024; CHECK-NEXT:    ret1025entry:1026  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv2i16.iXLen.i16.iXLen(iXLen 3, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)1027  ret <vscale x 2 x i16> %01028}1029 1030define <vscale x 4 x i16> @test_sf_vc_v_xv_se_e16m1(<vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1031; CHECK-LABEL: test_sf_vc_v_xv_se_e16m1:1032; CHECK:       # %bb.0: # %entry1033; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1034; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01035; CHECK-NEXT:    ret1036entry:1037  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv4i16.iXLen.i16.iXLen(iXLen 3, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)1038  ret <vscale x 4 x i16> %01039}1040 1041define <vscale x 8 x i16> @test_sf_vc_v_xv_se_e16m2(<vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1042; CHECK-LABEL: test_sf_vc_v_xv_se_e16m2:1043; CHECK:       # %bb.0: # %entry1044; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1045; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01046; CHECK-NEXT:    ret1047entry:1048  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv8i16.iXLen.i16.iXLen(iXLen 3, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)1049  ret <vscale x 8 x i16> %01050}1051 1052define <vscale x 16 x i16> @test_sf_vc_v_xv_se_e16m4(<vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1053; CHECK-LABEL: test_sf_vc_v_xv_se_e16m4:1054; CHECK:       # %bb.0: # %entry1055; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1056; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01057; CHECK-NEXT:    ret1058entry:1059  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv16i16.iXLen.i16.iXLen(iXLen 3, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)1060  ret <vscale x 16 x i16> %01061}1062 1063define <vscale x 32 x i16> @test_sf_vc_v_xv_se_e16m8(<vscale x 32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1064; CHECK-LABEL: test_sf_vc_v_xv_se_e16m8:1065; CHECK:       # %bb.0: # %entry1066; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1067; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01068; CHECK-NEXT:    ret1069entry:1070  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xv.se.nxv32i16.iXLen.i16.iXLen(iXLen 3, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)1071  ret <vscale x 32 x i16> %01072}1073 1074define <vscale x 1 x i32> @test_sf_vc_v_xv_se_e32mf2(<vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1075; CHECK-LABEL: test_sf_vc_v_xv_se_e32mf2:1076; CHECK:       # %bb.0: # %entry1077; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1078; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01079; CHECK-NEXT:    ret1080entry:1081  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv1i32.i32.i32.iXLen(iXLen 3, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)1082  ret <vscale x 1 x i32> %01083}1084 1085define <vscale x 2 x i32> @test_sf_vc_v_xv_se_e32m1(<vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1086; CHECK-LABEL: test_sf_vc_v_xv_se_e32m1:1087; CHECK:       # %bb.0: # %entry1088; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1089; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01090; CHECK-NEXT:    ret1091entry:1092  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv2i32.i32.i32.iXLen(iXLen 3, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)1093  ret <vscale x 2 x i32> %01094}1095 1096define <vscale x 4 x i32> @test_sf_vc_v_xv_se_e32m2(<vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1097; CHECK-LABEL: test_sf_vc_v_xv_se_e32m2:1098; CHECK:       # %bb.0: # %entry1099; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1100; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01101; CHECK-NEXT:    ret1102entry:1103  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i32.i32.iXLen(iXLen 3, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)1104  ret <vscale x 4 x i32> %01105}1106 1107define <vscale x 8 x i32> @test_sf_vc_v_xv_se_e32m4(<vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1108; CHECK-LABEL: test_sf_vc_v_xv_se_e32m4:1109; CHECK:       # %bb.0: # %entry1110; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1111; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01112; CHECK-NEXT:    ret1113entry:1114  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv8i32.i32.i32.iXLen(iXLen 3, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)1115  ret <vscale x 8 x i32> %01116}1117 1118define <vscale x 16 x i32> @test_sf_vc_v_xv_se_e32m8(<vscale x 16 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1119; CHECK-LABEL: test_sf_vc_v_xv_se_e32m8:1120; CHECK:       # %bb.0: # %entry1121; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1122; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01123; CHECK-NEXT:    ret1124entry:1125  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv16i32.i32.i32.iXLen(iXLen 3, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)1126  ret <vscale x 16 x i32> %01127}1128 1129define <vscale x 1 x i8> @test_sf_vc_v_xv_e8mf8(<vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1130; CHECK-LABEL: test_sf_vc_v_xv_e8mf8:1131; CHECK:       # %bb.0: # %entry1132; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma1133; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01134; CHECK-NEXT:    ret1135entry:1136  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xv.nxv1i8.iXLen.i8.iXLen(iXLen 3, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)1137  ret <vscale x 1 x i8> %01138}1139 1140define <vscale x 2 x i8> @test_sf_vc_v_xv_e8mf4(<vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1141; CHECK-LABEL: test_sf_vc_v_xv_e8mf4:1142; CHECK:       # %bb.0: # %entry1143; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma1144; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01145; CHECK-NEXT:    ret1146entry:1147  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xv.nxv2i8.iXLen.i8.iXLen(iXLen 3, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)1148  ret <vscale x 2 x i8> %01149}1150 1151define <vscale x 4 x i8> @test_sf_vc_v_xv_e8mf2(<vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1152; CHECK-LABEL: test_sf_vc_v_xv_e8mf2:1153; CHECK:       # %bb.0: # %entry1154; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma1155; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01156; CHECK-NEXT:    ret1157entry:1158  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xv.nxv4i8.iXLen.i8.iXLen(iXLen 3, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)1159  ret <vscale x 4 x i8> %01160}1161 1162define <vscale x 8 x i8> @test_sf_vc_v_xv_e8m1(<vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1163; CHECK-LABEL: test_sf_vc_v_xv_e8m1:1164; CHECK:       # %bb.0: # %entry1165; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma1166; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01167; CHECK-NEXT:    ret1168entry:1169  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xv.nxv8i8.iXLen.i8.iXLen(iXLen 3, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)1170  ret <vscale x 8 x i8> %01171}1172 1173define <vscale x 16 x i8> @test_sf_vc_v_xv_e8m2(<vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1174; CHECK-LABEL: test_sf_vc_v_xv_e8m2:1175; CHECK:       # %bb.0: # %entry1176; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma1177; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01178; CHECK-NEXT:    ret1179entry:1180  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xv.nxv16i8.iXLen.i8.iXLen(iXLen 3, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)1181  ret <vscale x 16 x i8> %01182}1183 1184define <vscale x 32 x i8> @test_sf_vc_v_xv_e8m4(<vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1185; CHECK-LABEL: test_sf_vc_v_xv_e8m4:1186; CHECK:       # %bb.0: # %entry1187; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma1188; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01189; CHECK-NEXT:    ret1190entry:1191  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xv.nxv32i8.iXLen.i8.iXLen(iXLen 3, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)1192  ret <vscale x 32 x i8> %01193}1194 1195define <vscale x 64 x i8> @test_sf_vc_v_xv_e8m8(<vscale x 64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1196; CHECK-LABEL: test_sf_vc_v_xv_e8m8:1197; CHECK:       # %bb.0: # %entry1198; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma1199; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01200; CHECK-NEXT:    ret1201entry:1202  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xv.nxv64i8.iXLen.i8.iXLen(iXLen 3, <vscale x 64 x i8> %vs2, i8 %rs1, iXLen %vl)1203  ret <vscale x 64 x i8> %01204}1205 1206define <vscale x 1 x i16> @test_sf_vc_v_xv_e16mf4(<vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1207; CHECK-LABEL: test_sf_vc_v_xv_e16mf4:1208; CHECK:       # %bb.0: # %entry1209; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1210; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01211; CHECK-NEXT:    ret1212entry:1213  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xv.nxv1i16.iXLen.i16.iXLen(iXLen 3, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)1214  ret <vscale x 1 x i16> %01215}1216 1217define <vscale x 2 x i16> @test_sf_vc_v_xv_e16mf2(<vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1218; CHECK-LABEL: test_sf_vc_v_xv_e16mf2:1219; CHECK:       # %bb.0: # %entry1220; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1221; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01222; CHECK-NEXT:    ret1223entry:1224  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xv.nxv2i16.iXLen.i16.iXLen(iXLen 3, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)1225  ret <vscale x 2 x i16> %01226}1227 1228define <vscale x 4 x i16> @test_sf_vc_v_xv_e16m1(<vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1229; CHECK-LABEL: test_sf_vc_v_xv_e16m1:1230; CHECK:       # %bb.0: # %entry1231; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1232; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01233; CHECK-NEXT:    ret1234entry:1235  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xv.nxv4i16.iXLen.i16.iXLen(iXLen 3, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)1236  ret <vscale x 4 x i16> %01237}1238 1239define <vscale x 8 x i16> @test_sf_vc_v_xv_e16m2(<vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1240; CHECK-LABEL: test_sf_vc_v_xv_e16m2:1241; CHECK:       # %bb.0: # %entry1242; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1243; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01244; CHECK-NEXT:    ret1245entry:1246  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xv.nxv8i16.iXLen.i16.iXLen(iXLen 3, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)1247  ret <vscale x 8 x i16> %01248}1249 1250define <vscale x 16 x i16> @test_sf_vc_v_xv_e16m4(<vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1251; CHECK-LABEL: test_sf_vc_v_xv_e16m4:1252; CHECK:       # %bb.0: # %entry1253; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1254; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01255; CHECK-NEXT:    ret1256entry:1257  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xv.nxv16i16.iXLen.i16.iXLen(iXLen 3, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)1258  ret <vscale x 16 x i16> %01259}1260 1261define <vscale x 32 x i16> @test_sf_vc_v_xv_e16m8(<vscale x 32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1262; CHECK-LABEL: test_sf_vc_v_xv_e16m8:1263; CHECK:       # %bb.0: # %entry1264; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1265; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01266; CHECK-NEXT:    ret1267entry:1268  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xv.nxv32i16.iXLen.i16.iXLen(iXLen 3, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)1269  ret <vscale x 32 x i16> %01270}1271 1272define <vscale x 1 x i32> @test_sf_vc_v_xv_e32mf2(<vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1273; CHECK-LABEL: test_sf_vc_v_xv_e32mf2:1274; CHECK:       # %bb.0: # %entry1275; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1276; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01277; CHECK-NEXT:    ret1278entry:1279  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xv.nxv1i32.i32.i32.iXLen(iXLen 3, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)1280  ret <vscale x 1 x i32> %01281}1282 1283define <vscale x 2 x i32> @test_sf_vc_v_xv_e32m1(<vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1284; CHECK-LABEL: test_sf_vc_v_xv_e32m1:1285; CHECK:       # %bb.0: # %entry1286; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1287; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01288; CHECK-NEXT:    ret1289entry:1290  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xv.nxv2i32.i32.i32.iXLen(iXLen 3, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)1291  ret <vscale x 2 x i32> %01292}1293 1294define <vscale x 4 x i32> @test_sf_vc_v_xv_e32m2(<vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1295; CHECK-LABEL: test_sf_vc_v_xv_e32m2:1296; CHECK:       # %bb.0: # %entry1297; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1298; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01299; CHECK-NEXT:    ret1300entry:1301  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.nxv4i32.i32.i32.iXLen(iXLen 3, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)1302  ret <vscale x 4 x i32> %01303}1304 1305define <vscale x 8 x i32> @test_sf_vc_v_xv_e32m4(<vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1306; CHECK-LABEL: test_sf_vc_v_xv_e32m4:1307; CHECK:       # %bb.0: # %entry1308; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1309; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01310; CHECK-NEXT:    ret1311entry:1312  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xv.nxv8i32.i32.i32.iXLen(iXLen 3, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)1313  ret <vscale x 8 x i32> %01314}1315 1316define <vscale x 16 x i32> @test_sf_vc_v_xv_e32m8(<vscale x 16 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1317; CHECK-LABEL: test_sf_vc_v_xv_e32m8:1318; CHECK:       # %bb.0: # %entry1319; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1320; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a01321; CHECK-NEXT:    ret1322entry:1323  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xv.nxv16i32.i32.i32.iXLen(iXLen 3, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)1324  ret <vscale x 16 x i32> %01325}1326 1327define void @test_sf_vc_iv_se_e8mf8(<vscale x 1 x i8> %vs2, iXLen %vl) {1328; CHECK-LABEL: test_sf_vc_iv_se_e8mf8:1329; CHECK:       # %bb.0: # %entry1330; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1331; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101332; CHECK-NEXT:    ret1333entry:1334  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i8.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1335  ret void1336}1337 1338define void @test_sf_vc_iv_se_e8mf4(<vscale x 2 x i8> %vs2, iXLen %vl) {1339; CHECK-LABEL: test_sf_vc_iv_se_e8mf4:1340; CHECK:       # %bb.0: # %entry1341; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1342; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101343; CHECK-NEXT:    ret1344entry:1345  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv2i8.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1346  ret void1347}1348 1349define void @test_sf_vc_iv_se_e8mf2(<vscale x 4 x i8> %vs2, iXLen %vl) {1350; CHECK-LABEL: test_sf_vc_iv_se_e8mf2:1351; CHECK:       # %bb.0: # %entry1352; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1353; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101354; CHECK-NEXT:    ret1355entry:1356  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv4i8.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1357  ret void1358}1359 1360define void @test_sf_vc_iv_se_e8m1(<vscale x 8 x i8> %vs2, iXLen %vl) {1361; CHECK-LABEL: test_sf_vc_iv_se_e8m1:1362; CHECK:       # %bb.0: # %entry1363; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1364; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101365; CHECK-NEXT:    ret1366entry:1367  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv8i8.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1368  ret void1369}1370 1371define void @test_sf_vc_iv_se_e8m2(<vscale x 16 x i8> %vs2, iXLen %vl) {1372; CHECK-LABEL: test_sf_vc_iv_se_e8m2:1373; CHECK:       # %bb.0: # %entry1374; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1375; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101376; CHECK-NEXT:    ret1377entry:1378  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv16i8.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1379  ret void1380}1381 1382define void @test_sf_vc_iv_se_e8m4(<vscale x 32 x i8> %vs2, iXLen %vl) {1383; CHECK-LABEL: test_sf_vc_iv_se_e8m4:1384; CHECK:       # %bb.0: # %entry1385; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1386; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101387; CHECK-NEXT:    ret1388entry:1389  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv32i8.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1390  ret void1391}1392 1393define void @test_sf_vc_iv_se_e8m8(<vscale x 64 x i8> %vs2, iXLen %vl) {1394; CHECK-LABEL: test_sf_vc_iv_se_e8m8:1395; CHECK:       # %bb.0: # %entry1396; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma1397; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101398; CHECK-NEXT:    ret1399entry:1400  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv64i8.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 64 x i8> %vs2, iXLen 10, iXLen %vl)1401  ret void1402}1403 1404define void @test_sf_vc_iv_se_e16mf4(<vscale x 1 x i16> %vs2, iXLen %vl) {1405; CHECK-LABEL: test_sf_vc_iv_se_e16mf4:1406; CHECK:       # %bb.0: # %entry1407; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1408; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101409; CHECK-NEXT:    ret1410entry:1411  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1412  ret void1413}1414 1415define void @test_sf_vc_iv_se_e16mf2(<vscale x 2 x i16> %vs2, iXLen %vl) {1416; CHECK-LABEL: test_sf_vc_iv_se_e16mf2:1417; CHECK:       # %bb.0: # %entry1418; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1419; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101420; CHECK-NEXT:    ret1421entry:1422  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv2i16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1423  ret void1424}1425 1426define void @test_sf_vc_iv_se_e16m1(<vscale x 4 x i16> %vs2, iXLen %vl) {1427; CHECK-LABEL: test_sf_vc_iv_se_e16m1:1428; CHECK:       # %bb.0: # %entry1429; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1430; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101431; CHECK-NEXT:    ret1432entry:1433  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv4i16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1434  ret void1435}1436 1437define void @test_sf_vc_iv_se_e16m2(<vscale x 8 x i16> %vs2, iXLen %vl) {1438; CHECK-LABEL: test_sf_vc_iv_se_e16m2:1439; CHECK:       # %bb.0: # %entry1440; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1441; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101442; CHECK-NEXT:    ret1443entry:1444  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv8i16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1445  ret void1446}1447 1448define void @test_sf_vc_iv_se_e16m4(<vscale x 16 x i16> %vs2, iXLen %vl) {1449; CHECK-LABEL: test_sf_vc_iv_se_e16m4:1450; CHECK:       # %bb.0: # %entry1451; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1452; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101453; CHECK-NEXT:    ret1454entry:1455  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv16i16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1456  ret void1457}1458 1459define void @test_sf_vc_iv_se_e16m8(<vscale x 32 x i16> %vs2, iXLen %vl) {1460; CHECK-LABEL: test_sf_vc_iv_se_e16m8:1461; CHECK:       # %bb.0: # %entry1462; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1463; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101464; CHECK-NEXT:    ret1465entry:1466  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv32i16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 32 x i16> %vs2, iXLen 10, iXLen %vl)1467  ret void1468}1469 1470define void @test_sf_vc_iv_se_e32mf2(<vscale x 1 x i32> %vs2, iXLen %vl) {1471; CHECK-LABEL: test_sf_vc_iv_se_e32mf2:1472; CHECK:       # %bb.0: # %entry1473; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1474; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101475; CHECK-NEXT:    ret1476entry:1477  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1478  ret void1479}1480 1481define void @test_sf_vc_iv_se_e32m1(<vscale x 2 x i32> %vs2, iXLen %vl) {1482; CHECK-LABEL: test_sf_vc_iv_se_e32m1:1483; CHECK:       # %bb.0: # %entry1484; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1485; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101486; CHECK-NEXT:    ret1487entry:1488  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv2i32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1489  ret void1490}1491 1492define void @test_sf_vc_iv_se_e32m2(<vscale x 4 x i32> %vs2, iXLen %vl) {1493; CHECK-LABEL: test_sf_vc_iv_se_e32m2:1494; CHECK:       # %bb.0: # %entry1495; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1496; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101497; CHECK-NEXT:    ret1498entry:1499  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv4i32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1500  ret void1501}1502 1503define void @test_sf_vc_iv_se_e32m4(<vscale x 8 x i32> %vs2, iXLen %vl) {1504; CHECK-LABEL: test_sf_vc_iv_se_e32m4:1505; CHECK:       # %bb.0: # %entry1506; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1507; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101508; CHECK-NEXT:    ret1509entry:1510  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv8i32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1511  ret void1512}1513 1514define void @test_sf_vc_iv_se_e32m8(<vscale x 16 x i32> %vs2, iXLen %vl) {1515; CHECK-LABEL: test_sf_vc_iv_se_e32m8:1516; CHECK:       # %bb.0: # %entry1517; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1518; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101519; CHECK-NEXT:    ret1520entry:1521  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv16i32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 16 x i32> %vs2, iXLen 10, iXLen %vl)1522  ret void1523}1524 1525define void @test_sf_vc_iv_se_e64m1(<vscale x 1 x i64> %vs2, iXLen %vl) {1526; CHECK-LABEL: test_sf_vc_iv_se_e64m1:1527; CHECK:       # %bb.0: # %entry1528; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1529; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101530; CHECK-NEXT:    ret1531entry:1532  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 1 x i64> %vs2, iXLen 10, iXLen %vl)1533  ret void1534}1535 1536define void @test_sf_vc_iv_se_e64m2(<vscale x 2 x i64> %vs2, iXLen %vl) {1537; CHECK-LABEL: test_sf_vc_iv_se_e64m2:1538; CHECK:       # %bb.0: # %entry1539; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1540; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101541; CHECK-NEXT:    ret1542entry:1543  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv2i64.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 2 x i64> %vs2, iXLen 10, iXLen %vl)1544  ret void1545}1546 1547define void @test_sf_vc_iv_se_e64m4(<vscale x 4 x i64> %vs2, iXLen %vl) {1548; CHECK-LABEL: test_sf_vc_iv_se_e64m4:1549; CHECK:       # %bb.0: # %entry1550; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1551; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101552; CHECK-NEXT:    ret1553entry:1554  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv4i64.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 4 x i64> %vs2, iXLen 10, iXLen %vl)1555  ret void1556}1557 1558define void @test_sf_vc_iv_se_e64m8(<vscale x 8 x i64> %vs2, iXLen %vl) {1559; CHECK-LABEL: test_sf_vc_iv_se_e64m8:1560; CHECK:       # %bb.0: # %entry1561; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1562; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 101563; CHECK-NEXT:    ret1564entry:1565  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv8i64.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 8 x i64> %vs2, iXLen 10, iXLen %vl)1566  ret void1567}1568 1569define <vscale x 1 x i8> @test_sf_vc_v_iv_se_e8mf8(<vscale x 1 x i8> %vs2, iXLen %vl) {1570; CHECK-LABEL: test_sf_vc_v_iv_se_e8mf8:1571; CHECK:       # %bb.0: # %entry1572; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1573; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101574; CHECK-NEXT:    ret1575entry:1576  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1577  ret <vscale x 1 x i8> %01578}1579 1580define <vscale x 2 x i8> @test_sf_vc_v_iv_se_e8mf4(<vscale x 2 x i8> %vs2, iXLen %vl) {1581; CHECK-LABEL: test_sf_vc_v_iv_se_e8mf4:1582; CHECK:       # %bb.0: # %entry1583; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1584; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101585; CHECK-NEXT:    ret1586entry:1587  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1588  ret <vscale x 2 x i8> %01589}1590 1591define <vscale x 4 x i8> @test_sf_vc_v_iv_se_e8mf2(<vscale x 4 x i8> %vs2, iXLen %vl) {1592; CHECK-LABEL: test_sf_vc_v_iv_se_e8mf2:1593; CHECK:       # %bb.0: # %entry1594; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1595; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101596; CHECK-NEXT:    ret1597entry:1598  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1599  ret <vscale x 4 x i8> %01600}1601 1602define <vscale x 8 x i8> @test_sf_vc_v_iv_se_e8m1(<vscale x 8 x i8> %vs2, iXLen %vl) {1603; CHECK-LABEL: test_sf_vc_v_iv_se_e8m1:1604; CHECK:       # %bb.0: # %entry1605; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1606; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101607; CHECK-NEXT:    ret1608entry:1609  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1610  ret <vscale x 8 x i8> %01611}1612 1613define <vscale x 16 x i8> @test_sf_vc_v_iv_se_e8m2(<vscale x 16 x i8> %vs2, iXLen %vl) {1614; CHECK-LABEL: test_sf_vc_v_iv_se_e8m2:1615; CHECK:       # %bb.0: # %entry1616; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1617; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101618; CHECK-NEXT:    ret1619entry:1620  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1621  ret <vscale x 16 x i8> %01622}1623 1624define <vscale x 32 x i8> @test_sf_vc_v_iv_se_e8m4(<vscale x 32 x i8> %vs2, iXLen %vl) {1625; CHECK-LABEL: test_sf_vc_v_iv_se_e8m4:1626; CHECK:       # %bb.0: # %entry1627; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1628; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101629; CHECK-NEXT:    ret1630entry:1631  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1632  ret <vscale x 32 x i8> %01633}1634 1635define <vscale x 64 x i8> @test_sf_vc_v_iv_se_e8m8(<vscale x 64 x i8> %vs2, iXLen %vl) {1636; CHECK-LABEL: test_sf_vc_v_iv_se_e8m8:1637; CHECK:       # %bb.0: # %entry1638; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma1639; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101640; CHECK-NEXT:    ret1641entry:1642  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.iv.se.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 64 x i8> %vs2, iXLen 10, iXLen %vl)1643  ret <vscale x 64 x i8> %01644}1645 1646define <vscale x 1 x i16> @test_sf_vc_v_iv_se_e16mf4(<vscale x 1 x i16> %vs2, iXLen %vl) {1647; CHECK-LABEL: test_sf_vc_v_iv_se_e16mf4:1648; CHECK:       # %bb.0: # %entry1649; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1650; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101651; CHECK-NEXT:    ret1652entry:1653  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1654  ret <vscale x 1 x i16> %01655}1656 1657define <vscale x 2 x i16> @test_sf_vc_v_iv_se_e16mf2(<vscale x 2 x i16> %vs2, iXLen %vl) {1658; CHECK-LABEL: test_sf_vc_v_iv_se_e16mf2:1659; CHECK:       # %bb.0: # %entry1660; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1661; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101662; CHECK-NEXT:    ret1663entry:1664  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1665  ret <vscale x 2 x i16> %01666}1667 1668define <vscale x 4 x i16> @test_sf_vc_v_iv_se_e16m1(<vscale x 4 x i16> %vs2, iXLen %vl) {1669; CHECK-LABEL: test_sf_vc_v_iv_se_e16m1:1670; CHECK:       # %bb.0: # %entry1671; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1672; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101673; CHECK-NEXT:    ret1674entry:1675  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1676  ret <vscale x 4 x i16> %01677}1678 1679define <vscale x 8 x i16> @test_sf_vc_v_iv_se_e16m2(<vscale x 8 x i16> %vs2, iXLen %vl) {1680; CHECK-LABEL: test_sf_vc_v_iv_se_e16m2:1681; CHECK:       # %bb.0: # %entry1682; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1683; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101684; CHECK-NEXT:    ret1685entry:1686  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1687  ret <vscale x 8 x i16> %01688}1689 1690define <vscale x 16 x i16> @test_sf_vc_v_iv_se_e16m4(<vscale x 16 x i16> %vs2, iXLen %vl) {1691; CHECK-LABEL: test_sf_vc_v_iv_se_e16m4:1692; CHECK:       # %bb.0: # %entry1693; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1694; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101695; CHECK-NEXT:    ret1696entry:1697  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1698  ret <vscale x 16 x i16> %01699}1700 1701define <vscale x 32 x i16> @test_sf_vc_v_iv_se_e16m8(<vscale x 32 x i16> %vs2, iXLen %vl) {1702; CHECK-LABEL: test_sf_vc_v_iv_se_e16m8:1703; CHECK:       # %bb.0: # %entry1704; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1705; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101706; CHECK-NEXT:    ret1707entry:1708  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.iv.se.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vs2, iXLen 10, iXLen %vl)1709  ret <vscale x 32 x i16> %01710}1711 1712define <vscale x 1 x i32> @test_sf_vc_v_iv_se_e32mf2(<vscale x 1 x i32> %vs2, iXLen %vl) {1713; CHECK-LABEL: test_sf_vc_v_iv_se_e32mf2:1714; CHECK:       # %bb.0: # %entry1715; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1716; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101717; CHECK-NEXT:    ret1718entry:1719  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1720  ret <vscale x 1 x i32> %01721}1722 1723define <vscale x 2 x i32> @test_sf_vc_v_iv_se_e32m1(<vscale x 2 x i32> %vs2, iXLen %vl) {1724; CHECK-LABEL: test_sf_vc_v_iv_se_e32m1:1725; CHECK:       # %bb.0: # %entry1726; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1727; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101728; CHECK-NEXT:    ret1729entry:1730  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1731  ret <vscale x 2 x i32> %01732}1733 1734define <vscale x 4 x i32> @test_sf_vc_v_iv_se_e32m2(<vscale x 4 x i32> %vs2, iXLen %vl) {1735; CHECK-LABEL: test_sf_vc_v_iv_se_e32m2:1736; CHECK:       # %bb.0: # %entry1737; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1738; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101739; CHECK-NEXT:    ret1740entry:1741  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1742  ret <vscale x 4 x i32> %01743}1744 1745define <vscale x 8 x i32> @test_sf_vc_v_iv_se_e32m4(<vscale x 8 x i32> %vs2, iXLen %vl) {1746; CHECK-LABEL: test_sf_vc_v_iv_se_e32m4:1747; CHECK:       # %bb.0: # %entry1748; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1749; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101750; CHECK-NEXT:    ret1751entry:1752  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1753  ret <vscale x 8 x i32> %01754}1755 1756define <vscale x 16 x i32> @test_sf_vc_v_iv_se_e32m8(<vscale x 16 x i32> %vs2, iXLen %vl) {1757; CHECK-LABEL: test_sf_vc_v_iv_se_e32m8:1758; CHECK:       # %bb.0: # %entry1759; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1760; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101761; CHECK-NEXT:    ret1762entry:1763  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vs2, iXLen 10, iXLen %vl)1764  ret <vscale x 16 x i32> %01765}1766 1767define <vscale x 1 x i64> @test_sf_vc_v_iv_se_e64m1(<vscale x 1 x i64> %vs2, iXLen %vl) {1768; CHECK-LABEL: test_sf_vc_v_iv_se_e64m1:1769; CHECK:       # %bb.0: # %entry1770; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1771; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101772; CHECK-NEXT:    ret1773entry:1774  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vs2, iXLen 10, iXLen %vl)1775  ret <vscale x 1 x i64> %01776}1777 1778define <vscale x 2 x i64> @test_sf_vc_v_iv_se_e64m2(<vscale x 2 x i64> %vs2, iXLen %vl) {1779; CHECK-LABEL: test_sf_vc_v_iv_se_e64m2:1780; CHECK:       # %bb.0: # %entry1781; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1782; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101783; CHECK-NEXT:    ret1784entry:1785  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vs2, iXLen 10, iXLen %vl)1786  ret <vscale x 2 x i64> %01787}1788 1789define <vscale x 4 x i64> @test_sf_vc_v_iv_se_e64m4(<vscale x 4 x i64> %vs2, iXLen %vl) {1790; CHECK-LABEL: test_sf_vc_v_iv_se_e64m4:1791; CHECK:       # %bb.0: # %entry1792; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1793; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101794; CHECK-NEXT:    ret1795entry:1796  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vs2, iXLen 10, iXLen %vl)1797  ret <vscale x 4 x i64> %01798}1799 1800define <vscale x 8 x i64> @test_sf_vc_v_iv_se_e64m8(<vscale x 8 x i64> %vs2, iXLen %vl) {1801; CHECK-LABEL: test_sf_vc_v_iv_se_e64m8:1802; CHECK:       # %bb.0: # %entry1803; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1804; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101805; CHECK-NEXT:    ret1806entry:1807  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.iv.se.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vs2, iXLen 10, iXLen %vl)1808  ret <vscale x 8 x i64> %01809}1810 1811define <vscale x 1 x i8> @test_sf_vc_v_iv_e8mf8(<vscale x 1 x i8> %vs2, iXLen %vl) {1812; CHECK-LABEL: test_sf_vc_v_iv_e8mf8:1813; CHECK:       # %bb.0: # %entry1814; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1815; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101816; CHECK-NEXT:    ret1817entry:1818  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.iv.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1819  ret <vscale x 1 x i8> %01820}1821 1822define <vscale x 2 x i8> @test_sf_vc_v_iv_e8mf4(<vscale x 2 x i8> %vs2, iXLen %vl) {1823; CHECK-LABEL: test_sf_vc_v_iv_e8mf4:1824; CHECK:       # %bb.0: # %entry1825; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1826; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101827; CHECK-NEXT:    ret1828entry:1829  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.iv.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1830  ret <vscale x 2 x i8> %01831}1832 1833define <vscale x 4 x i8> @test_sf_vc_v_iv_e8mf2(<vscale x 4 x i8> %vs2, iXLen %vl) {1834; CHECK-LABEL: test_sf_vc_v_iv_e8mf2:1835; CHECK:       # %bb.0: # %entry1836; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1837; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101838; CHECK-NEXT:    ret1839entry:1840  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.iv.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1841  ret <vscale x 4 x i8> %01842}1843 1844define <vscale x 8 x i8> @test_sf_vc_v_iv_e8m1(<vscale x 8 x i8> %vs2, iXLen %vl) {1845; CHECK-LABEL: test_sf_vc_v_iv_e8m1:1846; CHECK:       # %bb.0: # %entry1847; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1848; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101849; CHECK-NEXT:    ret1850entry:1851  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.iv.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1852  ret <vscale x 8 x i8> %01853}1854 1855define <vscale x 16 x i8> @test_sf_vc_v_iv_e8m2(<vscale x 16 x i8> %vs2, iXLen %vl) {1856; CHECK-LABEL: test_sf_vc_v_iv_e8m2:1857; CHECK:       # %bb.0: # %entry1858; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1859; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101860; CHECK-NEXT:    ret1861entry:1862  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.iv.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1863  ret <vscale x 16 x i8> %01864}1865 1866define <vscale x 32 x i8> @test_sf_vc_v_iv_e8m4(<vscale x 32 x i8> %vs2, iXLen %vl) {1867; CHECK-LABEL: test_sf_vc_v_iv_e8m4:1868; CHECK:       # %bb.0: # %entry1869; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1870; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101871; CHECK-NEXT:    ret1872entry:1873  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.iv.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1874  ret <vscale x 32 x i8> %01875}1876 1877define <vscale x 64 x i8> @test_sf_vc_v_iv_e8m8(<vscale x 64 x i8> %vs2, iXLen %vl) {1878; CHECK-LABEL: test_sf_vc_v_iv_e8m8:1879; CHECK:       # %bb.0: # %entry1880; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma1881; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101882; CHECK-NEXT:    ret1883entry:1884  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.iv.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 64 x i8> %vs2, iXLen 10, iXLen %vl)1885  ret <vscale x 64 x i8> %01886}1887 1888define <vscale x 1 x i16> @test_sf_vc_v_iv_e16mf4(<vscale x 1 x i16> %vs2, iXLen %vl) {1889; CHECK-LABEL: test_sf_vc_v_iv_e16mf4:1890; CHECK:       # %bb.0: # %entry1891; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1892; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101893; CHECK-NEXT:    ret1894entry:1895  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.iv.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1896  ret <vscale x 1 x i16> %01897}1898 1899define <vscale x 2 x i16> @test_sf_vc_v_iv_e16mf2(<vscale x 2 x i16> %vs2, iXLen %vl) {1900; CHECK-LABEL: test_sf_vc_v_iv_e16mf2:1901; CHECK:       # %bb.0: # %entry1902; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1903; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101904; CHECK-NEXT:    ret1905entry:1906  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.iv.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1907  ret <vscale x 2 x i16> %01908}1909 1910define <vscale x 4 x i16> @test_sf_vc_v_iv_e16m1(<vscale x 4 x i16> %vs2, iXLen %vl) {1911; CHECK-LABEL: test_sf_vc_v_iv_e16m1:1912; CHECK:       # %bb.0: # %entry1913; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1914; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101915; CHECK-NEXT:    ret1916entry:1917  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.iv.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1918  ret <vscale x 4 x i16> %01919}1920 1921define <vscale x 8 x i16> @test_sf_vc_v_iv_e16m2(<vscale x 8 x i16> %vs2, iXLen %vl) {1922; CHECK-LABEL: test_sf_vc_v_iv_e16m2:1923; CHECK:       # %bb.0: # %entry1924; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1925; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101926; CHECK-NEXT:    ret1927entry:1928  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.iv.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1929  ret <vscale x 8 x i16> %01930}1931 1932define <vscale x 16 x i16> @test_sf_vc_v_iv_e16m4(<vscale x 16 x i16> %vs2, iXLen %vl) {1933; CHECK-LABEL: test_sf_vc_v_iv_e16m4:1934; CHECK:       # %bb.0: # %entry1935; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1936; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101937; CHECK-NEXT:    ret1938entry:1939  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.iv.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1940  ret <vscale x 16 x i16> %01941}1942 1943define <vscale x 32 x i16> @test_sf_vc_v_iv_e16m8(<vscale x 32 x i16> %vs2, iXLen %vl) {1944; CHECK-LABEL: test_sf_vc_v_iv_e16m8:1945; CHECK:       # %bb.0: # %entry1946; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1947; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101948; CHECK-NEXT:    ret1949entry:1950  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.iv.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vs2, iXLen 10, iXLen %vl)1951  ret <vscale x 32 x i16> %01952}1953 1954define <vscale x 1 x i32> @test_sf_vc_v_iv_e32mf2(<vscale x 1 x i32> %vs2, iXLen %vl) {1955; CHECK-LABEL: test_sf_vc_v_iv_e32mf2:1956; CHECK:       # %bb.0: # %entry1957; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1958; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101959; CHECK-NEXT:    ret1960entry:1961  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.iv.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1962  ret <vscale x 1 x i32> %01963}1964 1965define <vscale x 2 x i32> @test_sf_vc_v_iv_e32m1(<vscale x 2 x i32> %vs2, iXLen %vl) {1966; CHECK-LABEL: test_sf_vc_v_iv_e32m1:1967; CHECK:       # %bb.0: # %entry1968; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1969; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101970; CHECK-NEXT:    ret1971entry:1972  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.iv.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1973  ret <vscale x 2 x i32> %01974}1975 1976define <vscale x 4 x i32> @test_sf_vc_v_iv_e32m2(<vscale x 4 x i32> %vs2, iXLen %vl) {1977; CHECK-LABEL: test_sf_vc_v_iv_e32m2:1978; CHECK:       # %bb.0: # %entry1979; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1980; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101981; CHECK-NEXT:    ret1982entry:1983  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1984  ret <vscale x 4 x i32> %01985}1986 1987define <vscale x 8 x i32> @test_sf_vc_v_iv_e32m4(<vscale x 8 x i32> %vs2, iXLen %vl) {1988; CHECK-LABEL: test_sf_vc_v_iv_e32m4:1989; CHECK:       # %bb.0: # %entry1990; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1991; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 101992; CHECK-NEXT:    ret1993entry:1994  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.iv.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1995  ret <vscale x 8 x i32> %01996}1997 1998define <vscale x 16 x i32> @test_sf_vc_v_iv_e32m8(<vscale x 16 x i32> %vs2, iXLen %vl) {1999; CHECK-LABEL: test_sf_vc_v_iv_e32m8:2000; CHECK:       # %bb.0: # %entry2001; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2002; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 102003; CHECK-NEXT:    ret2004entry:2005  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.iv.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vs2, iXLen 10, iXLen %vl)2006  ret <vscale x 16 x i32> %02007}2008 2009define <vscale x 1 x i64> @test_sf_vc_v_iv_e64m1(<vscale x 1 x i64> %vs2, iXLen %vl) {2010; CHECK-LABEL: test_sf_vc_v_iv_e64m1:2011; CHECK:       # %bb.0: # %entry2012; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2013; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 102014; CHECK-NEXT:    ret2015entry:2016  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.iv.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vs2, iXLen 10, iXLen %vl)2017  ret <vscale x 1 x i64> %02018}2019 2020define <vscale x 2 x i64> @test_sf_vc_v_iv_e64m2(<vscale x 2 x i64> %vs2, iXLen %vl) {2021; CHECK-LABEL: test_sf_vc_v_iv_e64m2:2022; CHECK:       # %bb.0: # %entry2023; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2024; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 102025; CHECK-NEXT:    ret2026entry:2027  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.iv.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vs2, iXLen 10, iXLen %vl)2028  ret <vscale x 2 x i64> %02029}2030 2031define <vscale x 4 x i64> @test_sf_vc_v_iv_e64m4(<vscale x 4 x i64> %vs2, iXLen %vl) {2032; CHECK-LABEL: test_sf_vc_v_iv_e64m4:2033; CHECK:       # %bb.0: # %entry2034; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2035; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 102036; CHECK-NEXT:    ret2037entry:2038  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.iv.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vs2, iXLen 10, iXLen %vl)2039  ret <vscale x 4 x i64> %02040}2041 2042define <vscale x 8 x i64> @test_sf_vc_v_iv_e64m8(<vscale x 8 x i64> %vs2, iXLen %vl) {2043; CHECK-LABEL: test_sf_vc_v_iv_e64m8:2044; CHECK:       # %bb.0: # %entry2045; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2046; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 102047; CHECK-NEXT:    ret2048entry:2049  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.iv.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vs2, iXLen 10, iXLen %vl)2050  ret <vscale x 8 x i64> %02051}2052 2053define void @test_sf_vc_fvv_se_e16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {2054; CHECK-LABEL: test_sf_vc_fvv_se_e16mf4:2055; CHECK:       # %bb.0: # %entry2056; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2057; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v92058; CHECK-NEXT:    ret2059entry:2060  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f16.nxv1i16.iXLen(iXLen 3, iXLen 31, <vscale x 1 x half> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)2061  ret void2062}2063 2064define <vscale x 1 x half> @test_sf_vc_v_fvv_se_e16mf4(<vscale x 1 x half> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {2065; CHECK-LABEL: test_sf_vc_v_fvv_se_e16mf4:2066; CHECK:       # %bb.0: # %entry2067; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2068; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v92069; CHECK-NEXT:    ret2070entry:2071  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.vv.se.nxv1f16.iXLen.nxv1f16.iXLen(iXLen 3, <vscale x 1 x half> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)2072  ret <vscale x 1 x half> %02073}2074 2075define void @test_sf_vc_fvv_se_e16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {2076; CHECK-LABEL: test_sf_vc_fvv_se_e16mf2:2077; CHECK:       # %bb.0: # %entry2078; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2079; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v92080; CHECK-NEXT:    ret2081entry:2082  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f16.nxv2i16.iXLen(iXLen 3, iXLen 31, <vscale x 2 x half> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)2083  ret void2084}2085 2086define <vscale x 2 x half> @test_sf_vc_v_fvv_se_e16mf2(<vscale x 2 x half> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {2087; CHECK-LABEL: test_sf_vc_v_fvv_se_e16mf2:2088; CHECK:       # %bb.0: # %entry2089; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2090; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v92091; CHECK-NEXT:    ret2092entry:2093  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.vv.se.nxv2f16.iXLen.nxv2f16.iXLen(iXLen 3, <vscale x 2 x half> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)2094  ret <vscale x 2 x half> %02095}2096 2097define void @test_sf_vc_fvv_se_e16m1(<vscale x 4 x half> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {2098; CHECK-LABEL: test_sf_vc_fvv_se_e16m1:2099; CHECK:       # %bb.0: # %entry2100; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2101; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v92102; CHECK-NEXT:    ret2103entry:2104  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f16.nxv4i16.iXLen(iXLen 3, iXLen 31, <vscale x 4 x half> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)2105  ret void2106}2107 2108define <vscale x 4 x half> @test_sf_vc_v_fvv_se_e16m1(<vscale x 4 x half> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {2109; CHECK-LABEL: test_sf_vc_v_fvv_se_e16m1:2110; CHECK:       # %bb.0: # %entry2111; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2112; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v92113; CHECK-NEXT:    ret2114entry:2115  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.vv.se.nxv4f16.iXLen.nxv4f16.iXLen(iXLen 3, <vscale x 4 x half> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)2116  ret <vscale x 4 x half> %02117}2118 2119define void @test_sf_vc_fvv_se_e16m2(<vscale x 8 x half> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {2120; CHECK-LABEL: test_sf_vc_fvv_se_e16m2:2121; CHECK:       # %bb.0: # %entry2122; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2123; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v102124; CHECK-NEXT:    ret2125entry:2126  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f16.nxv8i16.iXLen(iXLen 3, iXLen 31, <vscale x 8 x half> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)2127  ret void2128}2129 2130define <vscale x 8 x half> @test_sf_vc_v_fvv_se_e16m2(<vscale x 8 x half> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {2131; CHECK-LABEL: test_sf_vc_v_fvv_se_e16m2:2132; CHECK:       # %bb.0: # %entry2133; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2134; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v102135; CHECK-NEXT:    ret2136entry:2137  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.vv.se.nxv8f16.iXLen.nxv8f16.iXLen(iXLen 3, <vscale x 8 x half> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)2138  ret <vscale x 8 x half> %02139}2140 2141define void @test_sf_vc_fvv_se_e16m4(<vscale x 16 x half> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {2142; CHECK-LABEL: test_sf_vc_fvv_se_e16m4:2143; CHECK:       # %bb.0: # %entry2144; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2145; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v122146; CHECK-NEXT:    ret2147entry:2148  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16f16.nxv16i16.iXLen(iXLen 3, iXLen 31, <vscale x 16 x half> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)2149  ret void2150}2151 2152define <vscale x 16 x half> @test_sf_vc_v_fvv_se_e16m4(<vscale x 16 x half> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {2153; CHECK-LABEL: test_sf_vc_v_fvv_se_e16m4:2154; CHECK:       # %bb.0: # %entry2155; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2156; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v122157; CHECK-NEXT:    ret2158entry:2159  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.vv.se.nxv16f16.iXLen.nxv16f16.iXLen(iXLen 3, <vscale x 16 x half> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)2160  ret <vscale x 16 x half> %02161}2162 2163define void @test_sf_vc_fvv_se_e16m8(<vscale x 32 x half> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {2164; CHECK-LABEL: test_sf_vc_fvv_se_e16m8:2165; CHECK:       # %bb.0: # %entry2166; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2167; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v162168; CHECK-NEXT:    ret2169entry:2170  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv32f16.nxv32i16.iXLen(iXLen 3, iXLen 31, <vscale x 32 x half> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)2171  ret void2172}2173 2174define <vscale x 32 x half> @test_sf_vc_v_fvv_se_e16m8(<vscale x 32 x half> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {2175; CHECK-LABEL: test_sf_vc_v_fvv_se_e16m8:2176; CHECK:       # %bb.0: # %entry2177; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2178; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v162179; CHECK-NEXT:    ret2180entry:2181  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.vv.se.nxv32f16.iXLen.nxv32f16.iXLen(iXLen 3, <vscale x 32 x half> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)2182  ret <vscale x 32 x half> %02183}2184 2185define void @test_sf_vc_fvv_se_e32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {2186; CHECK-LABEL: test_sf_vc_fvv_se_e32mf2:2187; CHECK:       # %bb.0: # %entry2188; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2189; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v92190; CHECK-NEXT:    ret2191entry:2192  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f32.nxv1i32.iXLen(iXLen 3, iXLen 31, <vscale x 1 x float> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)2193  ret void2194}2195 2196define <vscale x 1 x float> @test_sf_vc_v_fvv_se_e32mf2(<vscale x 1 x float> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {2197; CHECK-LABEL: test_sf_vc_v_fvv_se_e32mf2:2198; CHECK:       # %bb.0: # %entry2199; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2200; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v92201; CHECK-NEXT:    ret2202entry:2203  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.vv.se.nxv1f32.iXLen.nxv1f32.iXLen(iXLen 3, <vscale x 1 x float> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)2204  ret <vscale x 1 x float> %02205}2206 2207define void @test_sf_vc_fvv_se_e32m1(<vscale x 2 x float> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {2208; CHECK-LABEL: test_sf_vc_fvv_se_e32m1:2209; CHECK:       # %bb.0: # %entry2210; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2211; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v92212; CHECK-NEXT:    ret2213entry:2214  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f32.nxv2i32.iXLen(iXLen 3, iXLen 31, <vscale x 2 x float> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)2215  ret void2216}2217 2218define <vscale x 2 x float> @test_sf_vc_v_fvv_se_e32m1(<vscale x 2 x float> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {2219; CHECK-LABEL: test_sf_vc_v_fvv_se_e32m1:2220; CHECK:       # %bb.0: # %entry2221; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2222; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v92223; CHECK-NEXT:    ret2224entry:2225  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.vv.se.nxv2f32.iXLen.nxv2f32.iXLen(iXLen 3, <vscale x 2 x float> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)2226  ret <vscale x 2 x float> %02227}2228 2229define void @test_sf_vc_fvv_se_e32m2(<vscale x 4 x float> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {2230; CHECK-LABEL: test_sf_vc_fvv_se_e32m2:2231; CHECK:       # %bb.0: # %entry2232; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2233; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v102234; CHECK-NEXT:    ret2235entry:2236  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f32.nxv4i32.iXLen(iXLen 3, iXLen 31, <vscale x 4 x float> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)2237  ret void2238}2239 2240define <vscale x 4 x float> @test_sf_vc_v_fvv_se_e32m2(<vscale x 4 x float> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {2241; CHECK-LABEL: test_sf_vc_v_fvv_se_e32m2:2242; CHECK:       # %bb.0: # %entry2243; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2244; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v102245; CHECK-NEXT:    ret2246entry:2247  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.vv.se.nxv4f32.iXLen.nxv4f32.iXLen(iXLen 3, <vscale x 4 x float> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)2248  ret <vscale x 4 x float> %02249}2250 2251define void @test_sf_vc_fvv_se_e32m4(<vscale x 8 x float> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {2252; CHECK-LABEL: test_sf_vc_fvv_se_e32m4:2253; CHECK:       # %bb.0: # %entry2254; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2255; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v122256; CHECK-NEXT:    ret2257entry:2258  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f32.nxv8i32.iXLen(iXLen 3, iXLen 31, <vscale x 8 x float> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)2259  ret void2260}2261 2262define <vscale x 8 x float> @test_sf_vc_v_fvv_se_e32m4(<vscale x 8 x float> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {2263; CHECK-LABEL: test_sf_vc_v_fvv_se_e32m4:2264; CHECK:       # %bb.0: # %entry2265; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2266; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v122267; CHECK-NEXT:    ret2268entry:2269  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.vv.se.nxv8f32.iXLen.nxv8f32.iXLen(iXLen 3, <vscale x 8 x float> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)2270  ret <vscale x 8 x float> %02271}2272 2273define void @test_sf_vc_fvv_se_e32m8(<vscale x 16 x float> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {2274; CHECK-LABEL: test_sf_vc_fvv_se_e32m8:2275; CHECK:       # %bb.0: # %entry2276; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2277; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v162278; CHECK-NEXT:    ret2279entry:2280  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv16f32.nxv16i32.iXLen(iXLen 3, iXLen 31, <vscale x 16 x float> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)2281  ret void2282}2283 2284define <vscale x 16 x float> @test_sf_vc_v_fvv_se_e32m8(<vscale x 16 x float> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {2285; CHECK-LABEL: test_sf_vc_v_fvv_se_e32m8:2286; CHECK:       # %bb.0: # %entry2287; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2288; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v162289; CHECK-NEXT:    ret2290entry:2291  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.vv.se.nxv16f32.iXLen.nxv16f32.iXLen(iXLen 3, <vscale x 16 x float> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)2292  ret <vscale x 16 x float> %02293}2294 2295define void @test_sf_vc_fvv_se_e64m1(<vscale x 1 x double> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {2296; CHECK-LABEL: test_sf_vc_fvv_se_e64m1:2297; CHECK:       # %bb.0: # %entry2298; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2299; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v92300; CHECK-NEXT:    ret2301entry:2302  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv1f64.nxv1i64.iXLen(iXLen 3, iXLen 31, <vscale x 1 x double> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)2303  ret void2304}2305 2306define <vscale x 1 x double> @test_sf_vc_v_fvv_se_e64m1(<vscale x 1 x double> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {2307; CHECK-LABEL: test_sf_vc_v_fvv_se_e64m1:2308; CHECK:       # %bb.0: # %entry2309; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2310; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v92311; CHECK-NEXT:    ret2312entry:2313  %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.vv.se.nxv1f64.iXLen.nxv1f64.iXLen(iXLen 3, <vscale x 1 x double> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)2314  ret <vscale x 1 x double> %02315}2316 2317define void @test_sf_vc_fvv_se_e64m2(<vscale x 2 x double> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {2318; CHECK-LABEL: test_sf_vc_fvv_se_e64m2:2319; CHECK:       # %bb.0: # %entry2320; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2321; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v102322; CHECK-NEXT:    ret2323entry:2324  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv2f64.nxv2i64.iXLen(iXLen 3, iXLen 31, <vscale x 2 x double> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)2325  ret void2326}2327 2328define <vscale x 2 x double> @test_sf_vc_v_fvv_se_e64m2(<vscale x 2 x double> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {2329; CHECK-LABEL: test_sf_vc_v_fvv_se_e64m2:2330; CHECK:       # %bb.0: # %entry2331; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2332; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v102333; CHECK-NEXT:    ret2334entry:2335  %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.vv.se.nxv2f64.iXLen.nxv2f64.iXLen(iXLen 3, <vscale x 2 x double> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)2336  ret <vscale x 2 x double> %02337}2338 2339define void @test_sf_vc_fvv_se_e64m4(<vscale x 4 x double> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {2340; CHECK-LABEL: test_sf_vc_fvv_se_e64m4:2341; CHECK:       # %bb.0: # %entry2342; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2343; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v122344; CHECK-NEXT:    ret2345entry:2346  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv4f64.nxv4i64.iXLen(iXLen 3, iXLen 31, <vscale x 4 x double> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)2347  ret void2348}2349 2350define <vscale x 4 x double> @test_sf_vc_v_fvv_se_e64m4(<vscale x 4 x double> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {2351; CHECK-LABEL: test_sf_vc_v_fvv_se_e64m4:2352; CHECK:       # %bb.0: # %entry2353; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2354; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v122355; CHECK-NEXT:    ret2356entry:2357  %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.vv.se.nxv4f64.iXLen.nxv4f64.iXLen(iXLen 3, <vscale x 4 x double> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)2358  ret <vscale x 4 x double> %02359}2360 2361define void @test_sf_vc_fvv_se_e64m8(<vscale x 8 x double> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {2362; CHECK-LABEL: test_sf_vc_fvv_se_e64m8:2363; CHECK:       # %bb.0: # %entry2364; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2365; CHECK-NEXT:    sf.vc.vv 3, 31, v8, v162366; CHECK-NEXT:    ret2367entry:2368  tail call void @llvm.riscv.sf.vc.vv.se.iXLen.nxv8f64.nxv8i64.iXLen(iXLen 3, iXLen 31, <vscale x 8 x double> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)2369  ret void2370}2371 2372define <vscale x 8 x double> @test_sf_vc_v_fvv_se_e64m8(<vscale x 8 x double> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {2373; CHECK-LABEL: test_sf_vc_v_fvv_se_e64m8:2374; CHECK:       # %bb.0: # %entry2375; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma2376; CHECK-NEXT:    sf.vc.v.vv 3, v8, v8, v162377; CHECK-NEXT:    ret2378entry:2379  %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.vv.se.nxv8f64.iXLen.nxv8f64.iXLen(iXLen 3, <vscale x 8 x double> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)2380  ret <vscale x 8 x double> %02381}2382 2383define void @test_sf_vc_fvx_se_e16mf4(<vscale x 1 x half> %vs2, i16 %rs1, iXLen %vl) {2384; CHECK-LABEL: test_sf_vc_fvx_se_e16mf4:2385; CHECK:       # %bb.0: # %entry2386; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2387; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02388; CHECK-NEXT:    ret2389entry:2390  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv1f16.nxv1f16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 1 x half> %vs2, i16 %rs1, iXLen %vl)2391  ret void2392}2393 2394define <vscale x 1 x half> @test_sf_vc_v_fvx_se_e16mf4(<vscale x 1 x half> %vs2, i16 %rs1, iXLen %vl) {2395; CHECK-LABEL: test_sf_vc_v_fvx_se_e16mf4:2396; CHECK:       # %bb.0: # %entry2397; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2398; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02399; CHECK-NEXT:    ret2400entry:2401  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.xv.se.nxv1f16.nxv1f16.i16.iXLen(iXLen 3, <vscale x 1 x half> %vs2, i16 %rs1, iXLen %vl)2402  ret <vscale x 1 x half> %02403}2404 2405define void @test_sf_vc_fvx_se_e16mf2(<vscale x 2 x half> %vs2, i16 %rs1, iXLen %vl) {2406; CHECK-LABEL: test_sf_vc_fvx_se_e16mf2:2407; CHECK:       # %bb.0: # %entry2408; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2409; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02410; CHECK-NEXT:    ret2411entry:2412  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv2f16.nxv2f16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 2 x half> %vs2, i16 %rs1, iXLen %vl)2413  ret void2414}2415 2416define <vscale x 2 x half> @test_sf_vc_v_fvx_se_e16mf2(<vscale x 2 x half> %vs2, i16 %rs1, iXLen %vl) {2417; CHECK-LABEL: test_sf_vc_v_fvx_se_e16mf2:2418; CHECK:       # %bb.0: # %entry2419; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2420; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02421; CHECK-NEXT:    ret2422entry:2423  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.xv.se.nxv2f16.nxv2f16.i16.iXLen(iXLen 3, <vscale x 2 x half> %vs2, i16 %rs1, iXLen %vl)2424  ret <vscale x 2 x half> %02425}2426 2427define void @test_sf_vc_fvx_se_e16m1(<vscale x 4 x half> %vs2, i16 %rs1, iXLen %vl) {2428; CHECK-LABEL: test_sf_vc_fvx_se_e16m1:2429; CHECK:       # %bb.0: # %entry2430; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2431; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02432; CHECK-NEXT:    ret2433entry:2434  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv4f16.nxv4f16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 4 x half> %vs2, i16 %rs1, iXLen %vl)2435  ret void2436}2437 2438define <vscale x 4 x half> @test_sf_vc_v_fvx_se_e16m1(<vscale x 4 x half> %vs2, i16 %rs1, iXLen %vl) {2439; CHECK-LABEL: test_sf_vc_v_fvx_se_e16m1:2440; CHECK:       # %bb.0: # %entry2441; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2442; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02443; CHECK-NEXT:    ret2444entry:2445  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.xv.se.nxv4f16.nxv4f16.i16.iXLen(iXLen 3, <vscale x 4 x half> %vs2, i16 %rs1, iXLen %vl)2446  ret <vscale x 4 x half> %02447}2448 2449define void @test_sf_vc_fvx_se_e16m2(<vscale x 8 x half> %vs2, i16 %rs1, iXLen %vl) {2450; CHECK-LABEL: test_sf_vc_fvx_se_e16m2:2451; CHECK:       # %bb.0: # %entry2452; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2453; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02454; CHECK-NEXT:    ret2455entry:2456  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv8f16.nxv8f16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 8 x half> %vs2, i16 %rs1, iXLen %vl)2457  ret void2458}2459 2460define <vscale x 8 x half> @test_sf_vc_v_fvx_se_e16m2(<vscale x 8 x half> %vs2, i16 %rs1, iXLen %vl) {2461; CHECK-LABEL: test_sf_vc_v_fvx_se_e16m2:2462; CHECK:       # %bb.0: # %entry2463; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2464; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02465; CHECK-NEXT:    ret2466entry:2467  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.xv.se.nxv8f16.nxv8f16.i16.iXLen(iXLen 3, <vscale x 8 x half> %vs2, i16 %rs1, iXLen %vl)2468  ret <vscale x 8 x half> %02469}2470 2471define void @test_sf_vc_fvx_se_e16m4(<vscale x 16 x half> %vs2, i16 %rs1, iXLen %vl) {2472; CHECK-LABEL: test_sf_vc_fvx_se_e16m4:2473; CHECK:       # %bb.0: # %entry2474; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2475; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02476; CHECK-NEXT:    ret2477entry:2478  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv16f16.nxv16f16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 16 x half> %vs2, i16 %rs1, iXLen %vl)2479  ret void2480}2481 2482define <vscale x 16 x half> @test_sf_vc_v_fvx_se_e16m4(<vscale x 16 x half> %vs2, i16 %rs1, iXLen %vl) {2483; CHECK-LABEL: test_sf_vc_v_fvx_se_e16m4:2484; CHECK:       # %bb.0: # %entry2485; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2486; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02487; CHECK-NEXT:    ret2488entry:2489  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.xv.se.nxv16f16.nxv16f16.i16.iXLen(iXLen 3, <vscale x 16 x half> %vs2, i16 %rs1, iXLen %vl)2490  ret <vscale x 16 x half> %02491}2492 2493define void @test_sf_vc_fvx_se_e16m8(<vscale x 32 x half> %vs2, i16 %rs1, iXLen %vl) {2494; CHECK-LABEL: test_sf_vc_fvx_se_e16m8:2495; CHECK:       # %bb.0: # %entry2496; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2497; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02498; CHECK-NEXT:    ret2499entry:2500  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv32f16.nxv32f16.i16.iXLen(iXLen 3, iXLen 31, <vscale x 32 x half> %vs2, i16 %rs1, iXLen %vl)2501  ret void2502}2503 2504define <vscale x 32 x half> @test_sf_vc_v_fvx_se_e16m8(<vscale x 32 x half> %vs2, i16 %rs1, iXLen %vl) {2505; CHECK-LABEL: test_sf_vc_v_fvx_se_e16m8:2506; CHECK:       # %bb.0: # %entry2507; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2508; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02509; CHECK-NEXT:    ret2510entry:2511  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.xv.se.nxv32f16.nxv32f16.i16.iXLen(iXLen 3, <vscale x 32 x half> %vs2, i16 %rs1, iXLen %vl)2512  ret <vscale x 32 x half> %02513}2514 2515define void @test_sf_vc_fvx_se_e32mf2(<vscale x 1 x float> %vs2, i32 %rs1, iXLen %vl) {2516; CHECK-LABEL: test_sf_vc_fvx_se_e32mf2:2517; CHECK:       # %bb.0: # %entry2518; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2519; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02520; CHECK-NEXT:    ret2521entry:2522  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv1f32.nxv1f32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 1 x float> %vs2, i32 %rs1, iXLen %vl)2523  ret void2524}2525 2526define <vscale x 1 x float> @test_sf_vc_v_fvx_se_e32mf2(<vscale x 1 x float> %vs2, i32 %rs1, iXLen %vl) {2527; CHECK-LABEL: test_sf_vc_v_fvx_se_e32mf2:2528; CHECK:       # %bb.0: # %entry2529; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2530; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02531; CHECK-NEXT:    ret2532entry:2533  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.xv.se.nxv1f32.nxv1f32.i32.iXLen(iXLen 3, <vscale x 1 x float> %vs2, i32 %rs1, iXLen %vl)2534  ret <vscale x 1 x float> %02535}2536 2537define void @test_sf_vc_fvx_se_e32m1(<vscale x 2 x float> %vs2, i32 %rs1, iXLen %vl) {2538; CHECK-LABEL: test_sf_vc_fvx_se_e32m1:2539; CHECK:       # %bb.0: # %entry2540; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2541; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02542; CHECK-NEXT:    ret2543entry:2544  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv2f32.nxv2f32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 2 x float> %vs2, i32 %rs1, iXLen %vl)2545  ret void2546}2547 2548define <vscale x 2 x float> @test_sf_vc_v_fvx_se_e32m1(<vscale x 2 x float> %vs2, i32 %rs1, iXLen %vl) {2549; CHECK-LABEL: test_sf_vc_v_fvx_se_e32m1:2550; CHECK:       # %bb.0: # %entry2551; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2552; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02553; CHECK-NEXT:    ret2554entry:2555  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.xv.se.nxv2f32.nxv2f32.i32.iXLen(iXLen 3, <vscale x 2 x float> %vs2, i32 %rs1, iXLen %vl)2556  ret <vscale x 2 x float> %02557}2558 2559define void @test_sf_vc_fvx_se_e32m2(<vscale x 4 x float> %vs2, i32 %rs1, iXLen %vl) {2560; CHECK-LABEL: test_sf_vc_fvx_se_e32m2:2561; CHECK:       # %bb.0: # %entry2562; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2563; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02564; CHECK-NEXT:    ret2565entry:2566  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv4f32.nxv4f32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 4 x float> %vs2, i32 %rs1, iXLen %vl)2567  ret void2568}2569 2570define <vscale x 4 x float> @test_sf_vc_v_fvx_se_e32m2(<vscale x 4 x float> %vs2, i32 %rs1, iXLen %vl) {2571; CHECK-LABEL: test_sf_vc_v_fvx_se_e32m2:2572; CHECK:       # %bb.0: # %entry2573; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2574; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02575; CHECK-NEXT:    ret2576entry:2577  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.xv.se.nxv4f32.nxv4f32.i32.iXLen(iXLen 3, <vscale x 4 x float> %vs2, i32 %rs1, iXLen %vl)2578  ret <vscale x 4 x float> %02579}2580 2581define void @test_sf_vc_fvx_se_e32m4(<vscale x 8 x float> %vs2, i32 %rs1, iXLen %vl) {2582; CHECK-LABEL: test_sf_vc_fvx_se_e32m4:2583; CHECK:       # %bb.0: # %entry2584; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2585; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02586; CHECK-NEXT:    ret2587entry:2588  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv8f32.nxv8f32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 8 x float> %vs2, i32 %rs1, iXLen %vl)2589  ret void2590}2591 2592define <vscale x 8 x float> @test_sf_vc_v_fvx_se_e32m4(<vscale x 8 x float> %vs2, i32 %rs1, iXLen %vl) {2593; CHECK-LABEL: test_sf_vc_v_fvx_se_e32m4:2594; CHECK:       # %bb.0: # %entry2595; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2596; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02597; CHECK-NEXT:    ret2598entry:2599  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.xv.se.nxv8f32.nxv8f32.i32.iXLen(iXLen 3, <vscale x 8 x float> %vs2, i32 %rs1, iXLen %vl)2600  ret <vscale x 8 x float> %02601}2602 2603define void @test_sf_vc_fvx_se_e32m8(<vscale x 16 x float> %vs2, i32 %rs1, iXLen %vl) {2604; CHECK-LABEL: test_sf_vc_fvx_se_e32m8:2605; CHECK:       # %bb.0: # %entry2606; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2607; CHECK-NEXT:    sf.vc.xv 3, 31, v8, a02608; CHECK-NEXT:    ret2609entry:2610  tail call void @llvm.riscv.sf.vc.xv.se.iXLen.nxv16f32.nxv16f32.i32.iXLen(iXLen 3, iXLen 31, <vscale x 16 x float> %vs2, i32 %rs1, iXLen %vl)2611  ret void2612}2613 2614define <vscale x 16 x float> @test_sf_vc_v_fvx_se_e32m8(<vscale x 16 x float> %vs2, i32 %rs1, iXLen %vl) {2615; CHECK-LABEL: test_sf_vc_v_fvx_se_e32m8:2616; CHECK:       # %bb.0: # %entry2617; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2618; CHECK-NEXT:    sf.vc.v.xv 3, v8, v8, a02619; CHECK-NEXT:    ret2620entry:2621  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.xv.se.nxv16f32.nxv16f32.i32.iXLen(iXLen 3, <vscale x 16 x float> %vs2, i32 %rs1, iXLen %vl)2622  ret <vscale x 16 x float> %02623}2624 2625define void @test_sf_vc_fvi_se_e16mf4(<vscale x 1 x half> %vs2, iXLen %vl) {2626; CHECK-LABEL: test_sf_vc_fvi_se_e16mf4:2627; CHECK:       # %bb.0: # %entry2628; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2629; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82630; CHECK-NEXT:    ret2631entry:2632  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1f16.nxv1f16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 1 x half> %vs2, iXLen 8, iXLen %vl)2633  ret void2634}2635 2636define <vscale x 1 x half> @test_sf_vc_v_fvi_se_e16mf4(<vscale x 1 x half> %vs2, iXLen %vl) {2637; CHECK-LABEL: test_sf_vc_v_fvi_se_e16mf4:2638; CHECK:       # %bb.0: # %entry2639; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2640; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82641; CHECK-NEXT:    ret2642entry:2643  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.iv.se.nxv1f16.nxv1f16.iXLen.iXLen(iXLen 3, <vscale x 1 x half> %vs2, iXLen 8, iXLen %vl)2644  ret <vscale x 1 x half> %02645}2646 2647define void @test_sf_vc_fvi_se_e16mf2(<vscale x 2 x half> %vs2, iXLen %vl) {2648; CHECK-LABEL: test_sf_vc_fvi_se_e16mf2:2649; CHECK:       # %bb.0: # %entry2650; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2651; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82652; CHECK-NEXT:    ret2653entry:2654  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv2f16.nxv2f16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 2 x half> %vs2, iXLen 8, iXLen %vl)2655  ret void2656}2657 2658define <vscale x 2 x half> @test_sf_vc_v_fvi_se_e16mf2(<vscale x 2 x half> %vs2, iXLen %vl) {2659; CHECK-LABEL: test_sf_vc_v_fvi_se_e16mf2:2660; CHECK:       # %bb.0: # %entry2661; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2662; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82663; CHECK-NEXT:    ret2664entry:2665  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.iv.se.nxv2f16.nxv2f16.iXLen.iXLen(iXLen 3, <vscale x 2 x half> %vs2, iXLen 8, iXLen %vl)2666  ret <vscale x 2 x half> %02667}2668 2669define void @test_sf_vc_fvi_se_e16m1(<vscale x 4 x half> %vs2, iXLen %vl) {2670; CHECK-LABEL: test_sf_vc_fvi_se_e16m1:2671; CHECK:       # %bb.0: # %entry2672; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2673; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82674; CHECK-NEXT:    ret2675entry:2676  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv4f16.nxv4f16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 4 x half> %vs2, iXLen 8, iXLen %vl)2677  ret void2678}2679 2680define <vscale x 4 x half> @test_sf_vc_v_fvi_se_e16m1(<vscale x 4 x half> %vs2, iXLen %vl) {2681; CHECK-LABEL: test_sf_vc_v_fvi_se_e16m1:2682; CHECK:       # %bb.0: # %entry2683; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2684; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82685; CHECK-NEXT:    ret2686entry:2687  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.iv.se.nxv4f16.nxv4f16.iXLen.iXLen(iXLen 3, <vscale x 4 x half> %vs2, iXLen 8, iXLen %vl)2688  ret <vscale x 4 x half> %02689}2690 2691define void @test_sf_vc_fvi_se_e16m2(<vscale x 8 x half> %vs2, iXLen %vl) {2692; CHECK-LABEL: test_sf_vc_fvi_se_e16m2:2693; CHECK:       # %bb.0: # %entry2694; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2695; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82696; CHECK-NEXT:    ret2697entry:2698  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv8f16.nxv8f16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 8 x half> %vs2, iXLen 8, iXLen %vl)2699  ret void2700}2701 2702define <vscale x 8 x half> @test_sf_vc_v_fvi_se_e16m2(<vscale x 8 x half> %vs2, iXLen %vl) {2703; CHECK-LABEL: test_sf_vc_v_fvi_se_e16m2:2704; CHECK:       # %bb.0: # %entry2705; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2706; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82707; CHECK-NEXT:    ret2708entry:2709  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.iv.se.nxv8f16.nxv8f16.iXLen.iXLen(iXLen 3, <vscale x 8 x half> %vs2, iXLen 8, iXLen %vl)2710  ret <vscale x 8 x half> %02711}2712 2713define void @test_sf_vc_fvi_se_e16m4(<vscale x 16 x half> %vs2, iXLen %vl) {2714; CHECK-LABEL: test_sf_vc_fvi_se_e16m4:2715; CHECK:       # %bb.0: # %entry2716; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2717; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82718; CHECK-NEXT:    ret2719entry:2720  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv16f16.nxv16f16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 16 x half> %vs2, iXLen 8, iXLen %vl)2721  ret void2722}2723 2724define <vscale x 16 x half> @test_sf_vc_v_fvi_se_e16m4(<vscale x 16 x half> %vs2, iXLen %vl) {2725; CHECK-LABEL: test_sf_vc_v_fvi_se_e16m4:2726; CHECK:       # %bb.0: # %entry2727; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2728; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82729; CHECK-NEXT:    ret2730entry:2731  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.iv.se.nxv16f16.nxv16f16.iXLen.iXLen(iXLen 3, <vscale x 16 x half> %vs2, iXLen 8, iXLen %vl)2732  ret <vscale x 16 x half> %02733}2734 2735define void @test_sf_vc_fvi_se_e16m8(<vscale x 32 x half> %vs2, iXLen %vl) {2736; CHECK-LABEL: test_sf_vc_fvi_se_e16m8:2737; CHECK:       # %bb.0: # %entry2738; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2739; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82740; CHECK-NEXT:    ret2741entry:2742  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv32f16.nxv32f16.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 32 x half> %vs2, iXLen 8, iXLen %vl)2743  ret void2744}2745 2746define <vscale x 32 x half> @test_sf_vc_v_fvi_se_e16m8(<vscale x 32 x half> %vs2, iXLen %vl) {2747; CHECK-LABEL: test_sf_vc_v_fvi_se_e16m8:2748; CHECK:       # %bb.0: # %entry2749; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2750; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82751; CHECK-NEXT:    ret2752entry:2753  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.iv.se.nxv32f16.nxv32f16.iXLen.iXLen(iXLen 3, <vscale x 32 x half> %vs2, iXLen 8, iXLen %vl)2754  ret <vscale x 32 x half> %02755}2756 2757define void @test_sf_vc_fvi_se_e32mf2(<vscale x 1 x float> %vs2, iXLen %vl) {2758; CHECK-LABEL: test_sf_vc_fvi_se_e32mf2:2759; CHECK:       # %bb.0: # %entry2760; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2761; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82762; CHECK-NEXT:    ret2763entry:2764  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1f32.nxv1f32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 1 x float> %vs2, iXLen 8, iXLen %vl)2765  ret void2766}2767 2768define <vscale x 1 x float> @test_sf_vc_v_fvi_se_e32mf2(<vscale x 1 x float> %vs2, iXLen %vl) {2769; CHECK-LABEL: test_sf_vc_v_fvi_se_e32mf2:2770; CHECK:       # %bb.0: # %entry2771; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2772; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82773; CHECK-NEXT:    ret2774entry:2775  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.iv.se.nxv1f32.nxv1f32.iXLen.iXLen(iXLen 3, <vscale x 1 x float> %vs2, iXLen 8, iXLen %vl)2776  ret <vscale x 1 x float> %02777}2778 2779define void @test_sf_vc_fvi_se_e32m1(<vscale x 2 x float> %vs2, iXLen %vl) {2780; CHECK-LABEL: test_sf_vc_fvi_se_e32m1:2781; CHECK:       # %bb.0: # %entry2782; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2783; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82784; CHECK-NEXT:    ret2785entry:2786  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv2f32.nxv2f32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 2 x float> %vs2, iXLen 8, iXLen %vl)2787  ret void2788}2789 2790define <vscale x 2 x float> @test_sf_vc_v_fvi_se_e32m1(<vscale x 2 x float> %vs2, iXLen %vl) {2791; CHECK-LABEL: test_sf_vc_v_fvi_se_e32m1:2792; CHECK:       # %bb.0: # %entry2793; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2794; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82795; CHECK-NEXT:    ret2796entry:2797  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.iv.se.nxv2f32.nxv2f32.iXLen.iXLen(iXLen 3, <vscale x 2 x float> %vs2, iXLen 8, iXLen %vl)2798  ret <vscale x 2 x float> %02799}2800 2801define void @test_sf_vc_fvi_se_e32m2(<vscale x 4 x float> %vs2, iXLen %vl) {2802; CHECK-LABEL: test_sf_vc_fvi_se_e32m2:2803; CHECK:       # %bb.0: # %entry2804; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2805; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82806; CHECK-NEXT:    ret2807entry:2808  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv4f32.nxv4f32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 4 x float> %vs2, iXLen 8, iXLen %vl)2809  ret void2810}2811 2812define <vscale x 4 x float> @test_sf_vc_v_fvi_se_e32m2(<vscale x 4 x float> %vs2, iXLen %vl) {2813; CHECK-LABEL: test_sf_vc_v_fvi_se_e32m2:2814; CHECK:       # %bb.0: # %entry2815; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2816; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82817; CHECK-NEXT:    ret2818entry:2819  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.iv.se.nxv4f32.nxv4f32.iXLen.iXLen(iXLen 3, <vscale x 4 x float> %vs2, iXLen 8, iXLen %vl)2820  ret <vscale x 4 x float> %02821}2822 2823define void @test_sf_vc_fvi_se_e32m4(<vscale x 8 x float> %vs2, iXLen %vl) {2824; CHECK-LABEL: test_sf_vc_fvi_se_e32m4:2825; CHECK:       # %bb.0: # %entry2826; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2827; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82828; CHECK-NEXT:    ret2829entry:2830  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv8f32.nxv8f32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 8 x float> %vs2, iXLen 8, iXLen %vl)2831  ret void2832}2833 2834define <vscale x 8 x float> @test_sf_vc_v_fvi_se_e32m4(<vscale x 8 x float> %vs2, iXLen %vl) {2835; CHECK-LABEL: test_sf_vc_v_fvi_se_e32m4:2836; CHECK:       # %bb.0: # %entry2837; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2838; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82839; CHECK-NEXT:    ret2840entry:2841  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.iv.se.nxv8f32.nxv8f32.iXLen.iXLen(iXLen 3, <vscale x 8 x float> %vs2, iXLen 8, iXLen %vl)2842  ret <vscale x 8 x float> %02843}2844 2845define void @test_sf_vc_fvi_se_e32m8(<vscale x 16 x float> %vs2, iXLen %vl) {2846; CHECK-LABEL: test_sf_vc_fvi_se_e32m8:2847; CHECK:       # %bb.0: # %entry2848; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2849; CHECK-NEXT:    sf.vc.iv 3, 31, v8, 82850; CHECK-NEXT:    ret2851entry:2852  tail call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv16f32.nxv16f32.iXLen.iXLen(iXLen 3, iXLen 31, <vscale x 16 x float> %vs2, iXLen 8, iXLen %vl)2853  ret void2854}2855 2856define <vscale x 16 x float> @test_sf_vc_v_fvi_se_e32m8(<vscale x 16 x float> %vs2, iXLen %vl) {2857; CHECK-LABEL: test_sf_vc_v_fvi_se_e32m8:2858; CHECK:       # %bb.0: # %entry2859; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2860; CHECK-NEXT:    sf.vc.v.iv 3, v8, v8, 82861; CHECK-NEXT:    ret2862entry:2863  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.iv.se.nxv16f32.nxv16f32.iXLen.iXLen(iXLen 3, <vscale x 16 x float> %vs2, iXLen 8, iXLen %vl)2864  ret <vscale x 16 x float> %02865}2866 2867define void @test_sf_vc_fvf_se_e16mf4(<vscale x 1 x half> %vs2, half %rs1, iXLen %vl) {2868; CHECK-LABEL: test_sf_vc_fvf_se_e16mf4:2869; CHECK:       # %bb.0: # %entry2870; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2871; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa02872; CHECK-NEXT:    ret2873entry:2874  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv1f16.nxv1f16.f16.iXLen(iXLen 1, iXLen 31, <vscale x 1 x half> %vs2, half %rs1, iXLen %vl)2875  ret void2876}2877 2878define <vscale x 1 x half> @test_sf_vc_v_fvf_se_e16mf4(<vscale x 1 x half> %vs2, half %rs1, iXLen %vl) {2879; CHECK-LABEL: test_sf_vc_v_fvf_se_e16mf4:2880; CHECK:       # %bb.0: # %entry2881; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2882; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa02883; CHECK-NEXT:    ret2884entry:2885  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.fv.se.nxv1f16.nxv1f16.iXLen.f16(iXLen 1, <vscale x 1 x half> %vs2, half %rs1, iXLen %vl)2886  ret <vscale x 1 x half> %02887}2888 2889define void @test_sf_vc_fvf_se_e16mf2(<vscale x 2 x half> %vs2, half %rs1, iXLen %vl) {2890; CHECK-LABEL: test_sf_vc_fvf_se_e16mf2:2891; CHECK:       # %bb.0: # %entry2892; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2893; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa02894; CHECK-NEXT:    ret2895entry:2896  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv2f16.nxv2f16.f16.iXLen(iXLen 1, iXLen 31, <vscale x 2 x half> %vs2, half %rs1, iXLen %vl)2897  ret void2898}2899 2900define <vscale x 2 x half> @test_sf_vc_v_fvf_se_e16mf2(<vscale x 2 x half> %vs2, half %rs1, iXLen %vl) {2901; CHECK-LABEL: test_sf_vc_v_fvf_se_e16mf2:2902; CHECK:       # %bb.0: # %entry2903; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2904; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa02905; CHECK-NEXT:    ret2906entry:2907  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.fv.se.nxv2f16.nxv2f16.iXLen.f16(iXLen 1, <vscale x 2 x half> %vs2, half %rs1, iXLen %vl)2908  ret <vscale x 2 x half> %02909}2910 2911define void @test_sf_vc_fvf_se_e16m1(<vscale x 4 x half> %vs2, half %rs1, iXLen %vl) {2912; CHECK-LABEL: test_sf_vc_fvf_se_e16m1:2913; CHECK:       # %bb.0: # %entry2914; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2915; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa02916; CHECK-NEXT:    ret2917entry:2918  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv4f16.nxv4f16.f16.iXLen(iXLen 1, iXLen 31, <vscale x 4 x half> %vs2, half %rs1, iXLen %vl)2919  ret void2920}2921 2922define <vscale x 4 x half> @test_sf_vc_v_fvf_se_e16m1(<vscale x 4 x half> %vs2, half %rs1, iXLen %vl) {2923; CHECK-LABEL: test_sf_vc_v_fvf_se_e16m1:2924; CHECK:       # %bb.0: # %entry2925; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2926; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa02927; CHECK-NEXT:    ret2928entry:2929  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.fv.se.nxv4f16.nxv4f16.iXLen.f16(iXLen 1, <vscale x 4 x half> %vs2, half %rs1, iXLen %vl)2930  ret <vscale x 4 x half> %02931}2932 2933define void @test_sf_vc_fvf_se_e16m2(<vscale x 8 x half> %vs2, half %rs1, iXLen %vl) {2934; CHECK-LABEL: test_sf_vc_fvf_se_e16m2:2935; CHECK:       # %bb.0: # %entry2936; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2937; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa02938; CHECK-NEXT:    ret2939entry:2940  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv8f16.nxv8f16.f16.iXLen(iXLen 1, iXLen 31, <vscale x 8 x half> %vs2, half %rs1, iXLen %vl)2941  ret void2942}2943 2944define <vscale x 8 x half> @test_sf_vc_v_fvf_se_e16m2(<vscale x 8 x half> %vs2, half %rs1, iXLen %vl) {2945; CHECK-LABEL: test_sf_vc_v_fvf_se_e16m2:2946; CHECK:       # %bb.0: # %entry2947; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2948; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa02949; CHECK-NEXT:    ret2950entry:2951  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.fv.se.nxv8f16.nxv8f16.iXLen.f16(iXLen 1, <vscale x 8 x half> %vs2, half %rs1, iXLen %vl)2952  ret <vscale x 8 x half> %02953}2954 2955define void @test_sf_vc_fvf_se_e16m4(<vscale x 16 x half> %vs2, half %rs1, iXLen %vl) {2956; CHECK-LABEL: test_sf_vc_fvf_se_e16m4:2957; CHECK:       # %bb.0: # %entry2958; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2959; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa02960; CHECK-NEXT:    ret2961entry:2962  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv16f16.nxv16f16.f16.iXLen(iXLen 1, iXLen 31, <vscale x 16 x half> %vs2, half %rs1, iXLen %vl)2963  ret void2964}2965 2966define <vscale x 16 x half> @test_sf_vc_v_fvf_se_e16m4(<vscale x 16 x half> %vs2, half %rs1, iXLen %vl) {2967; CHECK-LABEL: test_sf_vc_v_fvf_se_e16m4:2968; CHECK:       # %bb.0: # %entry2969; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2970; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa02971; CHECK-NEXT:    ret2972entry:2973  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.fv.se.nxv16f16.nxv16f16.iXLen.f16(iXLen 1, <vscale x 16 x half> %vs2, half %rs1, iXLen %vl)2974  ret <vscale x 16 x half> %02975}2976 2977define void @test_sf_vc_fvf_se_e16m8(<vscale x 32 x half> %vs2, half %rs1, iXLen %vl) {2978; CHECK-LABEL: test_sf_vc_fvf_se_e16m8:2979; CHECK:       # %bb.0: # %entry2980; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2981; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa02982; CHECK-NEXT:    ret2983entry:2984  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv32f16.nxv32f16.f16.iXLen(iXLen 1, iXLen 31, <vscale x 32 x half> %vs2, half %rs1, iXLen %vl)2985  ret void2986}2987 2988define <vscale x 32 x half> @test_sf_vc_v_fvf_se_e16m8(<vscale x 32 x half> %vs2, half %rs1, iXLen %vl) {2989; CHECK-LABEL: test_sf_vc_v_fvf_se_e16m8:2990; CHECK:       # %bb.0: # %entry2991; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2992; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa02993; CHECK-NEXT:    ret2994entry:2995  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.fv.se.nxv32f16.nxv32f16.iXLen.f16(iXLen 1, <vscale x 32 x half> %vs2, half %rs1, iXLen %vl)2996  ret <vscale x 32 x half> %02997}2998 2999define void @test_sf_vc_fvf_se_e32mf2(<vscale x 1 x float> %vs2, float %rs1, iXLen %vl) {3000; CHECK-LABEL: test_sf_vc_fvf_se_e32mf2:3001; CHECK:       # %bb.0: # %entry3002; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma3003; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa03004; CHECK-NEXT:    ret3005entry:3006  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv1f32.nxv1f32.f32.iXLen(iXLen 1, iXLen 31, <vscale x 1 x float> %vs2, float %rs1, iXLen %vl)3007  ret void3008}3009 3010define <vscale x 1 x float> @test_sf_vc_v_fvf_se_e32mf2(<vscale x 1 x float> %vs2, float %rs1, iXLen %vl) {3011; CHECK-LABEL: test_sf_vc_v_fvf_se_e32mf2:3012; CHECK:       # %bb.0: # %entry3013; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma3014; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa03015; CHECK-NEXT:    ret3016entry:3017  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.fv.se.nxv1f32.nxv1f32.iXLen.f32(iXLen 1, <vscale x 1 x float> %vs2, float %rs1, iXLen %vl)3018  ret <vscale x 1 x float> %03019}3020 3021define void @test_sf_vc_fvf_se_e32m1(<vscale x 2 x float> %vs2, float %rs1, iXLen %vl) {3022; CHECK-LABEL: test_sf_vc_fvf_se_e32m1:3023; CHECK:       # %bb.0: # %entry3024; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma3025; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa03026; CHECK-NEXT:    ret3027entry:3028  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv2f32.nxv2f32.f32.iXLen(iXLen 1, iXLen 31, <vscale x 2 x float> %vs2, float %rs1, iXLen %vl)3029  ret void3030}3031 3032define <vscale x 2 x float> @test_sf_vc_v_fvf_se_e32m1(<vscale x 2 x float> %vs2, float %rs1, iXLen %vl) {3033; CHECK-LABEL: test_sf_vc_v_fvf_se_e32m1:3034; CHECK:       # %bb.0: # %entry3035; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma3036; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa03037; CHECK-NEXT:    ret3038entry:3039  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.fv.se.nxv2f32.nxv2f32.iXLen.f32(iXLen 1, <vscale x 2 x float> %vs2, float %rs1, iXLen %vl)3040  ret <vscale x 2 x float> %03041}3042 3043define void @test_sf_vc_fvf_se_e32m2(<vscale x 4 x float> %vs2, float %rs1, iXLen %vl) {3044; CHECK-LABEL: test_sf_vc_fvf_se_e32m2:3045; CHECK:       # %bb.0: # %entry3046; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3047; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa03048; CHECK-NEXT:    ret3049entry:3050  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv4f32.nxv4f32.f32.iXLen(iXLen 1, iXLen 31, <vscale x 4 x float> %vs2, float %rs1, iXLen %vl)3051  ret void3052}3053 3054define <vscale x 4 x float> @test_sf_vc_v_fvf_se_e32m2(<vscale x 4 x float> %vs2, float %rs1, iXLen %vl) {3055; CHECK-LABEL: test_sf_vc_v_fvf_se_e32m2:3056; CHECK:       # %bb.0: # %entry3057; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3058; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa03059; CHECK-NEXT:    ret3060entry:3061  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.fv.se.nxv4f32.nxv4f32.iXLen.f32(iXLen 1, <vscale x 4 x float> %vs2, float %rs1, iXLen %vl)3062  ret <vscale x 4 x float> %03063}3064 3065define void @test_sf_vc_fvf_se_e32m4(<vscale x 8 x float> %vs2, float %rs1, iXLen %vl) {3066; CHECK-LABEL: test_sf_vc_fvf_se_e32m4:3067; CHECK:       # %bb.0: # %entry3068; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma3069; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa03070; CHECK-NEXT:    ret3071entry:3072  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv8f32.nxv8f32.f32.iXLen(iXLen 1, iXLen 31, <vscale x 8 x float> %vs2, float %rs1, iXLen %vl)3073  ret void3074}3075 3076define <vscale x 8 x float> @test_sf_vc_v_fvf_se_e32m4(<vscale x 8 x float> %vs2, float %rs1, iXLen %vl) {3077; CHECK-LABEL: test_sf_vc_v_fvf_se_e32m4:3078; CHECK:       # %bb.0: # %entry3079; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma3080; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa03081; CHECK-NEXT:    ret3082entry:3083  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.fv.se.nxv8f32.nxv8f32.iXLen.f32(iXLen 1, <vscale x 8 x float> %vs2, float %rs1, iXLen %vl)3084  ret <vscale x 8 x float> %03085}3086 3087define void @test_sf_vc_fvf_se_e32m8(<vscale x 16 x float> %vs2, float %rs1, iXLen %vl) {3088; CHECK-LABEL: test_sf_vc_fvf_se_e32m8:3089; CHECK:       # %bb.0: # %entry3090; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma3091; CHECK-NEXT:    sf.vc.fv 1, 31, v8, fa03092; CHECK-NEXT:    ret3093entry:3094  tail call void @llvm.riscv.sf.vc.fv.se.iXLen.nxv16f32.nxv16f32.f32.iXLen(iXLen 1, iXLen 31, <vscale x 16 x float> %vs2, float %rs1, iXLen %vl)3095  ret void3096}3097 3098define <vscale x 16 x float> @test_sf_vc_v_fvf_se_e32m8(<vscale x 16 x float> %vs2, float %rs1, iXLen %vl) {3099; CHECK-LABEL: test_sf_vc_v_fvf_se_e32m8:3100; CHECK:       # %bb.0: # %entry3101; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma3102; CHECK-NEXT:    sf.vc.v.fv 1, v8, v8, fa03103; CHECK-NEXT:    ret3104entry:3105  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.fv.se.nxv16f32.nxv16f32.iXLen.f32(iXLen 1, <vscale x 16 x float> %vs2, float %rs1, iXLen %vl)3106  ret <vscale x 16 x float> %03107}3108 3109