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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN:  sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh,+xsfvcp \3; RUN:    -verify-machineinstrs | FileCheck %s4; RUN:  sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh,+xsfvcp \5; RUN:    -verify-machineinstrs | FileCheck %s6 7define void @test_sf_vc_vvv_se_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {8; CHECK-LABEL: test_sf_vc_vvv_se_e8mf8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v1012; CHECK-NEXT:    ret13entry:14  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i8.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)15  ret void16}17 18define void @test_sf_vc_vvv_se_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {19; CHECK-LABEL: test_sf_vc_vvv_se_e8mf4:20; CHECK:       # %bb.0: # %entry21; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma22; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v1023; CHECK-NEXT:    ret24entry:25  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i8.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)26  ret void27}28 29define void @test_sf_vc_vvv_se_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {30; CHECK-LABEL: test_sf_vc_vvv_se_e8mf2:31; CHECK:       # %bb.0: # %entry32; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma33; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v1034; CHECK-NEXT:    ret35entry:36  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i8.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)37  ret void38}39 40define void @test_sf_vc_vvv_se_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {41; CHECK-LABEL: test_sf_vc_vvv_se_e8m1:42; CHECK:       # %bb.0: # %entry43; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma44; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v1045; CHECK-NEXT:    ret46entry:47  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i8.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)48  ret void49}50 51define void @test_sf_vc_vvv_se_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {52; CHECK-LABEL: test_sf_vc_vvv_se_e8m2:53; CHECK:       # %bb.0: # %entry54; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma55; CHECK-NEXT:    sf.vc.vvv 3, v8, v10, v1256; CHECK-NEXT:    ret57entry:58  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i8.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)59  ret void60}61 62define void @test_sf_vc_vvv_se_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {63; CHECK-LABEL: test_sf_vc_vvv_se_e8m4:64; CHECK:       # %bb.0: # %entry65; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma66; CHECK-NEXT:    sf.vc.vvv 3, v8, v12, v1667; CHECK-NEXT:    ret68entry:69  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32i8.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)70  ret void71}72 73define void @test_sf_vc_vvv_se_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl) {74; CHECK-LABEL: test_sf_vc_vvv_se_e8m8:75; CHECK:       # %bb.0: # %entry76; CHECK-NEXT:    vl8r.v v24, (a0)77; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma78; CHECK-NEXT:    sf.vc.vvv 3, v8, v16, v2479; CHECK-NEXT:    ret80entry:81  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv64i8.nxv64i8.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl)82  ret void83}84 85define void @test_sf_vc_vvv_se_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {86; CHECK-LABEL: test_sf_vc_vvv_se_e16mf4:87; CHECK:       # %bb.0: # %entry88; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma89; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v1090; CHECK-NEXT:    ret91entry:92  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)93  ret void94}95 96define void @test_sf_vc_vvv_se_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {97; CHECK-LABEL: test_sf_vc_vvv_se_e16mf2:98; CHECK:       # %bb.0: # %entry99; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma100; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v10101; CHECK-NEXT:    ret102entry:103  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)104  ret void105}106 107define void @test_sf_vc_vvv_se_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {108; CHECK-LABEL: test_sf_vc_vvv_se_e16m1:109; CHECK:       # %bb.0: # %entry110; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma111; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v10112; CHECK-NEXT:    ret113entry:114  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)115  ret void116}117 118define void @test_sf_vc_vvv_se_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {119; CHECK-LABEL: test_sf_vc_vvv_se_e16m2:120; CHECK:       # %bb.0: # %entry121; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma122; CHECK-NEXT:    sf.vc.vvv 3, v8, v10, v12123; CHECK-NEXT:    ret124entry:125  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)126  ret void127}128 129define void @test_sf_vc_vvv_se_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {130; CHECK-LABEL: test_sf_vc_vvv_se_e16m4:131; CHECK:       # %bb.0: # %entry132; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma133; CHECK-NEXT:    sf.vc.vvv 3, v8, v12, v16134; CHECK-NEXT:    ret135entry:136  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)137  ret void138}139 140define void @test_sf_vc_vvv_se_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {141; CHECK-LABEL: test_sf_vc_vvv_se_e16m8:142; CHECK:       # %bb.0: # %entry143; CHECK-NEXT:    vl8re16.v v24, (a0)144; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma145; CHECK-NEXT:    sf.vc.vvv 3, v8, v16, v24146; CHECK-NEXT:    ret147entry:148  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32i16.nxv32i16.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)149  ret void150}151 152define void @test_sf_vc_vvv_se_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {153; CHECK-LABEL: test_sf_vc_vvv_se_e32mf2:154; CHECK:       # %bb.0: # %entry155; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma156; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v10157; CHECK-NEXT:    ret158entry:159  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)160  ret void161}162 163define void @test_sf_vc_vvv_se_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {164; CHECK-LABEL: test_sf_vc_vvv_se_e32m1:165; CHECK:       # %bb.0: # %entry166; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma167; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v10168; CHECK-NEXT:    ret169entry:170  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)171  ret void172}173 174define void @test_sf_vc_vvv_se_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {175; CHECK-LABEL: test_sf_vc_vvv_se_e32m2:176; CHECK:       # %bb.0: # %entry177; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma178; CHECK-NEXT:    sf.vc.vvv 3, v8, v10, v12179; CHECK-NEXT:    ret180entry:181  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)182  ret void183}184 185define void @test_sf_vc_vvv_se_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {186; CHECK-LABEL: test_sf_vc_vvv_se_e32m4:187; CHECK:       # %bb.0: # %entry188; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma189; CHECK-NEXT:    sf.vc.vvv 3, v8, v12, v16190; CHECK-NEXT:    ret191entry:192  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)193  ret void194}195 196define void @test_sf_vc_vvv_se_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {197; CHECK-LABEL: test_sf_vc_vvv_se_e32m8:198; CHECK:       # %bb.0: # %entry199; CHECK-NEXT:    vl8re32.v v24, (a0)200; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma201; CHECK-NEXT:    sf.vc.vvv 3, v8, v16, v24202; CHECK-NEXT:    ret203entry:204  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16i32.nxv16i32.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)205  ret void206}207 208define void @test_sf_vc_vvv_se_e64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {209; CHECK-LABEL: test_sf_vc_vvv_se_e64m1:210; CHECK:       # %bb.0: # %entry211; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma212; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v10213; CHECK-NEXT:    ret214entry:215  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1i64.nxv1i64.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)216  ret void217}218 219define void @test_sf_vc_vvv_se_e64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {220; CHECK-LABEL: test_sf_vc_vvv_se_e64m2:221; CHECK:       # %bb.0: # %entry222; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma223; CHECK-NEXT:    sf.vc.vvv 3, v8, v10, v12224; CHECK-NEXT:    ret225entry:226  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2i64.nxv2i64.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)227  ret void228}229 230define void @test_sf_vc_vvv_se_e64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {231; CHECK-LABEL: test_sf_vc_vvv_se_e64m4:232; CHECK:       # %bb.0: # %entry233; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma234; CHECK-NEXT:    sf.vc.vvv 3, v8, v12, v16235; CHECK-NEXT:    ret236entry:237  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4i64.nxv4i64.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)238  ret void239}240 241define void @test_sf_vc_vvv_se_e64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {242; CHECK-LABEL: test_sf_vc_vvv_se_e64m8:243; CHECK:       # %bb.0: # %entry244; CHECK-NEXT:    vl8re64.v v24, (a0)245; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma246; CHECK-NEXT:    sf.vc.vvv 3, v8, v16, v24247; CHECK-NEXT:    ret248entry:249  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8i64.nxv8i64.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)250  ret void251}252 253define <vscale x 1 x i8> @test_sf_vc_v_vvv_se_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {254; CHECK-LABEL: test_sf_vc_v_vvv_se_e8mf8:255; CHECK:       # %bb.0: # %entry256; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma257; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10258; CHECK-NEXT:    ret259entry:260  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv1i8.iXLen.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)261  ret <vscale x 1 x i8> %0262}263 264define <vscale x 2 x i8> @test_sf_vc_v_vvv_se_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {265; CHECK-LABEL: test_sf_vc_v_vvv_se_e8mf4:266; CHECK:       # %bb.0: # %entry267; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma268; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10269; CHECK-NEXT:    ret270entry:271  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv2i8.iXLen.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)272  ret <vscale x 2 x i8> %0273}274 275define <vscale x 4 x i8> @test_sf_vc_v_vvv_se_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {276; CHECK-LABEL: test_sf_vc_v_vvv_se_e8mf2:277; CHECK:       # %bb.0: # %entry278; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma279; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10280; CHECK-NEXT:    ret281entry:282  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv4i8.iXLen.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)283  ret <vscale x 4 x i8> %0284}285 286define <vscale x 8 x i8> @test_sf_vc_v_vvv_se_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {287; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m1:288; CHECK:       # %bb.0: # %entry289; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma290; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10291; CHECK-NEXT:    ret292entry:293  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv8i8.iXLen.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)294  ret <vscale x 8 x i8> %0295}296 297define <vscale x 16 x i8> @test_sf_vc_v_vvv_se_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {298; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m2:299; CHECK:       # %bb.0: # %entry300; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma301; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12302; CHECK-NEXT:    ret303entry:304  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv16i8.iXLen.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)305  ret <vscale x 16 x i8> %0306}307 308define <vscale x 32 x i8> @test_sf_vc_v_vvv_se_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {309; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m4:310; CHECK:       # %bb.0: # %entry311; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma312; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16313; CHECK-NEXT:    ret314entry:315  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv32i8.iXLen.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)316  ret <vscale x 32 x i8> %0317}318 319define <vscale x 64 x i8> @test_sf_vc_v_vvv_se_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl) {320; CHECK-LABEL: test_sf_vc_v_vvv_se_e8m8:321; CHECK:       # %bb.0: # %entry322; CHECK-NEXT:    vl8r.v v24, (a0)323; CHECK-NEXT:    vsetvli zero, a1, e8, m8, tu, ma324; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24325; CHECK-NEXT:    ret326entry:327  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vvv.se.nxv64i8.iXLen.nxv64i8.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl)328  ret <vscale x 64 x i8> %0329}330 331define <vscale x 1 x i16> @test_sf_vc_v_vvv_se_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {332; CHECK-LABEL: test_sf_vc_v_vvv_se_e16mf4:333; CHECK:       # %bb.0: # %entry334; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma335; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10336; CHECK-NEXT:    ret337entry:338  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv1i16.iXLen.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)339  ret <vscale x 1 x i16> %0340}341 342define <vscale x 2 x i16> @test_sf_vc_v_vvv_se_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {343; CHECK-LABEL: test_sf_vc_v_vvv_se_e16mf2:344; CHECK:       # %bb.0: # %entry345; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma346; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10347; CHECK-NEXT:    ret348entry:349  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv2i16.iXLen.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)350  ret <vscale x 2 x i16> %0351}352 353define <vscale x 4 x i16> @test_sf_vc_v_vvv_se_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {354; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m1:355; CHECK:       # %bb.0: # %entry356; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma357; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10358; CHECK-NEXT:    ret359entry:360  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv4i16.iXLen.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)361  ret <vscale x 4 x i16> %0362}363 364define <vscale x 8 x i16> @test_sf_vc_v_vvv_se_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {365; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m2:366; CHECK:       # %bb.0: # %entry367; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma368; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12369; CHECK-NEXT:    ret370entry:371  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv8i16.iXLen.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)372  ret <vscale x 8 x i16> %0373}374 375define <vscale x 16 x i16> @test_sf_vc_v_vvv_se_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {376; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m4:377; CHECK:       # %bb.0: # %entry378; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma379; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16380; CHECK-NEXT:    ret381entry:382  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv16i16.iXLen.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)383  ret <vscale x 16 x i16> %0384}385 386define <vscale x 32 x i16> @test_sf_vc_v_vvv_se_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {387; CHECK-LABEL: test_sf_vc_v_vvv_se_e16m8:388; CHECK:       # %bb.0: # %entry389; CHECK-NEXT:    vl8re16.v v24, (a0)390; CHECK-NEXT:    vsetvli zero, a1, e16, m8, tu, ma391; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24392; CHECK-NEXT:    ret393entry:394  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvv.se.nxv32i16.iXLen.nxv32i16.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)395  ret <vscale x 32 x i16> %0396}397 398define <vscale x 1 x i32> @test_sf_vc_v_vvv_se_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {399; CHECK-LABEL: test_sf_vc_v_vvv_se_e32mf2:400; CHECK:       # %bb.0: # %entry401; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma402; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10403; CHECK-NEXT:    ret404entry:405  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv1i32.iXLen.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)406  ret <vscale x 1 x i32> %0407}408 409define <vscale x 2 x i32> @test_sf_vc_v_vvv_se_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {410; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m1:411; CHECK:       # %bb.0: # %entry412; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma413; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10414; CHECK-NEXT:    ret415entry:416  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv2i32.iXLen.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)417  ret <vscale x 2 x i32> %0418}419 420define <vscale x 4 x i32> @test_sf_vc_v_vvv_se_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {421; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m2:422; CHECK:       # %bb.0: # %entry423; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma424; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12425; CHECK-NEXT:    ret426entry:427  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv4i32.iXLen.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)428  ret <vscale x 4 x i32> %0429}430 431define <vscale x 8 x i32> @test_sf_vc_v_vvv_se_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {432; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m4:433; CHECK:       # %bb.0: # %entry434; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma435; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16436; CHECK-NEXT:    ret437entry:438  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv8i32.iXLen.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)439  ret <vscale x 8 x i32> %0440}441 442define <vscale x 16 x i32> @test_sf_vc_v_vvv_se_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {443; CHECK-LABEL: test_sf_vc_v_vvv_se_e32m8:444; CHECK:       # %bb.0: # %entry445; CHECK-NEXT:    vl8re32.v v24, (a0)446; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, ma447; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24448; CHECK-NEXT:    ret449entry:450  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvv.se.nxv16i32.iXLen.nxv16i32.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)451  ret <vscale x 16 x i32> %0452}453 454define <vscale x 1 x i64> @test_sf_vc_v_vvv_se_e64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {455; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m1:456; CHECK:       # %bb.0: # %entry457; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma458; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10459; CHECK-NEXT:    ret460entry:461  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv1i64.iXLen.nxv1i64.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)462  ret <vscale x 1 x i64> %0463}464 465define <vscale x 2 x i64> @test_sf_vc_v_vvv_se_e64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {466; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m2:467; CHECK:       # %bb.0: # %entry468; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma469; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12470; CHECK-NEXT:    ret471entry:472  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv2i64.iXLen.nxv2i64.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)473  ret <vscale x 2 x i64> %0474}475 476define <vscale x 4 x i64> @test_sf_vc_v_vvv_se_e64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {477; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m4:478; CHECK:       # %bb.0: # %entry479; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma480; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16481; CHECK-NEXT:    ret482entry:483  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv4i64.iXLen.nxv4i64.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)484  ret <vscale x 4 x i64> %0485}486 487define <vscale x 8 x i64> @test_sf_vc_v_vvv_se_e64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {488; CHECK-LABEL: test_sf_vc_v_vvv_se_e64m8:489; CHECK:       # %bb.0: # %entry490; CHECK-NEXT:    vl8re64.v v24, (a0)491; CHECK-NEXT:    vsetvli zero, a1, e64, m8, tu, ma492; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24493; CHECK-NEXT:    ret494entry:495  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvv.se.nxv8i64.iXLen.nxv8i64.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)496  ret <vscale x 8 x i64> %0497}498 499define <vscale x 1 x i8> @test_sf_vc_v_vvv_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {500; CHECK-LABEL: test_sf_vc_v_vvv_e8mf8:501; CHECK:       # %bb.0: # %entry502; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma503; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10504; CHECK-NEXT:    ret505entry:506  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.vvv.nxv1i8.iXLen.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)507  ret <vscale x 1 x i8> %0508}509 510define <vscale x 2 x i8> @test_sf_vc_v_vvv_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {511; CHECK-LABEL: test_sf_vc_v_vvv_e8mf4:512; CHECK:       # %bb.0: # %entry513; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma514; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10515; CHECK-NEXT:    ret516entry:517  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.vvv.nxv2i8.iXLen.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)518  ret <vscale x 2 x i8> %0519}520 521define <vscale x 4 x i8> @test_sf_vc_v_vvv_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {522; CHECK-LABEL: test_sf_vc_v_vvv_e8mf2:523; CHECK:       # %bb.0: # %entry524; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma525; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10526; CHECK-NEXT:    ret527entry:528  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.vvv.nxv4i8.iXLen.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)529  ret <vscale x 4 x i8> %0530}531 532define <vscale x 8 x i8> @test_sf_vc_v_vvv_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {533; CHECK-LABEL: test_sf_vc_v_vvv_e8m1:534; CHECK:       # %bb.0: # %entry535; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma536; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10537; CHECK-NEXT:    ret538entry:539  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.vvv.nxv8i8.iXLen.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)540  ret <vscale x 8 x i8> %0541}542 543define <vscale x 16 x i8> @test_sf_vc_v_vvv_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {544; CHECK-LABEL: test_sf_vc_v_vvv_e8m2:545; CHECK:       # %bb.0: # %entry546; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma547; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12548; CHECK-NEXT:    ret549entry:550  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.vvv.nxv16i8.iXLen.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)551  ret <vscale x 16 x i8> %0552}553 554define <vscale x 32 x i8> @test_sf_vc_v_vvv_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {555; CHECK-LABEL: test_sf_vc_v_vvv_e8m4:556; CHECK:       # %bb.0: # %entry557; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma558; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16559; CHECK-NEXT:    ret560entry:561  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.vvv.nxv32i8.iXLen.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)562  ret <vscale x 32 x i8> %0563}564 565define <vscale x 64 x i8> @test_sf_vc_v_vvv_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl) {566; CHECK-LABEL: test_sf_vc_v_vvv_e8m8:567; CHECK:       # %bb.0: # %entry568; CHECK-NEXT:    vl8r.v v24, (a0)569; CHECK-NEXT:    vsetvli zero, a1, e8, m8, tu, ma570; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24571; CHECK-NEXT:    ret572entry:573  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.vvv.nxv64i8.iXLen.nxv64i8.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, <vscale x 64 x i8> %vs1, iXLen %vl)574  ret <vscale x 64 x i8> %0575}576 577define <vscale x 1 x i16> @test_sf_vc_v_vvv_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {578; CHECK-LABEL: test_sf_vc_v_vvv_e16mf4:579; CHECK:       # %bb.0: # %entry580; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma581; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10582; CHECK-NEXT:    ret583entry:584  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvv.nxv1i16.iXLen.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)585  ret <vscale x 1 x i16> %0586}587 588define <vscale x 2 x i16> @test_sf_vc_v_vvv_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {589; CHECK-LABEL: test_sf_vc_v_vvv_e16mf2:590; CHECK:       # %bb.0: # %entry591; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma592; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10593; CHECK-NEXT:    ret594entry:595  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvv.nxv2i16.iXLen.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)596  ret <vscale x 2 x i16> %0597}598 599define <vscale x 4 x i16> @test_sf_vc_v_vvv_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {600; CHECK-LABEL: test_sf_vc_v_vvv_e16m1:601; CHECK:       # %bb.0: # %entry602; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma603; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10604; CHECK-NEXT:    ret605entry:606  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvv.nxv4i16.iXLen.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)607  ret <vscale x 4 x i16> %0608}609 610define <vscale x 8 x i16> @test_sf_vc_v_vvv_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {611; CHECK-LABEL: test_sf_vc_v_vvv_e16m2:612; CHECK:       # %bb.0: # %entry613; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma614; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12615; CHECK-NEXT:    ret616entry:617  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvv.nxv8i16.iXLen.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)618  ret <vscale x 8 x i16> %0619}620 621define <vscale x 16 x i16> @test_sf_vc_v_vvv_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {622; CHECK-LABEL: test_sf_vc_v_vvv_e16m4:623; CHECK:       # %bb.0: # %entry624; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma625; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16626; CHECK-NEXT:    ret627entry:628  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvv.nxv16i16.iXLen.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)629  ret <vscale x 16 x i16> %0630}631 632define <vscale x 32 x i16> @test_sf_vc_v_vvv_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {633; CHECK-LABEL: test_sf_vc_v_vvv_e16m8:634; CHECK:       # %bb.0: # %entry635; CHECK-NEXT:    vl8re16.v v24, (a0)636; CHECK-NEXT:    vsetvli zero, a1, e16, m8, tu, ma637; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24638; CHECK-NEXT:    ret639entry:640  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvv.nxv32i16.iXLen.nxv32i16.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)641  ret <vscale x 32 x i16> %0642}643 644define <vscale x 1 x i32> @test_sf_vc_v_vvv_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {645; CHECK-LABEL: test_sf_vc_v_vvv_e32mf2:646; CHECK:       # %bb.0: # %entry647; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma648; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10649; CHECK-NEXT:    ret650entry:651  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvv.nxv1i32.iXLen.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)652  ret <vscale x 1 x i32> %0653}654 655define <vscale x 2 x i32> @test_sf_vc_v_vvv_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {656; CHECK-LABEL: test_sf_vc_v_vvv_e32m1:657; CHECK:       # %bb.0: # %entry658; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma659; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10660; CHECK-NEXT:    ret661entry:662  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvv.nxv2i32.iXLen.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)663  ret <vscale x 2 x i32> %0664}665 666define <vscale x 4 x i32> @test_sf_vc_v_vvv_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {667; CHECK-LABEL: test_sf_vc_v_vvv_e32m2:668; CHECK:       # %bb.0: # %entry669; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma670; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12671; CHECK-NEXT:    ret672entry:673  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvv.nxv4i32.iXLen.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)674  ret <vscale x 4 x i32> %0675}676 677define <vscale x 8 x i32> @test_sf_vc_v_vvv_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {678; CHECK-LABEL: test_sf_vc_v_vvv_e32m4:679; CHECK:       # %bb.0: # %entry680; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma681; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16682; CHECK-NEXT:    ret683entry:684  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvv.nxv8i32.iXLen.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)685  ret <vscale x 8 x i32> %0686}687 688define <vscale x 16 x i32> @test_sf_vc_v_vvv_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {689; CHECK-LABEL: test_sf_vc_v_vvv_e32m8:690; CHECK:       # %bb.0: # %entry691; CHECK-NEXT:    vl8re32.v v24, (a0)692; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, ma693; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24694; CHECK-NEXT:    ret695entry:696  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvv.nxv16i32.iXLen.nxv16i32.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)697  ret <vscale x 16 x i32> %0698}699 700define <vscale x 1 x i64> @test_sf_vc_v_vvv_e64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {701; CHECK-LABEL: test_sf_vc_v_vvv_e64m1:702; CHECK:       # %bb.0: # %entry703; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma704; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v10705; CHECK-NEXT:    ret706entry:707  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvv.nxv1i64.iXLen.nxv1i64.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)708  ret <vscale x 1 x i64> %0709}710 711define <vscale x 2 x i64> @test_sf_vc_v_vvv_e64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {712; CHECK-LABEL: test_sf_vc_v_vvv_e64m2:713; CHECK:       # %bb.0: # %entry714; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma715; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v12716; CHECK-NEXT:    ret717entry:718  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvv.nxv2i64.iXLen.nxv2i64.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)719  ret <vscale x 2 x i64> %0720}721 722define <vscale x 4 x i64> @test_sf_vc_v_vvv_e64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {723; CHECK-LABEL: test_sf_vc_v_vvv_e64m4:724; CHECK:       # %bb.0: # %entry725; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma726; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v16727; CHECK-NEXT:    ret728entry:729  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvv.nxv4i64.iXLen.nxv4i64.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)730  ret <vscale x 4 x i64> %0731}732 733define <vscale x 8 x i64> @test_sf_vc_v_vvv_e64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {734; CHECK-LABEL: test_sf_vc_v_vvv_e64m8:735; CHECK:       # %bb.0: # %entry736; CHECK-NEXT:    vl8re64.v v24, (a0)737; CHECK-NEXT:    vsetvli zero, a1, e64, m8, tu, ma738; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v24739; CHECK-NEXT:    ret740entry:741  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvv.nxv8i64.iXLen.nxv8i64.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)742  ret <vscale x 8 x i64> %0743}744 745define void @test_sf_vc_xvv_se_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {746; CHECK-LABEL: test_sf_vc_xvv_se_e8mf8:747; CHECK:       # %bb.0: # %entry748; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma749; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0750; CHECK-NEXT:    ret751entry:752  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1i8.i8.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)753  ret void754}755 756define void @test_sf_vc_xvv_se_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {757; CHECK-LABEL: test_sf_vc_xvv_se_e8mf4:758; CHECK:       # %bb.0: # %entry759; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma760; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0761; CHECK-NEXT:    ret762entry:763  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2i8.i8.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)764  ret void765}766 767define void @test_sf_vc_xvv_se_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {768; CHECK-LABEL: test_sf_vc_xvv_se_e8mf2:769; CHECK:       # %bb.0: # %entry770; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma771; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0772; CHECK-NEXT:    ret773entry:774  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4i8.i8.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)775  ret void776}777 778define void @test_sf_vc_xvv_se_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {779; CHECK-LABEL: test_sf_vc_xvv_se_e8m1:780; CHECK:       # %bb.0: # %entry781; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma782; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0783; CHECK-NEXT:    ret784entry:785  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8i8.i8.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)786  ret void787}788 789define void @test_sf_vc_xvv_se_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {790; CHECK-LABEL: test_sf_vc_xvv_se_e8m2:791; CHECK:       # %bb.0: # %entry792; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma793; CHECK-NEXT:    sf.vc.xvv 3, v8, v10, a0794; CHECK-NEXT:    ret795entry:796  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16i8.i8.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)797  ret void798}799 800define void @test_sf_vc_xvv_se_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {801; CHECK-LABEL: test_sf_vc_xvv_se_e8m4:802; CHECK:       # %bb.0: # %entry803; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma804; CHECK-NEXT:    sf.vc.xvv 3, v8, v12, a0805; CHECK-NEXT:    ret806entry:807  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32i8.i8.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)808  ret void809}810 811define void @test_sf_vc_xvv_se_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {812; CHECK-LABEL: test_sf_vc_xvv_se_e8m8:813; CHECK:       # %bb.0: # %entry814; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma815; CHECK-NEXT:    sf.vc.xvv 3, v8, v16, a0816; CHECK-NEXT:    ret817entry:818  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv64i8.i8.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i8 %rs1, iXLen %vl)819  ret void820}821 822define void @test_sf_vc_xvv_se_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {823; CHECK-LABEL: test_sf_vc_xvv_se_e16mf4:824; CHECK:       # %bb.0: # %entry825; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma826; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0827; CHECK-NEXT:    ret828entry:829  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)830  ret void831}832 833define void @test_sf_vc_xvv_se_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {834; CHECK-LABEL: test_sf_vc_xvv_se_e16mf2:835; CHECK:       # %bb.0: # %entry836; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma837; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0838; CHECK-NEXT:    ret839entry:840  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)841  ret void842}843 844define void @test_sf_vc_xvv_se_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {845; CHECK-LABEL: test_sf_vc_xvv_se_e16m1:846; CHECK:       # %bb.0: # %entry847; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma848; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0849; CHECK-NEXT:    ret850entry:851  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)852  ret void853}854 855define void @test_sf_vc_xvv_se_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {856; CHECK-LABEL: test_sf_vc_xvv_se_e16m2:857; CHECK:       # %bb.0: # %entry858; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma859; CHECK-NEXT:    sf.vc.xvv 3, v8, v10, a0860; CHECK-NEXT:    ret861entry:862  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)863  ret void864}865 866define void @test_sf_vc_xvv_se_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {867; CHECK-LABEL: test_sf_vc_xvv_se_e16m4:868; CHECK:       # %bb.0: # %entry869; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma870; CHECK-NEXT:    sf.vc.xvv 3, v8, v12, a0871; CHECK-NEXT:    ret872entry:873  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)874  ret void875}876 877define void @test_sf_vc_xvv_se_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {878; CHECK-LABEL: test_sf_vc_xvv_se_e16m8:879; CHECK:       # %bb.0: # %entry880; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma881; CHECK-NEXT:    sf.vc.xvv 3, v8, v16, a0882; CHECK-NEXT:    ret883entry:884  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32i16.i16.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)885  ret void886}887 888define void @test_sf_vc_xvv_se_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {889; CHECK-LABEL: test_sf_vc_xvv_se_e32mf2:890; CHECK:       # %bb.0: # %entry891; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma892; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0893; CHECK-NEXT:    ret894entry:895  tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)896  ret void897}898 899define void @test_sf_vc_xvv_se_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {900; CHECK-LABEL: test_sf_vc_xvv_se_e32m1:901; CHECK:       # %bb.0: # %entry902; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma903; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a0904; CHECK-NEXT:    ret905entry:906  tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)907  ret void908}909 910define void @test_sf_vc_xvv_se_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {911; CHECK-LABEL: test_sf_vc_xvv_se_e32m2:912; CHECK:       # %bb.0: # %entry913; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma914; CHECK-NEXT:    sf.vc.xvv 3, v8, v10, a0915; CHECK-NEXT:    ret916entry:917  tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)918  ret void919}920 921define void @test_sf_vc_xvv_se_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {922; CHECK-LABEL: test_sf_vc_xvv_se_e32m4:923; CHECK:       # %bb.0: # %entry924; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma925; CHECK-NEXT:    sf.vc.xvv 3, v8, v12, a0926; CHECK-NEXT:    ret927entry:928  tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)929  ret void930}931 932define void @test_sf_vc_xvv_se_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 signext %rs1, iXLen %vl) {933; CHECK-LABEL: test_sf_vc_xvv_se_e32m8:934; CHECK:       # %bb.0: # %entry935; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma936; CHECK-NEXT:    sf.vc.xvv 3, v8, v16, a0937; CHECK-NEXT:    ret938entry:939  tail call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i32.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)940  ret void941}942 943define <vscale x 1 x i8> @test_sf_vc_v_xvv_se_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {944; CHECK-LABEL: test_sf_vc_v_xvv_se_e8mf8:945; CHECK:       # %bb.0: # %entry946; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, tu, ma947; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a0948; CHECK-NEXT:    ret949entry:950  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv1i8.iXLen.i8.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)951  ret <vscale x 1 x i8> %0952}953 954define <vscale x 2 x i8> @test_sf_vc_v_xvv_se_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {955; CHECK-LABEL: test_sf_vc_v_xvv_se_e8mf4:956; CHECK:       # %bb.0: # %entry957; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, tu, ma958; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a0959; CHECK-NEXT:    ret960entry:961  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv2i8.iXLen.i8.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)962  ret <vscale x 2 x i8> %0963}964 965define <vscale x 4 x i8> @test_sf_vc_v_xvv_se_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {966; CHECK-LABEL: test_sf_vc_v_xvv_se_e8mf2:967; CHECK:       # %bb.0: # %entry968; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, tu, ma969; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a0970; CHECK-NEXT:    ret971entry:972  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv4i8.iXLen.i8.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)973  ret <vscale x 4 x i8> %0974}975 976define <vscale x 8 x i8> @test_sf_vc_v_xvv_se_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {977; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m1:978; CHECK:       # %bb.0: # %entry979; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma980; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a0981; CHECK-NEXT:    ret982entry:983  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv8i8.iXLen.i8.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)984  ret <vscale x 8 x i8> %0985}986 987define <vscale x 16 x i8> @test_sf_vc_v_xvv_se_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {988; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m2:989; CHECK:       # %bb.0: # %entry990; CHECK-NEXT:    vsetvli zero, a1, e8, m2, tu, ma991; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a0992; CHECK-NEXT:    ret993entry:994  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv16i8.iXLen.i8.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)995  ret <vscale x 16 x i8> %0996}997 998define <vscale x 32 x i8> @test_sf_vc_v_xvv_se_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {999; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m4:1000; CHECK:       # %bb.0: # %entry1001; CHECK-NEXT:    vsetvli zero, a1, e8, m4, tu, ma1002; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a01003; CHECK-NEXT:    ret1004entry:1005  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv32i8.iXLen.i8.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)1006  ret <vscale x 32 x i8> %01007}1008 1009define <vscale x 64 x i8> @test_sf_vc_v_xvv_se_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1010; CHECK-LABEL: test_sf_vc_v_xvv_se_e8m8:1011; CHECK:       # %bb.0: # %entry1012; CHECK-NEXT:    vsetvli zero, a1, e8, m8, tu, ma1013; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a01014; CHECK-NEXT:    ret1015entry:1016  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xvv.se.nxv64i8.iXLen.i8.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i8 %rs1, iXLen %vl)1017  ret <vscale x 64 x i8> %01018}1019 1020define <vscale x 1 x i16> @test_sf_vc_v_xvv_se_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1021; CHECK-LABEL: test_sf_vc_v_xvv_se_e16mf4:1022; CHECK:       # %bb.0: # %entry1023; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, ma1024; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01025; CHECK-NEXT:    ret1026entry:1027  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv1i16.iXLen.i16.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)1028  ret <vscale x 1 x i16> %01029}1030 1031define <vscale x 2 x i16> @test_sf_vc_v_xvv_se_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1032; CHECK-LABEL: test_sf_vc_v_xvv_se_e16mf2:1033; CHECK:       # %bb.0: # %entry1034; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, ma1035; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01036; CHECK-NEXT:    ret1037entry:1038  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv2i16.iXLen.i16.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)1039  ret <vscale x 2 x i16> %01040}1041 1042define <vscale x 4 x i16> @test_sf_vc_v_xvv_se_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1043; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m1:1044; CHECK:       # %bb.0: # %entry1045; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma1046; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01047; CHECK-NEXT:    ret1048entry:1049  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv4i16.iXLen.i16.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)1050  ret <vscale x 4 x i16> %01051}1052 1053define <vscale x 8 x i16> @test_sf_vc_v_xvv_se_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1054; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m2:1055; CHECK:       # %bb.0: # %entry1056; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, ma1057; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a01058; CHECK-NEXT:    ret1059entry:1060  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv8i16.iXLen.i16.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)1061  ret <vscale x 8 x i16> %01062}1063 1064define <vscale x 16 x i16> @test_sf_vc_v_xvv_se_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1065; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m4:1066; CHECK:       # %bb.0: # %entry1067; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, ma1068; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a01069; CHECK-NEXT:    ret1070entry:1071  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv16i16.iXLen.i16.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)1072  ret <vscale x 16 x i16> %01073}1074 1075define <vscale x 32 x i16> @test_sf_vc_v_xvv_se_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1076; CHECK-LABEL: test_sf_vc_v_xvv_se_e16m8:1077; CHECK:       # %bb.0: # %entry1078; CHECK-NEXT:    vsetvli zero, a1, e16, m8, tu, ma1079; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a01080; CHECK-NEXT:    ret1081entry:1082  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvv.se.nxv32i16.iXLen.i16.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)1083  ret <vscale x 32 x i16> %01084}1085 1086define <vscale x 1 x i32> @test_sf_vc_v_xvv_se_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1087; CHECK-LABEL: test_sf_vc_v_xvv_se_e32mf2:1088; CHECK:       # %bb.0: # %entry1089; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma1090; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01091; CHECK-NEXT:    ret1092entry:1093  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv1i32.iXLen.i32.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)1094  ret <vscale x 1 x i32> %01095}1096 1097define <vscale x 2 x i32> @test_sf_vc_v_xvv_se_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1098; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m1:1099; CHECK:       # %bb.0: # %entry1100; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma1101; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01102; CHECK-NEXT:    ret1103entry:1104  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv2i32.iXLen.i32.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)1105  ret <vscale x 2 x i32> %01106}1107 1108define <vscale x 4 x i32> @test_sf_vc_v_xvv_se_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1109; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m2:1110; CHECK:       # %bb.0: # %entry1111; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma1112; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a01113; CHECK-NEXT:    ret1114entry:1115  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv4i32.iXLen.i32.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)1116  ret <vscale x 4 x i32> %01117}1118 1119define <vscale x 8 x i32> @test_sf_vc_v_xvv_se_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1120; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m4:1121; CHECK:       # %bb.0: # %entry1122; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma1123; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a01124; CHECK-NEXT:    ret1125entry:1126  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv8i32.iXLen.i32.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)1127  ret <vscale x 8 x i32> %01128}1129 1130define <vscale x 16 x i32> @test_sf_vc_v_xvv_se_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1131; CHECK-LABEL: test_sf_vc_v_xvv_se_e32m8:1132; CHECK:       # %bb.0: # %entry1133; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, ma1134; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a01135; CHECK-NEXT:    ret1136entry:1137  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvv.se.nxv16i32.iXLen.i32.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)1138  ret <vscale x 16 x i32> %01139}1140 1141define <vscale x 1 x i8> @test_sf_vc_v_xvv_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1142; CHECK-LABEL: test_sf_vc_v_xvv_e8mf8:1143; CHECK:       # %bb.0: # %entry1144; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, tu, ma1145; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01146; CHECK-NEXT:    ret1147entry:1148  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.xvv.nxv1i8.iXLen.i8.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)1149  ret <vscale x 1 x i8> %01150}1151 1152define <vscale x 2 x i8> @test_sf_vc_v_xvv_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1153; CHECK-LABEL: test_sf_vc_v_xvv_e8mf4:1154; CHECK:       # %bb.0: # %entry1155; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, tu, ma1156; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01157; CHECK-NEXT:    ret1158entry:1159  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.xvv.nxv2i8.iXLen.i8.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)1160  ret <vscale x 2 x i8> %01161}1162 1163define <vscale x 4 x i8> @test_sf_vc_v_xvv_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1164; CHECK-LABEL: test_sf_vc_v_xvv_e8mf2:1165; CHECK:       # %bb.0: # %entry1166; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, tu, ma1167; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01168; CHECK-NEXT:    ret1169entry:1170  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.xvv.nxv4i8.iXLen.i8.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)1171  ret <vscale x 4 x i8> %01172}1173 1174define <vscale x 8 x i8> @test_sf_vc_v_xvv_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1175; CHECK-LABEL: test_sf_vc_v_xvv_e8m1:1176; CHECK:       # %bb.0: # %entry1177; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma1178; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01179; CHECK-NEXT:    ret1180entry:1181  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.xvv.nxv8i8.iXLen.i8.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)1182  ret <vscale x 8 x i8> %01183}1184 1185define <vscale x 16 x i8> @test_sf_vc_v_xvv_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1186; CHECK-LABEL: test_sf_vc_v_xvv_e8m2:1187; CHECK:       # %bb.0: # %entry1188; CHECK-NEXT:    vsetvli zero, a1, e8, m2, tu, ma1189; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a01190; CHECK-NEXT:    ret1191entry:1192  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.xvv.nxv16i8.iXLen.i8.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)1193  ret <vscale x 16 x i8> %01194}1195 1196define <vscale x 32 x i8> @test_sf_vc_v_xvv_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1197; CHECK-LABEL: test_sf_vc_v_xvv_e8m4:1198; CHECK:       # %bb.0: # %entry1199; CHECK-NEXT:    vsetvli zero, a1, e8, m4, tu, ma1200; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a01201; CHECK-NEXT:    ret1202entry:1203  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.xvv.nxv32i8.iXLen.i8.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)1204  ret <vscale x 32 x i8> %01205}1206 1207define <vscale x 64 x i8> @test_sf_vc_v_xvv_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {1208; CHECK-LABEL: test_sf_vc_v_xvv_e8m8:1209; CHECK:       # %bb.0: # %entry1210; CHECK-NEXT:    vsetvli zero, a1, e8, m8, tu, ma1211; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a01212; CHECK-NEXT:    ret1213entry:1214  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.xvv.nxv64i8.iXLen.i8.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, i8 %rs1, iXLen %vl)1215  ret <vscale x 64 x i8> %01216}1217 1218define <vscale x 1 x i16> @test_sf_vc_v_xvv_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1219; CHECK-LABEL: test_sf_vc_v_xvv_e16mf4:1220; CHECK:       # %bb.0: # %entry1221; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, ma1222; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01223; CHECK-NEXT:    ret1224entry:1225  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvv.nxv1i16.iXLen.i16.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)1226  ret <vscale x 1 x i16> %01227}1228 1229define <vscale x 2 x i16> @test_sf_vc_v_xvv_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1230; CHECK-LABEL: test_sf_vc_v_xvv_e16mf2:1231; CHECK:       # %bb.0: # %entry1232; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, ma1233; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01234; CHECK-NEXT:    ret1235entry:1236  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvv.nxv2i16.iXLen.i16.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)1237  ret <vscale x 2 x i16> %01238}1239 1240define <vscale x 4 x i16> @test_sf_vc_v_xvv_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1241; CHECK-LABEL: test_sf_vc_v_xvv_e16m1:1242; CHECK:       # %bb.0: # %entry1243; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma1244; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01245; CHECK-NEXT:    ret1246entry:1247  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvv.nxv4i16.iXLen.i16.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)1248  ret <vscale x 4 x i16> %01249}1250 1251define <vscale x 8 x i16> @test_sf_vc_v_xvv_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1252; CHECK-LABEL: test_sf_vc_v_xvv_e16m2:1253; CHECK:       # %bb.0: # %entry1254; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, ma1255; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a01256; CHECK-NEXT:    ret1257entry:1258  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvv.nxv8i16.iXLen.i16.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)1259  ret <vscale x 8 x i16> %01260}1261 1262define <vscale x 16 x i16> @test_sf_vc_v_xvv_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1263; CHECK-LABEL: test_sf_vc_v_xvv_e16m4:1264; CHECK:       # %bb.0: # %entry1265; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, ma1266; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a01267; CHECK-NEXT:    ret1268entry:1269  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvv.nxv16i16.iXLen.i16.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)1270  ret <vscale x 16 x i16> %01271}1272 1273define <vscale x 32 x i16> @test_sf_vc_v_xvv_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {1274; CHECK-LABEL: test_sf_vc_v_xvv_e16m8:1275; CHECK:       # %bb.0: # %entry1276; CHECK-NEXT:    vsetvli zero, a1, e16, m8, tu, ma1277; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a01278; CHECK-NEXT:    ret1279entry:1280  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvv.nxv32i16.iXLen.i16.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)1281  ret <vscale x 32 x i16> %01282}1283 1284define <vscale x 1 x i32> @test_sf_vc_v_xvv_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1285; CHECK-LABEL: test_sf_vc_v_xvv_e32mf2:1286; CHECK:       # %bb.0: # %entry1287; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma1288; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01289; CHECK-NEXT:    ret1290entry:1291  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvv.nxv1i32.iXLen.i32.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)1292  ret <vscale x 1 x i32> %01293}1294 1295define <vscale x 2 x i32> @test_sf_vc_v_xvv_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1296; CHECK-LABEL: test_sf_vc_v_xvv_e32m1:1297; CHECK:       # %bb.0: # %entry1298; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma1299; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a01300; CHECK-NEXT:    ret1301entry:1302  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvv.nxv2i32.iXLen.i32.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)1303  ret <vscale x 2 x i32> %01304}1305 1306define <vscale x 4 x i32> @test_sf_vc_v_xvv_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1307; CHECK-LABEL: test_sf_vc_v_xvv_e32m2:1308; CHECK:       # %bb.0: # %entry1309; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma1310; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a01311; CHECK-NEXT:    ret1312entry:1313  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvv.nxv4i32.iXLen.i32.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)1314  ret <vscale x 4 x i32> %01315}1316 1317define <vscale x 8 x i32> @test_sf_vc_v_xvv_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1318; CHECK-LABEL: test_sf_vc_v_xvv_e32m4:1319; CHECK:       # %bb.0: # %entry1320; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma1321; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a01322; CHECK-NEXT:    ret1323entry:1324  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvv.nxv8i32.iXLen.i32.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)1325  ret <vscale x 8 x i32> %01326}1327 1328define <vscale x 16 x i32> @test_sf_vc_v_xvv_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 signext %rs1, iXLen %vl) {1329; CHECK-LABEL: test_sf_vc_v_xvv_e32m8:1330; CHECK:       # %bb.0: # %entry1331; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, ma1332; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a01333; CHECK-NEXT:    ret1334entry:1335  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvv.nxv16i32.iXLen.i32.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)1336  ret <vscale x 16 x i32> %01337}1338 1339define void @test_sf_vc_ivv_se_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, iXLen %vl) {1340; CHECK-LABEL: test_sf_vc_ivv_se_e8mf8:1341; CHECK:       # %bb.0: # %entry1342; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1343; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101344; CHECK-NEXT:    ret1345entry:1346  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i8.iXLen.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1347  ret void1348}1349 1350define void @test_sf_vc_ivv_se_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, iXLen %vl) {1351; CHECK-LABEL: test_sf_vc_ivv_se_e8mf4:1352; CHECK:       # %bb.0: # %entry1353; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1354; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101355; CHECK-NEXT:    ret1356entry:1357  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i8.iXLen.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1358  ret void1359}1360 1361define void @test_sf_vc_ivv_se_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, iXLen %vl) {1362; CHECK-LABEL: test_sf_vc_ivv_se_e8mf2:1363; CHECK:       # %bb.0: # %entry1364; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1365; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101366; CHECK-NEXT:    ret1367entry:1368  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i8.iXLen.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1369  ret void1370}1371 1372define void @test_sf_vc_ivv_se_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, iXLen %vl) {1373; CHECK-LABEL: test_sf_vc_ivv_se_e8m1:1374; CHECK:       # %bb.0: # %entry1375; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1376; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101377; CHECK-NEXT:    ret1378entry:1379  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i8.iXLen.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1380  ret void1381}1382 1383define void @test_sf_vc_ivv_se_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, iXLen %vl) {1384; CHECK-LABEL: test_sf_vc_ivv_se_e8m2:1385; CHECK:       # %bb.0: # %entry1386; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1387; CHECK-NEXT:    sf.vc.ivv 3, v8, v10, 101388; CHECK-NEXT:    ret1389entry:1390  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i8.iXLen.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1391  ret void1392}1393 1394define void @test_sf_vc_ivv_se_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, iXLen %vl) {1395; CHECK-LABEL: test_sf_vc_ivv_se_e8m4:1396; CHECK:       # %bb.0: # %entry1397; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1398; CHECK-NEXT:    sf.vc.ivv 3, v8, v12, 101399; CHECK-NEXT:    ret1400entry:1401  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32i8.iXLen.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1402  ret void1403}1404 1405define void @test_sf_vc_ivv_se_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, iXLen %vl) {1406; CHECK-LABEL: test_sf_vc_ivv_se_e8m8:1407; CHECK:       # %bb.0: # %entry1408; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma1409; CHECK-NEXT:    sf.vc.ivv 3, v8, v16, 101410; CHECK-NEXT:    ret1411entry:1412  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv64i8.iXLen.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, iXLen 10, iXLen %vl)1413  ret void1414}1415 1416define void @test_sf_vc_ivv_se_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1417; CHECK-LABEL: test_sf_vc_ivv_se_e16mf4:1418; CHECK:       # %bb.0: # %entry1419; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1420; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101421; CHECK-NEXT:    ret1422entry:1423  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1424  ret void1425}1426 1427define void @test_sf_vc_ivv_se_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1428; CHECK-LABEL: test_sf_vc_ivv_se_e16mf2:1429; CHECK:       # %bb.0: # %entry1430; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1431; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101432; CHECK-NEXT:    ret1433entry:1434  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1435  ret void1436}1437 1438define void @test_sf_vc_ivv_se_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1439; CHECK-LABEL: test_sf_vc_ivv_se_e16m1:1440; CHECK:       # %bb.0: # %entry1441; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1442; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101443; CHECK-NEXT:    ret1444entry:1445  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1446  ret void1447}1448 1449define void @test_sf_vc_ivv_se_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1450; CHECK-LABEL: test_sf_vc_ivv_se_e16m2:1451; CHECK:       # %bb.0: # %entry1452; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1453; CHECK-NEXT:    sf.vc.ivv 3, v8, v10, 101454; CHECK-NEXT:    ret1455entry:1456  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1457  ret void1458}1459 1460define void @test_sf_vc_ivv_se_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1461; CHECK-LABEL: test_sf_vc_ivv_se_e16m4:1462; CHECK:       # %bb.0: # %entry1463; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1464; CHECK-NEXT:    sf.vc.ivv 3, v8, v12, 101465; CHECK-NEXT:    ret1466entry:1467  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1468  ret void1469}1470 1471define void @test_sf_vc_ivv_se_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, iXLen %vl) {1472; CHECK-LABEL: test_sf_vc_ivv_se_e16m8:1473; CHECK:       # %bb.0: # %entry1474; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma1475; CHECK-NEXT:    sf.vc.ivv 3, v8, v16, 101476; CHECK-NEXT:    ret1477entry:1478  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32i16.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, iXLen 10, iXLen %vl)1479  ret void1480}1481 1482define void @test_sf_vc_ivv_se_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {1483; CHECK-LABEL: test_sf_vc_ivv_se_e32mf2:1484; CHECK:       # %bb.0: # %entry1485; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1486; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101487; CHECK-NEXT:    ret1488entry:1489  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1490  ret void1491}1492 1493define void @test_sf_vc_ivv_se_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {1494; CHECK-LABEL: test_sf_vc_ivv_se_e32m1:1495; CHECK:       # %bb.0: # %entry1496; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1497; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101498; CHECK-NEXT:    ret1499entry:1500  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1501  ret void1502}1503 1504define void @test_sf_vc_ivv_se_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {1505; CHECK-LABEL: test_sf_vc_ivv_se_e32m2:1506; CHECK:       # %bb.0: # %entry1507; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1508; CHECK-NEXT:    sf.vc.ivv 3, v8, v10, 101509; CHECK-NEXT:    ret1510entry:1511  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1512  ret void1513}1514 1515define void @test_sf_vc_ivv_se_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {1516; CHECK-LABEL: test_sf_vc_ivv_se_e32m4:1517; CHECK:       # %bb.0: # %entry1518; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1519; CHECK-NEXT:    sf.vc.ivv 3, v8, v12, 101520; CHECK-NEXT:    ret1521entry:1522  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1523  ret void1524}1525 1526define void @test_sf_vc_ivv_se_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, iXLen %vl) {1527; CHECK-LABEL: test_sf_vc_ivv_se_e32m8:1528; CHECK:       # %bb.0: # %entry1529; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1530; CHECK-NEXT:    sf.vc.ivv 3, v8, v16, 101531; CHECK-NEXT:    ret1532entry:1533  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16i32.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, iXLen 10, iXLen %vl)1534  ret void1535}1536 1537define void @test_sf_vc_ivv_se_e64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, iXLen %vl) {1538; CHECK-LABEL: test_sf_vc_ivv_se_e64m1:1539; CHECK:       # %bb.0: # %entry1540; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1541; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 101542; CHECK-NEXT:    ret1543entry:1544  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, iXLen 10, iXLen %vl)1545  ret void1546}1547 1548define void @test_sf_vc_ivv_se_e64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, iXLen %vl) {1549; CHECK-LABEL: test_sf_vc_ivv_se_e64m2:1550; CHECK:       # %bb.0: # %entry1551; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1552; CHECK-NEXT:    sf.vc.ivv 3, v8, v10, 101553; CHECK-NEXT:    ret1554entry:1555  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2i64.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, iXLen 10, iXLen %vl)1556  ret void1557}1558 1559define void @test_sf_vc_ivv_se_e64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, iXLen %vl) {1560; CHECK-LABEL: test_sf_vc_ivv_se_e64m4:1561; CHECK:       # %bb.0: # %entry1562; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1563; CHECK-NEXT:    sf.vc.ivv 3, v8, v12, 101564; CHECK-NEXT:    ret1565entry:1566  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4i64.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, iXLen 10, iXLen %vl)1567  ret void1568}1569 1570define void @test_sf_vc_ivv_se_e64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, iXLen %vl) {1571; CHECK-LABEL: test_sf_vc_ivv_se_e64m8:1572; CHECK:       # %bb.0: # %entry1573; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1574; CHECK-NEXT:    sf.vc.ivv 3, v8, v16, 101575; CHECK-NEXT:    ret1576entry:1577  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8i64.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, iXLen 10, iXLen %vl)1578  ret void1579}1580 1581define <vscale x 1 x i8> @test_sf_vc_v_ivv_se_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, iXLen %vl) {1582; CHECK-LABEL: test_sf_vc_v_ivv_se_e8mf8:1583; CHECK:       # %bb.0: # %entry1584; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma1585; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101586; CHECK-NEXT:    ret1587entry:1588  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1589  ret <vscale x 1 x i8> %01590}1591 1592define <vscale x 2 x i8> @test_sf_vc_v_ivv_se_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, iXLen %vl) {1593; CHECK-LABEL: test_sf_vc_v_ivv_se_e8mf4:1594; CHECK:       # %bb.0: # %entry1595; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma1596; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101597; CHECK-NEXT:    ret1598entry:1599  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1600  ret <vscale x 2 x i8> %01601}1602 1603define <vscale x 4 x i8> @test_sf_vc_v_ivv_se_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, iXLen %vl) {1604; CHECK-LABEL: test_sf_vc_v_ivv_se_e8mf2:1605; CHECK:       # %bb.0: # %entry1606; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma1607; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101608; CHECK-NEXT:    ret1609entry:1610  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1611  ret <vscale x 4 x i8> %01612}1613 1614define <vscale x 8 x i8> @test_sf_vc_v_ivv_se_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, iXLen %vl) {1615; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m1:1616; CHECK:       # %bb.0: # %entry1617; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma1618; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101619; CHECK-NEXT:    ret1620entry:1621  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1622  ret <vscale x 8 x i8> %01623}1624 1625define <vscale x 16 x i8> @test_sf_vc_v_ivv_se_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, iXLen %vl) {1626; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m2:1627; CHECK:       # %bb.0: # %entry1628; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma1629; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 101630; CHECK-NEXT:    ret1631entry:1632  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1633  ret <vscale x 16 x i8> %01634}1635 1636define <vscale x 32 x i8> @test_sf_vc_v_ivv_se_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, iXLen %vl) {1637; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m4:1638; CHECK:       # %bb.0: # %entry1639; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma1640; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 101641; CHECK-NEXT:    ret1642entry:1643  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1644  ret <vscale x 32 x i8> %01645}1646 1647define <vscale x 64 x i8> @test_sf_vc_v_ivv_se_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, iXLen %vl) {1648; CHECK-LABEL: test_sf_vc_v_ivv_se_e8m8:1649; CHECK:       # %bb.0: # %entry1650; CHECK-NEXT:    vsetvli zero, a0, e8, m8, tu, ma1651; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 101652; CHECK-NEXT:    ret1653entry:1654  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.ivv.se.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, iXLen 10, iXLen %vl)1655  ret <vscale x 64 x i8> %01656}1657 1658define <vscale x 1 x i16> @test_sf_vc_v_ivv_se_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1659; CHECK-LABEL: test_sf_vc_v_ivv_se_e16mf4:1660; CHECK:       # %bb.0: # %entry1661; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma1662; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101663; CHECK-NEXT:    ret1664entry:1665  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1666  ret <vscale x 1 x i16> %01667}1668 1669define <vscale x 2 x i16> @test_sf_vc_v_ivv_se_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1670; CHECK-LABEL: test_sf_vc_v_ivv_se_e16mf2:1671; CHECK:       # %bb.0: # %entry1672; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma1673; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101674; CHECK-NEXT:    ret1675entry:1676  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1677  ret <vscale x 2 x i16> %01678}1679 1680define <vscale x 4 x i16> @test_sf_vc_v_ivv_se_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1681; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m1:1682; CHECK:       # %bb.0: # %entry1683; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1684; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101685; CHECK-NEXT:    ret1686entry:1687  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1688  ret <vscale x 4 x i16> %01689}1690 1691define <vscale x 8 x i16> @test_sf_vc_v_ivv_se_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1692; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m2:1693; CHECK:       # %bb.0: # %entry1694; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma1695; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 101696; CHECK-NEXT:    ret1697entry:1698  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1699  ret <vscale x 8 x i16> %01700}1701 1702define <vscale x 16 x i16> @test_sf_vc_v_ivv_se_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1703; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m4:1704; CHECK:       # %bb.0: # %entry1705; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma1706; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 101707; CHECK-NEXT:    ret1708entry:1709  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1710  ret <vscale x 16 x i16> %01711}1712 1713define <vscale x 32 x i16> @test_sf_vc_v_ivv_se_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, iXLen %vl) {1714; CHECK-LABEL: test_sf_vc_v_ivv_se_e16m8:1715; CHECK:       # %bb.0: # %entry1716; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, ma1717; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 101718; CHECK-NEXT:    ret1719entry:1720  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivv.se.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, iXLen 10, iXLen %vl)1721  ret <vscale x 32 x i16> %01722}1723 1724define <vscale x 1 x i32> @test_sf_vc_v_ivv_se_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {1725; CHECK-LABEL: test_sf_vc_v_ivv_se_e32mf2:1726; CHECK:       # %bb.0: # %entry1727; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma1728; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101729; CHECK-NEXT:    ret1730entry:1731  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1732  ret <vscale x 1 x i32> %01733}1734 1735define <vscale x 2 x i32> @test_sf_vc_v_ivv_se_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {1736; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m1:1737; CHECK:       # %bb.0: # %entry1738; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma1739; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101740; CHECK-NEXT:    ret1741entry:1742  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1743  ret <vscale x 2 x i32> %01744}1745 1746define <vscale x 4 x i32> @test_sf_vc_v_ivv_se_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {1747; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m2:1748; CHECK:       # %bb.0: # %entry1749; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1750; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 101751; CHECK-NEXT:    ret1752entry:1753  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1754  ret <vscale x 4 x i32> %01755}1756 1757define <vscale x 8 x i32> @test_sf_vc_v_ivv_se_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {1758; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m4:1759; CHECK:       # %bb.0: # %entry1760; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma1761; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 101762; CHECK-NEXT:    ret1763entry:1764  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1765  ret <vscale x 8 x i32> %01766}1767 1768define <vscale x 16 x i32> @test_sf_vc_v_ivv_se_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, iXLen %vl) {1769; CHECK-LABEL: test_sf_vc_v_ivv_se_e32m8:1770; CHECK:       # %bb.0: # %entry1771; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma1772; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 101773; CHECK-NEXT:    ret1774entry:1775  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivv.se.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, iXLen 10, iXLen %vl)1776  ret <vscale x 16 x i32> %01777}1778 1779define <vscale x 1 x i64> @test_sf_vc_v_ivv_se_e64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, iXLen %vl) {1780; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m1:1781; CHECK:       # %bb.0: # %entry1782; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma1783; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101784; CHECK-NEXT:    ret1785entry:1786  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, iXLen 10, iXLen %vl)1787  ret <vscale x 1 x i64> %01788}1789 1790define <vscale x 2 x i64> @test_sf_vc_v_ivv_se_e64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, iXLen %vl) {1791; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m2:1792; CHECK:       # %bb.0: # %entry1793; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma1794; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 101795; CHECK-NEXT:    ret1796entry:1797  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, iXLen 10, iXLen %vl)1798  ret <vscale x 2 x i64> %01799}1800 1801define <vscale x 4 x i64> @test_sf_vc_v_ivv_se_e64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, iXLen %vl) {1802; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m4:1803; CHECK:       # %bb.0: # %entry1804; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma1805; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 101806; CHECK-NEXT:    ret1807entry:1808  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, iXLen 10, iXLen %vl)1809  ret <vscale x 4 x i64> %01810}1811 1812define <vscale x 8 x i64> @test_sf_vc_v_ivv_se_e64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, iXLen %vl) {1813; CHECK-LABEL: test_sf_vc_v_ivv_se_e64m8:1814; CHECK:       # %bb.0: # %entry1815; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, ma1816; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 101817; CHECK-NEXT:    ret1818entry:1819  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivv.se.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, iXLen 10, iXLen %vl)1820  ret <vscale x 8 x i64> %01821}1822 1823define <vscale x 1 x i8> @test_sf_vc_v_ivv_e8mf8(<vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, iXLen %vl) {1824; CHECK-LABEL: test_sf_vc_v_ivv_e8mf8:1825; CHECK:       # %bb.0: # %entry1826; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma1827; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101828; CHECK-NEXT:    ret1829entry:1830  %0 = tail call <vscale x 1 x i8> @llvm.riscv.sf.vc.v.ivv.nxv1i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i8> %vd, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1831  ret <vscale x 1 x i8> %01832}1833 1834define <vscale x 2 x i8> @test_sf_vc_v_ivv_e8mf4(<vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, iXLen %vl) {1835; CHECK-LABEL: test_sf_vc_v_ivv_e8mf4:1836; CHECK:       # %bb.0: # %entry1837; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma1838; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101839; CHECK-NEXT:    ret1840entry:1841  %0 = tail call <vscale x 2 x i8> @llvm.riscv.sf.vc.v.ivv.nxv2i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i8> %vd, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1842  ret <vscale x 2 x i8> %01843}1844 1845define <vscale x 4 x i8> @test_sf_vc_v_ivv_e8mf2(<vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, iXLen %vl) {1846; CHECK-LABEL: test_sf_vc_v_ivv_e8mf2:1847; CHECK:       # %bb.0: # %entry1848; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma1849; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101850; CHECK-NEXT:    ret1851entry:1852  %0 = tail call <vscale x 4 x i8> @llvm.riscv.sf.vc.v.ivv.nxv4i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i8> %vd, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1853  ret <vscale x 4 x i8> %01854}1855 1856define <vscale x 8 x i8> @test_sf_vc_v_ivv_e8m1(<vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, iXLen %vl) {1857; CHECK-LABEL: test_sf_vc_v_ivv_e8m1:1858; CHECK:       # %bb.0: # %entry1859; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma1860; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101861; CHECK-NEXT:    ret1862entry:1863  %0 = tail call <vscale x 8 x i8> @llvm.riscv.sf.vc.v.ivv.nxv8i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i8> %vd, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1864  ret <vscale x 8 x i8> %01865}1866 1867define <vscale x 16 x i8> @test_sf_vc_v_ivv_e8m2(<vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, iXLen %vl) {1868; CHECK-LABEL: test_sf_vc_v_ivv_e8m2:1869; CHECK:       # %bb.0: # %entry1870; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma1871; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 101872; CHECK-NEXT:    ret1873entry:1874  %0 = tail call <vscale x 16 x i8> @llvm.riscv.sf.vc.v.ivv.nxv16i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i8> %vd, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1875  ret <vscale x 16 x i8> %01876}1877 1878define <vscale x 32 x i8> @test_sf_vc_v_ivv_e8m4(<vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, iXLen %vl) {1879; CHECK-LABEL: test_sf_vc_v_ivv_e8m4:1880; CHECK:       # %bb.0: # %entry1881; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma1882; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 101883; CHECK-NEXT:    ret1884entry:1885  %0 = tail call <vscale x 32 x i8> @llvm.riscv.sf.vc.v.ivv.nxv32i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i8> %vd, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1886  ret <vscale x 32 x i8> %01887}1888 1889define <vscale x 64 x i8> @test_sf_vc_v_ivv_e8m8(<vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, iXLen %vl) {1890; CHECK-LABEL: test_sf_vc_v_ivv_e8m8:1891; CHECK:       # %bb.0: # %entry1892; CHECK-NEXT:    vsetvli zero, a0, e8, m8, tu, ma1893; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 101894; CHECK-NEXT:    ret1895entry:1896  %0 = tail call <vscale x 64 x i8> @llvm.riscv.sf.vc.v.ivv.nxv64i8.iXLen.iXLen.iXLen(iXLen 3, <vscale x 64 x i8> %vd, <vscale x 64 x i8> %vs2, iXLen 10, iXLen %vl)1897  ret <vscale x 64 x i8> %01898}1899 1900define <vscale x 1 x i16> @test_sf_vc_v_ivv_e16mf4(<vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1901; CHECK-LABEL: test_sf_vc_v_ivv_e16mf4:1902; CHECK:       # %bb.0: # %entry1903; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma1904; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101905; CHECK-NEXT:    ret1906entry:1907  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivv.nxv1i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1908  ret <vscale x 1 x i16> %01909}1910 1911define <vscale x 2 x i16> @test_sf_vc_v_ivv_e16mf2(<vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1912; CHECK-LABEL: test_sf_vc_v_ivv_e16mf2:1913; CHECK:       # %bb.0: # %entry1914; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma1915; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101916; CHECK-NEXT:    ret1917entry:1918  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivv.nxv2i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1919  ret <vscale x 2 x i16> %01920}1921 1922define <vscale x 4 x i16> @test_sf_vc_v_ivv_e16m1(<vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1923; CHECK-LABEL: test_sf_vc_v_ivv_e16m1:1924; CHECK:       # %bb.0: # %entry1925; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1926; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101927; CHECK-NEXT:    ret1928entry:1929  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivv.nxv4i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1930  ret <vscale x 4 x i16> %01931}1932 1933define <vscale x 8 x i16> @test_sf_vc_v_ivv_e16m2(<vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1934; CHECK-LABEL: test_sf_vc_v_ivv_e16m2:1935; CHECK:       # %bb.0: # %entry1936; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma1937; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 101938; CHECK-NEXT:    ret1939entry:1940  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivv.nxv8i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1941  ret <vscale x 8 x i16> %01942}1943 1944define <vscale x 16 x i16> @test_sf_vc_v_ivv_e16m4(<vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1945; CHECK-LABEL: test_sf_vc_v_ivv_e16m4:1946; CHECK:       # %bb.0: # %entry1947; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma1948; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 101949; CHECK-NEXT:    ret1950entry:1951  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivv.nxv16i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1952  ret <vscale x 16 x i16> %01953}1954 1955define <vscale x 32 x i16> @test_sf_vc_v_ivv_e16m8(<vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, iXLen %vl) {1956; CHECK-LABEL: test_sf_vc_v_ivv_e16m8:1957; CHECK:       # %bb.0: # %entry1958; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, ma1959; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 101960; CHECK-NEXT:    ret1961entry:1962  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivv.nxv32i16.iXLen.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i16> %vs2, iXLen 10, iXLen %vl)1963  ret <vscale x 32 x i16> %01964}1965 1966define <vscale x 1 x i32> @test_sf_vc_v_ivv_e32mf2(<vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {1967; CHECK-LABEL: test_sf_vc_v_ivv_e32mf2:1968; CHECK:       # %bb.0: # %entry1969; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma1970; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101971; CHECK-NEXT:    ret1972entry:1973  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivv.nxv1i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1974  ret <vscale x 1 x i32> %01975}1976 1977define <vscale x 2 x i32> @test_sf_vc_v_ivv_e32m1(<vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {1978; CHECK-LABEL: test_sf_vc_v_ivv_e32m1:1979; CHECK:       # %bb.0: # %entry1980; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma1981; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 101982; CHECK-NEXT:    ret1983entry:1984  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivv.nxv2i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1985  ret <vscale x 2 x i32> %01986}1987 1988define <vscale x 4 x i32> @test_sf_vc_v_ivv_e32m2(<vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {1989; CHECK-LABEL: test_sf_vc_v_ivv_e32m2:1990; CHECK:       # %bb.0: # %entry1991; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1992; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 101993; CHECK-NEXT:    ret1994entry:1995  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivv.nxv4i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1996  ret <vscale x 4 x i32> %01997}1998 1999define <vscale x 8 x i32> @test_sf_vc_v_ivv_e32m4(<vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {2000; CHECK-LABEL: test_sf_vc_v_ivv_e32m4:2001; CHECK:       # %bb.0: # %entry2002; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma2003; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 102004; CHECK-NEXT:    ret2005entry:2006  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivv.nxv8i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)2007  ret <vscale x 8 x i32> %02008}2009 2010define <vscale x 16 x i32> @test_sf_vc_v_ivv_e32m8(<vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, iXLen %vl) {2011; CHECK-LABEL: test_sf_vc_v_ivv_e32m8:2012; CHECK:       # %bb.0: # %entry2013; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma2014; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 102015; CHECK-NEXT:    ret2016entry:2017  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivv.nxv16i32.iXLen.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i32> %vs2, iXLen 10, iXLen %vl)2018  ret <vscale x 16 x i32> %02019}2020 2021define <vscale x 1 x i64> @test_sf_vc_v_ivv_e64m1(<vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, iXLen %vl) {2022; CHECK-LABEL: test_sf_vc_v_ivv_e64m1:2023; CHECK:       # %bb.0: # %entry2024; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma2025; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 102026; CHECK-NEXT:    ret2027entry:2028  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivv.nxv1i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i64> %vs2, iXLen 10, iXLen %vl)2029  ret <vscale x 1 x i64> %02030}2031 2032define <vscale x 2 x i64> @test_sf_vc_v_ivv_e64m2(<vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, iXLen %vl) {2033; CHECK-LABEL: test_sf_vc_v_ivv_e64m2:2034; CHECK:       # %bb.0: # %entry2035; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma2036; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 102037; CHECK-NEXT:    ret2038entry:2039  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivv.nxv2i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i64> %vs2, iXLen 10, iXLen %vl)2040  ret <vscale x 2 x i64> %02041}2042 2043define <vscale x 4 x i64> @test_sf_vc_v_ivv_e64m4(<vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, iXLen %vl) {2044; CHECK-LABEL: test_sf_vc_v_ivv_e64m4:2045; CHECK:       # %bb.0: # %entry2046; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma2047; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 102048; CHECK-NEXT:    ret2049entry:2050  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivv.nxv4i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i64> %vs2, iXLen 10, iXLen %vl)2051  ret <vscale x 4 x i64> %02052}2053 2054define <vscale x 8 x i64> @test_sf_vc_v_ivv_e64m8(<vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, iXLen %vl) {2055; CHECK-LABEL: test_sf_vc_v_ivv_e64m8:2056; CHECK:       # %bb.0: # %entry2057; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, ma2058; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 102059; CHECK-NEXT:    ret2060entry:2061  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivv.nxv8i64.iXLen.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i64> %vs2, iXLen 10, iXLen %vl)2062  ret <vscale x 8 x i64> %02063}2064 2065define void @test_sf_vc_fvvv_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {2066; CHECK-LABEL: test_sf_vc_fvvv_se_e16mf4:2067; CHECK:       # %bb.0: # %entry2068; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2069; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v102070; CHECK-NEXT:    ret2071entry:2072  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f16.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)2073  ret void2074}2075 2076define <vscale x 1 x half> @test_sf_vc_fv_fvv_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {2077; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16mf4:2078; CHECK:       # %bb.0: # %entry2079; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma2080; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v102081; CHECK-NEXT:    ret2082entry:2083  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv1f16.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)2084  ret <vscale x 1 x half> %02085}2086 2087define void @test_sf_vc_fvvv_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {2088; CHECK-LABEL: test_sf_vc_fvvv_se_e16mf2:2089; CHECK:       # %bb.0: # %entry2090; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2091; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v102092; CHECK-NEXT:    ret2093entry:2094  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f16.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)2095  ret void2096}2097 2098define <vscale x 2 x half> @test_sf_vc_fv_fvv_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {2099; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16mf2:2100; CHECK:       # %bb.0: # %entry2101; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma2102; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v102103; CHECK-NEXT:    ret2104entry:2105  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv2f16.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)2106  ret <vscale x 2 x half> %02107}2108 2109define void @test_sf_vc_fvvv_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {2110; CHECK-LABEL: test_sf_vc_fvvv_se_e16m1:2111; CHECK:       # %bb.0: # %entry2112; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2113; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v102114; CHECK-NEXT:    ret2115entry:2116  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f16.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)2117  ret void2118}2119 2120define <vscale x 4 x half> @test_sf_vc_fv_fvv_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {2121; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m1:2122; CHECK:       # %bb.0: # %entry2123; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma2124; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v102125; CHECK-NEXT:    ret2126entry:2127  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv4f16.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)2128  ret <vscale x 4 x half> %02129}2130 2131define void @test_sf_vc_fvvv_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {2132; CHECK-LABEL: test_sf_vc_fvvv_se_e16m2:2133; CHECK:       # %bb.0: # %entry2134; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2135; CHECK-NEXT:    sf.vc.vvv 3, v8, v10, v122136; CHECK-NEXT:    ret2137entry:2138  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f16.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)2139  ret void2140}2141 2142define <vscale x 8 x half> @test_sf_vc_fv_fvv_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {2143; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m2:2144; CHECK:       # %bb.0: # %entry2145; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma2146; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v122147; CHECK-NEXT:    ret2148entry:2149  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv8f16.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)2150  ret <vscale x 8 x half> %02151}2152 2153define void @test_sf_vc_fvvv_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {2154; CHECK-LABEL: test_sf_vc_fvvv_se_e16m4:2155; CHECK:       # %bb.0: # %entry2156; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2157; CHECK-NEXT:    sf.vc.vvv 3, v8, v12, v162158; CHECK-NEXT:    ret2159entry:2160  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16f16.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)2161  ret void2162}2163 2164define <vscale x 16 x half> @test_sf_vc_fv_fvv_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {2165; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m4:2166; CHECK:       # %bb.0: # %entry2167; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma2168; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v162169; CHECK-NEXT:    ret2170entry:2171  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv16f16.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)2172  ret <vscale x 16 x half> %02173}2174 2175define void @test_sf_vc_fvvv_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {2176; CHECK-LABEL: test_sf_vc_fvvv_se_e16m8:2177; CHECK:       # %bb.0: # %entry2178; CHECK-NEXT:    vl8re16.v v24, (a0)2179; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2180; CHECK-NEXT:    sf.vc.vvv 3, v8, v16, v242181; CHECK-NEXT:    ret2182entry:2183  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv32f16.nxv32i16.nxv32i16.iXLen(iXLen 3, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)2184  ret void2185}2186 2187define <vscale x 32 x half> @test_sf_vc_fv_fvv_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl) {2188; CHECK-LABEL: test_sf_vc_fv_fvv_se_e16m8:2189; CHECK:       # %bb.0: # %entry2190; CHECK-NEXT:    vl8re16.v v24, (a0)2191; CHECK-NEXT:    vsetvli zero, a1, e16, m8, tu, ma2192; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v242193; CHECK-NEXT:    ret2194entry:2195  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.vvv.se.nxv32f16.nxv32i16.nxv32i16.iXLen(iXLen 3, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, <vscale x 32 x i16> %vs1, iXLen %vl)2196  ret <vscale x 32 x half> %02197}2198 2199define void @test_sf_vc_fvvv_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {2200; CHECK-LABEL: test_sf_vc_fvvv_se_e32mf2:2201; CHECK:       # %bb.0: # %entry2202; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2203; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v102204; CHECK-NEXT:    ret2205entry:2206  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f32.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)2207  ret void2208}2209 2210define <vscale x 1 x float> @test_sf_vc_fv_fvv_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {2211; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32mf2:2212; CHECK:       # %bb.0: # %entry2213; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma2214; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v102215; CHECK-NEXT:    ret2216entry:2217  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv1f32.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)2218  ret <vscale x 1 x float> %02219}2220 2221define void @test_sf_vc_fvvv_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {2222; CHECK-LABEL: test_sf_vc_fvvv_se_e32m1:2223; CHECK:       # %bb.0: # %entry2224; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2225; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v102226; CHECK-NEXT:    ret2227entry:2228  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f32.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)2229  ret void2230}2231 2232define <vscale x 2 x float> @test_sf_vc_fv_fvv_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {2233; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m1:2234; CHECK:       # %bb.0: # %entry2235; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma2236; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v102237; CHECK-NEXT:    ret2238entry:2239  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv2f32.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)2240  ret <vscale x 2 x float> %02241}2242 2243define void @test_sf_vc_fvvv_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {2244; CHECK-LABEL: test_sf_vc_fvvv_se_e32m2:2245; CHECK:       # %bb.0: # %entry2246; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2247; CHECK-NEXT:    sf.vc.vvv 3, v8, v10, v122248; CHECK-NEXT:    ret2249entry:2250  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f32.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)2251  ret void2252}2253 2254define <vscale x 4 x float> @test_sf_vc_fv_fvv_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {2255; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m2:2256; CHECK:       # %bb.0: # %entry2257; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma2258; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v122259; CHECK-NEXT:    ret2260entry:2261  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv4f32.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)2262  ret <vscale x 4 x float> %02263}2264 2265define void @test_sf_vc_fvvv_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {2266; CHECK-LABEL: test_sf_vc_fvvv_se_e32m4:2267; CHECK:       # %bb.0: # %entry2268; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2269; CHECK-NEXT:    sf.vc.vvv 3, v8, v12, v162270; CHECK-NEXT:    ret2271entry:2272  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f32.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)2273  ret void2274}2275 2276define <vscale x 8 x float> @test_sf_vc_fv_fvv_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {2277; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m4:2278; CHECK:       # %bb.0: # %entry2279; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma2280; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v162281; CHECK-NEXT:    ret2282entry:2283  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv8f32.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)2284  ret <vscale x 8 x float> %02285}2286 2287define void @test_sf_vc_fvvv_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {2288; CHECK-LABEL: test_sf_vc_fvvv_se_e32m8:2289; CHECK:       # %bb.0: # %entry2290; CHECK-NEXT:    vl8re32.v v24, (a0)2291; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2292; CHECK-NEXT:    sf.vc.vvv 3, v8, v16, v242293; CHECK-NEXT:    ret2294entry:2295  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv16f32.nxv16i32.nxv16i32.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)2296  ret void2297}2298 2299define <vscale x 16 x float> @test_sf_vc_fv_fvv_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl) {2300; CHECK-LABEL: test_sf_vc_fv_fvv_se_e32m8:2301; CHECK:       # %bb.0: # %entry2302; CHECK-NEXT:    vl8re32.v v24, (a0)2303; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, ma2304; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v242305; CHECK-NEXT:    ret2306entry:2307  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.vvv.se.nxv16f32.nxv16i32.nxv16i32.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, <vscale x 16 x i32> %vs1, iXLen %vl)2308  ret <vscale x 16 x float> %02309}2310 2311define void @test_sf_vc_fvvv_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {2312; CHECK-LABEL: test_sf_vc_fvvv_se_e64m1:2313; CHECK:       # %bb.0: # %entry2314; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma2315; CHECK-NEXT:    sf.vc.vvv 3, v8, v9, v102316; CHECK-NEXT:    ret2317entry:2318  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv1f64.nxv1i64.nxv1i64.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)2319  ret void2320}2321 2322define <vscale x 1 x double> @test_sf_vc_fv_fvv_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl) {2323; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m1:2324; CHECK:       # %bb.0: # %entry2325; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma2326; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v9, v102327; CHECK-NEXT:    ret2328entry:2329  %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv1f64.nxv1i64.nxv1i64.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i64> %vs2, <vscale x 1 x i64> %vs1, iXLen %vl)2330  ret <vscale x 1 x double> %02331}2332 2333define void @test_sf_vc_fvvv_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {2334; CHECK-LABEL: test_sf_vc_fvvv_se_e64m2:2335; CHECK:       # %bb.0: # %entry2336; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma2337; CHECK-NEXT:    sf.vc.vvv 3, v8, v10, v122338; CHECK-NEXT:    ret2339entry:2340  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv2f64.nxv2i64.nxv2i64.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)2341  ret void2342}2343 2344define <vscale x 2 x double> @test_sf_vc_fv_fvv_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl) {2345; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m2:2346; CHECK:       # %bb.0: # %entry2347; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, ma2348; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v10, v122349; CHECK-NEXT:    ret2350entry:2351  %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv2f64.nxv2i64.nxv2i64.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i64> %vs2, <vscale x 2 x i64> %vs1, iXLen %vl)2352  ret <vscale x 2 x double> %02353}2354 2355define void @test_sf_vc_fvvv_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {2356; CHECK-LABEL: test_sf_vc_fvvv_se_e64m4:2357; CHECK:       # %bb.0: # %entry2358; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2359; CHECK-NEXT:    sf.vc.vvv 3, v8, v12, v162360; CHECK-NEXT:    ret2361entry:2362  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv4f64.nxv4i64.nxv4i64.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)2363  ret void2364}2365 2366define <vscale x 4 x double> @test_sf_vc_fv_fvv_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl) {2367; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m4:2368; CHECK:       # %bb.0: # %entry2369; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, ma2370; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v12, v162371; CHECK-NEXT:    ret2372entry:2373  %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv4f64.nxv4i64.nxv4i64.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i64> %vs2, <vscale x 4 x i64> %vs1, iXLen %vl)2374  ret <vscale x 4 x double> %02375}2376 2377define void @test_sf_vc_fvvv_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {2378; CHECK-LABEL: test_sf_vc_fvvv_se_e64m8:2379; CHECK:       # %bb.0: # %entry2380; CHECK-NEXT:    vl8re64.v v24, (a0)2381; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma2382; CHECK-NEXT:    sf.vc.vvv 3, v8, v16, v242383; CHECK-NEXT:    ret2384entry:2385  tail call void @llvm.riscv.sf.vc.vvv.se.iXLen.nxv8f64.nxv8i64.nxv8i64.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)2386  ret void2387}2388 2389define <vscale x 8 x double> @test_sf_vc_fv_fvv_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl) {2390; CHECK-LABEL: test_sf_vc_fv_fvv_se_e64m8:2391; CHECK:       # %bb.0: # %entry2392; CHECK-NEXT:    vl8re64.v v24, (a0)2393; CHECK-NEXT:    vsetvli zero, a1, e64, m8, tu, ma2394; CHECK-NEXT:    sf.vc.v.vvv 3, v8, v16, v242395; CHECK-NEXT:    ret2396entry:2397  %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.vvv.se.nxv8f64.nxv8i64.nxv8i64.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i64> %vs2, <vscale x 8 x i64> %vs1, iXLen %vl)2398  ret <vscale x 8 x double> %02399}2400 2401define void @test_sf_vc_fvvx_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl) {2402; CHECK-LABEL: test_sf_vc_fvvx_se_e16mf4:2403; CHECK:       # %bb.0: # %entry2404; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2405; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a02406; CHECK-NEXT:    ret2407entry:2408  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1f16.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)2409  ret void2410}2411 2412define <vscale x 1 x half> @test_sf_vc_v_fvvx_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl) {2413; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16mf4:2414; CHECK:       # %bb.0: # %entry2415; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, ma2416; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a02417; CHECK-NEXT:    ret2418entry:2419  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv1f16.nxv1f16.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)2420  ret <vscale x 1 x half> %02421}2422 2423define void @test_sf_vc_fvvx_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl) {2424; CHECK-LABEL: test_sf_vc_fvvx_se_e16mf2:2425; CHECK:       # %bb.0: # %entry2426; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2427; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a02428; CHECK-NEXT:    ret2429entry:2430  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2f16.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)2431  ret void2432}2433 2434define <vscale x 2 x half> @test_sf_vc_v_fvvx_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl) {2435; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16mf2:2436; CHECK:       # %bb.0: # %entry2437; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, ma2438; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a02439; CHECK-NEXT:    ret2440entry:2441  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv2f16.nxv2f16.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)2442  ret <vscale x 2 x half> %02443}2444 2445define void @test_sf_vc_fvvx_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl) {2446; CHECK-LABEL: test_sf_vc_fvvx_se_e16m1:2447; CHECK:       # %bb.0: # %entry2448; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2449; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a02450; CHECK-NEXT:    ret2451entry:2452  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4f16.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)2453  ret void2454}2455 2456define <vscale x 4 x half> @test_sf_vc_v_fvvx_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl) {2457; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m1:2458; CHECK:       # %bb.0: # %entry2459; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma2460; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a02461; CHECK-NEXT:    ret2462entry:2463  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv4f16.nxv4f16.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)2464  ret <vscale x 4 x half> %02465}2466 2467define void @test_sf_vc_fvvx_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl) {2468; CHECK-LABEL: test_sf_vc_fvvx_se_e16m2:2469; CHECK:       # %bb.0: # %entry2470; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2471; CHECK-NEXT:    sf.vc.xvv 3, v8, v10, a02472; CHECK-NEXT:    ret2473entry:2474  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8f16.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)2475  ret void2476}2477 2478define <vscale x 8 x half> @test_sf_vc_v_fvvx_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl) {2479; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m2:2480; CHECK:       # %bb.0: # %entry2481; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, ma2482; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a02483; CHECK-NEXT:    ret2484entry:2485  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv8f16.nxv8f16.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)2486  ret <vscale x 8 x half> %02487}2488 2489define void @test_sf_vc_fvvx_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl) {2490; CHECK-LABEL: test_sf_vc_fvvx_se_e16m4:2491; CHECK:       # %bb.0: # %entry2492; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2493; CHECK-NEXT:    sf.vc.xvv 3, v8, v12, a02494; CHECK-NEXT:    ret2495entry:2496  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16f16.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)2497  ret void2498}2499 2500define <vscale x 16 x half> @test_sf_vc_v_fvvx_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl) {2501; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m4:2502; CHECK:       # %bb.0: # %entry2503; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, ma2504; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a02505; CHECK-NEXT:    ret2506entry:2507  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv16f16.nxv16f16.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)2508  ret <vscale x 16 x half> %02509}2510 2511define void @test_sf_vc_fvvx_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl) {2512; CHECK-LABEL: test_sf_vc_fvvx_se_e16m8:2513; CHECK:       # %bb.0: # %entry2514; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2515; CHECK-NEXT:    sf.vc.xvv 3, v8, v16, a02516; CHECK-NEXT:    ret2517entry:2518  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv32f16.nxv32i16.i16.iXLen(iXLen 3, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)2519  ret void2520}2521 2522define <vscale x 32 x half> @test_sf_vc_v_fvvx_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl) {2523; CHECK-LABEL: test_sf_vc_v_fvvx_se_e16m8:2524; CHECK:       # %bb.0: # %entry2525; CHECK-NEXT:    vsetvli zero, a1, e16, m8, tu, ma2526; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a02527; CHECK-NEXT:    ret2528entry:2529  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.xvv.se.nxv32f16.nxv32f16.nxv32i16.i16.iXLen(iXLen 3, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, i16 %rs1, iXLen %vl)2530  ret <vscale x 32 x half> %02531}2532 2533define void @test_sf_vc_fvvx_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl) {2534; CHECK-LABEL: test_sf_vc_fvvx_se_e32mf2:2535; CHECK:       # %bb.0: # %entry2536; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2537; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a02538; CHECK-NEXT:    ret2539entry:2540  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv1f32.nxv1i32.i32.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)2541  ret void2542}2543 2544define <vscale x 1 x float> @test_sf_vc_v_fvvx_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl) {2545; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32mf2:2546; CHECK:       # %bb.0: # %entry2547; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma2548; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a02549; CHECK-NEXT:    ret2550entry:2551  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv1f32.nxv1f32.nxv1i32.i32.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)2552  ret <vscale x 1 x float> %02553}2554 2555define void @test_sf_vc_fvvx_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl) {2556; CHECK-LABEL: test_sf_vc_fvvx_se_e32m1:2557; CHECK:       # %bb.0: # %entry2558; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2559; CHECK-NEXT:    sf.vc.xvv 3, v8, v9, a02560; CHECK-NEXT:    ret2561entry:2562  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv2f32.nxv2i32.i32.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)2563  ret void2564}2565 2566define <vscale x 2 x float> @test_sf_vc_v_fvvx_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl) {2567; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m1:2568; CHECK:       # %bb.0: # %entry2569; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma2570; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v9, a02571; CHECK-NEXT:    ret2572entry:2573  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv2f32.nxv2f32.nxv2i32.i32.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)2574  ret <vscale x 2 x float> %02575}2576 2577define void @test_sf_vc_fvvx_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl) {2578; CHECK-LABEL: test_sf_vc_fvvx_se_e32m2:2579; CHECK:       # %bb.0: # %entry2580; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2581; CHECK-NEXT:    sf.vc.xvv 3, v8, v10, a02582; CHECK-NEXT:    ret2583entry:2584  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv4f32.nxv4i32.i32.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)2585  ret void2586}2587 2588define <vscale x 4 x float> @test_sf_vc_v_fvvx_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl) {2589; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m2:2590; CHECK:       # %bb.0: # %entry2591; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma2592; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v10, a02593; CHECK-NEXT:    ret2594entry:2595  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv4f32.nxv4f32.nxv4i32.i32.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)2596  ret <vscale x 4 x float> %02597}2598 2599define void @test_sf_vc_fvvx_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl) {2600; CHECK-LABEL: test_sf_vc_fvvx_se_e32m4:2601; CHECK:       # %bb.0: # %entry2602; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2603; CHECK-NEXT:    sf.vc.xvv 3, v8, v12, a02604; CHECK-NEXT:    ret2605entry:2606  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv8f32.nxv8i32.i32.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)2607  ret void2608}2609 2610define <vscale x 8 x float> @test_sf_vc_v_fvvx_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl) {2611; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m4:2612; CHECK:       # %bb.0: # %entry2613; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma2614; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v12, a02615; CHECK-NEXT:    ret2616entry:2617  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv8f32.nxv8f32.nxv8i32.i32.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)2618  ret <vscale x 8 x float> %02619}2620 2621define void @test_sf_vc_fvvx_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl) {2622; CHECK-LABEL: test_sf_vc_fvvx_se_e32m8:2623; CHECK:       # %bb.0: # %entry2624; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2625; CHECK-NEXT:    sf.vc.xvv 3, v8, v16, a02626; CHECK-NEXT:    ret2627entry:2628  tail call void @llvm.riscv.sf.vc.xvv.se.iXLen.nxv16f32.nxv16i32.i32.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)2629  ret void2630}2631 2632define <vscale x 16 x float> @test_sf_vc_v_fvvx_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl) {2633; CHECK-LABEL: test_sf_vc_v_fvvx_se_e32m8:2634; CHECK:       # %bb.0: # %entry2635; CHECK-NEXT:    vsetvli zero, a1, e32, m8, tu, ma2636; CHECK-NEXT:    sf.vc.v.xvv 3, v8, v16, a02637; CHECK-NEXT:    ret2638entry:2639  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.xvv.se.nxv16f32.nxv16f32.nxv16i32.i32.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, i32 %rs1, iXLen %vl)2640  ret <vscale x 16 x float> %02641}2642 2643define void @test_sf_vc_fvvi_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {2644; CHECK-LABEL: test_sf_vc_fvvi_se_e16mf4:2645; CHECK:       # %bb.0: # %entry2646; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2647; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 32648; CHECK-NEXT:    ret2649entry:2650  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1f16.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, iXLen 3, iXLen %vl)2651  ret void2652}2653 2654define <vscale x 1 x half> @test_sf_vc_fv_fvvi_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {2655; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16mf4:2656; CHECK:       # %bb.0: # %entry2657; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma2658; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 32659; CHECK-NEXT:    ret2660entry:2661  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv1f16.nxv1f16.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, iXLen 3, iXLen %vl)2662  ret <vscale x 1 x half> %02663}2664 2665define void @test_sf_vc_fvvi_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {2666; CHECK-LABEL: test_sf_vc_fvvi_se_e16mf2:2667; CHECK:       # %bb.0: # %entry2668; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2669; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 32670; CHECK-NEXT:    ret2671entry:2672  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2f16.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, iXLen 3, iXLen %vl)2673  ret void2674}2675 2676define <vscale x 2 x half> @test_sf_vc_fv_fvvi_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {2677; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16mf2:2678; CHECK:       # %bb.0: # %entry2679; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma2680; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 32681; CHECK-NEXT:    ret2682entry:2683  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv2f16.nxv2f16.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, iXLen 3, iXLen %vl)2684  ret <vscale x 2 x half> %02685}2686 2687define void @test_sf_vc_fvvi_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {2688; CHECK-LABEL: test_sf_vc_fvvi_se_e16m1:2689; CHECK:       # %bb.0: # %entry2690; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2691; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 32692; CHECK-NEXT:    ret2693entry:2694  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4f16.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, iXLen 3, iXLen %vl)2695  ret void2696}2697 2698define <vscale x 4 x half> @test_sf_vc_fv_fvvi_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {2699; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m1:2700; CHECK:       # %bb.0: # %entry2701; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma2702; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 32703; CHECK-NEXT:    ret2704entry:2705  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv4f16.nxv4f16.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, iXLen 3, iXLen %vl)2706  ret <vscale x 4 x half> %02707}2708 2709define void @test_sf_vc_fvvi_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {2710; CHECK-LABEL: test_sf_vc_fvvi_se_e16m2:2711; CHECK:       # %bb.0: # %entry2712; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2713; CHECK-NEXT:    sf.vc.ivv 3, v8, v10, 32714; CHECK-NEXT:    ret2715entry:2716  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8f16.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, iXLen 3, iXLen %vl)2717  ret void2718}2719 2720define <vscale x 8 x half> @test_sf_vc_fv_fvvi_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {2721; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m2:2722; CHECK:       # %bb.0: # %entry2723; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma2724; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 32725; CHECK-NEXT:    ret2726entry:2727  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv8f16.nxv8f16.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, iXLen 3, iXLen %vl)2728  ret <vscale x 8 x half> %02729}2730 2731define void @test_sf_vc_fvvi_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {2732; CHECK-LABEL: test_sf_vc_fvvi_se_e16m4:2733; CHECK:       # %bb.0: # %entry2734; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2735; CHECK-NEXT:    sf.vc.ivv 3, v8, v12, 32736; CHECK-NEXT:    ret2737entry:2738  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16f16.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, iXLen 3, iXLen %vl)2739  ret void2740}2741 2742define <vscale x 16 x half> @test_sf_vc_fv_fvvi_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {2743; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m4:2744; CHECK:       # %bb.0: # %entry2745; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma2746; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 32747; CHECK-NEXT:    ret2748entry:2749  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv16f16.nxv16f16.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, iXLen 3, iXLen %vl)2750  ret <vscale x 16 x half> %02751}2752 2753define void @test_sf_vc_fvvi_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, iXLen %vl) {2754; CHECK-LABEL: test_sf_vc_fvvi_se_e16m8:2755; CHECK:       # %bb.0: # %entry2756; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2757; CHECK-NEXT:    sf.vc.ivv 3, v8, v16, 32758; CHECK-NEXT:    ret2759entry:2760  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv32f16.nxv32i16.iXLen.iXLen(iXLen 3, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, iXLen 3, iXLen %vl)2761  ret void2762}2763 2764define <vscale x 32 x half> @test_sf_vc_fv_fvvi_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, iXLen %vl) {2765; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e16m8:2766; CHECK:       # %bb.0: # %entry2767; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, ma2768; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 32769; CHECK-NEXT:    ret2770entry:2771  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.ivv.se.nxv32f16.nxv32f16.nxv32i16.iXLen.iXLen(iXLen 3, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, iXLen 3, iXLen %vl)2772  ret <vscale x 32 x half> %02773}2774 2775define void @test_sf_vc_fvvi_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {2776; CHECK-LABEL: test_sf_vc_fvvi_se_e32mf2:2777; CHECK:       # %bb.0: # %entry2778; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2779; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 32780; CHECK-NEXT:    ret2781entry:2782  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv1f32.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, iXLen 3, iXLen %vl)2783  ret void2784}2785 2786define <vscale x 1 x float> @test_sf_vc_fv_fvvi_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {2787; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32mf2:2788; CHECK:       # %bb.0: # %entry2789; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma2790; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 32791; CHECK-NEXT:    ret2792entry:2793  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv1f32.nxv1f32.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, iXLen 3, iXLen %vl)2794  ret <vscale x 1 x float> %02795}2796 2797define void @test_sf_vc_fvvi_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {2798; CHECK-LABEL: test_sf_vc_fvvi_se_e32m1:2799; CHECK:       # %bb.0: # %entry2800; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2801; CHECK-NEXT:    sf.vc.ivv 3, v8, v9, 32802; CHECK-NEXT:    ret2803entry:2804  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv2f32.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, iXLen 3, iXLen %vl)2805  ret void2806}2807 2808define <vscale x 2 x float> @test_sf_vc_fv_fvvi_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {2809; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m1:2810; CHECK:       # %bb.0: # %entry2811; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma2812; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v9, 32813; CHECK-NEXT:    ret2814entry:2815  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv2f32.nxv2f32.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, iXLen 3, iXLen %vl)2816  ret <vscale x 2 x float> %02817}2818 2819define void @test_sf_vc_fvvi_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {2820; CHECK-LABEL: test_sf_vc_fvvi_se_e32m2:2821; CHECK:       # %bb.0: # %entry2822; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2823; CHECK-NEXT:    sf.vc.ivv 3, v8, v10, 32824; CHECK-NEXT:    ret2825entry:2826  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv4f32.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, iXLen 3, iXLen %vl)2827  ret void2828}2829 2830define <vscale x 4 x float> @test_sf_vc_fv_fvvi_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {2831; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m2:2832; CHECK:       # %bb.0: # %entry2833; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma2834; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v10, 32835; CHECK-NEXT:    ret2836entry:2837  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv4f32.nxv4f32.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, iXLen 3, iXLen %vl)2838  ret <vscale x 4 x float> %02839}2840 2841define void @test_sf_vc_fvvi_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {2842; CHECK-LABEL: test_sf_vc_fvvi_se_e32m4:2843; CHECK:       # %bb.0: # %entry2844; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2845; CHECK-NEXT:    sf.vc.ivv 3, v8, v12, 32846; CHECK-NEXT:    ret2847entry:2848  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv8f32.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, iXLen 3, iXLen %vl)2849  ret void2850}2851 2852define <vscale x 8 x float> @test_sf_vc_fv_fvvi_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {2853; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m4:2854; CHECK:       # %bb.0: # %entry2855; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma2856; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v12, 32857; CHECK-NEXT:    ret2858entry:2859  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv8f32.nxv8f32.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, iXLen 3, iXLen %vl)2860  ret <vscale x 8 x float> %02861}2862 2863define void @test_sf_vc_fvvi_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, iXLen %vl) {2864; CHECK-LABEL: test_sf_vc_fvvi_se_e32m8:2865; CHECK:       # %bb.0: # %entry2866; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma2867; CHECK-NEXT:    sf.vc.ivv 3, v8, v16, 32868; CHECK-NEXT:    ret2869entry:2870  tail call void @llvm.riscv.sf.vc.ivv.se.iXLen.nxv16f32.nxv16i32.iXLen.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, iXLen 3, iXLen %vl)2871  ret void2872}2873 2874define <vscale x 16 x float> @test_sf_vc_fv_fvvi_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, iXLen %vl) {2875; CHECK-LABEL: test_sf_vc_fv_fvvi_se_e32m8:2876; CHECK:       # %bb.0: # %entry2877; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma2878; CHECK-NEXT:    sf.vc.v.ivv 3, v8, v16, 32879; CHECK-NEXT:    ret2880entry:2881  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.ivv.se.nxv16f32.nxv16f32.nxv16i32.iXLen.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, iXLen 3, iXLen %vl)2882  ret <vscale x 16 x float> %02883}2884 2885define void @test_sf_vc_fvvf_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl) {2886; CHECK-LABEL: test_sf_vc_fvvf_se_e16mf4:2887; CHECK:       # %bb.0: # %entry2888; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2889; CHECK-NEXT:    sf.vc.fvv 1, v8, v9, fa02890; CHECK-NEXT:    ret2891entry:2892  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1f16.nxv1i16.f16.iXLen(iXLen 1, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl)2893  ret void2894}2895 2896define <vscale x 1 x half> @test_sf_vc_fv_fvvf_se_e16mf4(<vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl) {2897; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16mf4:2898; CHECK:       # %bb.0: # %entry2899; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma2900; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v9, fa02901; CHECK-NEXT:    ret2902entry:2903  %0 = tail call <vscale x 1 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv1f16.nxv1f16.nxv1i16.f16.iXLen(iXLen 1, <vscale x 1 x half> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl)2904  ret <vscale x 1 x half> %02905}2906 2907define void @test_sf_vc_fvvf_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl) {2908; CHECK-LABEL: test_sf_vc_fvvf_se_e16mf2:2909; CHECK:       # %bb.0: # %entry2910; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2911; CHECK-NEXT:    sf.vc.fvv 1, v8, v9, fa02912; CHECK-NEXT:    ret2913entry:2914  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv2f16.nxv2i16.f16.iXLen(iXLen 1, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl)2915  ret void2916}2917 2918define <vscale x 2 x half> @test_sf_vc_fv_fvvf_se_e16mf2(<vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl) {2919; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16mf2:2920; CHECK:       # %bb.0: # %entry2921; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma2922; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v9, fa02923; CHECK-NEXT:    ret2924entry:2925  %0 = tail call <vscale x 2 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv2f16.nxv2f16.nxv2i16.f16.iXLen(iXLen 1, <vscale x 2 x half> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl)2926  ret <vscale x 2 x half> %02927}2928 2929define void @test_sf_vc_fvvf_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl) {2930; CHECK-LABEL: test_sf_vc_fvvf_se_e16m1:2931; CHECK:       # %bb.0: # %entry2932; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2933; CHECK-NEXT:    sf.vc.fvv 1, v8, v9, fa02934; CHECK-NEXT:    ret2935entry:2936  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv4f16.nxv4i16.f16.iXLen(iXLen 1, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl)2937  ret void2938}2939 2940define <vscale x 4 x half> @test_sf_vc_fv_fvvf_se_e16m1(<vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl) {2941; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m1:2942; CHECK:       # %bb.0: # %entry2943; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma2944; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v9, fa02945; CHECK-NEXT:    ret2946entry:2947  %0 = tail call <vscale x 4 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv4f16.nxv4f16.nxv4i16.f16.iXLen(iXLen 1, <vscale x 4 x half> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl)2948  ret <vscale x 4 x half> %02949}2950 2951define void @test_sf_vc_fvvf_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl) {2952; CHECK-LABEL: test_sf_vc_fvvf_se_e16m2:2953; CHECK:       # %bb.0: # %entry2954; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2955; CHECK-NEXT:    sf.vc.fvv 1, v8, v10, fa02956; CHECK-NEXT:    ret2957entry:2958  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv8f16.nxv8i16.f16.iXLen(iXLen 1, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl)2959  ret void2960}2961 2962define <vscale x 8 x half> @test_sf_vc_fv_fvvf_se_e16m2(<vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl) {2963; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m2:2964; CHECK:       # %bb.0: # %entry2965; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma2966; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v10, fa02967; CHECK-NEXT:    ret2968entry:2969  %0 = tail call <vscale x 8 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv8f16.nxv8f16.nxv8i16.f16.iXLen(iXLen 1, <vscale x 8 x half> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl)2970  ret <vscale x 8 x half> %02971}2972 2973define void @test_sf_vc_fvvf_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl) {2974; CHECK-LABEL: test_sf_vc_fvvf_se_e16m4:2975; CHECK:       # %bb.0: # %entry2976; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2977; CHECK-NEXT:    sf.vc.fvv 1, v8, v12, fa02978; CHECK-NEXT:    ret2979entry:2980  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv16f16.nxv16i16.f16.iXLen(iXLen 1, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl)2981  ret void2982}2983 2984define <vscale x 16 x half> @test_sf_vc_fv_fvvf_se_e16m4(<vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl) {2985; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m4:2986; CHECK:       # %bb.0: # %entry2987; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma2988; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v12, fa02989; CHECK-NEXT:    ret2990entry:2991  %0 = tail call <vscale x 16 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv16f16.nxv16f16.nxv16i16.f16.iXLen(iXLen 1, <vscale x 16 x half> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl)2992  ret <vscale x 16 x half> %02993}2994 2995define void @test_sf_vc_fvvf_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, half %rs1, iXLen %vl) {2996; CHECK-LABEL: test_sf_vc_fvvf_se_e16m8:2997; CHECK:       # %bb.0: # %entry2998; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2999; CHECK-NEXT:    sf.vc.fvv 1, v8, v16, fa03000; CHECK-NEXT:    ret3001entry:3002  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv32f16.nxv32i16.f16.iXLen(iXLen 1, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, half %rs1, iXLen %vl)3003  ret void3004}3005 3006define <vscale x 32 x half> @test_sf_vc_fv_fvvf_se_e16m8(<vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, half %rs1, iXLen %vl) {3007; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e16m8:3008; CHECK:       # %bb.0: # %entry3009; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, ma3010; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v16, fa03011; CHECK-NEXT:    ret3012entry:3013  %0 = tail call <vscale x 32 x half> @llvm.riscv.sf.vc.v.fvv.se.nxv32f16.nxv32f16.nxv32i16.f16.iXLen(iXLen 1, <vscale x 32 x half> %vd, <vscale x 32 x i16> %vs2, half %rs1, iXLen %vl)3014  ret <vscale x 32 x half> %03015}3016 3017define void @test_sf_vc_fvvf_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl) {3018; CHECK-LABEL: test_sf_vc_fvvf_se_e32mf2:3019; CHECK:       # %bb.0: # %entry3020; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma3021; CHECK-NEXT:    sf.vc.fvv 1, v8, v9, fa03022; CHECK-NEXT:    ret3023entry:3024  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1f32.nxv1i32.f32.iXLen(iXLen 1, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl)3025  ret void3026}3027 3028define <vscale x 1 x float> @test_sf_vc_fv_fvvf_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl) {3029; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32mf2:3030; CHECK:       # %bb.0: # %entry3031; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma3032; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v9, fa03033; CHECK-NEXT:    ret3034entry:3035  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv1f32.nxv1f32.nxv1i32.f32.iXLen(iXLen 1, <vscale x 1 x float> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl)3036  ret <vscale x 1 x float> %03037}3038 3039define void @test_sf_vc_fvvf_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl) {3040; CHECK-LABEL: test_sf_vc_fvvf_se_e32m1:3041; CHECK:       # %bb.0: # %entry3042; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma3043; CHECK-NEXT:    sf.vc.fvv 1, v8, v9, fa03044; CHECK-NEXT:    ret3045entry:3046  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv2f32.nxv2i32.f32.iXLen(iXLen 1, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl)3047  ret void3048}3049 3050define <vscale x 2 x float> @test_sf_vc_fv_fvvf_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl) {3051; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m1:3052; CHECK:       # %bb.0: # %entry3053; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma3054; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v9, fa03055; CHECK-NEXT:    ret3056entry:3057  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv2f32.nxv2f32.nxv2i32.f32.iXLen(iXLen 1, <vscale x 2 x float> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl)3058  ret <vscale x 2 x float> %03059}3060 3061define void @test_sf_vc_fvvf_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl) {3062; CHECK-LABEL: test_sf_vc_fvvf_se_e32m2:3063; CHECK:       # %bb.0: # %entry3064; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3065; CHECK-NEXT:    sf.vc.fvv 1, v8, v10, fa03066; CHECK-NEXT:    ret3067entry:3068  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv4f32.nxv4i32.f32.iXLen(iXLen 1, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl)3069  ret void3070}3071 3072define <vscale x 4 x float> @test_sf_vc_fv_fvvf_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl) {3073; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m2:3074; CHECK:       # %bb.0: # %entry3075; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma3076; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v10, fa03077; CHECK-NEXT:    ret3078entry:3079  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv4f32.nxv4f32.nxv4i32.f32.iXLen(iXLen 1, <vscale x 4 x float> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl)3080  ret <vscale x 4 x float> %03081}3082 3083define void @test_sf_vc_fvvf_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl) {3084; CHECK-LABEL: test_sf_vc_fvvf_se_e32m4:3085; CHECK:       # %bb.0: # %entry3086; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma3087; CHECK-NEXT:    sf.vc.fvv 1, v8, v12, fa03088; CHECK-NEXT:    ret3089entry:3090  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv8f32.nxv8i32.f32.iXLen(iXLen 1, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl)3091  ret void3092}3093 3094define <vscale x 8 x float> @test_sf_vc_fv_fvvf_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl) {3095; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m4:3096; CHECK:       # %bb.0: # %entry3097; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma3098; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v12, fa03099; CHECK-NEXT:    ret3100entry:3101  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv8f32.nxv8f32.nxv8i32.f32.iXLen(iXLen 1, <vscale x 8 x float> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl)3102  ret <vscale x 8 x float> %03103}3104 3105define void @test_sf_vc_fvvf_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, float %rs1, iXLen %vl) {3106; CHECK-LABEL: test_sf_vc_fvvf_se_e32m8:3107; CHECK:       # %bb.0: # %entry3108; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma3109; CHECK-NEXT:    sf.vc.fvv 1, v8, v16, fa03110; CHECK-NEXT:    ret3111entry:3112  tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv16f32.nxv16i32.f32.iXLen(iXLen 1, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, float %rs1, iXLen %vl)3113  ret void3114}3115 3116define <vscale x 16 x float> @test_sf_vc_fv_fvvf_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, float %rs1, iXLen %vl) {3117; CHECK-LABEL: test_sf_vc_fv_fvvf_se_e32m8:3118; CHECK:       # %bb.0: # %entry3119; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, ma3120; CHECK-NEXT:    sf.vc.v.fvv 1, v8, v16, fa03121; CHECK-NEXT:    ret3122entry:3123  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv16f32.nxv16f32.nxv16i32.f32.iXLen(iXLen 1, <vscale x 16 x float> %vd, <vscale x 16 x i32> %vs2, float %rs1, iXLen %vl)3124  ret <vscale x 16 x float> %03125}3126 3127