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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN:  sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh,+xsfvcp \3; RUN:    -verify-machineinstrs | FileCheck %s4; RUN:  sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh,+xsfvcp \5; RUN:    -verify-machineinstrs | FileCheck %s6 7define void @test_sf_vc_vvw_se_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {8; CHECK-LABEL: test_sf_vc_vvw_se_e8mf8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v1012; CHECK-NEXT:    ret13entry:14  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv1i16.nxv1i8.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)15  ret void16}17 18define void @test_sf_vc_vvw_se_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {19; CHECK-LABEL: test_sf_vc_vvw_se_e8mf4:20; CHECK:       # %bb.0: # %entry21; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma22; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v1023; CHECK-NEXT:    ret24entry:25  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv2i16.nxv2i8.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)26  ret void27}28 29define void @test_sf_vc_vvw_se_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {30; CHECK-LABEL: test_sf_vc_vvw_se_e8mf2:31; CHECK:       # %bb.0: # %entry32; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma33; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v1034; CHECK-NEXT:    ret35entry:36  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv4i16.nxv4i8.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)37  ret void38}39 40define void @test_sf_vc_vvw_se_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {41; CHECK-LABEL: test_sf_vc_vvw_se_e8m1:42; CHECK:       # %bb.0: # %entry43; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma44; CHECK-NEXT:    sf.vc.vvw 3, v8, v10, v1145; CHECK-NEXT:    ret46entry:47  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv8i16.nxv8i8.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)48  ret void49}50 51define void @test_sf_vc_vvw_se_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {52; CHECK-LABEL: test_sf_vc_vvw_se_e8m2:53; CHECK:       # %bb.0: # %entry54; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma55; CHECK-NEXT:    sf.vc.vvw 3, v8, v12, v1456; CHECK-NEXT:    ret57entry:58  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv16i16.nxv16i8.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)59  ret void60}61 62define void @test_sf_vc_vvw_se_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {63; CHECK-LABEL: test_sf_vc_vvw_se_e8m4:64; CHECK:       # %bb.0: # %entry65; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma66; CHECK-NEXT:    sf.vc.vvw 3, v8, v16, v2067; CHECK-NEXT:    ret68entry:69  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv32i16.nxv32i8.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)70  ret void71}72 73define void @test_sf_vc_vvw_se_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {74; CHECK-LABEL: test_sf_vc_vvw_se_e16mf4:75; CHECK:       # %bb.0: # %entry76; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma77; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v1078; CHECK-NEXT:    ret79entry:80  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv1i32.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)81  ret void82}83 84define void @test_sf_vc_vvw_se_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {85; CHECK-LABEL: test_sf_vc_vvw_se_e16mf2:86; CHECK:       # %bb.0: # %entry87; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma88; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v1089; CHECK-NEXT:    ret90entry:91  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv2i32.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)92  ret void93}94 95define void @test_sf_vc_vvw_se_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {96; CHECK-LABEL: test_sf_vc_vvw_se_e16m1:97; CHECK:       # %bb.0: # %entry98; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma99; CHECK-NEXT:    sf.vc.vvw 3, v8, v10, v11100; CHECK-NEXT:    ret101entry:102  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv4i32.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)103  ret void104}105 106define void @test_sf_vc_vvw_se_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {107; CHECK-LABEL: test_sf_vc_vvw_se_e16m2:108; CHECK:       # %bb.0: # %entry109; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma110; CHECK-NEXT:    sf.vc.vvw 3, v8, v12, v14111; CHECK-NEXT:    ret112entry:113  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv8i32.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)114  ret void115}116 117define void @test_sf_vc_vvw_se_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {118; CHECK-LABEL: test_sf_vc_vvw_se_e16m4:119; CHECK:       # %bb.0: # %entry120; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma121; CHECK-NEXT:    sf.vc.vvw 3, v8, v16, v20122; CHECK-NEXT:    ret123entry:124  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv16i32.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)125  ret void126}127 128define void @test_sf_vc_vvw_se_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {129; CHECK-LABEL: test_sf_vc_vvw_se_e32mf2:130; CHECK:       # %bb.0: # %entry131; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma132; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v10133; CHECK-NEXT:    ret134entry:135  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv1i64.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)136  ret void137}138 139define void @test_sf_vc_vvw_se_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {140; CHECK-LABEL: test_sf_vc_vvw_se_e32m1:141; CHECK:       # %bb.0: # %entry142; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma143; CHECK-NEXT:    sf.vc.vvw 3, v8, v10, v11144; CHECK-NEXT:    ret145entry:146  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv2i64.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)147  ret void148}149 150define void @test_sf_vc_vvw_se_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {151; CHECK-LABEL: test_sf_vc_vvw_se_e32m2:152; CHECK:       # %bb.0: # %entry153; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma154; CHECK-NEXT:    sf.vc.vvw 3, v8, v12, v14155; CHECK-NEXT:    ret156entry:157  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv4i64.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)158  ret void159}160 161define void @test_sf_vc_vvw_se_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {162; CHECK-LABEL: test_sf_vc_vvw_se_e32m4:163; CHECK:       # %bb.0: # %entry164; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma165; CHECK-NEXT:    sf.vc.vvw 3, v8, v16, v20166; CHECK-NEXT:    ret167entry:168  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv8i64.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)169  ret void170}171 172define <vscale x 1 x i16> @test_sf_vc_v_vvw_se_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {173; CHECK-LABEL: test_sf_vc_v_vvw_se_e8mf8:174; CHECK:       # %bb.0: # %entry175; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma176; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10177; CHECK-NEXT:    ret178entry:179  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvw.se.nxv1i16.iXLen.nxv1i8.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)180  ret <vscale x 1 x i16> %0181}182 183define <vscale x 2 x i16> @test_sf_vc_v_vvw_se_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {184; CHECK-LABEL: test_sf_vc_v_vvw_se_e8mf4:185; CHECK:       # %bb.0: # %entry186; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma187; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10188; CHECK-NEXT:    ret189entry:190  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvw.se.nxv2i16.iXLen.nxv2i8.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)191  ret <vscale x 2 x i16> %0192}193 194define <vscale x 4 x i16> @test_sf_vc_v_vvw_se_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {195; CHECK-LABEL: test_sf_vc_v_vvw_se_e8mf2:196; CHECK:       # %bb.0: # %entry197; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma198; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10199; CHECK-NEXT:    ret200entry:201  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvw.se.nxv4i16.iXLen.nxv4i8.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)202  ret <vscale x 4 x i16> %0203}204 205define <vscale x 8 x i16> @test_sf_vc_v_vvw_se_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {206; CHECK-LABEL: test_sf_vc_v_vvw_se_e8m1:207; CHECK:       # %bb.0: # %entry208; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma209; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v11210; CHECK-NEXT:    ret211entry:212  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvw.se.nxv8i16.iXLen.nxv8i8.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)213  ret <vscale x 8 x i16> %0214}215 216define <vscale x 16 x i16> @test_sf_vc_v_vvw_se_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {217; CHECK-LABEL: test_sf_vc_v_vvw_se_e8m2:218; CHECK:       # %bb.0: # %entry219; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma220; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v14221; CHECK-NEXT:    ret222entry:223  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvw.se.nxv16i16.iXLen.nxv16i8.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)224  ret <vscale x 16 x i16> %0225}226 227define <vscale x 32 x i16> @test_sf_vc_v_vvw_se_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {228; CHECK-LABEL: test_sf_vc_v_vvw_se_e8m4:229; CHECK:       # %bb.0: # %entry230; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma231; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v20232; CHECK-NEXT:    ret233entry:234  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvw.se.nxv32i16.iXLen.nxv32i8.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)235  ret <vscale x 32 x i16> %0236}237 238define <vscale x 1 x i32> @test_sf_vc_v_vvw_se_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {239; CHECK-LABEL: test_sf_vc_v_vvw_se_e16mf4:240; CHECK:       # %bb.0: # %entry241; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma242; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10243; CHECK-NEXT:    ret244entry:245  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvw.se.nxv1i32.iXLen.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)246  ret <vscale x 1 x i32> %0247}248 249define <vscale x 2 x i32> @test_sf_vc_v_vvw_se_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {250; CHECK-LABEL: test_sf_vc_v_vvw_se_e16mf2:251; CHECK:       # %bb.0: # %entry252; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma253; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10254; CHECK-NEXT:    ret255entry:256  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvw.se.nxv2i32.iXLen.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)257  ret <vscale x 2 x i32> %0258}259 260define <vscale x 4 x i32> @test_sf_vc_v_vvw_se_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {261; CHECK-LABEL: test_sf_vc_v_vvw_se_e16m1:262; CHECK:       # %bb.0: # %entry263; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma264; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v11265; CHECK-NEXT:    ret266entry:267  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvw.se.nxv4i32.iXLen.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)268  ret <vscale x 4 x i32> %0269}270 271define <vscale x 8 x i32> @test_sf_vc_v_vvw_se_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {272; CHECK-LABEL: test_sf_vc_v_vvw_se_e16m2:273; CHECK:       # %bb.0: # %entry274; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma275; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v14276; CHECK-NEXT:    ret277entry:278  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvw.se.nxv8i32.iXLen.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)279  ret <vscale x 8 x i32> %0280}281 282define <vscale x 16 x i32> @test_sf_vc_v_vvw_se_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {283; CHECK-LABEL: test_sf_vc_v_vvw_se_e16m4:284; CHECK:       # %bb.0: # %entry285; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma286; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v20287; CHECK-NEXT:    ret288entry:289  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvw.se.nxv16i32.iXLen.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)290  ret <vscale x 16 x i32> %0291}292 293define <vscale x 1 x i64> @test_sf_vc_v_vvw_se_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {294; CHECK-LABEL: test_sf_vc_v_vvw_se_e32mf2:295; CHECK:       # %bb.0: # %entry296; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma297; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10298; CHECK-NEXT:    ret299entry:300  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvw.se.nxv1i64.iXLen.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)301  ret <vscale x 1 x i64> %0302}303 304define <vscale x 2 x i64> @test_sf_vc_v_vvw_se_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {305; CHECK-LABEL: test_sf_vc_v_vvw_se_e32m1:306; CHECK:       # %bb.0: # %entry307; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma308; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v11309; CHECK-NEXT:    ret310entry:311  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvw.se.nxv2i64.iXLen.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)312  ret <vscale x 2 x i64> %0313}314 315define <vscale x 4 x i64> @test_sf_vc_v_vvw_se_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {316; CHECK-LABEL: test_sf_vc_v_vvw_se_e32m2:317; CHECK:       # %bb.0: # %entry318; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma319; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v14320; CHECK-NEXT:    ret321entry:322  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvw.se.nxv4i64.iXLen.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)323  ret <vscale x 4 x i64> %0324}325 326define <vscale x 8 x i64> @test_sf_vc_v_vvw_se_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {327; CHECK-LABEL: test_sf_vc_v_vvw_se_e32m4:328; CHECK:       # %bb.0: # %entry329; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma330; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v20331; CHECK-NEXT:    ret332entry:333  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvw.se.nxv8i64.iXLen.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)334  ret <vscale x 8 x i64> %0335}336 337define <vscale x 1 x i16> @test_sf_vc_v_vvw_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl) {338; CHECK-LABEL: test_sf_vc_v_vvw_e8mf8:339; CHECK:       # %bb.0: # %entry340; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma341; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10342; CHECK-NEXT:    ret343entry:344  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.vvw.nxv1i16.iXLen.nxv1i8.nxv1i8.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, <vscale x 1 x i8> %vs1, iXLen %vl)345  ret <vscale x 1 x i16> %0346}347 348define <vscale x 2 x i16> @test_sf_vc_v_vvw_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl) {349; CHECK-LABEL: test_sf_vc_v_vvw_e8mf4:350; CHECK:       # %bb.0: # %entry351; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma352; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10353; CHECK-NEXT:    ret354entry:355  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.vvw.nxv2i16.iXLen.nxv2i8.nxv2i8.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, <vscale x 2 x i8> %vs1, iXLen %vl)356  ret <vscale x 2 x i16> %0357}358 359define <vscale x 4 x i16> @test_sf_vc_v_vvw_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl) {360; CHECK-LABEL: test_sf_vc_v_vvw_e8mf2:361; CHECK:       # %bb.0: # %entry362; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma363; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10364; CHECK-NEXT:    ret365entry:366  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.vvw.nxv4i16.iXLen.nxv4i8.nxv4i8.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, <vscale x 4 x i8> %vs1, iXLen %vl)367  ret <vscale x 4 x i16> %0368}369 370define <vscale x 8 x i16> @test_sf_vc_v_vvw_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl) {371; CHECK-LABEL: test_sf_vc_v_vvw_e8m1:372; CHECK:       # %bb.0: # %entry373; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma374; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v11375; CHECK-NEXT:    ret376entry:377  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.vvw.nxv8i16.iXLen.nxv8i8.nxv8i8.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, <vscale x 8 x i8> %vs1, iXLen %vl)378  ret <vscale x 8 x i16> %0379}380 381define <vscale x 16 x i16> @test_sf_vc_v_vvw_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl) {382; CHECK-LABEL: test_sf_vc_v_vvw_e8m2:383; CHECK:       # %bb.0: # %entry384; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma385; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v14386; CHECK-NEXT:    ret387entry:388  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.vvw.nxv16i16.iXLen.nxv16i8.nxv16i8.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, <vscale x 16 x i8> %vs1, iXLen %vl)389  ret <vscale x 16 x i16> %0390}391 392define <vscale x 32 x i16> @test_sf_vc_v_vvw_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl) {393; CHECK-LABEL: test_sf_vc_v_vvw_e8m4:394; CHECK:       # %bb.0: # %entry395; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma396; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v20397; CHECK-NEXT:    ret398entry:399  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.vvw.nxv32i16.iXLen.nxv32i8.nxv32i8.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, <vscale x 32 x i8> %vs1, iXLen %vl)400  ret <vscale x 32 x i16> %0401}402 403define <vscale x 1 x i32> @test_sf_vc_v_vvw_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {404; CHECK-LABEL: test_sf_vc_v_vvw_e16mf4:405; CHECK:       # %bb.0: # %entry406; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma407; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10408; CHECK-NEXT:    ret409entry:410  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.vvw.nxv1i32.iXLen.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)411  ret <vscale x 1 x i32> %0412}413 414define <vscale x 2 x i32> @test_sf_vc_v_vvw_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {415; CHECK-LABEL: test_sf_vc_v_vvw_e16mf2:416; CHECK:       # %bb.0: # %entry417; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma418; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10419; CHECK-NEXT:    ret420entry:421  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.vvw.nxv2i32.iXLen.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)422  ret <vscale x 2 x i32> %0423}424 425define <vscale x 4 x i32> @test_sf_vc_v_vvw_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {426; CHECK-LABEL: test_sf_vc_v_vvw_e16m1:427; CHECK:       # %bb.0: # %entry428; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma429; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v11430; CHECK-NEXT:    ret431entry:432  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vvw.nxv4i32.iXLen.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)433  ret <vscale x 4 x i32> %0434}435 436define <vscale x 8 x i32> @test_sf_vc_v_vvw_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {437; CHECK-LABEL: test_sf_vc_v_vvw_e16m2:438; CHECK:       # %bb.0: # %entry439; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma440; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v14441; CHECK-NEXT:    ret442entry:443  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.vvw.nxv8i32.iXLen.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)444  ret <vscale x 8 x i32> %0445}446 447define <vscale x 16 x i32> @test_sf_vc_v_vvw_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {448; CHECK-LABEL: test_sf_vc_v_vvw_e16m4:449; CHECK:       # %bb.0: # %entry450; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma451; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v20452; CHECK-NEXT:    ret453entry:454  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.vvw.nxv16i32.iXLen.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)455  ret <vscale x 16 x i32> %0456}457 458define <vscale x 1 x i64> @test_sf_vc_v_vvw_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {459; CHECK-LABEL: test_sf_vc_v_vvw_e32mf2:460; CHECK:       # %bb.0: # %entry461; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma462; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v10463; CHECK-NEXT:    ret464entry:465  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.vvw.nxv1i64.iXLen.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)466  ret <vscale x 1 x i64> %0467}468 469define <vscale x 2 x i64> @test_sf_vc_v_vvw_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {470; CHECK-LABEL: test_sf_vc_v_vvw_e32m1:471; CHECK:       # %bb.0: # %entry472; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma473; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v11474; CHECK-NEXT:    ret475entry:476  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.vvw.nxv2i64.iXLen.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)477  ret <vscale x 2 x i64> %0478}479 480define <vscale x 4 x i64> @test_sf_vc_v_vvw_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {481; CHECK-LABEL: test_sf_vc_v_vvw_e32m2:482; CHECK:       # %bb.0: # %entry483; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma484; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v14485; CHECK-NEXT:    ret486entry:487  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.vvw.nxv4i64.iXLen.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)488  ret <vscale x 4 x i64> %0489}490 491define <vscale x 8 x i64> @test_sf_vc_v_vvw_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {492; CHECK-LABEL: test_sf_vc_v_vvw_e32m4:493; CHECK:       # %bb.0: # %entry494; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma495; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v20496; CHECK-NEXT:    ret497entry:498  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.vvw.nxv8i64.iXLen.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)499  ret <vscale x 8 x i64> %0500}501 502define void @test_sf_vc_xvw_se_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {503; CHECK-LABEL: test_sf_vc_xvw_se_e8mf8:504; CHECK:       # %bb.0: # %entry505; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma506; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a0507; CHECK-NEXT:    ret508entry:509  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv1i16.nxv1i8.i8.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)510  ret void511}512 513define void @test_sf_vc_xvw_se_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {514; CHECK-LABEL: test_sf_vc_xvw_se_e8mf4:515; CHECK:       # %bb.0: # %entry516; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma517; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a0518; CHECK-NEXT:    ret519entry:520  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv2i16.nxv2i8.i8.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)521  ret void522}523 524define void @test_sf_vc_xvw_se_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {525; CHECK-LABEL: test_sf_vc_xvw_se_e8mf2:526; CHECK:       # %bb.0: # %entry527; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma528; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a0529; CHECK-NEXT:    ret530entry:531  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv4i16.nxv4i8.i8.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)532  ret void533}534 535define void @test_sf_vc_xvw_se_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {536; CHECK-LABEL: test_sf_vc_xvw_se_e8m1:537; CHECK:       # %bb.0: # %entry538; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma539; CHECK-NEXT:    sf.vc.xvw 3, v8, v10, a0540; CHECK-NEXT:    ret541entry:542  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv8i16.nxv8i8.i8.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)543  ret void544}545 546define void @test_sf_vc_xvw_se_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {547; CHECK-LABEL: test_sf_vc_xvw_se_e8m2:548; CHECK:       # %bb.0: # %entry549; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma550; CHECK-NEXT:    sf.vc.xvw 3, v8, v12, a0551; CHECK-NEXT:    ret552entry:553  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv16i16.nxv16i8.i8.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)554  ret void555}556 557define void @test_sf_vc_xvw_se_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {558; CHECK-LABEL: test_sf_vc_xvw_se_e8m4:559; CHECK:       # %bb.0: # %entry560; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma561; CHECK-NEXT:    sf.vc.xvw 3, v8, v16, a0562; CHECK-NEXT:    ret563entry:564  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv32i16.nxv32i8.i8.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)565  ret void566}567 568define void @test_sf_vc_xvw_se_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {569; CHECK-LABEL: test_sf_vc_xvw_se_e16mf4:570; CHECK:       # %bb.0: # %entry571; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma572; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a0573; CHECK-NEXT:    ret574entry:575  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv1i32.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)576  ret void577}578 579define void @test_sf_vc_xvw_se_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {580; CHECK-LABEL: test_sf_vc_xvw_se_e16mf2:581; CHECK:       # %bb.0: # %entry582; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma583; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a0584; CHECK-NEXT:    ret585entry:586  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv2i32.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)587  ret void588}589 590define void @test_sf_vc_xvw_se_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {591; CHECK-LABEL: test_sf_vc_xvw_se_e16m1:592; CHECK:       # %bb.0: # %entry593; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma594; CHECK-NEXT:    sf.vc.xvw 3, v8, v10, a0595; CHECK-NEXT:    ret596entry:597  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv4i32.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)598  ret void599}600 601define void @test_sf_vc_xvw_se_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {602; CHECK-LABEL: test_sf_vc_xvw_se_e16m2:603; CHECK:       # %bb.0: # %entry604; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma605; CHECK-NEXT:    sf.vc.xvw 3, v8, v12, a0606; CHECK-NEXT:    ret607entry:608  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv8i32.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)609  ret void610}611 612define void @test_sf_vc_xvw_se_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {613; CHECK-LABEL: test_sf_vc_xvw_se_e16m4:614; CHECK:       # %bb.0: # %entry615; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma616; CHECK-NEXT:    sf.vc.xvw 3, v8, v16, a0617; CHECK-NEXT:    ret618entry:619  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv16i32.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)620  ret void621}622 623define void @test_sf_vc_xvw_se_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {624; CHECK-LABEL: test_sf_vc_xvw_se_e32mf2:625; CHECK:       # %bb.0: # %entry626; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma627; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a0628; CHECK-NEXT:    ret629entry:630  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv1i64.nxv1i32.i32.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)631  ret void632}633 634define void @test_sf_vc_xvw_se_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {635; CHECK-LABEL: test_sf_vc_xvw_se_e32m1:636; CHECK:       # %bb.0: # %entry637; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma638; CHECK-NEXT:    sf.vc.xvw 3, v8, v10, a0639; CHECK-NEXT:    ret640entry:641  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv2i64.nxv2i32.i32.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)642  ret void643}644 645define void @test_sf_vc_xvw_se_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {646; CHECK-LABEL: test_sf_vc_xvw_se_e32m2:647; CHECK:       # %bb.0: # %entry648; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma649; CHECK-NEXT:    sf.vc.xvw 3, v8, v12, a0650; CHECK-NEXT:    ret651entry:652  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv4i64.nxv4i32.i32.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)653  ret void654}655 656define void @test_sf_vc_xvw_se_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {657; CHECK-LABEL: test_sf_vc_xvw_se_e32m4:658; CHECK:       # %bb.0: # %entry659; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma660; CHECK-NEXT:    sf.vc.xvw 3, v8, v16, a0661; CHECK-NEXT:    ret662entry:663  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv8i64.nxv8i32.i32.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)664  ret void665}666 667define <vscale x 1 x i16> @test_sf_vc_v_xvw_se_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {668; CHECK-LABEL: test_sf_vc_v_xvw_se_e8mf8:669; CHECK:       # %bb.0: # %entry670; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, tu, ma671; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0672; CHECK-NEXT:    ret673entry:674  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvw.se.nxv1i16.iXLen.nxv1i8.i8.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)675  ret <vscale x 1 x i16> %0676}677 678define <vscale x 2 x i16> @test_sf_vc_v_xvw_se_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {679; CHECK-LABEL: test_sf_vc_v_xvw_se_e8mf4:680; CHECK:       # %bb.0: # %entry681; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, tu, ma682; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0683; CHECK-NEXT:    ret684entry:685  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvw.se.nxv2i16.iXLen.nxv2i8.i8.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)686  ret <vscale x 2 x i16> %0687}688 689define <vscale x 4 x i16> @test_sf_vc_v_xvw_se_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {690; CHECK-LABEL: test_sf_vc_v_xvw_se_e8mf2:691; CHECK:       # %bb.0: # %entry692; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, tu, ma693; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0694; CHECK-NEXT:    ret695entry:696  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvw.se.nxv4i16.iXLen.nxv4i8.i8.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)697  ret <vscale x 4 x i16> %0698}699 700define <vscale x 8 x i16> @test_sf_vc_v_xvw_se_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {701; CHECK-LABEL: test_sf_vc_v_xvw_se_e8m1:702; CHECK:       # %bb.0: # %entry703; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma704; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a0705; CHECK-NEXT:    ret706entry:707  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvw.se.nxv8i16.iXLen.nxv8i8.i8.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)708  ret <vscale x 8 x i16> %0709}710 711define <vscale x 16 x i16> @test_sf_vc_v_xvw_se_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {712; CHECK-LABEL: test_sf_vc_v_xvw_se_e8m2:713; CHECK:       # %bb.0: # %entry714; CHECK-NEXT:    vsetvli zero, a1, e8, m2, tu, ma715; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a0716; CHECK-NEXT:    ret717entry:718  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvw.se.nxv16i16.iXLen.nxv16i8.i8.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)719  ret <vscale x 16 x i16> %0720}721 722define <vscale x 32 x i16> @test_sf_vc_v_xvw_se_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {723; CHECK-LABEL: test_sf_vc_v_xvw_se_e8m4:724; CHECK:       # %bb.0: # %entry725; CHECK-NEXT:    vsetvli zero, a1, e8, m4, tu, ma726; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a0727; CHECK-NEXT:    ret728entry:729  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvw.se.nxv32i16.iXLen.nxv32i8.i8.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)730  ret <vscale x 32 x i16> %0731}732 733define <vscale x 1 x i32> @test_sf_vc_v_xvw_se_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {734; CHECK-LABEL: test_sf_vc_v_xvw_se_e16mf4:735; CHECK:       # %bb.0: # %entry736; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, ma737; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0738; CHECK-NEXT:    ret739entry:740  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvw.se.nxv1i32.iXLen.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)741  ret <vscale x 1 x i32> %0742}743 744define <vscale x 2 x i32> @test_sf_vc_v_xvw_se_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {745; CHECK-LABEL: test_sf_vc_v_xvw_se_e16mf2:746; CHECK:       # %bb.0: # %entry747; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, ma748; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0749; CHECK-NEXT:    ret750entry:751  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvw.se.nxv2i32.iXLen.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)752  ret <vscale x 2 x i32> %0753}754 755define <vscale x 4 x i32> @test_sf_vc_v_xvw_se_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {756; CHECK-LABEL: test_sf_vc_v_xvw_se_e16m1:757; CHECK:       # %bb.0: # %entry758; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma759; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a0760; CHECK-NEXT:    ret761entry:762  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvw.se.nxv4i32.iXLen.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)763  ret <vscale x 4 x i32> %0764}765 766define <vscale x 8 x i32> @test_sf_vc_v_xvw_se_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {767; CHECK-LABEL: test_sf_vc_v_xvw_se_e16m2:768; CHECK:       # %bb.0: # %entry769; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, ma770; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a0771; CHECK-NEXT:    ret772entry:773  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvw.se.nxv8i32.iXLen.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)774  ret <vscale x 8 x i32> %0775}776 777define <vscale x 16 x i32> @test_sf_vc_v_xvw_se_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {778; CHECK-LABEL: test_sf_vc_v_xvw_se_e16m4:779; CHECK:       # %bb.0: # %entry780; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, ma781; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a0782; CHECK-NEXT:    ret783entry:784  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvw.se.nxv16i32.iXLen.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)785  ret <vscale x 16 x i32> %0786}787 788define <vscale x 1 x i64> @test_sf_vc_v_xvw_se_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {789; CHECK-LABEL: test_sf_vc_v_xvw_se_e32mf2:790; CHECK:       # %bb.0: # %entry791; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma792; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0793; CHECK-NEXT:    ret794entry:795  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvw.se.nxv1i64.i32.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)796  ret <vscale x 1 x i64> %0797}798 799define <vscale x 2 x i64> @test_sf_vc_v_xvw_se_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {800; CHECK-LABEL: test_sf_vc_v_xvw_se_e32m1:801; CHECK:       # %bb.0: # %entry802; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma803; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a0804; CHECK-NEXT:    ret805entry:806  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvw.se.nxv2i64.i32.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)807  ret <vscale x 2 x i64> %0808}809 810define <vscale x 4 x i64> @test_sf_vc_v_xvw_se_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {811; CHECK-LABEL: test_sf_vc_v_xvw_se_e32m2:812; CHECK:       # %bb.0: # %entry813; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma814; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a0815; CHECK-NEXT:    ret816entry:817  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvw.se.nxv4i64.i32.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)818  ret <vscale x 4 x i64> %0819}820 821define <vscale x 8 x i64> @test_sf_vc_v_xvw_se_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {822; CHECK-LABEL: test_sf_vc_v_xvw_se_e32m4:823; CHECK:       # %bb.0: # %entry824; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma825; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a0826; CHECK-NEXT:    ret827entry:828  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvw.se.nxv8i64.i32.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)829  ret <vscale x 8 x i64> %0830}831 832define <vscale x 1 x i16> @test_sf_vc_v_xvw_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {833; CHECK-LABEL: test_sf_vc_v_xvw_e8mf8:834; CHECK:       # %bb.0: # %entry835; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, tu, ma836; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0837; CHECK-NEXT:    ret838entry:839  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.xvw.nxv1i16.iXLen.nxv1i8.i8.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, i8 %rs1, iXLen %vl)840  ret <vscale x 1 x i16> %0841}842 843define <vscale x 2 x i16> @test_sf_vc_v_xvw_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {844; CHECK-LABEL: test_sf_vc_v_xvw_e8mf4:845; CHECK:       # %bb.0: # %entry846; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, tu, ma847; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0848; CHECK-NEXT:    ret849entry:850  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.xvw.nxv2i16.iXLen.nxv2i8.i8.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, i8 %rs1, iXLen %vl)851  ret <vscale x 2 x i16> %0852}853 854define <vscale x 4 x i16> @test_sf_vc_v_xvw_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {855; CHECK-LABEL: test_sf_vc_v_xvw_e8mf2:856; CHECK:       # %bb.0: # %entry857; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, tu, ma858; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0859; CHECK-NEXT:    ret860entry:861  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.xvw.nxv4i16.iXLen.nxv4i8.i8.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, i8 %rs1, iXLen %vl)862  ret <vscale x 4 x i16> %0863}864 865define <vscale x 8 x i16> @test_sf_vc_v_xvw_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {866; CHECK-LABEL: test_sf_vc_v_xvw_e8m1:867; CHECK:       # %bb.0: # %entry868; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, ma869; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a0870; CHECK-NEXT:    ret871entry:872  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.xvw.nxv8i16.iXLen.nxv8i8.i8.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, i8 %rs1, iXLen %vl)873  ret <vscale x 8 x i16> %0874}875 876define <vscale x 16 x i16> @test_sf_vc_v_xvw_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {877; CHECK-LABEL: test_sf_vc_v_xvw_e8m2:878; CHECK:       # %bb.0: # %entry879; CHECK-NEXT:    vsetvli zero, a1, e8, m2, tu, ma880; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a0881; CHECK-NEXT:    ret882entry:883  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.xvw.nxv16i16.iXLen.nxv16i8.i8.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, i8 %rs1, iXLen %vl)884  ret <vscale x 16 x i16> %0885}886 887define <vscale x 32 x i16> @test_sf_vc_v_xvw_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, i8 zeroext %rs1, iXLen %vl) {888; CHECK-LABEL: test_sf_vc_v_xvw_e8m4:889; CHECK:       # %bb.0: # %entry890; CHECK-NEXT:    vsetvli zero, a1, e8, m4, tu, ma891; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a0892; CHECK-NEXT:    ret893entry:894  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.xvw.nxv32i16.iXLen.nxv32i8.i8.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, i8 %rs1, iXLen %vl)895  ret <vscale x 32 x i16> %0896}897 898define <vscale x 1 x i32> @test_sf_vc_v_xvw_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {899; CHECK-LABEL: test_sf_vc_v_xvw_e16mf4:900; CHECK:       # %bb.0: # %entry901; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, ma902; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0903; CHECK-NEXT:    ret904entry:905  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.xvw.nxv1i32.iXLen.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)906  ret <vscale x 1 x i32> %0907}908 909define <vscale x 2 x i32> @test_sf_vc_v_xvw_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {910; CHECK-LABEL: test_sf_vc_v_xvw_e16mf2:911; CHECK:       # %bb.0: # %entry912; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, ma913; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0914; CHECK-NEXT:    ret915entry:916  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.xvw.nxv2i32.iXLen.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)917  ret <vscale x 2 x i32> %0918}919 920define <vscale x 4 x i32> @test_sf_vc_v_xvw_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {921; CHECK-LABEL: test_sf_vc_v_xvw_e16m1:922; CHECK:       # %bb.0: # %entry923; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma924; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a0925; CHECK-NEXT:    ret926entry:927  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xvw.nxv4i32.iXLen.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)928  ret <vscale x 4 x i32> %0929}930 931define <vscale x 8 x i32> @test_sf_vc_v_xvw_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {932; CHECK-LABEL: test_sf_vc_v_xvw_e16m2:933; CHECK:       # %bb.0: # %entry934; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, ma935; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a0936; CHECK-NEXT:    ret937entry:938  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.xvw.nxv8i32.iXLen.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)939  ret <vscale x 8 x i32> %0940}941 942define <vscale x 16 x i32> @test_sf_vc_v_xvw_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, i16 zeroext %rs1, iXLen %vl) {943; CHECK-LABEL: test_sf_vc_v_xvw_e16m4:944; CHECK:       # %bb.0: # %entry945; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, ma946; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a0947; CHECK-NEXT:    ret948entry:949  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.xvw.nxv16i32.iXLen.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)950  ret <vscale x 16 x i32> %0951}952 953define <vscale x 1 x i64> @test_sf_vc_v_xvw_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, i32 signext %rs1, iXLen %vl) {954; CHECK-LABEL: test_sf_vc_v_xvw_e32mf2:955; CHECK:       # %bb.0: # %entry956; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma957; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a0958; CHECK-NEXT:    ret959entry:960  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.xvw.nxv1i64.iXLen.nxv1i32.i32.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)961  ret <vscale x 1 x i64> %0962}963 964define <vscale x 2 x i64> @test_sf_vc_v_xvw_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, i32 signext %rs1, iXLen %vl) {965; CHECK-LABEL: test_sf_vc_v_xvw_e32m1:966; CHECK:       # %bb.0: # %entry967; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma968; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a0969; CHECK-NEXT:    ret970entry:971  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.xvw.nxv2i64.iXLen.nxv2i32.i32.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)972  ret <vscale x 2 x i64> %0973}974 975define <vscale x 4 x i64> @test_sf_vc_v_xvw_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, i32 signext %rs1, iXLen %vl) {976; CHECK-LABEL: test_sf_vc_v_xvw_e32m2:977; CHECK:       # %bb.0: # %entry978; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma979; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a0980; CHECK-NEXT:    ret981entry:982  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.xvw.nxv4i64.iXLen.nxv4i32.i32.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)983  ret <vscale x 4 x i64> %0984}985 986define <vscale x 8 x i64> @test_sf_vc_v_xvw_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, i32 signext %rs1, iXLen %vl) {987; CHECK-LABEL: test_sf_vc_v_xvw_e32m4:988; CHECK:       # %bb.0: # %entry989; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma990; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a0991; CHECK-NEXT:    ret992entry:993  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.xvw.nxv8i64.iXLen.nxv8i32.i32.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)994  ret <vscale x 8 x i64> %0995}996 997define void @test_sf_vc_ivw_se_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, iXLen %vl) {998; CHECK-LABEL: test_sf_vc_ivw_se_e8mf8:999; CHECK:       # %bb.0: # %entry1000; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma1001; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 101002; CHECK-NEXT:    ret1003entry:1004  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv1i16.nxv1i8.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1005  ret void1006}1007 1008define void @test_sf_vc_ivw_se_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, iXLen %vl) {1009; CHECK-LABEL: test_sf_vc_ivw_se_e8mf4:1010; CHECK:       # %bb.0: # %entry1011; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma1012; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 101013; CHECK-NEXT:    ret1014entry:1015  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv2i16.nxv2i8.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1016  ret void1017}1018 1019define void @test_sf_vc_ivw_se_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, iXLen %vl) {1020; CHECK-LABEL: test_sf_vc_ivw_se_e8mf2:1021; CHECK:       # %bb.0: # %entry1022; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma1023; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 101024; CHECK-NEXT:    ret1025entry:1026  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv4i16.nxv4i8.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1027  ret void1028}1029 1030define void @test_sf_vc_ivw_se_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, iXLen %vl) {1031; CHECK-LABEL: test_sf_vc_ivw_se_e8m1:1032; CHECK:       # %bb.0: # %entry1033; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma1034; CHECK-NEXT:    sf.vc.ivw 3, v8, v10, 101035; CHECK-NEXT:    ret1036entry:1037  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv8i16.nxv8i8.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1038  ret void1039}1040 1041define void @test_sf_vc_ivw_se_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, iXLen %vl) {1042; CHECK-LABEL: test_sf_vc_ivw_se_e8m2:1043; CHECK:       # %bb.0: # %entry1044; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma1045; CHECK-NEXT:    sf.vc.ivw 3, v8, v12, 101046; CHECK-NEXT:    ret1047entry:1048  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv16i16.nxv16i8.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1049  ret void1050}1051 1052define void @test_sf_vc_ivw_se_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, iXLen %vl) {1053; CHECK-LABEL: test_sf_vc_ivw_se_e8m4:1054; CHECK:       # %bb.0: # %entry1055; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma1056; CHECK-NEXT:    sf.vc.ivw 3, v8, v16, 101057; CHECK-NEXT:    ret1058entry:1059  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv32i16.nxv32i8.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1060  ret void1061}1062 1063define void @test_sf_vc_ivw_se_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1064; CHECK-LABEL: test_sf_vc_ivw_se_e16mf4:1065; CHECK:       # %bb.0: # %entry1066; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1067; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 101068; CHECK-NEXT:    ret1069entry:1070  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv1i32.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1071  ret void1072}1073 1074define void @test_sf_vc_ivw_se_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1075; CHECK-LABEL: test_sf_vc_ivw_se_e16mf2:1076; CHECK:       # %bb.0: # %entry1077; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1078; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 101079; CHECK-NEXT:    ret1080entry:1081  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv2i32.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1082  ret void1083}1084 1085define void @test_sf_vc_ivw_se_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1086; CHECK-LABEL: test_sf_vc_ivw_se_e16m1:1087; CHECK:       # %bb.0: # %entry1088; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1089; CHECK-NEXT:    sf.vc.ivw 3, v8, v10, 101090; CHECK-NEXT:    ret1091entry:1092  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv4i32.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1093  ret void1094}1095 1096define void @test_sf_vc_ivw_se_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1097; CHECK-LABEL: test_sf_vc_ivw_se_e16m2:1098; CHECK:       # %bb.0: # %entry1099; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1100; CHECK-NEXT:    sf.vc.ivw 3, v8, v12, 101101; CHECK-NEXT:    ret1102entry:1103  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv8i32.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1104  ret void1105}1106 1107define void @test_sf_vc_ivw_se_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1108; CHECK-LABEL: test_sf_vc_ivw_se_e16m4:1109; CHECK:       # %bb.0: # %entry1110; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1111; CHECK-NEXT:    sf.vc.ivw 3, v8, v16, 101112; CHECK-NEXT:    ret1113entry:1114  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv16i32.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1115  ret void1116}1117 1118define void @test_sf_vc_ivw_se_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {1119; CHECK-LABEL: test_sf_vc_ivw_se_e32mf2:1120; CHECK:       # %bb.0: # %entry1121; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1122; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 101123; CHECK-NEXT:    ret1124entry:1125  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv1i64.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1126  ret void1127}1128 1129define void @test_sf_vc_ivw_se_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {1130; CHECK-LABEL: test_sf_vc_ivw_se_e32m1:1131; CHECK:       # %bb.0: # %entry1132; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1133; CHECK-NEXT:    sf.vc.ivw 3, v8, v10, 101134; CHECK-NEXT:    ret1135entry:1136  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv2i64.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1137  ret void1138}1139 1140define void @test_sf_vc_ivw_se_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {1141; CHECK-LABEL: test_sf_vc_ivw_se_e32m2:1142; CHECK:       # %bb.0: # %entry1143; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1144; CHECK-NEXT:    sf.vc.ivw 3, v8, v12, 101145; CHECK-NEXT:    ret1146entry:1147  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv4i64.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1148  ret void1149}1150 1151define void @test_sf_vc_ivw_se_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {1152; CHECK-LABEL: test_sf_vc_ivw_se_e32m4:1153; CHECK:       # %bb.0: # %entry1154; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1155; CHECK-NEXT:    sf.vc.ivw 3, v8, v16, 101156; CHECK-NEXT:    ret1157entry:1158  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv8i64.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1159  ret void1160}1161 1162define <vscale x 1 x i16> @test_sf_vc_v_ivw_se_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, iXLen %vl) {1163; CHECK-LABEL: test_sf_vc_v_ivw_se_e8mf8:1164; CHECK:       # %bb.0: # %entry1165; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma1166; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101167; CHECK-NEXT:    ret1168entry:1169  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivw.se.nxv1i16.iXLen.nxv1i8.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1170  ret <vscale x 1 x i16> %01171}1172 1173define <vscale x 2 x i16> @test_sf_vc_v_ivw_se_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, iXLen %vl) {1174; CHECK-LABEL: test_sf_vc_v_ivw_se_e8mf4:1175; CHECK:       # %bb.0: # %entry1176; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma1177; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101178; CHECK-NEXT:    ret1179entry:1180  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivw.se.nxv2i16.iXLen.nxv2i8.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1181  ret <vscale x 2 x i16> %01182}1183 1184define <vscale x 4 x i16> @test_sf_vc_v_ivw_se_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, iXLen %vl) {1185; CHECK-LABEL: test_sf_vc_v_ivw_se_e8mf2:1186; CHECK:       # %bb.0: # %entry1187; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma1188; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101189; CHECK-NEXT:    ret1190entry:1191  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivw.se.nxv4i16.iXLen.nxv4i8.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1192  ret <vscale x 4 x i16> %01193}1194 1195define <vscale x 8 x i16> @test_sf_vc_v_ivw_se_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, iXLen %vl) {1196; CHECK-LABEL: test_sf_vc_v_ivw_se_e8m1:1197; CHECK:       # %bb.0: # %entry1198; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma1199; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 101200; CHECK-NEXT:    ret1201entry:1202  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivw.se.nxv8i16.iXLen.nxv8i8.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1203  ret <vscale x 8 x i16> %01204}1205 1206define <vscale x 16 x i16> @test_sf_vc_v_ivw_se_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, iXLen %vl) {1207; CHECK-LABEL: test_sf_vc_v_ivw_se_e8m2:1208; CHECK:       # %bb.0: # %entry1209; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma1210; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 101211; CHECK-NEXT:    ret1212entry:1213  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivw.se.nxv16i16.iXLen.nxv16i8.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1214  ret <vscale x 16 x i16> %01215}1216 1217define <vscale x 32 x i16> @test_sf_vc_v_ivw_se_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, iXLen %vl) {1218; CHECK-LABEL: test_sf_vc_v_ivw_se_e8m4:1219; CHECK:       # %bb.0: # %entry1220; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma1221; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 101222; CHECK-NEXT:    ret1223entry:1224  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivw.se.nxv32i16.iXLen.nxv32i8.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1225  ret <vscale x 32 x i16> %01226}1227 1228define <vscale x 1 x i32> @test_sf_vc_v_ivw_se_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1229; CHECK-LABEL: test_sf_vc_v_ivw_se_e16mf4:1230; CHECK:       # %bb.0: # %entry1231; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma1232; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101233; CHECK-NEXT:    ret1234entry:1235  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivw.se.nxv1i32.iXLen.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1236  ret <vscale x 1 x i32> %01237}1238 1239define <vscale x 2 x i32> @test_sf_vc_v_ivw_se_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1240; CHECK-LABEL: test_sf_vc_v_ivw_se_e16mf2:1241; CHECK:       # %bb.0: # %entry1242; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma1243; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101244; CHECK-NEXT:    ret1245entry:1246  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivw.se.nxv2i32.iXLen.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1247  ret <vscale x 2 x i32> %01248}1249 1250define <vscale x 4 x i32> @test_sf_vc_v_ivw_se_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1251; CHECK-LABEL: test_sf_vc_v_ivw_se_e16m1:1252; CHECK:       # %bb.0: # %entry1253; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1254; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 101255; CHECK-NEXT:    ret1256entry:1257  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivw.se.nxv4i32.iXLen.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1258  ret <vscale x 4 x i32> %01259}1260 1261define <vscale x 8 x i32> @test_sf_vc_v_ivw_se_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1262; CHECK-LABEL: test_sf_vc_v_ivw_se_e16m2:1263; CHECK:       # %bb.0: # %entry1264; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma1265; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 101266; CHECK-NEXT:    ret1267entry:1268  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivw.se.nxv8i32.iXLen.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1269  ret <vscale x 8 x i32> %01270}1271 1272define <vscale x 16 x i32> @test_sf_vc_v_ivw_se_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1273; CHECK-LABEL: test_sf_vc_v_ivw_se_e16m4:1274; CHECK:       # %bb.0: # %entry1275; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma1276; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 101277; CHECK-NEXT:    ret1278entry:1279  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivw.se.nxv16i32.iXLen.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1280  ret <vscale x 16 x i32> %01281}1282 1283define <vscale x 1 x i64> @test_sf_vc_v_ivw_se_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {1284; CHECK-LABEL: test_sf_vc_v_ivw_se_e32mf2:1285; CHECK:       # %bb.0: # %entry1286; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma1287; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101288; CHECK-NEXT:    ret1289entry:1290  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivw.se.nxv1i64.iXLen.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1291  ret <vscale x 1 x i64> %01292}1293 1294define <vscale x 2 x i64> @test_sf_vc_v_ivw_se_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {1295; CHECK-LABEL: test_sf_vc_v_ivw_se_e32m1:1296; CHECK:       # %bb.0: # %entry1297; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma1298; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 101299; CHECK-NEXT:    ret1300entry:1301  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivw.se.nxv2i64.iXLen.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1302  ret <vscale x 2 x i64> %01303}1304 1305define <vscale x 4 x i64> @test_sf_vc_v_ivw_se_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {1306; CHECK-LABEL: test_sf_vc_v_ivw_se_e32m2:1307; CHECK:       # %bb.0: # %entry1308; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1309; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 101310; CHECK-NEXT:    ret1311entry:1312  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivw.se.nxv4i64.iXLen.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1313  ret <vscale x 4 x i64> %01314}1315 1316define <vscale x 8 x i64> @test_sf_vc_v_ivw_se_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {1317; CHECK-LABEL: test_sf_vc_v_ivw_se_e32m4:1318; CHECK:       # %bb.0: # %entry1319; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma1320; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 101321; CHECK-NEXT:    ret1322entry:1323  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivw.se.nxv8i64.iXLen.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1324  ret <vscale x 8 x i64> %01325}1326 1327define <vscale x 1 x i16> @test_sf_vc_v_ivw_e8mf8(<vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, iXLen %vl) {1328; CHECK-LABEL: test_sf_vc_v_ivw_e8mf8:1329; CHECK:       # %bb.0: # %entry1330; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma1331; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101332; CHECK-NEXT:    ret1333entry:1334  %0 = tail call <vscale x 1 x i16> @llvm.riscv.sf.vc.v.ivw.nxv1i16.iXLen.nxv1i8.iXLen.iXLen(iXLen 3, <vscale x 1 x i16> %vd, <vscale x 1 x i8> %vs2, iXLen 10, iXLen %vl)1335  ret <vscale x 1 x i16> %01336}1337 1338define <vscale x 2 x i16> @test_sf_vc_v_ivw_e8mf4(<vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, iXLen %vl) {1339; CHECK-LABEL: test_sf_vc_v_ivw_e8mf4:1340; CHECK:       # %bb.0: # %entry1341; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, ma1342; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101343; CHECK-NEXT:    ret1344entry:1345  %0 = tail call <vscale x 2 x i16> @llvm.riscv.sf.vc.v.ivw.nxv2i16.iXLen.nxv2i8.iXLen.iXLen(iXLen 3, <vscale x 2 x i16> %vd, <vscale x 2 x i8> %vs2, iXLen 10, iXLen %vl)1346  ret <vscale x 2 x i16> %01347}1348 1349define <vscale x 4 x i16> @test_sf_vc_v_ivw_e8mf2(<vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, iXLen %vl) {1350; CHECK-LABEL: test_sf_vc_v_ivw_e8mf2:1351; CHECK:       # %bb.0: # %entry1352; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, ma1353; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101354; CHECK-NEXT:    ret1355entry:1356  %0 = tail call <vscale x 4 x i16> @llvm.riscv.sf.vc.v.ivw.nxv4i16.iXLen.nxv4i8.iXLen.iXLen(iXLen 3, <vscale x 4 x i16> %vd, <vscale x 4 x i8> %vs2, iXLen 10, iXLen %vl)1357  ret <vscale x 4 x i16> %01358}1359 1360define <vscale x 8 x i16> @test_sf_vc_v_ivw_e8m1(<vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, iXLen %vl) {1361; CHECK-LABEL: test_sf_vc_v_ivw_e8m1:1362; CHECK:       # %bb.0: # %entry1363; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, ma1364; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 101365; CHECK-NEXT:    ret1366entry:1367  %0 = tail call <vscale x 8 x i16> @llvm.riscv.sf.vc.v.ivw.nxv8i16.iXLen.nxv8i8.iXLen.iXLen(iXLen 3, <vscale x 8 x i16> %vd, <vscale x 8 x i8> %vs2, iXLen 10, iXLen %vl)1368  ret <vscale x 8 x i16> %01369}1370 1371define <vscale x 16 x i16> @test_sf_vc_v_ivw_e8m2(<vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, iXLen %vl) {1372; CHECK-LABEL: test_sf_vc_v_ivw_e8m2:1373; CHECK:       # %bb.0: # %entry1374; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, ma1375; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 101376; CHECK-NEXT:    ret1377entry:1378  %0 = tail call <vscale x 16 x i16> @llvm.riscv.sf.vc.v.ivw.nxv16i16.iXLen.nxv16i8.iXLen.iXLen(iXLen 3, <vscale x 16 x i16> %vd, <vscale x 16 x i8> %vs2, iXLen 10, iXLen %vl)1379  ret <vscale x 16 x i16> %01380}1381 1382define <vscale x 32 x i16> @test_sf_vc_v_ivw_e8m4(<vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, iXLen %vl) {1383; CHECK-LABEL: test_sf_vc_v_ivw_e8m4:1384; CHECK:       # %bb.0: # %entry1385; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, ma1386; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 101387; CHECK-NEXT:    ret1388entry:1389  %0 = tail call <vscale x 32 x i16> @llvm.riscv.sf.vc.v.ivw.nxv32i16.iXLen.nxv32i8.iXLen.iXLen(iXLen 3, <vscale x 32 x i16> %vd, <vscale x 32 x i8> %vs2, iXLen 10, iXLen %vl)1390  ret <vscale x 32 x i16> %01391}1392 1393define <vscale x 1 x i32> @test_sf_vc_v_ivw_e16mf4(<vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1394; CHECK-LABEL: test_sf_vc_v_ivw_e16mf4:1395; CHECK:       # %bb.0: # %entry1396; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma1397; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101398; CHECK-NEXT:    ret1399entry:1400  %0 = tail call <vscale x 1 x i32> @llvm.riscv.sf.vc.v.ivw.nxv1i32.iXLen.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x i32> %vd, <vscale x 1 x i16> %vs2, iXLen 10, iXLen %vl)1401  ret <vscale x 1 x i32> %01402}1403 1404define <vscale x 2 x i32> @test_sf_vc_v_ivw_e16mf2(<vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1405; CHECK-LABEL: test_sf_vc_v_ivw_e16mf2:1406; CHECK:       # %bb.0: # %entry1407; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma1408; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101409; CHECK-NEXT:    ret1410entry:1411  %0 = tail call <vscale x 2 x i32> @llvm.riscv.sf.vc.v.ivw.nxv2i32.iXLen.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x i32> %vd, <vscale x 2 x i16> %vs2, iXLen 10, iXLen %vl)1412  ret <vscale x 2 x i32> %01413}1414 1415define <vscale x 4 x i32> @test_sf_vc_v_ivw_e16m1(<vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1416; CHECK-LABEL: test_sf_vc_v_ivw_e16m1:1417; CHECK:       # %bb.0: # %entry1418; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1419; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 101420; CHECK-NEXT:    ret1421entry:1422  %0 = tail call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.ivw.nxv4i32.iXLen.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x i32> %vd, <vscale x 4 x i16> %vs2, iXLen 10, iXLen %vl)1423  ret <vscale x 4 x i32> %01424}1425 1426define <vscale x 8 x i32> @test_sf_vc_v_ivw_e16m2(<vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1427; CHECK-LABEL: test_sf_vc_v_ivw_e16m2:1428; CHECK:       # %bb.0: # %entry1429; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma1430; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 101431; CHECK-NEXT:    ret1432entry:1433  %0 = tail call <vscale x 8 x i32> @llvm.riscv.sf.vc.v.ivw.nxv8i32.iXLen.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x i32> %vd, <vscale x 8 x i16> %vs2, iXLen 10, iXLen %vl)1434  ret <vscale x 8 x i32> %01435}1436 1437define <vscale x 16 x i32> @test_sf_vc_v_ivw_e16m4(<vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1438; CHECK-LABEL: test_sf_vc_v_ivw_e16m4:1439; CHECK:       # %bb.0: # %entry1440; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma1441; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 101442; CHECK-NEXT:    ret1443entry:1444  %0 = tail call <vscale x 16 x i32> @llvm.riscv.sf.vc.v.ivw.nxv16i32.iXLen.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x i32> %vd, <vscale x 16 x i16> %vs2, iXLen 10, iXLen %vl)1445  ret <vscale x 16 x i32> %01446}1447 1448define <vscale x 1 x i64> @test_sf_vc_v_ivw_e32mf2(<vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {1449; CHECK-LABEL: test_sf_vc_v_ivw_e32mf2:1450; CHECK:       # %bb.0: # %entry1451; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma1452; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 101453; CHECK-NEXT:    ret1454entry:1455  %0 = tail call <vscale x 1 x i64> @llvm.riscv.sf.vc.v.ivw.nxv1i64.iXLen.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x i64> %vd, <vscale x 1 x i32> %vs2, iXLen 10, iXLen %vl)1456  ret <vscale x 1 x i64> %01457}1458 1459define <vscale x 2 x i64> @test_sf_vc_v_ivw_e32m1(<vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {1460; CHECK-LABEL: test_sf_vc_v_ivw_e32m1:1461; CHECK:       # %bb.0: # %entry1462; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma1463; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 101464; CHECK-NEXT:    ret1465entry:1466  %0 = tail call <vscale x 2 x i64> @llvm.riscv.sf.vc.v.ivw.nxv2i64.iXLen.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x i64> %vd, <vscale x 2 x i32> %vs2, iXLen 10, iXLen %vl)1467  ret <vscale x 2 x i64> %01468}1469 1470define <vscale x 4 x i64> @test_sf_vc_v_ivw_e32m2(<vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {1471; CHECK-LABEL: test_sf_vc_v_ivw_e32m2:1472; CHECK:       # %bb.0: # %entry1473; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1474; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 101475; CHECK-NEXT:    ret1476entry:1477  %0 = tail call <vscale x 4 x i64> @llvm.riscv.sf.vc.v.ivw.nxv4i64.iXLen.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x i64> %vd, <vscale x 4 x i32> %vs2, iXLen 10, iXLen %vl)1478  ret <vscale x 4 x i64> %01479}1480 1481define <vscale x 8 x i64> @test_sf_vc_v_ivw_e32m4(<vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {1482; CHECK-LABEL: test_sf_vc_v_ivw_e32m4:1483; CHECK:       # %bb.0: # %entry1484; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma1485; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 101486; CHECK-NEXT:    ret1487entry:1488  %0 = tail call <vscale x 8 x i64> @llvm.riscv.sf.vc.v.ivw.nxv8i64.iXLen.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x i64> %vd, <vscale x 8 x i32> %vs2, iXLen 10, iXLen %vl)1489  ret <vscale x 8 x i64> %01490}1491 1492define void @test_sf_vc_fwvv_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {1493; CHECK-LABEL: test_sf_vc_fwvv_se_e32mf2:1494; CHECK:       # %bb.0: # %entry1495; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1496; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v101497; CHECK-NEXT:    ret1498entry:1499  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv1f32.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)1500  ret void1501}1502 1503define <vscale x 1 x float> @test_sf_vc_fw_fwvvv_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl) {1504; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e32mf2:1505; CHECK:       # %bb.0: # %entry1506; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma1507; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v101508; CHECK-NEXT:    ret1509entry:1510  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.vvw.se.nxv1f32.nxv1i16.nxv1i16.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, <vscale x 1 x i16> %vs1, iXLen %vl)1511  ret <vscale x 1 x float> %01512}1513 1514define void @test_sf_vc_fwvv_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {1515; CHECK-LABEL: test_sf_vc_fwvv_se_e32m1:1516; CHECK:       # %bb.0: # %entry1517; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1518; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v101519; CHECK-NEXT:    ret1520entry:1521  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv2f32.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)1522  ret void1523}1524 1525define <vscale x 2 x float> @test_sf_vc_fw_fwvvv_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl) {1526; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e32m1:1527; CHECK:       # %bb.0: # %entry1528; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma1529; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v101530; CHECK-NEXT:    ret1531entry:1532  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.vvw.se.nxv2f32.nxv2i16.nxv2i16.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, <vscale x 2 x i16> %vs1, iXLen %vl)1533  ret <vscale x 2 x float> %01534}1535 1536define void @test_sf_vc_fwvv_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {1537; CHECK-LABEL: test_sf_vc_fwvv_se_e32m2:1538; CHECK:       # %bb.0: # %entry1539; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1540; CHECK-NEXT:    sf.vc.vvw 3, v8, v10, v111541; CHECK-NEXT:    ret1542entry:1543  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv4f32.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)1544  ret void1545}1546 1547define <vscale x 4 x float> @test_sf_vc_fw_fwvvv_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl) {1548; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e32m2:1549; CHECK:       # %bb.0: # %entry1550; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1551; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v111552; CHECK-NEXT:    ret1553entry:1554  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.vvw.se.nxv4f32.nxv4i16.nxv4i16.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, <vscale x 4 x i16> %vs1, iXLen %vl)1555  ret <vscale x 4 x float> %01556}1557 1558define void @test_sf_vc_fwvv_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {1559; CHECK-LABEL: test_sf_vc_fwvv_se_e32m4:1560; CHECK:       # %bb.0: # %entry1561; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1562; CHECK-NEXT:    sf.vc.vvw 3, v8, v12, v141563; CHECK-NEXT:    ret1564entry:1565  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv8f32.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)1566  ret void1567}1568 1569define <vscale x 8 x float> @test_sf_vc_fw_fwvvv_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl) {1570; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e32m4:1571; CHECK:       # %bb.0: # %entry1572; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma1573; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v141574; CHECK-NEXT:    ret1575entry:1576  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.vvw.se.nxv8f32.nxv8i16.nxv8i16.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, <vscale x 8 x i16> %vs1, iXLen %vl)1577  ret <vscale x 8 x float> %01578}1579 1580define void @test_sf_vc_fwvv_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {1581; CHECK-LABEL: test_sf_vc_fwvv_se_e32m8:1582; CHECK:       # %bb.0: # %entry1583; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1584; CHECK-NEXT:    sf.vc.vvw 3, v8, v16, v201585; CHECK-NEXT:    ret1586entry:1587  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv16f32.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)1588  ret void1589}1590 1591define <vscale x 16 x float> @test_sf_vc_fw_fwvvv_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl) {1592; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e32m8:1593; CHECK:       # %bb.0: # %entry1594; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma1595; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v201596; CHECK-NEXT:    ret1597entry:1598  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.vvw.se.nxv16f32.nxv16i16.nxv16i16.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, <vscale x 16 x i16> %vs1, iXLen %vl)1599  ret <vscale x 16 x float> %01600}1601 1602define void @test_sf_vc_fwvv_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {1603; CHECK-LABEL: test_sf_vc_fwvv_se_e64m1:1604; CHECK:       # %bb.0: # %entry1605; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1606; CHECK-NEXT:    sf.vc.vvw 3, v8, v9, v101607; CHECK-NEXT:    ret1608entry:1609  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv1f64.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)1610  ret void1611}1612 1613define <vscale x 1 x double> @test_sf_vc_fw_fwvvv_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl) {1614; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e64m1:1615; CHECK:       # %bb.0: # %entry1616; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma1617; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v9, v101618; CHECK-NEXT:    ret1619entry:1620  %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.vvw.se.nxv1f64.nxv1i32.nxv1i32.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, <vscale x 1 x i32> %vs1, iXLen %vl)1621  ret <vscale x 1 x double> %01622}1623 1624define void @test_sf_vc_fwvv_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {1625; CHECK-LABEL: test_sf_vc_fwvv_se_e64m2:1626; CHECK:       # %bb.0: # %entry1627; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1628; CHECK-NEXT:    sf.vc.vvw 3, v8, v10, v111629; CHECK-NEXT:    ret1630entry:1631  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv2f64.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)1632  ret void1633}1634 1635define <vscale x 2 x double> @test_sf_vc_fw_fwvvv_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl) {1636; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e64m2:1637; CHECK:       # %bb.0: # %entry1638; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma1639; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v10, v111640; CHECK-NEXT:    ret1641entry:1642  %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.vvw.se.nxv2f64.nxv2i32.nxv2i32.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, <vscale x 2 x i32> %vs1, iXLen %vl)1643  ret <vscale x 2 x double> %01644}1645 1646define void @test_sf_vc_fwvv_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {1647; CHECK-LABEL: test_sf_vc_fwvv_se_e64m4:1648; CHECK:       # %bb.0: # %entry1649; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1650; CHECK-NEXT:    sf.vc.vvw 3, v8, v12, v141651; CHECK-NEXT:    ret1652entry:1653  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv4f64.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)1654  ret void1655}1656 1657define <vscale x 4 x double> @test_sf_vc_fw_fwvvv_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl) {1658; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e64m4:1659; CHECK:       # %bb.0: # %entry1660; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma1661; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v12, v141662; CHECK-NEXT:    ret1663entry:1664  %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.vvw.se.nxv4f64.nxv4i32.nxv4i32.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, <vscale x 4 x i32> %vs1, iXLen %vl)1665  ret <vscale x 4 x double> %01666}1667 1668define void @test_sf_vc_fwvv_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {1669; CHECK-LABEL: test_sf_vc_fwvv_se_e64m8:1670; CHECK:       # %bb.0: # %entry1671; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1672; CHECK-NEXT:    sf.vc.vvw 3, v8, v16, v201673; CHECK-NEXT:    ret1674entry:1675  tail call void @llvm.riscv.sf.vc.vvw.se.iXLen.nxv8f64.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)1676  ret void1677}1678 1679define <vscale x 8 x double> @test_sf_vc_fw_fwvvv_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl) {1680; CHECK-LABEL: test_sf_vc_fw_fwvvv_se_e64m8:1681; CHECK:       # %bb.0: # %entry1682; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma1683; CHECK-NEXT:    sf.vc.v.vvw 3, v8, v16, v201684; CHECK-NEXT:    ret1685entry:1686  %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.vvw.se.nxv8f64.nxv8i32.nxv8i32.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, <vscale x 8 x i32> %vs1, iXLen %vl)1687  ret <vscale x 8 x double> %01688}1689 1690define void @test_sf_vc_fwvx_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl) {1691; CHECK-LABEL: test_sf_vc_fwvx_se_e32mf2:1692; CHECK:       # %bb.0: # %entry1693; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1694; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a01695; CHECK-NEXT:    ret1696entry:1697  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv1f32.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)1698  ret void1699}1700 1701define <vscale x 1 x float> @test_sf_vc_w_fwvx_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl) {1702; CHECK-LABEL: test_sf_vc_w_fwvx_se_e32mf2:1703; CHECK:       # %bb.0: # %entry1704; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, ma1705; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a01706; CHECK-NEXT:    ret1707entry:1708  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.xvw.se.nxv1f32.nxv1f16.nxv1i16.i16.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, i16 %rs1, iXLen %vl)1709  ret <vscale x 1 x float> %01710}1711 1712define void @test_sf_vc_fwvx_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl) {1713; CHECK-LABEL: test_sf_vc_fwvx_se_e32m1:1714; CHECK:       # %bb.0: # %entry1715; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1716; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a01717; CHECK-NEXT:    ret1718entry:1719  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv2f32.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)1720  ret void1721}1722 1723define <vscale x 2 x float> @test_sf_vc_w_fwvx_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl) {1724; CHECK-LABEL: test_sf_vc_w_fwvx_se_e32m1:1725; CHECK:       # %bb.0: # %entry1726; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, ma1727; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a01728; CHECK-NEXT:    ret1729entry:1730  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.xvw.se.nxv2f32.nxv2f16.nxv2i16.i16.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, i16 %rs1, iXLen %vl)1731  ret <vscale x 2 x float> %01732}1733 1734define void @test_sf_vc_fwvx_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl) {1735; CHECK-LABEL: test_sf_vc_fwvx_se_e32m2:1736; CHECK:       # %bb.0: # %entry1737; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1738; CHECK-NEXT:    sf.vc.xvw 3, v8, v10, a01739; CHECK-NEXT:    ret1740entry:1741  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv4f32.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)1742  ret void1743}1744 1745define <vscale x 4 x float> @test_sf_vc_w_fwvx_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl) {1746; CHECK-LABEL: test_sf_vc_w_fwvx_se_e32m2:1747; CHECK:       # %bb.0: # %entry1748; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, ma1749; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a01750; CHECK-NEXT:    ret1751entry:1752  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.xvw.se.nxv4f32.nxv4f16.nxv4i16.i16.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, i16 %rs1, iXLen %vl)1753  ret <vscale x 4 x float> %01754}1755 1756define void @test_sf_vc_fwvx_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl) {1757; CHECK-LABEL: test_sf_vc_fwvx_se_e32m4:1758; CHECK:       # %bb.0: # %entry1759; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1760; CHECK-NEXT:    sf.vc.xvw 3, v8, v12, a01761; CHECK-NEXT:    ret1762entry:1763  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv8f32.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)1764  ret void1765}1766 1767define <vscale x 8 x float> @test_sf_vc_w_fwvx_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl) {1768; CHECK-LABEL: test_sf_vc_w_fwvx_se_e32m4:1769; CHECK:       # %bb.0: # %entry1770; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, ma1771; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a01772; CHECK-NEXT:    ret1773entry:1774  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.xvw.se.nxv8f32.nxv8f16.nxv8i16.i16.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, i16 %rs1, iXLen %vl)1775  ret <vscale x 8 x float> %01776}1777 1778define void @test_sf_vc_fwvx_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl) {1779; CHECK-LABEL: test_sf_vc_fwvx_se_e32m8:1780; CHECK:       # %bb.0: # %entry1781; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1782; CHECK-NEXT:    sf.vc.xvw 3, v8, v16, a01783; CHECK-NEXT:    ret1784entry:1785  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv16f32.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)1786  ret void1787}1788 1789define <vscale x 16 x float> @test_sf_vc_w_fwvx_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl) {1790; CHECK-LABEL: test_sf_vc_w_fwvx_se_e32m8:1791; CHECK:       # %bb.0: # %entry1792; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, ma1793; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a01794; CHECK-NEXT:    ret1795entry:1796  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.xvw.se.nxv16f32.nxv16f16.nxv16i16.i16.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, i16 %rs1, iXLen %vl)1797  ret <vscale x 16 x float> %01798}1799 1800define void @test_sf_vc_fwvx_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl) {1801; CHECK-LABEL: test_sf_vc_fwvx_se_e64m1:1802; CHECK:       # %bb.0: # %entry1803; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1804; CHECK-NEXT:    sf.vc.xvw 3, v8, v9, a01805; CHECK-NEXT:    ret1806entry:1807  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv1f64.nxv1i32.i32.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)1808  ret void1809}1810 1811define <vscale x 1 x double> @test_sf_vc_w_fwvx_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl) {1812; CHECK-LABEL: test_sf_vc_w_fwvx_se_e64m1:1813; CHECK:       # %bb.0: # %entry1814; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, ma1815; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v9, a01816; CHECK-NEXT:    ret1817entry:1818  %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.xvw.se.nxv1f64.nxv1f32.nxv1i32.i32.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, i32 %rs1, iXLen %vl)1819  ret <vscale x 1 x double> %01820}1821 1822define void @test_sf_vc_fwvx_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl) {1823; CHECK-LABEL: test_sf_vc_fwvx_se_e64m2:1824; CHECK:       # %bb.0: # %entry1825; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1826; CHECK-NEXT:    sf.vc.xvw 3, v8, v10, a01827; CHECK-NEXT:    ret1828entry:1829  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv2f64.nxv2i32.i32.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)1830  ret void1831}1832 1833define <vscale x 2 x double> @test_sf_vc_w_fwvx_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl) {1834; CHECK-LABEL: test_sf_vc_w_fwvx_se_e64m2:1835; CHECK:       # %bb.0: # %entry1836; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, ma1837; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v10, a01838; CHECK-NEXT:    ret1839entry:1840  %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.xvw.se.nxv2f64.nxv2f32.nxv2i32.i32.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, i32 %rs1, iXLen %vl)1841  ret <vscale x 2 x double> %01842}1843 1844define void @test_sf_vc_fwvx_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl) {1845; CHECK-LABEL: test_sf_vc_fwvx_se_e64m4:1846; CHECK:       # %bb.0: # %entry1847; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1848; CHECK-NEXT:    sf.vc.xvw 3, v8, v12, a01849; CHECK-NEXT:    ret1850entry:1851  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv4f64.nxv4i32.i32.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)1852  ret void1853}1854 1855define <vscale x 4 x double> @test_sf_vc_w_fwvx_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl) {1856; CHECK-LABEL: test_sf_vc_w_fwvx_se_e64m4:1857; CHECK:       # %bb.0: # %entry1858; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, ma1859; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v12, a01860; CHECK-NEXT:    ret1861entry:1862  %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.xvw.se.nxv4f64.nxv4f32.nxv4i32.i32.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, i32 %rs1, iXLen %vl)1863  ret <vscale x 4 x double> %01864}1865 1866define void @test_sf_vc_fwvx_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl) {1867; CHECK-LABEL: test_sf_vc_fwvx_se_e64m8:1868; CHECK:       # %bb.0: # %entry1869; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1870; CHECK-NEXT:    sf.vc.xvw 3, v8, v16, a01871; CHECK-NEXT:    ret1872entry:1873  tail call void @llvm.riscv.sf.vc.xvw.se.iXLen.nxv8f64.nxv8i32.i32.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)1874  ret void1875}1876 1877define <vscale x 8 x double> @test_sf_vc_w_fwvx_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl) {1878; CHECK-LABEL: test_sf_vc_w_fwvx_se_e64m8:1879; CHECK:       # %bb.0: # %entry1880; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, ma1881; CHECK-NEXT:    sf.vc.v.xvw 3, v8, v16, a01882; CHECK-NEXT:    ret1883entry:1884  %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.xvw.se.nxv8f64.nxv8f32.nxv8i32.i32.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, i32 %rs1, iXLen %vl)1885  ret <vscale x 8 x double> %01886}1887 1888define void @test_sf_vc_fwvi_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1889; CHECK-LABEL: test_sf_vc_fwvi_se_e32mf2:1890; CHECK:       # %bb.0: # %entry1891; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1892; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 31893; CHECK-NEXT:    ret1894entry:1895  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv1f32.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, iXLen 3, iXLen %vl)1896  ret void1897}1898 1899define <vscale x 1 x float> @test_sf_vc_fw_fwvi_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, iXLen %vl) {1900; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e32mf2:1901; CHECK:       # %bb.0: # %entry1902; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma1903; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 31904; CHECK-NEXT:    ret1905entry:1906  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.ivw.se.nxv1f32.nxv1f16.nxv1i16.iXLen.iXLen(iXLen 3, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, iXLen 3, iXLen %vl)1907  ret <vscale x 1 x float> %01908}1909 1910define void @test_sf_vc_fwvi_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1911; CHECK-LABEL: test_sf_vc_fwvi_se_e32m1:1912; CHECK:       # %bb.0: # %entry1913; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1914; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 31915; CHECK-NEXT:    ret1916entry:1917  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv2f32.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, iXLen 3, iXLen %vl)1918  ret void1919}1920 1921define <vscale x 2 x float> @test_sf_vc_fw_fwvi_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, iXLen %vl) {1922; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e32m1:1923; CHECK:       # %bb.0: # %entry1924; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma1925; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 31926; CHECK-NEXT:    ret1927entry:1928  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.ivw.se.nxv2f32.nxv2f16.nxv2i16.iXLen.iXLen(iXLen 3, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, iXLen 3, iXLen %vl)1929  ret <vscale x 2 x float> %01930}1931 1932define void @test_sf_vc_fwvi_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1933; CHECK-LABEL: test_sf_vc_fwvi_se_e32m2:1934; CHECK:       # %bb.0: # %entry1935; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1936; CHECK-NEXT:    sf.vc.ivw 3, v8, v10, 31937; CHECK-NEXT:    ret1938entry:1939  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv4f32.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, iXLen 3, iXLen %vl)1940  ret void1941}1942 1943define <vscale x 4 x float> @test_sf_vc_fw_fwvi_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, iXLen %vl) {1944; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e32m2:1945; CHECK:       # %bb.0: # %entry1946; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma1947; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 31948; CHECK-NEXT:    ret1949entry:1950  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.ivw.se.nxv4f32.nxv4f16.nxv4i16.iXLen.iXLen(iXLen 3, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, iXLen 3, iXLen %vl)1951  ret <vscale x 4 x float> %01952}1953 1954define void @test_sf_vc_fwvi_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1955; CHECK-LABEL: test_sf_vc_fwvi_se_e32m4:1956; CHECK:       # %bb.0: # %entry1957; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1958; CHECK-NEXT:    sf.vc.ivw 3, v8, v12, 31959; CHECK-NEXT:    ret1960entry:1961  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv8f32.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, iXLen 3, iXLen %vl)1962  ret void1963}1964 1965define <vscale x 8 x float> @test_sf_vc_fw_fwvi_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, iXLen %vl) {1966; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e32m4:1967; CHECK:       # %bb.0: # %entry1968; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma1969; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 31970; CHECK-NEXT:    ret1971entry:1972  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.ivw.se.nxv8f32.nxv8f16.nxv8i16.iXLen.iXLen(iXLen 3, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, iXLen 3, iXLen %vl)1973  ret <vscale x 8 x float> %01974}1975 1976define void @test_sf_vc_fwvi_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1977; CHECK-LABEL: test_sf_vc_fwvi_se_e32m8:1978; CHECK:       # %bb.0: # %entry1979; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1980; CHECK-NEXT:    sf.vc.ivw 3, v8, v16, 31981; CHECK-NEXT:    ret1982entry:1983  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv16f32.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, iXLen 3, iXLen %vl)1984  ret void1985}1986 1987define <vscale x 16 x float> @test_sf_vc_fw_fwvi_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, iXLen %vl) {1988; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e32m8:1989; CHECK:       # %bb.0: # %entry1990; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma1991; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 31992; CHECK-NEXT:    ret1993entry:1994  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.ivw.se.nxv16f32.nxv16f16.nxv16i16.iXLen.iXLen(iXLen 3, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, iXLen 3, iXLen %vl)1995  ret <vscale x 16 x float> %01996}1997 1998define void @test_sf_vc_fwvi_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {1999; CHECK-LABEL: test_sf_vc_fwvi_se_e64m1:2000; CHECK:       # %bb.0: # %entry2001; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2002; CHECK-NEXT:    sf.vc.ivw 3, v8, v9, 32003; CHECK-NEXT:    ret2004entry:2005  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv1f64.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, iXLen 3, iXLen %vl)2006  ret void2007}2008 2009define <vscale x 1 x double> @test_sf_vc_fw_fwvi_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, iXLen %vl) {2010; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e64m1:2011; CHECK:       # %bb.0: # %entry2012; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma2013; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v9, 32014; CHECK-NEXT:    ret2015entry:2016  %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.ivw.se.nxv1f64.nxv1f32.nxv1i32.iXLen.iXLen(iXLen 3, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, iXLen 3, iXLen %vl)2017  ret <vscale x 1 x double> %02018}2019 2020define void @test_sf_vc_fwvi_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {2021; CHECK-LABEL: test_sf_vc_fwvi_se_e64m2:2022; CHECK:       # %bb.0: # %entry2023; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2024; CHECK-NEXT:    sf.vc.ivw 3, v8, v10, 32025; CHECK-NEXT:    ret2026entry:2027  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv2f64.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, iXLen 3, iXLen %vl)2028  ret void2029}2030 2031define <vscale x 2 x double> @test_sf_vc_fw_fwvi_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, iXLen %vl) {2032; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e64m2:2033; CHECK:       # %bb.0: # %entry2034; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma2035; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v10, 32036; CHECK-NEXT:    ret2037entry:2038  %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.ivw.se.nxv2f64.nxv2f32.nxv2i32.iXLen.iXLen(iXLen 3, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, iXLen 3, iXLen %vl)2039  ret <vscale x 2 x double> %02040}2041 2042define void @test_sf_vc_fwvi_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {2043; CHECK-LABEL: test_sf_vc_fwvi_se_e64m4:2044; CHECK:       # %bb.0: # %entry2045; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2046; CHECK-NEXT:    sf.vc.ivw 3, v8, v12, 32047; CHECK-NEXT:    ret2048entry:2049  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv4f64.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, iXLen 3, iXLen %vl)2050  ret void2051}2052 2053define <vscale x 4 x double> @test_sf_vc_fw_fwvi_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, iXLen %vl) {2054; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e64m4:2055; CHECK:       # %bb.0: # %entry2056; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma2057; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v12, 32058; CHECK-NEXT:    ret2059entry:2060  %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.ivw.se.nxv4f64.nxv4f32.nxv4i32.iXLen.iXLen(iXLen 3, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, iXLen 3, iXLen %vl)2061  ret <vscale x 4 x double> %02062}2063 2064define void @test_sf_vc_fwvi_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {2065; CHECK-LABEL: test_sf_vc_fwvi_se_e64m8:2066; CHECK:       # %bb.0: # %entry2067; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2068; CHECK-NEXT:    sf.vc.ivw 3, v8, v16, 32069; CHECK-NEXT:    ret2070entry:2071  tail call void @llvm.riscv.sf.vc.ivw.se.iXLen.nxv8f64.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, iXLen 3, iXLen %vl)2072  ret void2073}2074 2075define <vscale x 8 x double> @test_sf_vc_fw_fwvi_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, iXLen %vl) {2076; CHECK-LABEL: test_sf_vc_fw_fwvi_se_e64m8:2077; CHECK:       # %bb.0: # %entry2078; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma2079; CHECK-NEXT:    sf.vc.v.ivw 3, v8, v16, 32080; CHECK-NEXT:    ret2081entry:2082  %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.ivw.se.nxv8f64.nxv8f32.nxv8i32.iXLen.iXLen(iXLen 3, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, iXLen 3, iXLen %vl)2083  ret <vscale x 8 x double> %02084}2085 2086define void @test_sf_vc_fwvf_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl) {2087; CHECK-LABEL: test_sf_vc_fwvf_se_e32mf2:2088; CHECK:       # %bb.0: # %entry2089; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2090; CHECK-NEXT:    sf.vc.fvw 1, v8, v9, fa02091; CHECK-NEXT:    ret2092entry:2093  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv1f32.nxv1i16.f16.iXLen(iXLen 1, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl)2094  ret void2095}2096 2097define <vscale x 1 x float> @test_sf_vc_fw_fwvf_se_e32mf2(<vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl) {2098; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e32mf2:2099; CHECK:       # %bb.0: # %entry2100; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, ma2101; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v9, fa02102; CHECK-NEXT:    ret2103entry:2104  %0 = tail call <vscale x 1 x float> @llvm.riscv.sf.vc.v.fvw.se.nxv1f32.nxv1f16.nxv1i16.f16.iXLen(iXLen 1, <vscale x 1 x float> %vd, <vscale x 1 x i16> %vs2, half %rs1, iXLen %vl)2105  ret <vscale x 1 x float> %02106}2107 2108define void @test_sf_vc_fwvf_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl) {2109; CHECK-LABEL: test_sf_vc_fwvf_se_e32m1:2110; CHECK:       # %bb.0: # %entry2111; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2112; CHECK-NEXT:    sf.vc.fvw 1, v8, v9, fa02113; CHECK-NEXT:    ret2114entry:2115  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv2f32.nxv2i16.f16.iXLen(iXLen 1, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl)2116  ret void2117}2118 2119define <vscale x 2 x float> @test_sf_vc_fw_fwvf_se_e32m1(<vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl) {2120; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e32m1:2121; CHECK:       # %bb.0: # %entry2122; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, ma2123; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v9, fa02124; CHECK-NEXT:    ret2125entry:2126  %0 = tail call <vscale x 2 x float> @llvm.riscv.sf.vc.v.fvw.se.nxv2f32.nxv2f16.nxv2i16.f16.iXLen(iXLen 1, <vscale x 2 x float> %vd, <vscale x 2 x i16> %vs2, half %rs1, iXLen %vl)2127  ret <vscale x 2 x float> %02128}2129 2130define void @test_sf_vc_fwvf_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl) {2131; CHECK-LABEL: test_sf_vc_fwvf_se_e32m2:2132; CHECK:       # %bb.0: # %entry2133; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2134; CHECK-NEXT:    sf.vc.fvw 1, v8, v10, fa02135; CHECK-NEXT:    ret2136entry:2137  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv4f32.nxv4i16.f16.iXLen(iXLen 1, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl)2138  ret void2139}2140 2141define <vscale x 4 x float> @test_sf_vc_fw_fwvf_se_e32m2(<vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl) {2142; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e32m2:2143; CHECK:       # %bb.0: # %entry2144; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, ma2145; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v10, fa02146; CHECK-NEXT:    ret2147entry:2148  %0 = tail call <vscale x 4 x float> @llvm.riscv.sf.vc.v.fvw.se.nxv4f32.nxv4f16.nxv4i16.f16.iXLen(iXLen 1, <vscale x 4 x float> %vd, <vscale x 4 x i16> %vs2, half %rs1, iXLen %vl)2149  ret <vscale x 4 x float> %02150}2151 2152define void @test_sf_vc_fwvf_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl) {2153; CHECK-LABEL: test_sf_vc_fwvf_se_e32m4:2154; CHECK:       # %bb.0: # %entry2155; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2156; CHECK-NEXT:    sf.vc.fvw 1, v8, v12, fa02157; CHECK-NEXT:    ret2158entry:2159  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv8f32.nxv8i16.f16.iXLen(iXLen 1, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl)2160  ret void2161}2162 2163define <vscale x 8 x float> @test_sf_vc_fw_fwvf_se_e32m4(<vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl) {2164; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e32m4:2165; CHECK:       # %bb.0: # %entry2166; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, ma2167; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v12, fa02168; CHECK-NEXT:    ret2169entry:2170  %0 = tail call <vscale x 8 x float> @llvm.riscv.sf.vc.v.fvw.se.nxv8f32.nxv8f16.nxv8i16.f16.iXLen(iXLen 1, <vscale x 8 x float> %vd, <vscale x 8 x i16> %vs2, half %rs1, iXLen %vl)2171  ret <vscale x 8 x float> %02172}2173 2174define void @test_sf_vc_fwvf_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl) {2175; CHECK-LABEL: test_sf_vc_fwvf_se_e32m8:2176; CHECK:       # %bb.0: # %entry2177; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2178; CHECK-NEXT:    sf.vc.fvw 1, v8, v16, fa02179; CHECK-NEXT:    ret2180entry:2181  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv16f32.nxv16i16.f16.iXLen(iXLen 1, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl)2182  ret void2183}2184 2185define <vscale x 16 x float> @test_sf_vc_fw_fwvf_se_e32m8(<vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl) {2186; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e32m8:2187; CHECK:       # %bb.0: # %entry2188; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, ma2189; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v16, fa02190; CHECK-NEXT:    ret2191entry:2192  %0 = tail call <vscale x 16 x float> @llvm.riscv.sf.vc.v.fvw.se.nxv16f32.nxv16f16.nxv16i16.f16.iXLen(iXLen 1, <vscale x 16 x float> %vd, <vscale x 16 x i16> %vs2, half %rs1, iXLen %vl)2193  ret <vscale x 16 x float> %02194}2195 2196define void @test_sf_vc_fwvf_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl) {2197; CHECK-LABEL: test_sf_vc_fwvf_se_e64m1:2198; CHECK:       # %bb.0: # %entry2199; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2200; CHECK-NEXT:    sf.vc.fvw 1, v8, v9, fa02201; CHECK-NEXT:    ret2202entry:2203  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv1f64.nxv1i32.f32.iXLen(iXLen 1, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl)2204  ret void2205}2206 2207define <vscale x 1 x double> @test_sf_vc_fw_fwvf_se_e64m1(<vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl) {2208; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e64m1:2209; CHECK:       # %bb.0: # %entry2210; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, ma2211; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v9, fa02212; CHECK-NEXT:    ret2213entry:2214  %0 = tail call <vscale x 1 x double> @llvm.riscv.sf.vc.v.fvw.se.nxv1f64.nxv1f32.nxv1i32.f32.iXLen(iXLen 1, <vscale x 1 x double> %vd, <vscale x 1 x i32> %vs2, float %rs1, iXLen %vl)2215  ret <vscale x 1 x double> %02216}2217 2218define void @test_sf_vc_fwvf_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl) {2219; CHECK-LABEL: test_sf_vc_fwvf_se_e64m2:2220; CHECK:       # %bb.0: # %entry2221; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma2222; CHECK-NEXT:    sf.vc.fvw 1, v8, v10, fa02223; CHECK-NEXT:    ret2224entry:2225  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv2f64.nxv2i32.f32.iXLen(iXLen 1, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl)2226  ret void2227}2228 2229define <vscale x 2 x double> @test_sf_vc_fw_fwvf_se_e64m2(<vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl) {2230; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e64m2:2231; CHECK:       # %bb.0: # %entry2232; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma2233; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v10, fa02234; CHECK-NEXT:    ret2235entry:2236  %0 = tail call <vscale x 2 x double> @llvm.riscv.sf.vc.v.fvw.se.nxv2f64.nxv2f32.nxv2i32.f32.iXLen(iXLen 1, <vscale x 2 x double> %vd, <vscale x 2 x i32> %vs2, float %rs1, iXLen %vl)2237  ret <vscale x 2 x double> %02238}2239 2240define void @test_sf_vc_fwvf_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl) {2241; CHECK-LABEL: test_sf_vc_fwvf_se_e64m4:2242; CHECK:       # %bb.0: # %entry2243; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma2244; CHECK-NEXT:    sf.vc.fvw 1, v8, v12, fa02245; CHECK-NEXT:    ret2246entry:2247  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv4f64.nxv4i32.f32.iXLen(iXLen 1, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl)2248  ret void2249}2250 2251define <vscale x 4 x double> @test_sf_vc_fw_fwvf_se_e64m4(<vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl) {2252; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e64m4:2253; CHECK:       # %bb.0: # %entry2254; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, ma2255; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v12, fa02256; CHECK-NEXT:    ret2257entry:2258  %0 = tail call <vscale x 4 x double> @llvm.riscv.sf.vc.v.fvw.se.nxv4f64.nxv4f32.nxv4i32.f32.iXLen(iXLen 1, <vscale x 4 x double> %vd, <vscale x 4 x i32> %vs2, float %rs1, iXLen %vl)2259  ret <vscale x 4 x double> %02260}2261 2262define void @test_sf_vc_fwvf_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl) {2263; CHECK-LABEL: test_sf_vc_fwvf_se_e64m8:2264; CHECK:       # %bb.0: # %entry2265; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma2266; CHECK-NEXT:    sf.vc.fvw 1, v8, v16, fa02267; CHECK-NEXT:    ret2268entry:2269  tail call void @llvm.riscv.sf.vc.fvw.se.iXLen.nxv8f64.nxv8i32.f32.iXLen(iXLen 1, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl)2270  ret void2271}2272 2273define <vscale x 8 x double> @test_sf_vc_fw_fwvf_se_e64m8(<vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl) {2274; CHECK-LABEL: test_sf_vc_fw_fwvf_se_e64m8:2275; CHECK:       # %bb.0: # %entry2276; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, ma2277; CHECK-NEXT:    sf.vc.v.fvw 1, v8, v16, fa02278; CHECK-NEXT:    ret2279entry:2280  %0 = tail call <vscale x 8 x double> @llvm.riscv.sf.vc.v.fvw.se.nxv8f64.nxv8f32.nxv8i32.f32.iXLen(iXLen 1, <vscale x 8 x double> %vd, <vscale x 8 x i32> %vs2, float %rs1, iXLen %vl)2281  ret <vscale x 8 x double> %02282}2283 2284