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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+xtheadvdot \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+xtheadvdot \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i32> @intrinsic_th_vmaqaus_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv1i32_i8_nxv4i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma11; CHECK-NEXT: th.vmaqaus.vx v8, a0, v912; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.nxv1i32.i8(15 <vscale x 1 x i32> %0,16 i8 %1,17 <vscale x 4 x i8> %2,18 iXLen %3, iXLen 0)19 20 ret <vscale x 1 x i32> %a21}22 23define <vscale x 1 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv1i32_i8_nxv4i8(<vscale x 1 x i32> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv1i32_i8_nxv4i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu27; CHECK-NEXT: th.vmaqaus.vx v8, a0, v9, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i32> @llvm.riscv.th.vmaqaus.mask.nxv1i32.i8(31 <vscale x 1 x i32> %0,32 i8 %1,33 <vscale x 4 x i8> %2,34 <vscale x 4 x i1> %3,35 iXLen %4, iXLen 0)36 37 ret <vscale x 1 x i32> %a38}39 40define <vscale x 2 x i32> @intrinsic_th_vmaqaus_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {41; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv2i32_i8_nxv8i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma44; CHECK-NEXT: th.vmaqaus.vx v8, a0, v945; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.nxv2i32.i8(48 <vscale x 2 x i32> %0,49 i8 %1,50 <vscale x 8 x i8> %2,51 iXLen %3, iXLen 0)52 53 ret <vscale x 2 x i32> %a54}55 56define <vscale x 2 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv2i32_i8_nxv8i8(<vscale x 2 x i32> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv2i32_i8_nxv8i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu60; CHECK-NEXT: th.vmaqaus.vx v8, a0, v9, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i32> @llvm.riscv.th.vmaqaus.mask.nxv2i32.i8(64 <vscale x 2 x i32> %0,65 i8 %1,66 <vscale x 8 x i8> %2,67 <vscale x 8 x i1> %3,68 iXLen %4, iXLen 0)69 70 ret <vscale x 2 x i32> %a71}72 73define <vscale x 4 x i32> @intrinsic_th_vmaqaus_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {74; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv4i32_i8_nxv16i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma77; CHECK-NEXT: th.vmaqaus.vx v8, a0, v1078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.nxv4i32.i8(81 <vscale x 4 x i32> %0,82 i8 %1,83 <vscale x 16 x i8> %2,84 iXLen %3, iXLen 0)85 86 ret <vscale x 4 x i32> %a87}88 89define <vscale x 4 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv4i32_i8_nxv16i8(<vscale x 4 x i32> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv4i32_i8_nxv16i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu93; CHECK-NEXT: th.vmaqaus.vx v8, a0, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i32> @llvm.riscv.th.vmaqaus.mask.nxv4i32.i8(97 <vscale x 4 x i32> %0,98 i8 %1,99 <vscale x 16 x i8> %2,100 <vscale x 16 x i1> %3,101 iXLen %4, iXLen 0)102 103 ret <vscale x 4 x i32> %a104}105 106define <vscale x 8 x i32> @intrinsic_th_vmaqaus_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {107; CHECK-LABEL: intrinsic_th_vmaqaus_vx_nxv8i32_i8_nxv32i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma110; CHECK-NEXT: th.vmaqaus.vx v8, a0, v12111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.nxv8i32.i8(114 <vscale x 8 x i32> %0,115 i8 %1,116 <vscale x 32 x i8> %2,117 iXLen %3, iXLen 0)118 119 ret <vscale x 8 x i32> %a120}121 122define <vscale x 8 x i32> @intrinsic_th_vmaqaus_mask_vx_nxv8i32_i8_nxv32i8(<vscale x 8 x i32> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_th_vmaqaus_mask_vx_nxv8i32_i8_nxv32i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu126; CHECK-NEXT: th.vmaqaus.vx v8, a0, v12, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i32> @llvm.riscv.th.vmaqaus.mask.nxv8i32.i8(130 <vscale x 8 x i32> %0,131 i8 %1,132 <vscale x 32 x i8> %2,133 <vscale x 32 x i1> %3,134 iXLen %4, iXLen 0)135 136 ret <vscale x 8 x i32> %a137}138