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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s4 5; Test that we reverse InstCombinerImpl::transformZExtICmp when unprofitable6 7define <vscale x 1 x i8> @reverse_zexticmp_i16(<vscale x 1 x i16> %x) {8; CHECK-LABEL: reverse_zexticmp_i16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vnsrl.wi v8, v8, 012; CHECK-NEXT: vsrl.vi v8, v8, 213; CHECK-NEXT: vand.vi v8, v8, 114; CHECK-NEXT: ret15 %1 = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>16 %2 = lshr <vscale x 1 x i8> %1, splat (i8 2)17 %3 = and <vscale x 1 x i8> %2, splat (i8 1)18 ret <vscale x 1 x i8> %319}20 21define <vscale x 1 x i8> @reverse_zexticmp_i32(<vscale x 1 x i32> %x) {22; CHECK-LABEL: reverse_zexticmp_i32:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma25; CHECK-NEXT: vand.vi v8, v8, 426; CHECK-NEXT: vmsne.vi v0, v8, 027; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma28; CHECK-NEXT: vmv.v.i v8, 029; CHECK-NEXT: vmerge.vim v8, v8, 1, v030; CHECK-NEXT: ret31 %1 = trunc <vscale x 1 x i32> %x to <vscale x 1 x i8>32 %2 = lshr <vscale x 1 x i8> %1, splat (i8 2)33 %3 = and <vscale x 1 x i8> %2, splat (i8 1)34 ret <vscale x 1 x i8> %335}36 37define <vscale x 1 x i8> @reverse_zexticmp_neg_i32(<vscale x 1 x i32> %x) {38; CHECK-LABEL: reverse_zexticmp_neg_i32:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma41; CHECK-NEXT: vand.vi v8, v8, 442; CHECK-NEXT: vmseq.vi v0, v8, 043; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma44; CHECK-NEXT: vmv.v.i v8, 045; CHECK-NEXT: vmerge.vim v8, v8, 1, v046; CHECK-NEXT: ret47 %1 = trunc <vscale x 1 x i32> %x to <vscale x 1 x i8>48 %2 = xor <vscale x 1 x i8> %1, splat (i8 -1)49 %3 = lshr <vscale x 1 x i8> %2, splat (i8 2)50 %4 = and <vscale x 1 x i8> %3, splat (i8 1)51 ret <vscale x 1 x i8> %452}53 54define <vscale x 1 x i8> @reverse_zexticmp_i64(<vscale x 1 x i64> %x) {55; CHECK-LABEL: reverse_zexticmp_i64:56; CHECK: # %bb.0:57; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma58; CHECK-NEXT: vand.vi v8, v8, 459; CHECK-NEXT: vmsne.vi v0, v8, 060; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma61; CHECK-NEXT: vmv.v.i v8, 062; CHECK-NEXT: vmerge.vim v8, v8, 1, v063; CHECK-NEXT: ret64 %1 = trunc <vscale x 1 x i64> %x to <vscale x 1 x i8>65 %2 = lshr <vscale x 1 x i8> %1, splat (i8 2)66 %3 = and <vscale x 1 x i8> %2, splat (i8 1)67 ret <vscale x 1 x i8> %368}69 70define <vscale x 1 x i8> @reverse_zexticmp_neg_i64(<vscale x 1 x i64> %x) {71; CHECK-LABEL: reverse_zexticmp_neg_i64:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma74; CHECK-NEXT: vand.vi v8, v8, 475; CHECK-NEXT: vmseq.vi v0, v8, 076; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma77; CHECK-NEXT: vmv.v.i v8, 078; CHECK-NEXT: vmerge.vim v8, v8, 1, v079; CHECK-NEXT: ret80 %1 = trunc <vscale x 1 x i64> %x to <vscale x 1 x i8>81 %2 = xor <vscale x 1 x i8> %1, splat (i8 -1)82 %3 = lshr <vscale x 1 x i8> %2, splat (i8 2)83 %4 = and <vscale x 1 x i8> %3, splat (i8 1)84 ret <vscale x 1 x i8> %485}86 87