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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+prefer-w-inst \3; RUN: -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {6; CHECK-LABEL: vrol_vx_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: addiw a0, a0, 19; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma10; CHECK-NEXT: vrol.vx v8, v8, a011; CHECK-NEXT: ret12 %s = add i8 %b, 113 %b.head = insertelement <vscale x 1 x i8> poison, i8 %s, i32 014 %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer15 %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)16 ret <vscale x 1 x i8> %x17}18 19define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {20; CHECK-LABEL: vror_vx_nxv1i8:21; CHECK: # %bb.0:22; CHECK-NEXT: addiw a0, a0, 123; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma24; CHECK-NEXT: vror.vx v8, v8, a025; CHECK-NEXT: ret26 %s = add i8 %b, 127 %b.head = insertelement <vscale x 1 x i8> poison, i8 %s, i32 028 %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer29 %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)30 ret <vscale x 1 x i8> %x31}32 33define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b) {34; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma37; CHECK-NEXT: vmv1r.v v10, v838; CHECK-NEXT: addiw a0, a0, 139; CHECK-NEXT: vwsll.vx v8, v10, a040; CHECK-NEXT: ret41 %s = add i8 %b, 142 %head = insertelement <vscale x 2 x i8> poison, i8 %s, i32 043 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer44 %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>45 %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>46 %z = shl <vscale x 2 x i64> %x, %y47 ret <vscale x 2 x i64> %z48}49 50define <vscale x 1 x i8> @vandn_vx_nxv1i8(i8 %x, <vscale x 1 x i8> %y) {51; CHECK-LABEL: vandn_vx_nxv1i8:52; CHECK: # %bb.0:53; CHECK-NEXT: addiw a0, a0, 154; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma55; CHECK-NEXT: vandn.vx v8, v8, a056; CHECK-NEXT: ret57 %s = add i8 %x, 158 %a = xor i8 %s, -159 %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 060 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer61 %b = and <vscale x 1 x i8> %splat, %y62 ret <vscale x 1 x i8> %b63}64