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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple riscv64 -mattr=+v -verify-machineinstrs -run-pass=postrapseudos %s -o - | FileCheck %s3 4...5---6name: copy_zvlsseg_N27body: |8 bb.0:9 ; CHECK-LABEL: name: copy_zvlsseg_N210 ; CHECK: $v2m2 = VMV2R_V $v4m211 ; CHECK-NEXT: $v3 = VMV1R_V $v412 ; CHECK-NEXT: $v4 = VMV1R_V $v513 ; CHECK-NEXT: $v6 = VMV1R_V $v514 ; CHECK-NEXT: $v5 = VMV1R_V $v415 ; CHECK-NEXT: $v6m2 = VMV2R_V $v4m216 ; CHECK-NEXT: $v0m4 = VMV4R_V $v4m417 ; CHECK-NEXT: $v2m2 = VMV2R_V $v4m218 ; CHECK-NEXT: $v4m2 = VMV2R_V $v6m219 ; CHECK-NEXT: $v8m2 = VMV2R_V $v6m220 ; CHECK-NEXT: $v6m2 = VMV2R_V $v4m221 ; CHECK-NEXT: $v8m4 = VMV4R_V $v4m422 ; CHECK-NEXT: $v0m8 = VMV8R_V $v8m823 ; CHECK-NEXT: $v4m4 = VMV4R_V $v8m424 ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m425 ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m426 ; CHECK-NEXT: $v12m4 = VMV4R_V $v8m427 ; CHECK-NEXT: $v16m8 = VMV8R_V $v8m828 $v2_v3 = COPY $v4_v529 $v3_v4 = COPY $v4_v530 $v5_v6 = COPY $v4_v531 $v6_v7 = COPY $v4_v532 33 $v0m2_v2m2 = COPY $v4m2_v6m234 $v2m2_v4m2 = COPY $v4m2_v6m235 $v6m2_v8m2 = COPY $v4m2_v6m236 $v8m2_v10m2 = COPY $v4m2_v6m237 38 $v0m4_v4m4 = COPY $v8m4_v12m439 $v4m4_v8m4 = COPY $v8m4_v12m440 $v12m4_v16m4 = COPY $v8m4_v12m441 $v16m4_v20m4 = COPY $v8m4_v12m442...43---44name: copy_zvlsseg_N345body: |46 bb.0:47 ; CHECK-LABEL: name: copy_zvlsseg_N348 ; CHECK: $v2 = VMV1R_V $v549 ; CHECK-NEXT: $v3 = VMV1R_V $v650 ; CHECK-NEXT: $v4 = VMV1R_V $v751 ; CHECK-NEXT: $v3 = VMV1R_V $v552 ; CHECK-NEXT: $v4m2 = VMV2R_V $v6m253 ; CHECK-NEXT: $v4 = VMV1R_V $v554 ; CHECK-NEXT: $v5 = VMV1R_V $v655 ; CHECK-NEXT: $v6 = VMV1R_V $v756 ; CHECK-NEXT: $v8m2 = VMV2R_V $v6m257 ; CHECK-NEXT: $v7 = VMV1R_V $v558 ; CHECK-NEXT: $v9 = VMV1R_V $v559 ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m260 ; CHECK-NEXT: $v0m2 = VMV2R_V $v6m261 ; CHECK-NEXT: $v2m2 = VMV2R_V $v8m262 ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m263 ; CHECK-NEXT: $v2m2 = VMV2R_V $v6m264 ; CHECK-NEXT: $v4m4 = VMV4R_V $v8m465 ; CHECK-NEXT: $v12m4 = VMV4R_V $v8m466 ; CHECK-NEXT: $v10m2 = VMV2R_V $v6m267 ; CHECK-NEXT: $v12m2 = VMV2R_V $v6m268 ; CHECK-NEXT: $v14m2 = VMV2R_V $v8m269 ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m270 $v2_v3_v4 = COPY $v5_v6_v771 $v3_v4_v5 = COPY $v5_v6_v772 $v4_v5_v6 = COPY $v5_v6_v773 $v7_v8_v9 = COPY $v5_v6_v774 $v9_v10_v11 = COPY $v5_v6_v775 76 $v0m2_v2m2_v4m2 = COPY $v6m2_v8m2_v10m277 $v2m2_v4m2_v6m2 = COPY $v6m2_v8m2_v10m278 $v10m2_v12m2_v14m2 = COPY $v6m2_v8m2_v10m279 $v12m2_v14m2_v16m2 = COPY $v6m2_v8m2_v10m280...81---82name: copy_zvlsseg_N483body: |84 bb.0:85 ; CHECK-LABEL: name: copy_zvlsseg_N486 ; CHECK: $v6m2 = VMV2R_V $v10m287 ; CHECK-NEXT: $v8m2 = VMV2R_V $v12m288 ; CHECK-NEXT: $v7 = VMV1R_V $v1089 ; CHECK-NEXT: $v8 = VMV1R_V $v1190 ; CHECK-NEXT: $v9 = VMV1R_V $v1291 ; CHECK-NEXT: $v10 = VMV1R_V $v1392 ; CHECK-NEXT: $v16 = VMV1R_V $v1393 ; CHECK-NEXT: $v15 = VMV1R_V $v1294 ; CHECK-NEXT: $v14 = VMV1R_V $v1195 ; CHECK-NEXT: $v13 = VMV1R_V $v1096 ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m297 ; CHECK-NEXT: $v16m2 = VMV2R_V $v12m298 ; CHECK-NEXT: $v2m2 = VMV2R_V $v10m299 ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4100 ; CHECK-NEXT: $v8m2 = VMV2R_V $v16m2101 ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2102 ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2103 ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2104 ; CHECK-NEXT: $v10m2 = VMV2R_V $v16m2105 ; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2106 ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2107 ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2108 ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2109 ; CHECK-NEXT: $v18m2 = VMV2R_V $v10m2110 ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4111 ; CHECK-NEXT: $v24m2 = VMV2R_V $v16m2112 $v6_v7_v8_v9 = COPY $v10_v11_v12_v13113 $v7_v8_v9_v10 = COPY $v10_v11_v12_v13114 $v13_v14_v15_v16 = COPY $v10_v11_v12_v13115 $v14_v15_v16_v17 = COPY $v10_v11_v12_v13116 117 $v2m2_v4m2_v6m2_v8m2 = COPY $v10m2_v12m2_v14m2_v16m2118 $v4m2_v6m2_v8m2_v10m2 = COPY $v10m2_v12m2_v14m2_v16m2119 $v16m2_v18m2_v20m2_v22m2 = COPY $v10m2_v12m2_v14m2_v16m2120 $v18m2_v20m2_v22m2_v24m2 = COPY $v10m2_v12m2_v14m2_v16m2121...122---123name: copy_zvlsseg_N5124body: |125 bb.0:126 ; CHECK-LABEL: name: copy_zvlsseg_N5127 ; CHECK: $v5 = VMV1R_V $v10128 ; CHECK-NEXT: $v6 = VMV1R_V $v11129 ; CHECK-NEXT: $v7 = VMV1R_V $v12130 ; CHECK-NEXT: $v8 = VMV1R_V $v13131 ; CHECK-NEXT: $v9 = VMV1R_V $v14132 ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2133 ; CHECK-NEXT: $v8m2 = VMV2R_V $v12m2134 ; CHECK-NEXT: $v10 = VMV1R_V $v14135 ; CHECK-NEXT: $v18 = VMV1R_V $v14136 ; CHECK-NEXT: $v16m2 = VMV2R_V $v12m2137 ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2138 ; CHECK-NEXT: $v15 = VMV1R_V $v10139 ; CHECK-NEXT: $v16 = VMV1R_V $v11140 ; CHECK-NEXT: $v17 = VMV1R_V $v12141 ; CHECK-NEXT: $v18 = VMV1R_V $v13142 ; CHECK-NEXT: $v19 = VMV1R_V $v14143 ; CHECK-NEXT: $v7 = VMV1R_V $v11144 ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4145 ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4146 ; CHECK-NEXT: $v15 = VMV1R_V $v11147 $v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14148 $v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14149 $v14_v15_v16_v17_v18 = COPY $v10_v11_v12_v13_v14150 $v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14151 $v7_v8_v9_v10_v11 = COPY $v11_v12_v13_v14_v15152 $v15_v16_v17_v18_v19 = COPY $v11_v12_v13_v14_v15153...154---155name: copy_zvlsseg_N6156body: |157 bb.0:158 ; CHECK-LABEL: name: copy_zvlsseg_N6159 ; CHECK: $v4m2 = VMV2R_V $v10m2160 ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2161 ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2162 ; CHECK-NEXT: $v5 = VMV1R_V $v10163 ; CHECK-NEXT: $v6 = VMV1R_V $v11164 ; CHECK-NEXT: $v7 = VMV1R_V $v12165 ; CHECK-NEXT: $v8 = VMV1R_V $v13166 ; CHECK-NEXT: $v9 = VMV1R_V $v14167 ; CHECK-NEXT: $v10 = VMV1R_V $v15168 ; CHECK-NEXT: $v6m2 = VMV2R_V $v10m2169 ; CHECK-NEXT: $v8m4 = VMV4R_V $v12m4170 ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4171 ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2172 ; CHECK-NEXT: $v20 = VMV1R_V $v15173 ; CHECK-NEXT: $v19 = VMV1R_V $v14174 ; CHECK-NEXT: $v18 = VMV1R_V $v13175 ; CHECK-NEXT: $v17 = VMV1R_V $v12176 ; CHECK-NEXT: $v16 = VMV1R_V $v11177 ; CHECK-NEXT: $v15 = VMV1R_V $v10178 ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2179 ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2180 ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2181 $v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15182 $v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15183 $v6_v7_v8_v9_v10_v11 = COPY $v10_v11_v12_v13_v14_v15184 $v14_v15_v16_v17_v18_v19 = COPY $v10_v11_v12_v13_v14_v15185 $v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15186 $v16_v17_v18_v19_v20_v21 = COPY $v10_v11_v12_v13_v14_v15187...188---189name: copy_zvlsseg_N7190body: |191 bb.0:192 ; CHECK-LABEL: name: copy_zvlsseg_N7193 ; CHECK: $v3 = VMV1R_V $v10194 ; CHECK-NEXT: $v4 = VMV1R_V $v11195 ; CHECK-NEXT: $v5 = VMV1R_V $v12196 ; CHECK-NEXT: $v6 = VMV1R_V $v13197 ; CHECK-NEXT: $v7 = VMV1R_V $v14198 ; CHECK-NEXT: $v8 = VMV1R_V $v15199 ; CHECK-NEXT: $v9 = VMV1R_V $v16200 ; CHECK-NEXT: $v4m2 = VMV2R_V $v10m2201 ; CHECK-NEXT: $v6m2 = VMV2R_V $v12m2202 ; CHECK-NEXT: $v8m2 = VMV2R_V $v14m2203 ; CHECK-NEXT: $v10 = VMV1R_V $v16204 ; CHECK-NEXT: $v20 = VMV1R_V $v16205 ; CHECK-NEXT: $v16m4 = VMV4R_V $v12m4206 ; CHECK-NEXT: $v14m2 = VMV2R_V $v10m2207 ; CHECK-NEXT: $v22 = VMV1R_V $v16208 ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2209 ; CHECK-NEXT: $v18m2 = VMV2R_V $v12m2210 ; CHECK-NEXT: $v16m2 = VMV2R_V $v10m2211 ; CHECK-NEXT: $v17 = VMV1R_V $v10212 ; CHECK-NEXT: $v18 = VMV1R_V $v11213 ; CHECK-NEXT: $v19 = VMV1R_V $v12214 ; CHECK-NEXT: $v20 = VMV1R_V $v13215 ; CHECK-NEXT: $v21 = VMV1R_V $v14216 ; CHECK-NEXT: $v22 = VMV1R_V $v15217 ; CHECK-NEXT: $v23 = VMV1R_V $v16218 ; CHECK-NEXT: $v22 = VMV1R_V $v21219 ; CHECK-NEXT: $v21 = VMV1R_V $v20220 ; CHECK-NEXT: $v20 = VMV1R_V $v19221 ; CHECK-NEXT: $v19 = VMV1R_V $v18222 ; CHECK-NEXT: $v18 = VMV1R_V $v17223 ; CHECK-NEXT: $v17 = VMV1R_V $v16224 ; CHECK-NEXT: $v16 = VMV1R_V $v15225 $v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16226 $v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16227 $v14_v15_v16_v17_v18_v19_v20 = COPY $v10_v11_v12_v13_v14_v15_v16228 $v16_v17_v18_v19_v20_v21_v22 = COPY $v10_v11_v12_v13_v14_v15_v16229 $v17_v18_v19_v20_v21_v22_v23 = COPY $v10_v11_v12_v13_v14_v15_v16230 $v16_v17_v18_v19_v20_v21_v22 = COPY $v15_v16_v17_v18_v19_v20_v21231...232---233name: copy_zvlsseg_N8234body: |235 bb.0:236 ; CHECK-LABEL: name: copy_zvlsseg_N8237 ; CHECK: $v2m2 = VMV2R_V $v10m2238 ; CHECK-NEXT: $v4m4 = VMV4R_V $v12m4239 ; CHECK-NEXT: $v8m2 = VMV2R_V $v16m2240 ; CHECK-NEXT: $v3 = VMV1R_V $v10241 ; CHECK-NEXT: $v4 = VMV1R_V $v11242 ; CHECK-NEXT: $v5 = VMV1R_V $v12243 ; CHECK-NEXT: $v6 = VMV1R_V $v13244 ; CHECK-NEXT: $v7 = VMV1R_V $v14245 ; CHECK-NEXT: $v8 = VMV1R_V $v15246 ; CHECK-NEXT: $v9 = VMV1R_V $v16247 ; CHECK-NEXT: $v10 = VMV1R_V $v17248 ; CHECK-NEXT: $v24 = VMV1R_V $v17249 ; CHECK-NEXT: $v23 = VMV1R_V $v16250 ; CHECK-NEXT: $v22 = VMV1R_V $v15251 ; CHECK-NEXT: $v21 = VMV1R_V $v14252 ; CHECK-NEXT: $v20 = VMV1R_V $v13253 ; CHECK-NEXT: $v19 = VMV1R_V $v12254 ; CHECK-NEXT: $v18 = VMV1R_V $v11255 ; CHECK-NEXT: $v17 = VMV1R_V $v10256 ; CHECK-NEXT: $v18m2 = VMV2R_V $v10m2257 ; CHECK-NEXT: $v20m4 = VMV4R_V $v12m4258 ; CHECK-NEXT: $v24m2 = VMV2R_V $v16m2259 ; CHECK-NEXT: $v8m8 = VMV8R_V $v0m8260 ; CHECK-NEXT: $v0m8 = VMV8R_V $v8m8261 $v2_v3_v4_v5_v6_v7_v8_v9 = COPY $v10_v11_v12_v13_v14_v15_v16_v17262 $v3_v4_v5_v6_v7_v8_v9_v10 = COPY $v10_v11_v12_v13_v14_v15_v16_v17263 $v17_v18_v19_v20_v21_v22_v23_v24 = COPY $v10_v11_v12_v13_v14_v15_v16_v17264 $v18_v19_v20_v21_v22_v23_v24_v25 = COPY $v10_v11_v12_v13_v14_v15_v16_v17265 $v8_v9_v10_v11_v12_v13_v14_v15 = COPY $v0_v1_v2_v3_v4_v5_v6_v7266 $v0_v1_v2_v3_v4_v5_v6_v7 = COPY $v8_v9_v10_v11_v12_v13_v14_v15267...268