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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+zve32x \3; RUN: -verify-machineinstrs < %s | FileCheck %s4 5; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use6; for these intrinsics.7 8define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(ptr %base, <vscale x 16 x i1> %mask) {9; CHECK-LABEL: test_vlseg2_mask_nxv16i16:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma12; CHECK-NEXT: vlseg2e16.v v4, (a0)13; CHECK-NEXT: ret14entry:15 %0 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, i64 0, i64 4)16 %1 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlseg2.mask.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %base, <vscale x 16 x i1> %mask, i64 0, i64 1, i64 4)17 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, i32 1)18 ret <vscale x 16 x i16> %219}20 21define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(ptr %base, i64 %offset, <vscale x 16 x i1> %mask) {22; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu25; CHECK-NEXT: vlsseg2e16.v v4, (a0), a126; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t27; CHECK-NEXT: ret28entry:29 %0 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, i64 %offset, i64 0, i64 4)30 %1 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0, i64 1, i64 4)31 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, i32 1)32 ret <vscale x 16 x i16> %233}34 35define <vscale x 16 x i16> @test_vloxseg2_mask_nxv16i16_nxv16i16(ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {36; CHECK-LABEL: test_vloxseg2_mask_nxv16i16_nxv16i16:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu39; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v840; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8, v0.t41; CHECK-NEXT: vmv4r.v v8, v1642; CHECK-NEXT: ret43entry:44 %0 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, <vscale x 16 x i16> %index, i64 0, i64 4)45 %1 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0, i64 1, i64 4)46 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, i32 1)47 ret <vscale x 16 x i16> %248}49 50define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i16(ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {51; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i16:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu54; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v855; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8, v0.t56; CHECK-NEXT: vmv4r.v v8, v1657; CHECK-NEXT: ret58entry:59 %0 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, <vscale x 16 x i16> %index, i64 0, i64 4)60 %1 = tail call target("riscv.vector.tuple", <vscale x 32 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %0, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0, i64 1, i64 4)61 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, i32 1)62 ret <vscale x 16 x i16> %263}64 65define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(ptr %base, ptr %outvl) {66; CHECK-LABEL: test_vlseg2ff_nxv16i16:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma69; CHECK-NEXT: vlseg2e16ff.v v8, (a0)70; CHECK-NEXT: csrr a0, vl71; CHECK-NEXT: sd a0, 0(a1)72; CHECK-NEXT: ret73entry:74 %0 = tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) poison, ptr %base, i64 0, i64 4)75 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64} %0, 076 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, i32 0)77 %3 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64} %0, 178 store i64 %3, ptr %outvl79 ret <vscale x 16 x i16> %280}81 82define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, ptr %outvl) {83; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, mu86; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t87; CHECK-NEXT: csrr a0, vl88; CHECK-NEXT: sd a0, 0(a1)89; CHECK-NEXT: ret90entry:91 %0 = tail call {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64} @llvm.riscv.vlseg2ff.mask.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i64 0, i64 1, i64 4)92 %1 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64} %0, 093 %2 = call <vscale x 16 x i16> @llvm.riscv.tuple.extract.nxv16i16.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %1, i32 0)94 %3 = extractvalue {target("riscv.vector.tuple", <vscale x 32 x i8>, 2), i64} %0, 195 store i64 %3, ptr %outvl96 ret <vscale x 16 x i16> %297}98 99define void @test_vsseg2_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base) {100; CHECK-LABEL: test_vsseg2_nxv16i16:101; CHECK: # %bb.0: # %entry102; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma103; CHECK-NEXT: vsseg2e16.v v8, (a0)104; CHECK-NEXT: ret105entry:106 tail call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i64 0, i64 4)107 ret void108}109 110define void @test_vsseg2_mask_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask) {111; CHECK-LABEL: test_vsseg2_mask_nxv16i16:112; CHECK: # %bb.0: # %entry113; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma114; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t115; CHECK-NEXT: ret116entry:117 tail call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i1> %mask, i64 0, i64 4)118 ret void119}120 121define void @test_vssseg2_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i64 %offset) {122; CHECK-LABEL: test_vssseg2_nxv16i16:123; CHECK: # %bb.0: # %entry124; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma125; CHECK-NEXT: vssseg2e16.v v8, (a0), a1126; CHECK-NEXT: ret127entry:128 tail call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i64 %offset, i64 0, i64 4)129 ret void130}131 132define void @test_vssseg2_mask_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i64 %offset, <vscale x 16 x i1> %mask) {133; CHECK-LABEL: test_vssseg2_mask_nxv16i16:134; CHECK: # %bb.0: # %entry135; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma136; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t137; CHECK-NEXT: ret138entry:139 tail call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0, i64 4)140 ret void141}142 143define void @test_vsoxseg2_nxv16i16_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index) {144; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma147; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16148; CHECK-NEXT: ret149entry:150 tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 0, i64 4)151 ret void152}153 154define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {155; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:156; CHECK: # %bb.0: # %entry157; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma158; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v16, v0.t159; CHECK-NEXT: ret160entry:161 tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0, i64 4)162 ret void163}164 165define void @test_vsuxseg2_nxv16i16_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index) {166; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:167; CHECK: # %bb.0: # %entry168; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma169; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16170; CHECK-NEXT: ret171entry:172 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, i64 0, i64 4)173 ret void174}175 176define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {177; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:178; CHECK: # %bb.0: # %entry179; CHECK-NEXT: vsetivli zero, 0, e16, m4, ta, ma180; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v16, v0.t181; CHECK-NEXT: ret182entry:183 tail call void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv32i8_2t.nxv16i16(target("riscv.vector.tuple", <vscale x 32 x i8>, 2) %val, ptr %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0, i64 4)184 ret void185}186