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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32,RV32I3; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64,RV64I4; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32,RV32IZbb5; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64,RV64IZbb6 7define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {8; RV32-LABEL: func:9; RV32: # %bb.0:10; RV32-NEXT: mv a2, a011; RV32-NEXT: add a0, a0, a112; RV32-NEXT: slt a2, a0, a213; RV32-NEXT: srli a1, a1, 3114; RV32-NEXT: beq a1, a2, .LBB0_215; RV32-NEXT: # %bb.1:16; RV32-NEXT: srai a0, a0, 3117; RV32-NEXT: lui a1, 52428818; RV32-NEXT: xor a0, a0, a119; RV32-NEXT: .LBB0_2:20; RV32-NEXT: ret21;22; RV64I-LABEL: func:23; RV64I: # %bb.0:24; RV64I-NEXT: add a2, a0, a125; RV64I-NEXT: addw a0, a0, a126; RV64I-NEXT: beq a0, a2, .LBB0_227; RV64I-NEXT: # %bb.1:28; RV64I-NEXT: srli a0, a0, 3129; RV64I-NEXT: li a1, 130; RV64I-NEXT: slli a1, a1, 3131; RV64I-NEXT: xor a2, a0, a132; RV64I-NEXT: .LBB0_2:33; RV64I-NEXT: sext.w a0, a234; RV64I-NEXT: ret35;36; RV64IZbb-LABEL: func:37; RV64IZbb: # %bb.0:38; RV64IZbb-NEXT: add a0, a0, a139; RV64IZbb-NEXT: lui a1, 52428840; RV64IZbb-NEXT: addiw a2, a1, -141; RV64IZbb-NEXT: min a0, a0, a242; RV64IZbb-NEXT: max a0, a0, a143; RV64IZbb-NEXT: ret44 %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);45 ret i32 %tmp;46}47 48define i64 @func2(i64 %x, i64 %y) nounwind {49; RV32I-LABEL: func2:50; RV32I: # %bb.0:51; RV32I-NEXT: mv a4, a152; RV32I-NEXT: mv a1, a053; RV32I-NEXT: add a5, a4, a354; RV32I-NEXT: add a0, a0, a255; RV32I-NEXT: xor a3, a4, a356; RV32I-NEXT: sltu a1, a0, a157; RV32I-NEXT: add a1, a5, a158; RV32I-NEXT: xor a4, a4, a159; RV32I-NEXT: not a2, a360; RV32I-NEXT: and a2, a2, a461; RV32I-NEXT: bgez a2, .LBB1_262; RV32I-NEXT: # %bb.1:63; RV32I-NEXT: srai a0, a1, 3164; RV32I-NEXT: lui a1, 52428865; RV32I-NEXT: xor a1, a0, a166; RV32I-NEXT: .LBB1_2:67; RV32I-NEXT: ret68;69; RV64-LABEL: func2:70; RV64: # %bb.0:71; RV64-NEXT: mv a2, a072; RV64-NEXT: add a0, a0, a173; RV64-NEXT: slt a2, a0, a274; RV64-NEXT: srli a1, a1, 6375; RV64-NEXT: beq a1, a2, .LBB1_276; RV64-NEXT: # %bb.1:77; RV64-NEXT: srai a0, a0, 6378; RV64-NEXT: li a1, -179; RV64-NEXT: slli a1, a1, 6380; RV64-NEXT: xor a0, a0, a181; RV64-NEXT: .LBB1_2:82; RV64-NEXT: ret83;84; RV32IZbb-LABEL: func2:85; RV32IZbb: # %bb.0:86; RV32IZbb-NEXT: mv a4, a187; RV32IZbb-NEXT: mv a1, a088; RV32IZbb-NEXT: add a5, a4, a389; RV32IZbb-NEXT: add a0, a0, a290; RV32IZbb-NEXT: sltu a1, a0, a191; RV32IZbb-NEXT: add a1, a5, a192; RV32IZbb-NEXT: xor a2, a4, a193; RV32IZbb-NEXT: xor a3, a4, a394; RV32IZbb-NEXT: andn a2, a2, a395; RV32IZbb-NEXT: bgez a2, .LBB1_296; RV32IZbb-NEXT: # %bb.1:97; RV32IZbb-NEXT: srai a0, a1, 3198; RV32IZbb-NEXT: lui a1, 52428899; RV32IZbb-NEXT: xor a1, a0, a1100; RV32IZbb-NEXT: .LBB1_2:101; RV32IZbb-NEXT: ret102 %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);103 ret i64 %tmp;104}105 106define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {107; RV32I-LABEL: func16:108; RV32I: # %bb.0:109; RV32I-NEXT: add a0, a0, a1110; RV32I-NEXT: lui a1, 8111; RV32I-NEXT: addi a1, a1, -1112; RV32I-NEXT: bge a0, a1, .LBB2_3113; RV32I-NEXT: # %bb.1:114; RV32I-NEXT: lui a1, 1048568115; RV32I-NEXT: bge a1, a0, .LBB2_4116; RV32I-NEXT: .LBB2_2:117; RV32I-NEXT: ret118; RV32I-NEXT: .LBB2_3:119; RV32I-NEXT: mv a0, a1120; RV32I-NEXT: lui a1, 1048568121; RV32I-NEXT: blt a1, a0, .LBB2_2122; RV32I-NEXT: .LBB2_4:123; RV32I-NEXT: lui a0, 1048568124; RV32I-NEXT: ret125;126; RV64I-LABEL: func16:127; RV64I: # %bb.0:128; RV64I-NEXT: add a0, a0, a1129; RV64I-NEXT: lui a1, 8130; RV64I-NEXT: addi a1, a1, -1131; RV64I-NEXT: bge a0, a1, .LBB2_3132; RV64I-NEXT: # %bb.1:133; RV64I-NEXT: lui a1, 1048568134; RV64I-NEXT: bge a1, a0, .LBB2_4135; RV64I-NEXT: .LBB2_2:136; RV64I-NEXT: ret137; RV64I-NEXT: .LBB2_3:138; RV64I-NEXT: mv a0, a1139; RV64I-NEXT: lui a1, 1048568140; RV64I-NEXT: blt a1, a0, .LBB2_2141; RV64I-NEXT: .LBB2_4:142; RV64I-NEXT: lui a0, 1048568143; RV64I-NEXT: ret144;145; RV32IZbb-LABEL: func16:146; RV32IZbb: # %bb.0:147; RV32IZbb-NEXT: add a0, a0, a1148; RV32IZbb-NEXT: lui a1, 8149; RV32IZbb-NEXT: addi a1, a1, -1150; RV32IZbb-NEXT: min a0, a0, a1151; RV32IZbb-NEXT: lui a1, 1048568152; RV32IZbb-NEXT: max a0, a0, a1153; RV32IZbb-NEXT: ret154;155; RV64IZbb-LABEL: func16:156; RV64IZbb: # %bb.0:157; RV64IZbb-NEXT: add a0, a0, a1158; RV64IZbb-NEXT: lui a1, 8159; RV64IZbb-NEXT: addi a1, a1, -1160; RV64IZbb-NEXT: min a0, a0, a1161; RV64IZbb-NEXT: lui a1, 1048568162; RV64IZbb-NEXT: max a0, a0, a1163; RV64IZbb-NEXT: ret164 %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);165 ret i16 %tmp;166}167 168define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {169; RV32I-LABEL: func8:170; RV32I: # %bb.0:171; RV32I-NEXT: add a0, a0, a1172; RV32I-NEXT: li a1, 127173; RV32I-NEXT: bge a0, a1, .LBB3_3174; RV32I-NEXT: # %bb.1:175; RV32I-NEXT: li a1, -128176; RV32I-NEXT: bge a1, a0, .LBB3_4177; RV32I-NEXT: .LBB3_2:178; RV32I-NEXT: ret179; RV32I-NEXT: .LBB3_3:180; RV32I-NEXT: li a0, 127181; RV32I-NEXT: li a1, -128182; RV32I-NEXT: blt a1, a0, .LBB3_2183; RV32I-NEXT: .LBB3_4:184; RV32I-NEXT: li a0, -128185; RV32I-NEXT: ret186;187; RV64I-LABEL: func8:188; RV64I: # %bb.0:189; RV64I-NEXT: add a0, a0, a1190; RV64I-NEXT: li a1, 127191; RV64I-NEXT: bge a0, a1, .LBB3_3192; RV64I-NEXT: # %bb.1:193; RV64I-NEXT: li a1, -128194; RV64I-NEXT: bge a1, a0, .LBB3_4195; RV64I-NEXT: .LBB3_2:196; RV64I-NEXT: ret197; RV64I-NEXT: .LBB3_3:198; RV64I-NEXT: li a0, 127199; RV64I-NEXT: li a1, -128200; RV64I-NEXT: blt a1, a0, .LBB3_2201; RV64I-NEXT: .LBB3_4:202; RV64I-NEXT: li a0, -128203; RV64I-NEXT: ret204;205; RV32IZbb-LABEL: func8:206; RV32IZbb: # %bb.0:207; RV32IZbb-NEXT: add a0, a0, a1208; RV32IZbb-NEXT: li a1, 127209; RV32IZbb-NEXT: min a0, a0, a1210; RV32IZbb-NEXT: li a1, -128211; RV32IZbb-NEXT: max a0, a0, a1212; RV32IZbb-NEXT: ret213;214; RV64IZbb-LABEL: func8:215; RV64IZbb: # %bb.0:216; RV64IZbb-NEXT: add a0, a0, a1217; RV64IZbb-NEXT: li a1, 127218; RV64IZbb-NEXT: min a0, a0, a1219; RV64IZbb-NEXT: li a1, -128220; RV64IZbb-NEXT: max a0, a0, a1221; RV64IZbb-NEXT: ret222 %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);223 ret i8 %tmp;224}225 226define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {227; RV32I-LABEL: func3:228; RV32I: # %bb.0:229; RV32I-NEXT: add a0, a0, a1230; RV32I-NEXT: li a1, 7231; RV32I-NEXT: bge a0, a1, .LBB4_3232; RV32I-NEXT: # %bb.1:233; RV32I-NEXT: li a1, -8234; RV32I-NEXT: bge a1, a0, .LBB4_4235; RV32I-NEXT: .LBB4_2:236; RV32I-NEXT: ret237; RV32I-NEXT: .LBB4_3:238; RV32I-NEXT: li a0, 7239; RV32I-NEXT: li a1, -8240; RV32I-NEXT: blt a1, a0, .LBB4_2241; RV32I-NEXT: .LBB4_4:242; RV32I-NEXT: li a0, -8243; RV32I-NEXT: ret244;245; RV64I-LABEL: func3:246; RV64I: # %bb.0:247; RV64I-NEXT: add a0, a0, a1248; RV64I-NEXT: li a1, 7249; RV64I-NEXT: bge a0, a1, .LBB4_3250; RV64I-NEXT: # %bb.1:251; RV64I-NEXT: li a1, -8252; RV64I-NEXT: bge a1, a0, .LBB4_4253; RV64I-NEXT: .LBB4_2:254; RV64I-NEXT: ret255; RV64I-NEXT: .LBB4_3:256; RV64I-NEXT: li a0, 7257; RV64I-NEXT: li a1, -8258; RV64I-NEXT: blt a1, a0, .LBB4_2259; RV64I-NEXT: .LBB4_4:260; RV64I-NEXT: li a0, -8261; RV64I-NEXT: ret262;263; RV32IZbb-LABEL: func3:264; RV32IZbb: # %bb.0:265; RV32IZbb-NEXT: add a0, a0, a1266; RV32IZbb-NEXT: li a1, 7267; RV32IZbb-NEXT: min a0, a0, a1268; RV32IZbb-NEXT: li a1, -8269; RV32IZbb-NEXT: max a0, a0, a1270; RV32IZbb-NEXT: ret271;272; RV64IZbb-LABEL: func3:273; RV64IZbb: # %bb.0:274; RV64IZbb-NEXT: add a0, a0, a1275; RV64IZbb-NEXT: li a1, 7276; RV64IZbb-NEXT: min a0, a0, a1277; RV64IZbb-NEXT: li a1, -8278; RV64IZbb-NEXT: max a0, a0, a1279; RV64IZbb-NEXT: ret280 %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);281 ret i4 %tmp;282}283