225 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefix=RV32I3; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefix=RV64I4 5define i8 @scmp.8.8(i8 signext %x, i8 signext %y) nounwind {6; RV32I-LABEL: scmp.8.8:7; RV32I: # %bb.0:8; RV32I-NEXT: slt a2, a0, a19; RV32I-NEXT: slt a0, a1, a010; RV32I-NEXT: sub a0, a0, a211; RV32I-NEXT: ret12;13; RV64I-LABEL: scmp.8.8:14; RV64I: # %bb.0:15; RV64I-NEXT: slt a2, a0, a116; RV64I-NEXT: slt a0, a1, a017; RV64I-NEXT: sub a0, a0, a218; RV64I-NEXT: ret19 %1 = call i8 @llvm.scmp(i8 %x, i8 %y)20 ret i8 %121}22 23define i8 @scmp.8.16(i16 signext %x, i16 signext %y) nounwind {24; RV32I-LABEL: scmp.8.16:25; RV32I: # %bb.0:26; RV32I-NEXT: slt a2, a0, a127; RV32I-NEXT: slt a0, a1, a028; RV32I-NEXT: sub a0, a0, a229; RV32I-NEXT: ret30;31; RV64I-LABEL: scmp.8.16:32; RV64I: # %bb.0:33; RV64I-NEXT: slt a2, a0, a134; RV64I-NEXT: slt a0, a1, a035; RV64I-NEXT: sub a0, a0, a236; RV64I-NEXT: ret37 %1 = call i8 @llvm.scmp(i16 %x, i16 %y)38 ret i8 %139}40 41define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {42; RV32I-LABEL: scmp.8.32:43; RV32I: # %bb.0:44; RV32I-NEXT: slt a2, a0, a145; RV32I-NEXT: slt a0, a1, a046; RV32I-NEXT: sub a0, a0, a247; RV32I-NEXT: ret48;49; RV64I-LABEL: scmp.8.32:50; RV64I: # %bb.0:51; RV64I-NEXT: sext.w a1, a152; RV64I-NEXT: sext.w a0, a053; RV64I-NEXT: slt a2, a0, a154; RV64I-NEXT: slt a0, a1, a055; RV64I-NEXT: sub a0, a0, a256; RV64I-NEXT: ret57 %1 = call i8 @llvm.scmp(i32 %x, i32 %y)58 ret i8 %159}60 61define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {62; RV32I-LABEL: scmp.8.64:63; RV32I: # %bb.0:64; RV32I-NEXT: beq a1, a3, .LBB3_265; RV32I-NEXT: # %bb.1:66; RV32I-NEXT: slt a4, a1, a367; RV32I-NEXT: slt a0, a3, a168; RV32I-NEXT: sub a0, a0, a469; RV32I-NEXT: ret70; RV32I-NEXT: .LBB3_2:71; RV32I-NEXT: sltu a4, a0, a272; RV32I-NEXT: sltu a0, a2, a073; RV32I-NEXT: sub a0, a0, a474; RV32I-NEXT: ret75;76; RV64I-LABEL: scmp.8.64:77; RV64I: # %bb.0:78; RV64I-NEXT: slt a2, a0, a179; RV64I-NEXT: slt a0, a1, a080; RV64I-NEXT: sub a0, a0, a281; RV64I-NEXT: ret82 %1 = call i8 @llvm.scmp(i64 %x, i64 %y)83 ret i8 %184}85 86define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {87; RV32I-LABEL: scmp.8.128:88; RV32I: # %bb.0:89; RV32I-NEXT: lw a2, 4(a1)90; RV32I-NEXT: lw a4, 8(a1)91; RV32I-NEXT: lw a5, 12(a1)92; RV32I-NEXT: lw a3, 4(a0)93; RV32I-NEXT: lw a6, 12(a0)94; RV32I-NEXT: lw a7, 8(a0)95; RV32I-NEXT: beq a6, a5, .LBB4_296; RV32I-NEXT: # %bb.1:97; RV32I-NEXT: slt t2, a6, a598; RV32I-NEXT: j .LBB4_399; RV32I-NEXT: .LBB4_2:100; RV32I-NEXT: sltu t2, a7, a4101; RV32I-NEXT: .LBB4_3:102; RV32I-NEXT: lw a1, 0(a1)103; RV32I-NEXT: lw t0, 0(a0)104; RV32I-NEXT: beq a3, a2, .LBB4_5105; RV32I-NEXT: # %bb.4:106; RV32I-NEXT: sltu a0, a3, a2107; RV32I-NEXT: j .LBB4_6108; RV32I-NEXT: .LBB4_5:109; RV32I-NEXT: sltu a0, t0, a1110; RV32I-NEXT: .LBB4_6:111; RV32I-NEXT: xor t1, a6, a5112; RV32I-NEXT: xor t3, a7, a4113; RV32I-NEXT: or t1, t3, t1114; RV32I-NEXT: beqz t1, .LBB4_8115; RV32I-NEXT: # %bb.7:116; RV32I-NEXT: mv a0, t2117; RV32I-NEXT: .LBB4_8:118; RV32I-NEXT: beq a6, a5, .LBB4_11119; RV32I-NEXT: # %bb.9:120; RV32I-NEXT: slt a4, a5, a6121; RV32I-NEXT: bne a3, a2, .LBB4_12122; RV32I-NEXT: .LBB4_10:123; RV32I-NEXT: sltu a1, a1, t0124; RV32I-NEXT: bnez t1, .LBB4_13125; RV32I-NEXT: j .LBB4_14126; RV32I-NEXT: .LBB4_11:127; RV32I-NEXT: sltu a4, a4, a7128; RV32I-NEXT: beq a3, a2, .LBB4_10129; RV32I-NEXT: .LBB4_12:130; RV32I-NEXT: sltu a1, a2, a3131; RV32I-NEXT: beqz t1, .LBB4_14132; RV32I-NEXT: .LBB4_13:133; RV32I-NEXT: mv a1, a4134; RV32I-NEXT: .LBB4_14:135; RV32I-NEXT: sub a0, a1, a0136; RV32I-NEXT: ret137;138; RV64I-LABEL: scmp.8.128:139; RV64I: # %bb.0:140; RV64I-NEXT: beq a1, a3, .LBB4_2141; RV64I-NEXT: # %bb.1:142; RV64I-NEXT: slt a4, a1, a3143; RV64I-NEXT: slt a0, a3, a1144; RV64I-NEXT: sub a0, a0, a4145; RV64I-NEXT: ret146; RV64I-NEXT: .LBB4_2:147; RV64I-NEXT: sltu a4, a0, a2148; RV64I-NEXT: sltu a0, a2, a0149; RV64I-NEXT: sub a0, a0, a4150; RV64I-NEXT: ret151 %1 = call i8 @llvm.scmp(i128 %x, i128 %y)152 ret i8 %1153}154 155define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {156; RV32I-LABEL: scmp.32.32:157; RV32I: # %bb.0:158; RV32I-NEXT: slt a2, a0, a1159; RV32I-NEXT: slt a0, a1, a0160; RV32I-NEXT: sub a0, a0, a2161; RV32I-NEXT: ret162;163; RV64I-LABEL: scmp.32.32:164; RV64I: # %bb.0:165; RV64I-NEXT: sext.w a1, a1166; RV64I-NEXT: sext.w a0, a0167; RV64I-NEXT: slt a2, a0, a1168; RV64I-NEXT: slt a0, a1, a0169; RV64I-NEXT: sub a0, a0, a2170; RV64I-NEXT: ret171 %1 = call i32 @llvm.scmp(i32 %x, i32 %y)172 ret i32 %1173}174 175define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {176; RV32I-LABEL: scmp.32.64:177; RV32I: # %bb.0:178; RV32I-NEXT: beq a1, a3, .LBB6_2179; RV32I-NEXT: # %bb.1:180; RV32I-NEXT: slt a4, a1, a3181; RV32I-NEXT: slt a0, a3, a1182; RV32I-NEXT: sub a0, a0, a4183; RV32I-NEXT: ret184; RV32I-NEXT: .LBB6_2:185; RV32I-NEXT: sltu a4, a0, a2186; RV32I-NEXT: sltu a0, a2, a0187; RV32I-NEXT: sub a0, a0, a4188; RV32I-NEXT: ret189;190; RV64I-LABEL: scmp.32.64:191; RV64I: # %bb.0:192; RV64I-NEXT: slt a2, a0, a1193; RV64I-NEXT: slt a0, a1, a0194; RV64I-NEXT: sub a0, a0, a2195; RV64I-NEXT: ret196 %1 = call i32 @llvm.scmp(i64 %x, i64 %y)197 ret i32 %1198}199 200define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {201; RV32I-LABEL: scmp.64.64:202; RV32I: # %bb.0:203; RV32I-NEXT: beq a1, a3, .LBB7_2204; RV32I-NEXT: # %bb.1:205; RV32I-NEXT: slt a4, a1, a3206; RV32I-NEXT: slt a0, a3, a1207; RV32I-NEXT: j .LBB7_3208; RV32I-NEXT: .LBB7_2:209; RV32I-NEXT: sltu a4, a0, a2210; RV32I-NEXT: sltu a0, a2, a0211; RV32I-NEXT: .LBB7_3:212; RV32I-NEXT: sub a0, a0, a4213; RV32I-NEXT: srai a1, a0, 31214; RV32I-NEXT: ret215;216; RV64I-LABEL: scmp.64.64:217; RV64I: # %bb.0:218; RV64I-NEXT: slt a2, a0, a1219; RV64I-NEXT: slt a0, a1, a0220; RV64I-NEXT: sub a0, a0, a2221; RV64I-NEXT: ret222 %1 = call i64 @llvm.scmp(i64 %x, i64 %y)223 ret i64 %1224}225