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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s6; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefixes=RV32IXQCI8 9define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {10; RV32I-LABEL: bare_select:11; RV32I: # %bb.0:12; RV32I-NEXT: andi a3, a0, 113; RV32I-NEXT: mv a0, a114; RV32I-NEXT: bnez a3, .LBB0_215; RV32I-NEXT: # %bb.1:16; RV32I-NEXT: mv a0, a217; RV32I-NEXT: .LBB0_2:18; RV32I-NEXT: ret19;20; RV64I-CCMOV-LABEL: bare_select:21; RV64I-CCMOV: # %bb.0:22; RV64I-CCMOV-NEXT: andi a0, a0, 123; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a224; RV64I-CCMOV-NEXT: ret25;26; RV32IXQCI-LABEL: bare_select:27; RV32IXQCI: # %bb.0:28; RV32IXQCI-NEXT: andi a0, a0, 129; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a230; RV32IXQCI-NEXT: mv a0, a131; RV32IXQCI-NEXT: ret32 %1 = select i1 %a, i32 %b, i32 %c33 ret i32 %134}35 36define float @bare_select_float(i1 %a, float %b, float %c) nounwind {37; RV32I-LABEL: bare_select_float:38; RV32I: # %bb.0:39; RV32I-NEXT: andi a3, a0, 140; RV32I-NEXT: mv a0, a141; RV32I-NEXT: bnez a3, .LBB1_242; RV32I-NEXT: # %bb.1:43; RV32I-NEXT: mv a0, a244; RV32I-NEXT: .LBB1_2:45; RV32I-NEXT: ret46;47; RV64I-CCMOV-LABEL: bare_select_float:48; RV64I-CCMOV: # %bb.0:49; RV64I-CCMOV-NEXT: andi a0, a0, 150; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a251; RV64I-CCMOV-NEXT: ret52;53; RV32IXQCI-LABEL: bare_select_float:54; RV32IXQCI: # %bb.0:55; RV32IXQCI-NEXT: andi a0, a0, 156; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a257; RV32IXQCI-NEXT: mv a0, a158; RV32IXQCI-NEXT: ret59 %1 = select i1 %a, float %b, float %c60 ret float %161}62