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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefixes=RV32I %s4; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=RV32IXQCI6; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \7; RUN: | FileCheck -check-prefixes=RV64I %s8; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \9; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s10 11define signext i32 @foo(i32 signext %a, ptr %b) nounwind {12; RV32I-LABEL: foo:13; RV32I: # %bb.0:14; RV32I-NEXT: lw a2, 0(a1)15; RV32I-NEXT: beq a0, a2, .LBB0_216; RV32I-NEXT: # %bb.1:17; RV32I-NEXT: mv a0, a218; RV32I-NEXT: .LBB0_2:19; RV32I-NEXT: lw a2, 0(a1)20; RV32I-NEXT: bne a0, a2, .LBB0_421; RV32I-NEXT: # %bb.3:22; RV32I-NEXT: mv a0, a223; RV32I-NEXT: .LBB0_4:24; RV32I-NEXT: lw a2, 0(a1)25; RV32I-NEXT: bltu a2, a0, .LBB0_626; RV32I-NEXT: # %bb.5:27; RV32I-NEXT: mv a0, a228; RV32I-NEXT: .LBB0_6:29; RV32I-NEXT: lw a2, 0(a1)30; RV32I-NEXT: bgeu a0, a2, .LBB0_831; RV32I-NEXT: # %bb.7:32; RV32I-NEXT: mv a0, a233; RV32I-NEXT: .LBB0_8:34; RV32I-NEXT: lw a2, 0(a1)35; RV32I-NEXT: bltu a0, a2, .LBB0_1036; RV32I-NEXT: # %bb.9:37; RV32I-NEXT: mv a0, a238; RV32I-NEXT: .LBB0_10:39; RV32I-NEXT: lw a2, 0(a1)40; RV32I-NEXT: bgeu a2, a0, .LBB0_1241; RV32I-NEXT: # %bb.11:42; RV32I-NEXT: mv a0, a243; RV32I-NEXT: .LBB0_12:44; RV32I-NEXT: lw a2, 0(a1)45; RV32I-NEXT: blt a2, a0, .LBB0_1446; RV32I-NEXT: # %bb.13:47; RV32I-NEXT: mv a0, a248; RV32I-NEXT: .LBB0_14:49; RV32I-NEXT: lw a2, 0(a1)50; RV32I-NEXT: bge a0, a2, .LBB0_1651; RV32I-NEXT: # %bb.15:52; RV32I-NEXT: mv a0, a253; RV32I-NEXT: .LBB0_16:54; RV32I-NEXT: lw a2, 0(a1)55; RV32I-NEXT: blt a0, a2, .LBB0_1856; RV32I-NEXT: # %bb.17:57; RV32I-NEXT: mv a0, a258; RV32I-NEXT: .LBB0_18:59; RV32I-NEXT: lw a2, 0(a1)60; RV32I-NEXT: bge a2, a0, .LBB0_2061; RV32I-NEXT: # %bb.19:62; RV32I-NEXT: mv a0, a263; RV32I-NEXT: .LBB0_20:64; RV32I-NEXT: lw a2, 0(a1)65; RV32I-NEXT: blez a2, .LBB0_2266; RV32I-NEXT: # %bb.21:67; RV32I-NEXT: mv a0, a268; RV32I-NEXT: .LBB0_22:69; RV32I-NEXT: lw a3, 0(a1)70; RV32I-NEXT: bgez a2, .LBB0_2471; RV32I-NEXT: # %bb.23:72; RV32I-NEXT: mv a0, a373; RV32I-NEXT: .LBB0_24:74; RV32I-NEXT: lw a3, 0(a1)75; RV32I-NEXT: li a4, 102476; RV32I-NEXT: blt a4, a3, .LBB0_2677; RV32I-NEXT: # %bb.25:78; RV32I-NEXT: mv a0, a379; RV32I-NEXT: .LBB0_26:80; RV32I-NEXT: lw a1, 0(a1)81; RV32I-NEXT: li a3, 204682; RV32I-NEXT: bltu a3, a2, .LBB0_2883; RV32I-NEXT: # %bb.27:84; RV32I-NEXT: mv a0, a185; RV32I-NEXT: .LBB0_28:86; RV32I-NEXT: ret87;88; RV32IXQCI-LABEL: foo:89; RV32IXQCI: # %bb.0:90; RV32IXQCI-NEXT: lw a2, 0(a1)91; RV32IXQCI-NEXT: lw a3, 0(a1)92; RV32IXQCI-NEXT: lw a4, 0(a1)93; RV32IXQCI-NEXT: lw a5, 0(a1)94; RV32IXQCI-NEXT: qc.mvne a0, a0, a2, a295; RV32IXQCI-NEXT: qc.mveq a0, a0, a3, a396; RV32IXQCI-NEXT: lw a2, 0(a1)97; RV32IXQCI-NEXT: qc.mvgeu a0, a4, a0, a498; RV32IXQCI-NEXT: lw a3, 0(a1)99; RV32IXQCI-NEXT: qc.mvltu a0, a0, a5, a5100; RV32IXQCI-NEXT: lw a4, 0(a1)101; RV32IXQCI-NEXT: qc.mvgeu a0, a0, a2, a2102; RV32IXQCI-NEXT: lw a2, 0(a1)103; RV32IXQCI-NEXT: qc.mvltu a0, a3, a0, a3104; RV32IXQCI-NEXT: lw a3, 0(a1)105; RV32IXQCI-NEXT: qc.mvge a0, a4, a0, a4106; RV32IXQCI-NEXT: lw a4, 0(a1)107; RV32IXQCI-NEXT: qc.mvlt a0, a0, a2, a2108; RV32IXQCI-NEXT: lw a2, 0(a1)109; RV32IXQCI-NEXT: qc.mvge a0, a0, a3, a3110; RV32IXQCI-NEXT: lw a3, 0(a1)111; RV32IXQCI-NEXT: qc.mvlt a0, a4, a0, a4112; RV32IXQCI-NEXT: lw a4, 0(a1)113; RV32IXQCI-NEXT: lw a1, 0(a1)114; RV32IXQCI-NEXT: blez a2, .LBB0_2115; RV32IXQCI-NEXT: # %bb.1:116; RV32IXQCI-NEXT: mv a0, a2117; RV32IXQCI-NEXT: .LBB0_2:118; RV32IXQCI-NEXT: qc.mvlti a0, a2, 0, a3119; RV32IXQCI-NEXT: li a3, 1024120; RV32IXQCI-NEXT: qc.mvge a0, a3, a4, a4121; RV32IXQCI-NEXT: li a3, 2046122; RV32IXQCI-NEXT: qc.mvgeu a0, a3, a2, a1123; RV32IXQCI-NEXT: ret124;125; RV64I-LABEL: foo:126; RV64I: # %bb.0:127; RV64I-NEXT: lw a2, 0(a1)128; RV64I-NEXT: beq a0, a2, .LBB0_2129; RV64I-NEXT: # %bb.1:130; RV64I-NEXT: mv a0, a2131; RV64I-NEXT: .LBB0_2:132; RV64I-NEXT: lw a2, 0(a1)133; RV64I-NEXT: bne a0, a2, .LBB0_4134; RV64I-NEXT: # %bb.3:135; RV64I-NEXT: mv a0, a2136; RV64I-NEXT: .LBB0_4:137; RV64I-NEXT: lw a2, 0(a1)138; RV64I-NEXT: bltu a2, a0, .LBB0_6139; RV64I-NEXT: # %bb.5:140; RV64I-NEXT: mv a0, a2141; RV64I-NEXT: .LBB0_6:142; RV64I-NEXT: lw a2, 0(a1)143; RV64I-NEXT: bgeu a0, a2, .LBB0_8144; RV64I-NEXT: # %bb.7:145; RV64I-NEXT: mv a0, a2146; RV64I-NEXT: .LBB0_8:147; RV64I-NEXT: lw a2, 0(a1)148; RV64I-NEXT: bltu a0, a2, .LBB0_10149; RV64I-NEXT: # %bb.9:150; RV64I-NEXT: mv a0, a2151; RV64I-NEXT: .LBB0_10:152; RV64I-NEXT: lw a2, 0(a1)153; RV64I-NEXT: bgeu a2, a0, .LBB0_12154; RV64I-NEXT: # %bb.11:155; RV64I-NEXT: mv a0, a2156; RV64I-NEXT: .LBB0_12:157; RV64I-NEXT: lw a2, 0(a1)158; RV64I-NEXT: blt a2, a0, .LBB0_14159; RV64I-NEXT: # %bb.13:160; RV64I-NEXT: mv a0, a2161; RV64I-NEXT: .LBB0_14:162; RV64I-NEXT: lw a2, 0(a1)163; RV64I-NEXT: bge a0, a2, .LBB0_16164; RV64I-NEXT: # %bb.15:165; RV64I-NEXT: mv a0, a2166; RV64I-NEXT: .LBB0_16:167; RV64I-NEXT: lw a2, 0(a1)168; RV64I-NEXT: blt a0, a2, .LBB0_18169; RV64I-NEXT: # %bb.17:170; RV64I-NEXT: mv a0, a2171; RV64I-NEXT: .LBB0_18:172; RV64I-NEXT: lw a2, 0(a1)173; RV64I-NEXT: bge a2, a0, .LBB0_20174; RV64I-NEXT: # %bb.19:175; RV64I-NEXT: mv a0, a2176; RV64I-NEXT: .LBB0_20:177; RV64I-NEXT: lw a2, 0(a1)178; RV64I-NEXT: blez a2, .LBB0_22179; RV64I-NEXT: # %bb.21:180; RV64I-NEXT: mv a0, a2181; RV64I-NEXT: .LBB0_22:182; RV64I-NEXT: lw a3, 0(a1)183; RV64I-NEXT: bgez a2, .LBB0_24184; RV64I-NEXT: # %bb.23:185; RV64I-NEXT: mv a0, a3186; RV64I-NEXT: .LBB0_24:187; RV64I-NEXT: lw a3, 0(a1)188; RV64I-NEXT: li a4, 1024189; RV64I-NEXT: blt a4, a3, .LBB0_26190; RV64I-NEXT: # %bb.25:191; RV64I-NEXT: mv a0, a3192; RV64I-NEXT: .LBB0_26:193; RV64I-NEXT: lw a1, 0(a1)194; RV64I-NEXT: li a3, 2046195; RV64I-NEXT: bltu a3, a2, .LBB0_28196; RV64I-NEXT: # %bb.27:197; RV64I-NEXT: mv a0, a1198; RV64I-NEXT: .LBB0_28:199; RV64I-NEXT: ret200;201; RV64I-CCMOV-LABEL: foo:202; RV64I-CCMOV: # %bb.0:203; RV64I-CCMOV-NEXT: lw a2, 0(a1)204; RV64I-CCMOV-NEXT: lw a3, 0(a1)205; RV64I-CCMOV-NEXT: lw a4, 0(a1)206; RV64I-CCMOV-NEXT: lw a5, 0(a1)207; RV64I-CCMOV-NEXT: xor a6, a0, a2208; RV64I-CCMOV-NEXT: mips.ccmov a0, a6, a2, a0209; RV64I-CCMOV-NEXT: xor a2, a0, a3210; RV64I-CCMOV-NEXT: mips.ccmov a0, a2, a0, a3211; RV64I-CCMOV-NEXT: lw a2, 0(a1)212; RV64I-CCMOV-NEXT: sltu a3, a4, a0213; RV64I-CCMOV-NEXT: mips.ccmov a0, a3, a0, a4214; RV64I-CCMOV-NEXT: lw a3, 0(a1)215; RV64I-CCMOV-NEXT: sltu a4, a0, a5216; RV64I-CCMOV-NEXT: mips.ccmov a0, a4, a5, a0217; RV64I-CCMOV-NEXT: lw a4, 0(a1)218; RV64I-CCMOV-NEXT: sltu a5, a0, a2219; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a2220; RV64I-CCMOV-NEXT: lw a2, 0(a1)221; RV64I-CCMOV-NEXT: sltu a5, a3, a0222; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a3, a0223; RV64I-CCMOV-NEXT: lw a3, 0(a1)224; RV64I-CCMOV-NEXT: sext.w a5, a0225; RV64I-CCMOV-NEXT: slt a5, a4, a5226; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a4227; RV64I-CCMOV-NEXT: lw a4, 0(a1)228; RV64I-CCMOV-NEXT: sext.w a5, a0229; RV64I-CCMOV-NEXT: slt a5, a5, a2230; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a2, a0231; RV64I-CCMOV-NEXT: lw a2, 0(a1)232; RV64I-CCMOV-NEXT: sext.w a5, a0233; RV64I-CCMOV-NEXT: slt a5, a5, a3234; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a3235; RV64I-CCMOV-NEXT: lw a3, 0(a1)236; RV64I-CCMOV-NEXT: sext.w a5, a0237; RV64I-CCMOV-NEXT: slt a5, a4, a5238; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a4, a0239; RV64I-CCMOV-NEXT: lw a4, 0(a1)240; RV64I-CCMOV-NEXT: slti a5, a2, 1241; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a2242; RV64I-CCMOV-NEXT: srli a5, a2, 63243; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a3, a0244; RV64I-CCMOV-NEXT: lw a1, 0(a1)245; RV64I-CCMOV-NEXT: slti a3, a4, 1025246; RV64I-CCMOV-NEXT: mips.ccmov a0, a3, a4, a0247; RV64I-CCMOV-NEXT: sltiu a2, a2, 2047248; RV64I-CCMOV-NEXT: mips.ccmov a0, a2, a1, a0249; RV64I-CCMOV-NEXT: sext.w a0, a0250; RV64I-CCMOV-NEXT: ret251 %val1 = load volatile i32, ptr %b252 %tst1 = icmp eq i32 %a, %val1253 %val2 = select i1 %tst1, i32 %a, i32 %val1254 255 %val3 = load volatile i32, ptr %b256 %tst2 = icmp ne i32 %val2, %val3257 %val4 = select i1 %tst2, i32 %val2, i32 %val3258 259 %val5 = load volatile i32, ptr %b260 %tst3 = icmp ugt i32 %val4, %val5261 %val6 = select i1 %tst3, i32 %val4, i32 %val5262 263 %val7 = load volatile i32, ptr %b264 %tst4 = icmp uge i32 %val6, %val7265 %val8 = select i1 %tst4, i32 %val6, i32 %val7266 267 %val9 = load volatile i32, ptr %b268 %tst5 = icmp ult i32 %val8, %val9269 %val10 = select i1 %tst5, i32 %val8, i32 %val9270 271 %val11 = load volatile i32, ptr %b272 %tst6 = icmp ule i32 %val10, %val11273 %val12 = select i1 %tst6, i32 %val10, i32 %val11274 275 %val13 = load volatile i32, ptr %b276 %tst7 = icmp sgt i32 %val12, %val13277 %val14 = select i1 %tst7, i32 %val12, i32 %val13278 279 %val15 = load volatile i32, ptr %b280 %tst8 = icmp sge i32 %val14, %val15281 %val16 = select i1 %tst8, i32 %val14, i32 %val15282 283 %val17 = load volatile i32, ptr %b284 %tst9 = icmp slt i32 %val16, %val17285 %val18 = select i1 %tst9, i32 %val16, i32 %val17286 287 %val19 = load volatile i32, ptr %b288 %tst10 = icmp sle i32 %val18, %val19289 %val20 = select i1 %tst10, i32 %val18, i32 %val19290 291 %val21 = load volatile i32, ptr %b292 %tst11 = icmp slt i32 %val21, 1293 %val22 = select i1 %tst11, i32 %val20, i32 %val21294 295 %val23 = load volatile i32, ptr %b296 %tst12 = icmp sgt i32 %val21, -1297 %val24 = select i1 %tst12, i32 %val22, i32 %val23298 299 %val25 = load volatile i32, ptr %b300 %tst13 = icmp sgt i32 %val25, 1024301 %val26 = select i1 %tst13, i32 %val24, i32 %val25302 303 %val27 = load volatile i32, ptr %b304 %tst14 = icmp ugt i32 %val21, 2046305 %val28 = select i1 %tst14, i32 %val26, i32 %val27306 ret i32 %val28307}308 309; Test that we can ComputeNumSignBits across basic blocks when the live out is310; RISCVISD::SELECT_CC. There should be no slli+srai or sext.h in the output.311define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) nounwind {312; RV32I-LABEL: numsignbits:313; RV32I: # %bb.0:314; RV32I-NEXT: addi sp, sp, -16315; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill316; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill317; RV32I-NEXT: mv s0, a3318; RV32I-NEXT: beqz a0, .LBB1_2319; RV32I-NEXT: # %bb.1:320; RV32I-NEXT: mv s0, a2321; RV32I-NEXT: .LBB1_2:322; RV32I-NEXT: beqz a1, .LBB1_4323; RV32I-NEXT: # %bb.3:324; RV32I-NEXT: mv a0, s0325; RV32I-NEXT: call bar326; RV32I-NEXT: .LBB1_4:327; RV32I-NEXT: mv a0, s0328; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload329; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload330; RV32I-NEXT: addi sp, sp, 16331; RV32I-NEXT: ret332;333; RV32IXQCI-LABEL: numsignbits:334; RV32IXQCI: # %bb.0:335; RV32IXQCI-NEXT: addi sp, sp, -16336; RV32IXQCI-NEXT: sw ra, 12(sp) # 4-byte Folded Spill337; RV32IXQCI-NEXT: sw s0, 8(sp) # 4-byte Folded Spill338; RV32IXQCI-NEXT: mv s0, a2339; RV32IXQCI-NEXT: qc.mveqi s0, a0, 0, a3340; RV32IXQCI-NEXT: beqz a1, .LBB1_2341; RV32IXQCI-NEXT: # %bb.1:342; RV32IXQCI-NEXT: mv a0, s0343; RV32IXQCI-NEXT: call bar344; RV32IXQCI-NEXT: .LBB1_2:345; RV32IXQCI-NEXT: mv a0, s0346; RV32IXQCI-NEXT: lw ra, 12(sp) # 4-byte Folded Reload347; RV32IXQCI-NEXT: lw s0, 8(sp) # 4-byte Folded Reload348; RV32IXQCI-NEXT: addi sp, sp, 16349; RV32IXQCI-NEXT: ret350;351; RV64I-LABEL: numsignbits:352; RV64I: # %bb.0:353; RV64I-NEXT: addi sp, sp, -16354; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill355; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill356; RV64I-NEXT: mv s0, a3357; RV64I-NEXT: beqz a0, .LBB1_2358; RV64I-NEXT: # %bb.1:359; RV64I-NEXT: mv s0, a2360; RV64I-NEXT: .LBB1_2:361; RV64I-NEXT: beqz a1, .LBB1_4362; RV64I-NEXT: # %bb.3:363; RV64I-NEXT: mv a0, s0364; RV64I-NEXT: call bar365; RV64I-NEXT: .LBB1_4:366; RV64I-NEXT: mv a0, s0367; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload368; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload369; RV64I-NEXT: addi sp, sp, 16370; RV64I-NEXT: ret371;372; RV64I-CCMOV-LABEL: numsignbits:373; RV64I-CCMOV: # %bb.0:374; RV64I-CCMOV-NEXT: addi sp, sp, -16375; RV64I-CCMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill376; RV64I-CCMOV-NEXT: sd s0, 0(sp) # 8-byte Folded Spill377; RV64I-CCMOV-NEXT: mips.ccmov s0, a0, a2, a3378; RV64I-CCMOV-NEXT: beqz a1, .LBB1_2379; RV64I-CCMOV-NEXT: # %bb.1:380; RV64I-CCMOV-NEXT: mv a0, s0381; RV64I-CCMOV-NEXT: call bar382; RV64I-CCMOV-NEXT: .LBB1_2:383; RV64I-CCMOV-NEXT: mv a0, s0384; RV64I-CCMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload385; RV64I-CCMOV-NEXT: ld s0, 0(sp) # 8-byte Folded Reload386; RV64I-CCMOV-NEXT: addi sp, sp, 16387; RV64I-CCMOV-NEXT: ret388 %5 = icmp eq i16 %0, 0389 %6 = select i1 %5, i16 %3, i16 %2390 %7 = icmp eq i16 %1, 0391 br i1 %7, label %9, label %8392 3938: ; preds = %4394 tail call void @bar(i16 signext %6)395 br label %9396 3979: ; preds = %8, %4398 ret i16 %6399}400 401declare void @bar(i16 signext)402 403define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z) {404; RV32I-LABEL: select_sge_int16min:405; RV32I: # %bb.0:406; RV32I-NEXT: lui a3, 1048560407; RV32I-NEXT: addi a3, a3, -1408; RV32I-NEXT: blt a3, a0, .LBB2_2409; RV32I-NEXT: # %bb.1:410; RV32I-NEXT: mv a1, a2411; RV32I-NEXT: .LBB2_2:412; RV32I-NEXT: mv a0, a1413; RV32I-NEXT: ret414;415; RV32IXQCI-LABEL: select_sge_int16min:416; RV32IXQCI: # %bb.0:417; RV32IXQCI-NEXT: lui a3, 1048560418; RV32IXQCI-NEXT: addi a3, a3, -1419; RV32IXQCI-NEXT: qc.mvge a1, a3, a0, a2420; RV32IXQCI-NEXT: mv a0, a1421; RV32IXQCI-NEXT: ret422;423; RV64I-LABEL: select_sge_int16min:424; RV64I: # %bb.0:425; RV64I-NEXT: lui a3, 1048560426; RV64I-NEXT: addi a3, a3, -1427; RV64I-NEXT: blt a3, a0, .LBB2_2428; RV64I-NEXT: # %bb.1:429; RV64I-NEXT: mv a1, a2430; RV64I-NEXT: .LBB2_2:431; RV64I-NEXT: mv a0, a1432; RV64I-NEXT: ret433;434; RV64I-CCMOV-LABEL: select_sge_int16min:435; RV64I-CCMOV: # %bb.0:436; RV64I-CCMOV-NEXT: lui a3, 1048560437; RV64I-CCMOV-NEXT: addi a3, a3, -1438; RV64I-CCMOV-NEXT: slt a0, a3, a0439; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2440; RV64I-CCMOV-NEXT: ret441 %a = icmp sge i32 %x, -65536442 %b = select i1 %a, i32 %y, i32 %z443 ret i32 %b444}445 446define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {447; RV32I-LABEL: select_sge_int32min:448; RV32I: # %bb.0:449; RV32I-NEXT: li a6, -1450; RV32I-NEXT: bne a1, a6, .LBB3_2451; RV32I-NEXT: # %bb.1:452; RV32I-NEXT: srli a0, a0, 31453; RV32I-NEXT: j .LBB3_3454; RV32I-NEXT: .LBB3_2:455; RV32I-NEXT: srli a1, a1, 31456; RV32I-NEXT: xori a0, a1, 1457; RV32I-NEXT: .LBB3_3:458; RV32I-NEXT: bnez a0, .LBB3_5459; RV32I-NEXT: # %bb.4:460; RV32I-NEXT: mv a2, a4461; RV32I-NEXT: mv a3, a5462; RV32I-NEXT: .LBB3_5:463; RV32I-NEXT: mv a0, a2464; RV32I-NEXT: mv a1, a3465; RV32I-NEXT: ret466;467; RV32IXQCI-LABEL: select_sge_int32min:468; RV32IXQCI: # %bb.0:469; RV32IXQCI-NEXT: srli a6, a0, 31470; RV32IXQCI-NEXT: srli a0, a1, 31471; RV32IXQCI-NEXT: xori a0, a0, 1472; RV32IXQCI-NEXT: qc.mveqi a0, a1, -1, a6473; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4474; RV32IXQCI-NEXT: qc.mveqi a3, a0, 0, a5475; RV32IXQCI-NEXT: mv a0, a2476; RV32IXQCI-NEXT: mv a1, a3477; RV32IXQCI-NEXT: ret478;479; RV64I-LABEL: select_sge_int32min:480; RV64I: # %bb.0:481; RV64I-NEXT: lui a3, 524288482; RV64I-NEXT: addi a3, a3, -1483; RV64I-NEXT: blt a3, a0, .LBB3_2484; RV64I-NEXT: # %bb.1:485; RV64I-NEXT: mv a1, a2486; RV64I-NEXT: .LBB3_2:487; RV64I-NEXT: mv a0, a1488; RV64I-NEXT: ret489;490; RV64I-CCMOV-LABEL: select_sge_int32min:491; RV64I-CCMOV: # %bb.0:492; RV64I-CCMOV-NEXT: lui a3, 524288493; RV64I-CCMOV-NEXT: addi a3, a3, -1494; RV64I-CCMOV-NEXT: slt a0, a3, a0495; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a1, a2496; RV64I-CCMOV-NEXT: ret497 %a = icmp sge i64 %x, -2147483648498 %b = select i1 %a, i64 %y, i64 %z499 ret i64 %b500}501