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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=RV324; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=RV32-THEAD6; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \7; RUN: | FileCheck %s --check-prefixes=RV32-XQCICM8; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \9; RUN: | FileCheck %s --check-prefixes=RV32-XQCICS10; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \11; RUN: | FileCheck %s --check-prefixes=RV32IXQCI12; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \13; RUN: | FileCheck %s --check-prefixes=RV6414; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \15; RUN: | FileCheck %s --check-prefixes=RV64-MIPS16 17define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 signext %y) nounwind {18; RV32-LABEL: select_i32_trunc:19; RV32: # %bb.0:20; RV32-NEXT: andi a3, a0, 121; RV32-NEXT: mv a0, a122; RV32-NEXT: bnez a3, .LBB0_223; RV32-NEXT: # %bb.1:24; RV32-NEXT: mv a0, a225; RV32-NEXT: .LBB0_2:26; RV32-NEXT: ret27;28; RV32-THEAD-LABEL: select_i32_trunc:29; RV32-THEAD: # %bb.0:30; RV32-THEAD-NEXT: andi a0, a0, 131; RV32-THEAD-NEXT: th.mveqz a1, a2, a032; RV32-THEAD-NEXT: mv a0, a133; RV32-THEAD-NEXT: ret34;35; RV32-XQCICM-LABEL: select_i32_trunc:36; RV32-XQCICM: # %bb.0:37; RV32-XQCICM-NEXT: andi a0, a0, 138; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a239; RV32-XQCICM-NEXT: mv a0, a140; RV32-XQCICM-NEXT: ret41;42; RV32-XQCICS-LABEL: select_i32_trunc:43; RV32-XQCICS: # %bb.0:44; RV32-XQCICS-NEXT: andi a0, a0, 145; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a246; RV32-XQCICS-NEXT: ret47;48; RV32IXQCI-LABEL: select_i32_trunc:49; RV32IXQCI: # %bb.0:50; RV32IXQCI-NEXT: andi a0, a0, 151; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a252; RV32IXQCI-NEXT: mv a0, a153; RV32IXQCI-NEXT: ret54;55; RV64-LABEL: select_i32_trunc:56; RV64: # %bb.0:57; RV64-NEXT: andi a3, a0, 158; RV64-NEXT: mv a0, a159; RV64-NEXT: bnez a3, .LBB0_260; RV64-NEXT: # %bb.1:61; RV64-NEXT: mv a0, a262; RV64-NEXT: .LBB0_2:63; RV64-NEXT: ret64;65; RV64-MIPS-LABEL: select_i32_trunc:66; RV64-MIPS: # %bb.0:67; RV64-MIPS-NEXT: andi a0, a0, 168; RV64-MIPS-NEXT: mips.ccmov a0, a0, a1, a269; RV64-MIPS-NEXT: ret70 %cond_trunc = trunc i32 %cond to i171 %res = select i1 %cond_trunc, i32 %x, i32 %y72 ret i32 %res73}74 75define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signext %y) nounwind {76; RV32-LABEL: select_i32_param:77; RV32: # %bb.0:78; RV32-NEXT: andi a3, a0, 179; RV32-NEXT: mv a0, a180; RV32-NEXT: bnez a3, .LBB1_281; RV32-NEXT: # %bb.1:82; RV32-NEXT: mv a0, a283; RV32-NEXT: .LBB1_2:84; RV32-NEXT: ret85;86; RV32-THEAD-LABEL: select_i32_param:87; RV32-THEAD: # %bb.0:88; RV32-THEAD-NEXT: andi a0, a0, 189; RV32-THEAD-NEXT: th.mveqz a1, a2, a090; RV32-THEAD-NEXT: mv a0, a191; RV32-THEAD-NEXT: ret92;93; RV32-XQCICM-LABEL: select_i32_param:94; RV32-XQCICM: # %bb.0:95; RV32-XQCICM-NEXT: andi a0, a0, 196; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a297; RV32-XQCICM-NEXT: mv a0, a198; RV32-XQCICM-NEXT: ret99;100; RV32-XQCICS-LABEL: select_i32_param:101; RV32-XQCICS: # %bb.0:102; RV32-XQCICS-NEXT: andi a0, a0, 1103; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2104; RV32-XQCICS-NEXT: ret105;106; RV32IXQCI-LABEL: select_i32_param:107; RV32IXQCI: # %bb.0:108; RV32IXQCI-NEXT: andi a0, a0, 1109; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2110; RV32IXQCI-NEXT: mv a0, a1111; RV32IXQCI-NEXT: ret112;113; RV64-LABEL: select_i32_param:114; RV64: # %bb.0:115; RV64-NEXT: andi a3, a0, 1116; RV64-NEXT: mv a0, a1117; RV64-NEXT: bnez a3, .LBB1_2118; RV64-NEXT: # %bb.1:119; RV64-NEXT: mv a0, a2120; RV64-NEXT: .LBB1_2:121; RV64-NEXT: ret122;123; RV64-MIPS-LABEL: select_i32_param:124; RV64-MIPS: # %bb.0:125; RV64-MIPS-NEXT: andi a0, a0, 1126; RV64-MIPS-NEXT: mips.ccmov a0, a0, a1, a2127; RV64-MIPS-NEXT: ret128 %res = select i1 %cond, i32 %x, i32 %y129 ret i32 %res130}131 132define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {133; RV32-LABEL: select_i32_eq:134; RV32: # %bb.0:135; RV32-NEXT: beq a0, a1, .LBB2_2136; RV32-NEXT: # %bb.1:137; RV32-NEXT: mv a2, a3138; RV32-NEXT: .LBB2_2:139; RV32-NEXT: mv a0, a2140; RV32-NEXT: ret141;142; RV32-THEAD-LABEL: select_i32_eq:143; RV32-THEAD: # %bb.0:144; RV32-THEAD-NEXT: xor a0, a0, a1145; RV32-THEAD-NEXT: th.mvnez a2, a3, a0146; RV32-THEAD-NEXT: mv a0, a2147; RV32-THEAD-NEXT: ret148;149; RV32-XQCICM-LABEL: select_i32_eq:150; RV32-XQCICM: # %bb.0:151; RV32-XQCICM-NEXT: qc.mvne a2, a0, a1, a3152; RV32-XQCICM-NEXT: mv a0, a2153; RV32-XQCICM-NEXT: ret154;155; RV32-XQCICS-LABEL: select_i32_eq:156; RV32-XQCICS: # %bb.0:157; RV32-XQCICS-NEXT: beq a0, a1, .LBB2_2158; RV32-XQCICS-NEXT: # %bb.1:159; RV32-XQCICS-NEXT: mv a2, a3160; RV32-XQCICS-NEXT: .LBB2_2:161; RV32-XQCICS-NEXT: mv a0, a2162; RV32-XQCICS-NEXT: ret163;164; RV32IXQCI-LABEL: select_i32_eq:165; RV32IXQCI: # %bb.0:166; RV32IXQCI-NEXT: qc.mvne a2, a0, a1, a3167; RV32IXQCI-NEXT: mv a0, a2168; RV32IXQCI-NEXT: ret169;170; RV64-LABEL: select_i32_eq:171; RV64: # %bb.0:172; RV64-NEXT: beq a0, a1, .LBB2_2173; RV64-NEXT: # %bb.1:174; RV64-NEXT: mv a2, a3175; RV64-NEXT: .LBB2_2:176; RV64-NEXT: mv a0, a2177; RV64-NEXT: ret178;179; RV64-MIPS-LABEL: select_i32_eq:180; RV64-MIPS: # %bb.0:181; RV64-MIPS-NEXT: xor a0, a0, a1182; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a2183; RV64-MIPS-NEXT: ret184 %cond = icmp eq i32 %a, %b185 %res = select i1 %cond, i32 %x, i32 %y186 ret i32 %res187}188 189define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {190; RV32-LABEL: select_i32_ne:191; RV32: # %bb.0:192; RV32-NEXT: bne a0, a1, .LBB3_2193; RV32-NEXT: # %bb.1:194; RV32-NEXT: mv a2, a3195; RV32-NEXT: .LBB3_2:196; RV32-NEXT: mv a0, a2197; RV32-NEXT: ret198;199; RV32-THEAD-LABEL: select_i32_ne:200; RV32-THEAD: # %bb.0:201; RV32-THEAD-NEXT: xor a0, a0, a1202; RV32-THEAD-NEXT: th.mveqz a2, a3, a0203; RV32-THEAD-NEXT: mv a0, a2204; RV32-THEAD-NEXT: ret205;206; RV32-XQCICM-LABEL: select_i32_ne:207; RV32-XQCICM: # %bb.0:208; RV32-XQCICM-NEXT: qc.mveq a2, a0, a1, a3209; RV32-XQCICM-NEXT: mv a0, a2210; RV32-XQCICM-NEXT: ret211;212; RV32-XQCICS-LABEL: select_i32_ne:213; RV32-XQCICS: # %bb.0:214; RV32-XQCICS-NEXT: bne a0, a1, .LBB3_2215; RV32-XQCICS-NEXT: # %bb.1:216; RV32-XQCICS-NEXT: mv a2, a3217; RV32-XQCICS-NEXT: .LBB3_2:218; RV32-XQCICS-NEXT: mv a0, a2219; RV32-XQCICS-NEXT: ret220;221; RV32IXQCI-LABEL: select_i32_ne:222; RV32IXQCI: # %bb.0:223; RV32IXQCI-NEXT: qc.mveq a2, a0, a1, a3224; RV32IXQCI-NEXT: mv a0, a2225; RV32IXQCI-NEXT: ret226;227; RV64-LABEL: select_i32_ne:228; RV64: # %bb.0:229; RV64-NEXT: bne a0, a1, .LBB3_2230; RV64-NEXT: # %bb.1:231; RV64-NEXT: mv a2, a3232; RV64-NEXT: .LBB3_2:233; RV64-NEXT: mv a0, a2234; RV64-NEXT: ret235;236; RV64-MIPS-LABEL: select_i32_ne:237; RV64-MIPS: # %bb.0:238; RV64-MIPS-NEXT: xor a0, a0, a1239; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a3240; RV64-MIPS-NEXT: ret241 %cond = icmp ne i32 %a, %b242 %res = select i1 %cond, i32 %x, i32 %y243 ret i32 %res244}245 246define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {247; RV32-LABEL: select_i32_ugt:248; RV32: # %bb.0:249; RV32-NEXT: bltu a1, a0, .LBB4_2250; RV32-NEXT: # %bb.1:251; RV32-NEXT: mv a2, a3252; RV32-NEXT: .LBB4_2:253; RV32-NEXT: mv a0, a2254; RV32-NEXT: ret255;256; RV32-THEAD-LABEL: select_i32_ugt:257; RV32-THEAD: # %bb.0:258; RV32-THEAD-NEXT: sltu a0, a1, a0259; RV32-THEAD-NEXT: th.mveqz a2, a3, a0260; RV32-THEAD-NEXT: mv a0, a2261; RV32-THEAD-NEXT: ret262;263; RV32-XQCICM-LABEL: select_i32_ugt:264; RV32-XQCICM: # %bb.0:265; RV32-XQCICM-NEXT: qc.mvgeu a2, a1, a0, a3266; RV32-XQCICM-NEXT: mv a0, a2267; RV32-XQCICM-NEXT: ret268;269; RV32-XQCICS-LABEL: select_i32_ugt:270; RV32-XQCICS: # %bb.0:271; RV32-XQCICS-NEXT: bltu a1, a0, .LBB4_2272; RV32-XQCICS-NEXT: # %bb.1:273; RV32-XQCICS-NEXT: mv a2, a3274; RV32-XQCICS-NEXT: .LBB4_2:275; RV32-XQCICS-NEXT: mv a0, a2276; RV32-XQCICS-NEXT: ret277;278; RV32IXQCI-LABEL: select_i32_ugt:279; RV32IXQCI: # %bb.0:280; RV32IXQCI-NEXT: qc.mvgeu a2, a1, a0, a3281; RV32IXQCI-NEXT: mv a0, a2282; RV32IXQCI-NEXT: ret283;284; RV64-LABEL: select_i32_ugt:285; RV64: # %bb.0:286; RV64-NEXT: bltu a1, a0, .LBB4_2287; RV64-NEXT: # %bb.1:288; RV64-NEXT: mv a2, a3289; RV64-NEXT: .LBB4_2:290; RV64-NEXT: mv a0, a2291; RV64-NEXT: ret292;293; RV64-MIPS-LABEL: select_i32_ugt:294; RV64-MIPS: # %bb.0:295; RV64-MIPS-NEXT: sltu a0, a1, a0296; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a3297; RV64-MIPS-NEXT: ret298 %cond = icmp ugt i32 %a, %b299 %res = select i1 %cond, i32 %x, i32 %y300 ret i32 %res301}302 303define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {304; RV32-LABEL: select_i32_uge:305; RV32: # %bb.0:306; RV32-NEXT: bgeu a0, a1, .LBB5_2307; RV32-NEXT: # %bb.1:308; RV32-NEXT: mv a2, a3309; RV32-NEXT: .LBB5_2:310; RV32-NEXT: mv a0, a2311; RV32-NEXT: ret312;313; RV32-THEAD-LABEL: select_i32_uge:314; RV32-THEAD: # %bb.0:315; RV32-THEAD-NEXT: sltu a0, a0, a1316; RV32-THEAD-NEXT: th.mvnez a2, a3, a0317; RV32-THEAD-NEXT: mv a0, a2318; RV32-THEAD-NEXT: ret319;320; RV32-XQCICM-LABEL: select_i32_uge:321; RV32-XQCICM: # %bb.0:322; RV32-XQCICM-NEXT: qc.mvltu a2, a0, a1, a3323; RV32-XQCICM-NEXT: mv a0, a2324; RV32-XQCICM-NEXT: ret325;326; RV32-XQCICS-LABEL: select_i32_uge:327; RV32-XQCICS: # %bb.0:328; RV32-XQCICS-NEXT: bgeu a0, a1, .LBB5_2329; RV32-XQCICS-NEXT: # %bb.1:330; RV32-XQCICS-NEXT: mv a2, a3331; RV32-XQCICS-NEXT: .LBB5_2:332; RV32-XQCICS-NEXT: mv a0, a2333; RV32-XQCICS-NEXT: ret334;335; RV32IXQCI-LABEL: select_i32_uge:336; RV32IXQCI: # %bb.0:337; RV32IXQCI-NEXT: qc.mvltu a2, a0, a1, a3338; RV32IXQCI-NEXT: mv a0, a2339; RV32IXQCI-NEXT: ret340;341; RV64-LABEL: select_i32_uge:342; RV64: # %bb.0:343; RV64-NEXT: bgeu a0, a1, .LBB5_2344; RV64-NEXT: # %bb.1:345; RV64-NEXT: mv a2, a3346; RV64-NEXT: .LBB5_2:347; RV64-NEXT: mv a0, a2348; RV64-NEXT: ret349;350; RV64-MIPS-LABEL: select_i32_uge:351; RV64-MIPS: # %bb.0:352; RV64-MIPS-NEXT: sltu a0, a0, a1353; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a2354; RV64-MIPS-NEXT: ret355 %cond = icmp uge i32 %a, %b356 %res = select i1 %cond, i32 %x, i32 %y357 ret i32 %res358}359 360define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {361; RV32-LABEL: select_i32_ult:362; RV32: # %bb.0:363; RV32-NEXT: bltu a0, a1, .LBB6_2364; RV32-NEXT: # %bb.1:365; RV32-NEXT: mv a2, a3366; RV32-NEXT: .LBB6_2:367; RV32-NEXT: mv a0, a2368; RV32-NEXT: ret369;370; RV32-THEAD-LABEL: select_i32_ult:371; RV32-THEAD: # %bb.0:372; RV32-THEAD-NEXT: sltu a0, a0, a1373; RV32-THEAD-NEXT: th.mveqz a2, a3, a0374; RV32-THEAD-NEXT: mv a0, a2375; RV32-THEAD-NEXT: ret376;377; RV32-XQCICM-LABEL: select_i32_ult:378; RV32-XQCICM: # %bb.0:379; RV32-XQCICM-NEXT: qc.mvgeu a2, a0, a1, a3380; RV32-XQCICM-NEXT: mv a0, a2381; RV32-XQCICM-NEXT: ret382;383; RV32-XQCICS-LABEL: select_i32_ult:384; RV32-XQCICS: # %bb.0:385; RV32-XQCICS-NEXT: bltu a0, a1, .LBB6_2386; RV32-XQCICS-NEXT: # %bb.1:387; RV32-XQCICS-NEXT: mv a2, a3388; RV32-XQCICS-NEXT: .LBB6_2:389; RV32-XQCICS-NEXT: mv a0, a2390; RV32-XQCICS-NEXT: ret391;392; RV32IXQCI-LABEL: select_i32_ult:393; RV32IXQCI: # %bb.0:394; RV32IXQCI-NEXT: qc.mvgeu a2, a0, a1, a3395; RV32IXQCI-NEXT: mv a0, a2396; RV32IXQCI-NEXT: ret397;398; RV64-LABEL: select_i32_ult:399; RV64: # %bb.0:400; RV64-NEXT: bltu a0, a1, .LBB6_2401; RV64-NEXT: # %bb.1:402; RV64-NEXT: mv a2, a3403; RV64-NEXT: .LBB6_2:404; RV64-NEXT: mv a0, a2405; RV64-NEXT: ret406;407; RV64-MIPS-LABEL: select_i32_ult:408; RV64-MIPS: # %bb.0:409; RV64-MIPS-NEXT: sltu a0, a0, a1410; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a3411; RV64-MIPS-NEXT: ret412 %cond = icmp ult i32 %a, %b413 %res = select i1 %cond, i32 %x, i32 %y414 ret i32 %res415}416 417define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {418; RV32-LABEL: select_i32_ule:419; RV32: # %bb.0:420; RV32-NEXT: bgeu a1, a0, .LBB7_2421; RV32-NEXT: # %bb.1:422; RV32-NEXT: mv a2, a3423; RV32-NEXT: .LBB7_2:424; RV32-NEXT: mv a0, a2425; RV32-NEXT: ret426;427; RV32-THEAD-LABEL: select_i32_ule:428; RV32-THEAD: # %bb.0:429; RV32-THEAD-NEXT: sltu a0, a1, a0430; RV32-THEAD-NEXT: th.mvnez a2, a3, a0431; RV32-THEAD-NEXT: mv a0, a2432; RV32-THEAD-NEXT: ret433;434; RV32-XQCICM-LABEL: select_i32_ule:435; RV32-XQCICM: # %bb.0:436; RV32-XQCICM-NEXT: qc.mvltu a2, a1, a0, a3437; RV32-XQCICM-NEXT: mv a0, a2438; RV32-XQCICM-NEXT: ret439;440; RV32-XQCICS-LABEL: select_i32_ule:441; RV32-XQCICS: # %bb.0:442; RV32-XQCICS-NEXT: bgeu a1, a0, .LBB7_2443; RV32-XQCICS-NEXT: # %bb.1:444; RV32-XQCICS-NEXT: mv a2, a3445; RV32-XQCICS-NEXT: .LBB7_2:446; RV32-XQCICS-NEXT: mv a0, a2447; RV32-XQCICS-NEXT: ret448;449; RV32IXQCI-LABEL: select_i32_ule:450; RV32IXQCI: # %bb.0:451; RV32IXQCI-NEXT: qc.mvltu a2, a1, a0, a3452; RV32IXQCI-NEXT: mv a0, a2453; RV32IXQCI-NEXT: ret454;455; RV64-LABEL: select_i32_ule:456; RV64: # %bb.0:457; RV64-NEXT: bgeu a1, a0, .LBB7_2458; RV64-NEXT: # %bb.1:459; RV64-NEXT: mv a2, a3460; RV64-NEXT: .LBB7_2:461; RV64-NEXT: mv a0, a2462; RV64-NEXT: ret463;464; RV64-MIPS-LABEL: select_i32_ule:465; RV64-MIPS: # %bb.0:466; RV64-MIPS-NEXT: sltu a0, a1, a0467; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a2468; RV64-MIPS-NEXT: ret469 %cond = icmp ule i32 %a, %b470 %res = select i1 %cond, i32 %x, i32 %y471 ret i32 %res472}473 474define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {475; RV32-LABEL: select_i32_sgt:476; RV32: # %bb.0:477; RV32-NEXT: blt a1, a0, .LBB8_2478; RV32-NEXT: # %bb.1:479; RV32-NEXT: mv a2, a3480; RV32-NEXT: .LBB8_2:481; RV32-NEXT: mv a0, a2482; RV32-NEXT: ret483;484; RV32-THEAD-LABEL: select_i32_sgt:485; RV32-THEAD: # %bb.0:486; RV32-THEAD-NEXT: slt a0, a1, a0487; RV32-THEAD-NEXT: th.mveqz a2, a3, a0488; RV32-THEAD-NEXT: mv a0, a2489; RV32-THEAD-NEXT: ret490;491; RV32-XQCICM-LABEL: select_i32_sgt:492; RV32-XQCICM: # %bb.0:493; RV32-XQCICM-NEXT: qc.mvge a2, a1, a0, a3494; RV32-XQCICM-NEXT: mv a0, a2495; RV32-XQCICM-NEXT: ret496;497; RV32-XQCICS-LABEL: select_i32_sgt:498; RV32-XQCICS: # %bb.0:499; RV32-XQCICS-NEXT: blt a1, a0, .LBB8_2500; RV32-XQCICS-NEXT: # %bb.1:501; RV32-XQCICS-NEXT: mv a2, a3502; RV32-XQCICS-NEXT: .LBB8_2:503; RV32-XQCICS-NEXT: mv a0, a2504; RV32-XQCICS-NEXT: ret505;506; RV32IXQCI-LABEL: select_i32_sgt:507; RV32IXQCI: # %bb.0:508; RV32IXQCI-NEXT: qc.mvge a2, a1, a0, a3509; RV32IXQCI-NEXT: mv a0, a2510; RV32IXQCI-NEXT: ret511;512; RV64-LABEL: select_i32_sgt:513; RV64: # %bb.0:514; RV64-NEXT: blt a1, a0, .LBB8_2515; RV64-NEXT: # %bb.1:516; RV64-NEXT: mv a2, a3517; RV64-NEXT: .LBB8_2:518; RV64-NEXT: mv a0, a2519; RV64-NEXT: ret520;521; RV64-MIPS-LABEL: select_i32_sgt:522; RV64-MIPS: # %bb.0:523; RV64-MIPS-NEXT: slt a0, a1, a0524; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a3525; RV64-MIPS-NEXT: ret526 %cond = icmp sgt i32 %a, %b527 %res = select i1 %cond, i32 %x, i32 %y528 ret i32 %res529}530 531define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {532; RV32-LABEL: select_i32_sge:533; RV32: # %bb.0:534; RV32-NEXT: bge a0, a1, .LBB9_2535; RV32-NEXT: # %bb.1:536; RV32-NEXT: mv a2, a3537; RV32-NEXT: .LBB9_2:538; RV32-NEXT: mv a0, a2539; RV32-NEXT: ret540;541; RV32-THEAD-LABEL: select_i32_sge:542; RV32-THEAD: # %bb.0:543; RV32-THEAD-NEXT: slt a0, a0, a1544; RV32-THEAD-NEXT: th.mvnez a2, a3, a0545; RV32-THEAD-NEXT: mv a0, a2546; RV32-THEAD-NEXT: ret547;548; RV32-XQCICM-LABEL: select_i32_sge:549; RV32-XQCICM: # %bb.0:550; RV32-XQCICM-NEXT: qc.mvlt a2, a0, a1, a3551; RV32-XQCICM-NEXT: mv a0, a2552; RV32-XQCICM-NEXT: ret553;554; RV32-XQCICS-LABEL: select_i32_sge:555; RV32-XQCICS: # %bb.0:556; RV32-XQCICS-NEXT: bge a0, a1, .LBB9_2557; RV32-XQCICS-NEXT: # %bb.1:558; RV32-XQCICS-NEXT: mv a2, a3559; RV32-XQCICS-NEXT: .LBB9_2:560; RV32-XQCICS-NEXT: mv a0, a2561; RV32-XQCICS-NEXT: ret562;563; RV32IXQCI-LABEL: select_i32_sge:564; RV32IXQCI: # %bb.0:565; RV32IXQCI-NEXT: qc.mvlt a2, a0, a1, a3566; RV32IXQCI-NEXT: mv a0, a2567; RV32IXQCI-NEXT: ret568;569; RV64-LABEL: select_i32_sge:570; RV64: # %bb.0:571; RV64-NEXT: bge a0, a1, .LBB9_2572; RV64-NEXT: # %bb.1:573; RV64-NEXT: mv a2, a3574; RV64-NEXT: .LBB9_2:575; RV64-NEXT: mv a0, a2576; RV64-NEXT: ret577;578; RV64-MIPS-LABEL: select_i32_sge:579; RV64-MIPS: # %bb.0:580; RV64-MIPS-NEXT: slt a0, a0, a1581; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a2582; RV64-MIPS-NEXT: ret583 %cond = icmp sge i32 %a, %b584 %res = select i1 %cond, i32 %x, i32 %y585 ret i32 %res586}587 588define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {589; RV32-LABEL: select_i32_slt:590; RV32: # %bb.0:591; RV32-NEXT: blt a0, a1, .LBB10_2592; RV32-NEXT: # %bb.1:593; RV32-NEXT: mv a2, a3594; RV32-NEXT: .LBB10_2:595; RV32-NEXT: mv a0, a2596; RV32-NEXT: ret597;598; RV32-THEAD-LABEL: select_i32_slt:599; RV32-THEAD: # %bb.0:600; RV32-THEAD-NEXT: slt a0, a0, a1601; RV32-THEAD-NEXT: th.mveqz a2, a3, a0602; RV32-THEAD-NEXT: mv a0, a2603; RV32-THEAD-NEXT: ret604;605; RV32-XQCICM-LABEL: select_i32_slt:606; RV32-XQCICM: # %bb.0:607; RV32-XQCICM-NEXT: qc.mvge a2, a0, a1, a3608; RV32-XQCICM-NEXT: mv a0, a2609; RV32-XQCICM-NEXT: ret610;611; RV32-XQCICS-LABEL: select_i32_slt:612; RV32-XQCICS: # %bb.0:613; RV32-XQCICS-NEXT: blt a0, a1, .LBB10_2614; RV32-XQCICS-NEXT: # %bb.1:615; RV32-XQCICS-NEXT: mv a2, a3616; RV32-XQCICS-NEXT: .LBB10_2:617; RV32-XQCICS-NEXT: mv a0, a2618; RV32-XQCICS-NEXT: ret619;620; RV32IXQCI-LABEL: select_i32_slt:621; RV32IXQCI: # %bb.0:622; RV32IXQCI-NEXT: qc.mvge a2, a0, a1, a3623; RV32IXQCI-NEXT: mv a0, a2624; RV32IXQCI-NEXT: ret625;626; RV64-LABEL: select_i32_slt:627; RV64: # %bb.0:628; RV64-NEXT: blt a0, a1, .LBB10_2629; RV64-NEXT: # %bb.1:630; RV64-NEXT: mv a2, a3631; RV64-NEXT: .LBB10_2:632; RV64-NEXT: mv a0, a2633; RV64-NEXT: ret634;635; RV64-MIPS-LABEL: select_i32_slt:636; RV64-MIPS: # %bb.0:637; RV64-MIPS-NEXT: slt a0, a0, a1638; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a3639; RV64-MIPS-NEXT: ret640 %cond = icmp slt i32 %a, %b641 %res = select i1 %cond, i32 %x, i32 %y642 ret i32 %res643}644 645define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %x, i32 signext %y) nounwind {646; RV32-LABEL: select_i32_sle:647; RV32: # %bb.0:648; RV32-NEXT: bge a1, a0, .LBB11_2649; RV32-NEXT: # %bb.1:650; RV32-NEXT: mv a2, a3651; RV32-NEXT: .LBB11_2:652; RV32-NEXT: mv a0, a2653; RV32-NEXT: ret654;655; RV32-THEAD-LABEL: select_i32_sle:656; RV32-THEAD: # %bb.0:657; RV32-THEAD-NEXT: slt a0, a1, a0658; RV32-THEAD-NEXT: th.mvnez a2, a3, a0659; RV32-THEAD-NEXT: mv a0, a2660; RV32-THEAD-NEXT: ret661;662; RV32-XQCICM-LABEL: select_i32_sle:663; RV32-XQCICM: # %bb.0:664; RV32-XQCICM-NEXT: qc.mvlt a2, a1, a0, a3665; RV32-XQCICM-NEXT: mv a0, a2666; RV32-XQCICM-NEXT: ret667;668; RV32-XQCICS-LABEL: select_i32_sle:669; RV32-XQCICS: # %bb.0:670; RV32-XQCICS-NEXT: bge a1, a0, .LBB11_2671; RV32-XQCICS-NEXT: # %bb.1:672; RV32-XQCICS-NEXT: mv a2, a3673; RV32-XQCICS-NEXT: .LBB11_2:674; RV32-XQCICS-NEXT: mv a0, a2675; RV32-XQCICS-NEXT: ret676;677; RV32IXQCI-LABEL: select_i32_sle:678; RV32IXQCI: # %bb.0:679; RV32IXQCI-NEXT: qc.mvlt a2, a1, a0, a3680; RV32IXQCI-NEXT: mv a0, a2681; RV32IXQCI-NEXT: ret682;683; RV64-LABEL: select_i32_sle:684; RV64: # %bb.0:685; RV64-NEXT: bge a1, a0, .LBB11_2686; RV64-NEXT: # %bb.1:687; RV64-NEXT: mv a2, a3688; RV64-NEXT: .LBB11_2:689; RV64-NEXT: mv a0, a2690; RV64-NEXT: ret691;692; RV64-MIPS-LABEL: select_i32_sle:693; RV64-MIPS: # %bb.0:694; RV64-MIPS-NEXT: slt a0, a1, a0695; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a2696; RV64-MIPS-NEXT: ret697 %cond = icmp sle i32 %a, %b698 %res = select i1 %cond, i32 %x, i32 %y699 ret i32 %res700}701 702define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {703; RV32-LABEL: select_i64_trunc:704; RV32: # %bb.0:705; RV32-NEXT: mv a1, a3706; RV32-NEXT: andi a3, a0, 1707; RV32-NEXT: mv a0, a2708; RV32-NEXT: bnez a3, .LBB12_2709; RV32-NEXT: # %bb.1:710; RV32-NEXT: mv a0, a4711; RV32-NEXT: mv a1, a5712; RV32-NEXT: .LBB12_2:713; RV32-NEXT: ret714;715; RV32-THEAD-LABEL: select_i64_trunc:716; RV32-THEAD: # %bb.0:717; RV32-THEAD-NEXT: mv a1, a3718; RV32-THEAD-NEXT: andi a0, a0, 1719; RV32-THEAD-NEXT: th.mveqz a2, a4, a0720; RV32-THEAD-NEXT: th.mveqz a1, a5, a0721; RV32-THEAD-NEXT: mv a0, a2722; RV32-THEAD-NEXT: ret723;724; RV32-XQCICM-LABEL: select_i64_trunc:725; RV32-XQCICM: # %bb.0:726; RV32-XQCICM-NEXT: mv a1, a3727; RV32-XQCICM-NEXT: andi a0, a0, 1728; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4729; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a5730; RV32-XQCICM-NEXT: mv a0, a2731; RV32-XQCICM-NEXT: ret732;733; RV32-XQCICS-LABEL: select_i64_trunc:734; RV32-XQCICS: # %bb.0:735; RV32-XQCICS-NEXT: andi a1, a0, 1736; RV32-XQCICS-NEXT: mv a0, a1737; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a3, a5738; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a4739; RV32-XQCICS-NEXT: ret740;741; RV32IXQCI-LABEL: select_i64_trunc:742; RV32IXQCI: # %bb.0:743; RV32IXQCI-NEXT: mv a1, a3744; RV32IXQCI-NEXT: andi a0, a0, 1745; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4746; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a5747; RV32IXQCI-NEXT: mv a0, a2748; RV32IXQCI-NEXT: ret749;750; RV64-LABEL: select_i64_trunc:751; RV64: # %bb.0:752; RV64-NEXT: andi a3, a0, 1753; RV64-NEXT: mv a0, a1754; RV64-NEXT: bnez a3, .LBB12_2755; RV64-NEXT: # %bb.1:756; RV64-NEXT: mv a0, a2757; RV64-NEXT: .LBB12_2:758; RV64-NEXT: ret759;760; RV64-MIPS-LABEL: select_i64_trunc:761; RV64-MIPS: # %bb.0:762; RV64-MIPS-NEXT: andi a0, a0, 1763; RV64-MIPS-NEXT: mips.ccmov a0, a0, a1, a2764; RV64-MIPS-NEXT: ret765 %cond_trunc = trunc i64 %cond to i1766 %res = select i1 %cond_trunc, i64 %x, i64 %y767 ret i64 %res768}769 770define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {771; RV32-LABEL: select_i64_param:772; RV32: # %bb.0:773; RV32-NEXT: andi a5, a0, 1774; RV32-NEXT: mv a0, a1775; RV32-NEXT: bnez a5, .LBB13_2776; RV32-NEXT: # %bb.1:777; RV32-NEXT: mv a0, a3778; RV32-NEXT: mv a2, a4779; RV32-NEXT: .LBB13_2:780; RV32-NEXT: mv a1, a2781; RV32-NEXT: ret782;783; RV32-THEAD-LABEL: select_i64_param:784; RV32-THEAD: # %bb.0:785; RV32-THEAD-NEXT: andi a0, a0, 1786; RV32-THEAD-NEXT: th.mveqz a1, a3, a0787; RV32-THEAD-NEXT: th.mveqz a2, a4, a0788; RV32-THEAD-NEXT: mv a0, a1789; RV32-THEAD-NEXT: mv a1, a2790; RV32-THEAD-NEXT: ret791;792; RV32-XQCICM-LABEL: select_i64_param:793; RV32-XQCICM: # %bb.0:794; RV32-XQCICM-NEXT: andi a0, a0, 1795; RV32-XQCICM-NEXT: qc.mveqi a1, a0, 0, a3796; RV32-XQCICM-NEXT: qc.mveqi a2, a0, 0, a4797; RV32-XQCICM-NEXT: mv a0, a1798; RV32-XQCICM-NEXT: mv a1, a2799; RV32-XQCICM-NEXT: ret800;801; RV32-XQCICS-LABEL: select_i64_param:802; RV32-XQCICS: # %bb.0:803; RV32-XQCICS-NEXT: andi a5, a0, 1804; RV32-XQCICS-NEXT: mv a0, a5805; RV32-XQCICS-NEXT: qc.selectnei a5, 0, a2, a4806; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a3807; RV32-XQCICS-NEXT: mv a1, a5808; RV32-XQCICS-NEXT: ret809;810; RV32IXQCI-LABEL: select_i64_param:811; RV32IXQCI: # %bb.0:812; RV32IXQCI-NEXT: andi a0, a0, 1813; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a3814; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4815; RV32IXQCI-NEXT: mv a0, a1816; RV32IXQCI-NEXT: mv a1, a2817; RV32IXQCI-NEXT: ret818;819; RV64-LABEL: select_i64_param:820; RV64: # %bb.0:821; RV64-NEXT: andi a3, a0, 1822; RV64-NEXT: mv a0, a1823; RV64-NEXT: bnez a3, .LBB13_2824; RV64-NEXT: # %bb.1:825; RV64-NEXT: mv a0, a2826; RV64-NEXT: .LBB13_2:827; RV64-NEXT: ret828;829; RV64-MIPS-LABEL: select_i64_param:830; RV64-MIPS: # %bb.0:831; RV64-MIPS-NEXT: andi a0, a0, 1832; RV64-MIPS-NEXT: mips.ccmov a0, a0, a1, a2833; RV64-MIPS-NEXT: ret834 %res = select i1 %cond, i64 %x, i64 %y835 ret i64 %res836}837 838define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {839; RV32-LABEL: select_i64_eq:840; RV32: # %bb.0:841; RV32-NEXT: xor a1, a1, a3842; RV32-NEXT: xor a0, a0, a2843; RV32-NEXT: or a1, a0, a1844; RV32-NEXT: mv a0, a4845; RV32-NEXT: beqz a1, .LBB14_2846; RV32-NEXT: # %bb.1:847; RV32-NEXT: mv a0, a6848; RV32-NEXT: mv a5, a7849; RV32-NEXT: .LBB14_2:850; RV32-NEXT: mv a1, a5851; RV32-NEXT: ret852;853; RV32-THEAD-LABEL: select_i64_eq:854; RV32-THEAD: # %bb.0:855; RV32-THEAD-NEXT: xor a1, a1, a3856; RV32-THEAD-NEXT: xor a0, a0, a2857; RV32-THEAD-NEXT: or a0, a0, a1858; RV32-THEAD-NEXT: th.mvnez a4, a6, a0859; RV32-THEAD-NEXT: th.mvnez a5, a7, a0860; RV32-THEAD-NEXT: mv a0, a4861; RV32-THEAD-NEXT: mv a1, a5862; RV32-THEAD-NEXT: ret863;864; RV32-XQCICM-LABEL: select_i64_eq:865; RV32-XQCICM: # %bb.0:866; RV32-XQCICM-NEXT: xor a1, a1, a3867; RV32-XQCICM-NEXT: xor a0, a0, a2868; RV32-XQCICM-NEXT: or a0, a0, a1869; RV32-XQCICM-NEXT: qc.mvnei a4, a0, 0, a6870; RV32-XQCICM-NEXT: qc.mvnei a5, a0, 0, a7871; RV32-XQCICM-NEXT: mv a0, a4872; RV32-XQCICM-NEXT: mv a1, a5873; RV32-XQCICM-NEXT: ret874;875; RV32-XQCICS-LABEL: select_i64_eq:876; RV32-XQCICS: # %bb.0:877; RV32-XQCICS-NEXT: xor a1, a1, a3878; RV32-XQCICS-NEXT: xor a0, a0, a2879; RV32-XQCICS-NEXT: or a1, a0, a1880; RV32-XQCICS-NEXT: mv a0, a1881; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6882; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7883; RV32-XQCICS-NEXT: ret884;885; RV32IXQCI-LABEL: select_i64_eq:886; RV32IXQCI: # %bb.0:887; RV32IXQCI-NEXT: xor a1, a1, a3888; RV32IXQCI-NEXT: xor a0, a0, a2889; RV32IXQCI-NEXT: or a0, a0, a1890; RV32IXQCI-NEXT: qc.mvnei a4, a0, 0, a6891; RV32IXQCI-NEXT: qc.mvnei a5, a0, 0, a7892; RV32IXQCI-NEXT: mv a0, a4893; RV32IXQCI-NEXT: mv a1, a5894; RV32IXQCI-NEXT: ret895;896; RV64-LABEL: select_i64_eq:897; RV64: # %bb.0:898; RV64-NEXT: beq a0, a1, .LBB14_2899; RV64-NEXT: # %bb.1:900; RV64-NEXT: mv a2, a3901; RV64-NEXT: .LBB14_2:902; RV64-NEXT: mv a0, a2903; RV64-NEXT: ret904;905; RV64-MIPS-LABEL: select_i64_eq:906; RV64-MIPS: # %bb.0:907; RV64-MIPS-NEXT: xor a0, a0, a1908; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a2909; RV64-MIPS-NEXT: ret910 %cond = icmp eq i64 %a, %b911 %res = select i1 %cond, i64 %x, i64 %y912 ret i64 %res913}914 915define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {916; RV32-LABEL: select_i64_ne:917; RV32: # %bb.0:918; RV32-NEXT: xor a1, a1, a3919; RV32-NEXT: xor a0, a0, a2920; RV32-NEXT: or a1, a0, a1921; RV32-NEXT: mv a0, a4922; RV32-NEXT: bnez a1, .LBB15_2923; RV32-NEXT: # %bb.1:924; RV32-NEXT: mv a0, a6925; RV32-NEXT: mv a5, a7926; RV32-NEXT: .LBB15_2:927; RV32-NEXT: mv a1, a5928; RV32-NEXT: ret929;930; RV32-THEAD-LABEL: select_i64_ne:931; RV32-THEAD: # %bb.0:932; RV32-THEAD-NEXT: xor a1, a1, a3933; RV32-THEAD-NEXT: xor a0, a0, a2934; RV32-THEAD-NEXT: or a0, a0, a1935; RV32-THEAD-NEXT: th.mveqz a4, a6, a0936; RV32-THEAD-NEXT: th.mveqz a5, a7, a0937; RV32-THEAD-NEXT: mv a0, a4938; RV32-THEAD-NEXT: mv a1, a5939; RV32-THEAD-NEXT: ret940;941; RV32-XQCICM-LABEL: select_i64_ne:942; RV32-XQCICM: # %bb.0:943; RV32-XQCICM-NEXT: xor a1, a1, a3944; RV32-XQCICM-NEXT: xor a0, a0, a2945; RV32-XQCICM-NEXT: or a0, a0, a1946; RV32-XQCICM-NEXT: qc.mveqi a4, a0, 0, a6947; RV32-XQCICM-NEXT: qc.mveqi a5, a0, 0, a7948; RV32-XQCICM-NEXT: mv a0, a4949; RV32-XQCICM-NEXT: mv a1, a5950; RV32-XQCICM-NEXT: ret951;952; RV32-XQCICS-LABEL: select_i64_ne:953; RV32-XQCICS: # %bb.0:954; RV32-XQCICS-NEXT: xor a1, a1, a3955; RV32-XQCICS-NEXT: xor a0, a0, a2956; RV32-XQCICS-NEXT: or a1, a0, a1957; RV32-XQCICS-NEXT: mv a0, a1958; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6959; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7960; RV32-XQCICS-NEXT: ret961;962; RV32IXQCI-LABEL: select_i64_ne:963; RV32IXQCI: # %bb.0:964; RV32IXQCI-NEXT: xor a1, a1, a3965; RV32IXQCI-NEXT: xor a0, a0, a2966; RV32IXQCI-NEXT: or a0, a0, a1967; RV32IXQCI-NEXT: qc.mveqi a4, a0, 0, a6968; RV32IXQCI-NEXT: qc.mveqi a5, a0, 0, a7969; RV32IXQCI-NEXT: mv a0, a4970; RV32IXQCI-NEXT: mv a1, a5971; RV32IXQCI-NEXT: ret972;973; RV64-LABEL: select_i64_ne:974; RV64: # %bb.0:975; RV64-NEXT: bne a0, a1, .LBB15_2976; RV64-NEXT: # %bb.1:977; RV64-NEXT: mv a2, a3978; RV64-NEXT: .LBB15_2:979; RV64-NEXT: mv a0, a2980; RV64-NEXT: ret981;982; RV64-MIPS-LABEL: select_i64_ne:983; RV64-MIPS: # %bb.0:984; RV64-MIPS-NEXT: xor a0, a0, a1985; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a3986; RV64-MIPS-NEXT: ret987 %cond = icmp ne i64 %a, %b988 %res = select i1 %cond, i64 %x, i64 %y989 ret i64 %res990}991 992define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {993; RV32-LABEL: select_i64_ugt:994; RV32: # %bb.0:995; RV32-NEXT: beq a1, a3, .LBB16_2996; RV32-NEXT: # %bb.1:997; RV32-NEXT: sltu a0, a3, a1998; RV32-NEXT: beqz a0, .LBB16_3999; RV32-NEXT: j .LBB16_41000; RV32-NEXT: .LBB16_2:1001; RV32-NEXT: sltu a0, a2, a01002; RV32-NEXT: bnez a0, .LBB16_41003; RV32-NEXT: .LBB16_3:1004; RV32-NEXT: mv a4, a61005; RV32-NEXT: mv a5, a71006; RV32-NEXT: .LBB16_4:1007; RV32-NEXT: mv a0, a41008; RV32-NEXT: mv a1, a51009; RV32-NEXT: ret1010;1011; RV32-THEAD-LABEL: select_i64_ugt:1012; RV32-THEAD: # %bb.0:1013; RV32-THEAD-NEXT: xor t0, a1, a31014; RV32-THEAD-NEXT: sltu a1, a3, a11015; RV32-THEAD-NEXT: sltu a0, a2, a01016; RV32-THEAD-NEXT: th.mvnez a0, a1, t01017; RV32-THEAD-NEXT: th.mveqz a4, a6, a01018; RV32-THEAD-NEXT: th.mveqz a5, a7, a01019; RV32-THEAD-NEXT: mv a0, a41020; RV32-THEAD-NEXT: mv a1, a51021; RV32-THEAD-NEXT: ret1022;1023; RV32-XQCICM-LABEL: select_i64_ugt:1024; RV32-XQCICM: # %bb.0:1025; RV32-XQCICM-NEXT: sltu a0, a2, a01026; RV32-XQCICM-NEXT: sltu a2, a3, a11027; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01028; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a61029; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a71030; RV32-XQCICM-NEXT: mv a0, a41031; RV32-XQCICM-NEXT: mv a1, a51032; RV32-XQCICM-NEXT: ret1033;1034; RV32-XQCICS-LABEL: select_i64_ugt:1035; RV32-XQCICS: # %bb.0:1036; RV32-XQCICS-NEXT: beq a1, a3, .LBB16_21037; RV32-XQCICS-NEXT: # %bb.1:1038; RV32-XQCICS-NEXT: sltu a1, a3, a11039; RV32-XQCICS-NEXT: j .LBB16_31040; RV32-XQCICS-NEXT: .LBB16_2:1041; RV32-XQCICS-NEXT: sltu a1, a2, a01042; RV32-XQCICS-NEXT: .LBB16_3:1043; RV32-XQCICS-NEXT: mv a0, a11044; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a71045; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a61046; RV32-XQCICS-NEXT: ret1047;1048; RV32IXQCI-LABEL: select_i64_ugt:1049; RV32IXQCI: # %bb.0:1050; RV32IXQCI-NEXT: sltu a0, a2, a01051; RV32IXQCI-NEXT: sltu a2, a3, a11052; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01053; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a61054; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a71055; RV32IXQCI-NEXT: mv a0, a41056; RV32IXQCI-NEXT: mv a1, a51057; RV32IXQCI-NEXT: ret1058;1059; RV64-LABEL: select_i64_ugt:1060; RV64: # %bb.0:1061; RV64-NEXT: bltu a1, a0, .LBB16_21062; RV64-NEXT: # %bb.1:1063; RV64-NEXT: mv a2, a31064; RV64-NEXT: .LBB16_2:1065; RV64-NEXT: mv a0, a21066; RV64-NEXT: ret1067;1068; RV64-MIPS-LABEL: select_i64_ugt:1069; RV64-MIPS: # %bb.0:1070; RV64-MIPS-NEXT: sltu a0, a1, a01071; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a31072; RV64-MIPS-NEXT: ret1073 %cond = icmp ugt i64 %a, %b1074 %res = select i1 %cond, i64 %x, i64 %y1075 ret i64 %res1076}1077 1078define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {1079; RV32-LABEL: select_i64_uge:1080; RV32: # %bb.0:1081; RV32-NEXT: beq a1, a3, .LBB17_21082; RV32-NEXT: # %bb.1:1083; RV32-NEXT: sltu a0, a1, a31084; RV32-NEXT: bnez a0, .LBB17_31085; RV32-NEXT: j .LBB17_41086; RV32-NEXT: .LBB17_2:1087; RV32-NEXT: sltu a0, a0, a21088; RV32-NEXT: beqz a0, .LBB17_41089; RV32-NEXT: .LBB17_3:1090; RV32-NEXT: mv a4, a61091; RV32-NEXT: mv a5, a71092; RV32-NEXT: .LBB17_4:1093; RV32-NEXT: mv a0, a41094; RV32-NEXT: mv a1, a51095; RV32-NEXT: ret1096;1097; RV32-THEAD-LABEL: select_i64_uge:1098; RV32-THEAD: # %bb.0:1099; RV32-THEAD-NEXT: xor t0, a1, a31100; RV32-THEAD-NEXT: sltu a1, a1, a31101; RV32-THEAD-NEXT: sltu a0, a0, a21102; RV32-THEAD-NEXT: th.mvnez a0, a1, t01103; RV32-THEAD-NEXT: th.mvnez a4, a6, a01104; RV32-THEAD-NEXT: th.mvnez a5, a7, a01105; RV32-THEAD-NEXT: mv a0, a41106; RV32-THEAD-NEXT: mv a1, a51107; RV32-THEAD-NEXT: ret1108;1109; RV32-XQCICM-LABEL: select_i64_uge:1110; RV32-XQCICM: # %bb.0:1111; RV32-XQCICM-NEXT: sltu a0, a0, a21112; RV32-XQCICM-NEXT: sltu a2, a1, a31113; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01114; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a61115; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a71116; RV32-XQCICM-NEXT: mv a0, a41117; RV32-XQCICM-NEXT: mv a1, a51118; RV32-XQCICM-NEXT: ret1119;1120; RV32-XQCICS-LABEL: select_i64_uge:1121; RV32-XQCICS: # %bb.0:1122; RV32-XQCICS-NEXT: beq a1, a3, .LBB17_21123; RV32-XQCICS-NEXT: # %bb.1:1124; RV32-XQCICS-NEXT: sltu a1, a1, a31125; RV32-XQCICS-NEXT: j .LBB17_31126; RV32-XQCICS-NEXT: .LBB17_2:1127; RV32-XQCICS-NEXT: sltu a1, a0, a21128; RV32-XQCICS-NEXT: .LBB17_3:1129; RV32-XQCICS-NEXT: mv a0, a11130; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a71131; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a61132; RV32-XQCICS-NEXT: ret1133;1134; RV32IXQCI-LABEL: select_i64_uge:1135; RV32IXQCI: # %bb.0:1136; RV32IXQCI-NEXT: sltu a0, a0, a21137; RV32IXQCI-NEXT: sltu a2, a1, a31138; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01139; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a61140; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a71141; RV32IXQCI-NEXT: mv a0, a41142; RV32IXQCI-NEXT: mv a1, a51143; RV32IXQCI-NEXT: ret1144;1145; RV64-LABEL: select_i64_uge:1146; RV64: # %bb.0:1147; RV64-NEXT: bgeu a0, a1, .LBB17_21148; RV64-NEXT: # %bb.1:1149; RV64-NEXT: mv a2, a31150; RV64-NEXT: .LBB17_2:1151; RV64-NEXT: mv a0, a21152; RV64-NEXT: ret1153;1154; RV64-MIPS-LABEL: select_i64_uge:1155; RV64-MIPS: # %bb.0:1156; RV64-MIPS-NEXT: sltu a0, a0, a11157; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a21158; RV64-MIPS-NEXT: ret1159 %cond = icmp uge i64 %a, %b1160 %res = select i1 %cond, i64 %x, i64 %y1161 ret i64 %res1162}1163 1164define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {1165; RV32-LABEL: select_i64_ult:1166; RV32: # %bb.0:1167; RV32-NEXT: beq a1, a3, .LBB18_21168; RV32-NEXT: # %bb.1:1169; RV32-NEXT: sltu a0, a1, a31170; RV32-NEXT: beqz a0, .LBB18_31171; RV32-NEXT: j .LBB18_41172; RV32-NEXT: .LBB18_2:1173; RV32-NEXT: sltu a0, a0, a21174; RV32-NEXT: bnez a0, .LBB18_41175; RV32-NEXT: .LBB18_3:1176; RV32-NEXT: mv a4, a61177; RV32-NEXT: mv a5, a71178; RV32-NEXT: .LBB18_4:1179; RV32-NEXT: mv a0, a41180; RV32-NEXT: mv a1, a51181; RV32-NEXT: ret1182;1183; RV32-THEAD-LABEL: select_i64_ult:1184; RV32-THEAD: # %bb.0:1185; RV32-THEAD-NEXT: xor t0, a1, a31186; RV32-THEAD-NEXT: sltu a1, a1, a31187; RV32-THEAD-NEXT: sltu a0, a0, a21188; RV32-THEAD-NEXT: th.mvnez a0, a1, t01189; RV32-THEAD-NEXT: th.mveqz a4, a6, a01190; RV32-THEAD-NEXT: th.mveqz a5, a7, a01191; RV32-THEAD-NEXT: mv a0, a41192; RV32-THEAD-NEXT: mv a1, a51193; RV32-THEAD-NEXT: ret1194;1195; RV32-XQCICM-LABEL: select_i64_ult:1196; RV32-XQCICM: # %bb.0:1197; RV32-XQCICM-NEXT: sltu a0, a0, a21198; RV32-XQCICM-NEXT: sltu a2, a1, a31199; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01200; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a61201; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a71202; RV32-XQCICM-NEXT: mv a0, a41203; RV32-XQCICM-NEXT: mv a1, a51204; RV32-XQCICM-NEXT: ret1205;1206; RV32-XQCICS-LABEL: select_i64_ult:1207; RV32-XQCICS: # %bb.0:1208; RV32-XQCICS-NEXT: beq a1, a3, .LBB18_21209; RV32-XQCICS-NEXT: # %bb.1:1210; RV32-XQCICS-NEXT: sltu a1, a1, a31211; RV32-XQCICS-NEXT: j .LBB18_31212; RV32-XQCICS-NEXT: .LBB18_2:1213; RV32-XQCICS-NEXT: sltu a1, a0, a21214; RV32-XQCICS-NEXT: .LBB18_3:1215; RV32-XQCICS-NEXT: mv a0, a11216; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a71217; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a61218; RV32-XQCICS-NEXT: ret1219;1220; RV32IXQCI-LABEL: select_i64_ult:1221; RV32IXQCI: # %bb.0:1222; RV32IXQCI-NEXT: sltu a0, a0, a21223; RV32IXQCI-NEXT: sltu a2, a1, a31224; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01225; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a61226; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a71227; RV32IXQCI-NEXT: mv a0, a41228; RV32IXQCI-NEXT: mv a1, a51229; RV32IXQCI-NEXT: ret1230;1231; RV64-LABEL: select_i64_ult:1232; RV64: # %bb.0:1233; RV64-NEXT: bltu a0, a1, .LBB18_21234; RV64-NEXT: # %bb.1:1235; RV64-NEXT: mv a2, a31236; RV64-NEXT: .LBB18_2:1237; RV64-NEXT: mv a0, a21238; RV64-NEXT: ret1239;1240; RV64-MIPS-LABEL: select_i64_ult:1241; RV64-MIPS: # %bb.0:1242; RV64-MIPS-NEXT: sltu a0, a0, a11243; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a31244; RV64-MIPS-NEXT: ret1245 %cond = icmp ult i64 %a, %b1246 %res = select i1 %cond, i64 %x, i64 %y1247 ret i64 %res1248}1249 1250define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {1251; RV32-LABEL: select_i64_ule:1252; RV32: # %bb.0:1253; RV32-NEXT: beq a1, a3, .LBB19_21254; RV32-NEXT: # %bb.1:1255; RV32-NEXT: sltu a0, a3, a11256; RV32-NEXT: bnez a0, .LBB19_31257; RV32-NEXT: j .LBB19_41258; RV32-NEXT: .LBB19_2:1259; RV32-NEXT: sltu a0, a2, a01260; RV32-NEXT: beqz a0, .LBB19_41261; RV32-NEXT: .LBB19_3:1262; RV32-NEXT: mv a4, a61263; RV32-NEXT: mv a5, a71264; RV32-NEXT: .LBB19_4:1265; RV32-NEXT: mv a0, a41266; RV32-NEXT: mv a1, a51267; RV32-NEXT: ret1268;1269; RV32-THEAD-LABEL: select_i64_ule:1270; RV32-THEAD: # %bb.0:1271; RV32-THEAD-NEXT: xor t0, a1, a31272; RV32-THEAD-NEXT: sltu a1, a3, a11273; RV32-THEAD-NEXT: sltu a0, a2, a01274; RV32-THEAD-NEXT: th.mvnez a0, a1, t01275; RV32-THEAD-NEXT: th.mvnez a4, a6, a01276; RV32-THEAD-NEXT: th.mvnez a5, a7, a01277; RV32-THEAD-NEXT: mv a0, a41278; RV32-THEAD-NEXT: mv a1, a51279; RV32-THEAD-NEXT: ret1280;1281; RV32-XQCICM-LABEL: select_i64_ule:1282; RV32-XQCICM: # %bb.0:1283; RV32-XQCICM-NEXT: sltu a0, a2, a01284; RV32-XQCICM-NEXT: sltu a2, a3, a11285; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01286; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a61287; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a71288; RV32-XQCICM-NEXT: mv a0, a41289; RV32-XQCICM-NEXT: mv a1, a51290; RV32-XQCICM-NEXT: ret1291;1292; RV32-XQCICS-LABEL: select_i64_ule:1293; RV32-XQCICS: # %bb.0:1294; RV32-XQCICS-NEXT: beq a1, a3, .LBB19_21295; RV32-XQCICS-NEXT: # %bb.1:1296; RV32-XQCICS-NEXT: sltu a1, a3, a11297; RV32-XQCICS-NEXT: j .LBB19_31298; RV32-XQCICS-NEXT: .LBB19_2:1299; RV32-XQCICS-NEXT: sltu a1, a2, a01300; RV32-XQCICS-NEXT: .LBB19_3:1301; RV32-XQCICS-NEXT: mv a0, a11302; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a71303; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a61304; RV32-XQCICS-NEXT: ret1305;1306; RV32IXQCI-LABEL: select_i64_ule:1307; RV32IXQCI: # %bb.0:1308; RV32IXQCI-NEXT: sltu a0, a2, a01309; RV32IXQCI-NEXT: sltu a2, a3, a11310; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01311; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a61312; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a71313; RV32IXQCI-NEXT: mv a0, a41314; RV32IXQCI-NEXT: mv a1, a51315; RV32IXQCI-NEXT: ret1316;1317; RV64-LABEL: select_i64_ule:1318; RV64: # %bb.0:1319; RV64-NEXT: bgeu a1, a0, .LBB19_21320; RV64-NEXT: # %bb.1:1321; RV64-NEXT: mv a2, a31322; RV64-NEXT: .LBB19_2:1323; RV64-NEXT: mv a0, a21324; RV64-NEXT: ret1325;1326; RV64-MIPS-LABEL: select_i64_ule:1327; RV64-MIPS: # %bb.0:1328; RV64-MIPS-NEXT: sltu a0, a1, a01329; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a21330; RV64-MIPS-NEXT: ret1331 %cond = icmp ule i64 %a, %b1332 %res = select i1 %cond, i64 %x, i64 %y1333 ret i64 %res1334}1335 1336define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {1337; RV32-LABEL: select_i64_sgt:1338; RV32: # %bb.0:1339; RV32-NEXT: beq a1, a3, .LBB20_21340; RV32-NEXT: # %bb.1:1341; RV32-NEXT: slt a0, a3, a11342; RV32-NEXT: beqz a0, .LBB20_31343; RV32-NEXT: j .LBB20_41344; RV32-NEXT: .LBB20_2:1345; RV32-NEXT: sltu a0, a2, a01346; RV32-NEXT: bnez a0, .LBB20_41347; RV32-NEXT: .LBB20_3:1348; RV32-NEXT: mv a4, a61349; RV32-NEXT: mv a5, a71350; RV32-NEXT: .LBB20_4:1351; RV32-NEXT: mv a0, a41352; RV32-NEXT: mv a1, a51353; RV32-NEXT: ret1354;1355; RV32-THEAD-LABEL: select_i64_sgt:1356; RV32-THEAD: # %bb.0:1357; RV32-THEAD-NEXT: xor t0, a1, a31358; RV32-THEAD-NEXT: slt a1, a3, a11359; RV32-THEAD-NEXT: sltu a0, a2, a01360; RV32-THEAD-NEXT: th.mvnez a0, a1, t01361; RV32-THEAD-NEXT: th.mveqz a4, a6, a01362; RV32-THEAD-NEXT: th.mveqz a5, a7, a01363; RV32-THEAD-NEXT: mv a0, a41364; RV32-THEAD-NEXT: mv a1, a51365; RV32-THEAD-NEXT: ret1366;1367; RV32-XQCICM-LABEL: select_i64_sgt:1368; RV32-XQCICM: # %bb.0:1369; RV32-XQCICM-NEXT: sltu a0, a2, a01370; RV32-XQCICM-NEXT: slt a2, a3, a11371; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01372; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a61373; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a71374; RV32-XQCICM-NEXT: mv a0, a41375; RV32-XQCICM-NEXT: mv a1, a51376; RV32-XQCICM-NEXT: ret1377;1378; RV32-XQCICS-LABEL: select_i64_sgt:1379; RV32-XQCICS: # %bb.0:1380; RV32-XQCICS-NEXT: beq a1, a3, .LBB20_21381; RV32-XQCICS-NEXT: # %bb.1:1382; RV32-XQCICS-NEXT: slt a1, a3, a11383; RV32-XQCICS-NEXT: j .LBB20_31384; RV32-XQCICS-NEXT: .LBB20_2:1385; RV32-XQCICS-NEXT: sltu a1, a2, a01386; RV32-XQCICS-NEXT: .LBB20_3:1387; RV32-XQCICS-NEXT: mv a0, a11388; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a71389; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a61390; RV32-XQCICS-NEXT: ret1391;1392; RV32IXQCI-LABEL: select_i64_sgt:1393; RV32IXQCI: # %bb.0:1394; RV32IXQCI-NEXT: sltu a0, a2, a01395; RV32IXQCI-NEXT: slt a2, a3, a11396; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01397; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a61398; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a71399; RV32IXQCI-NEXT: mv a0, a41400; RV32IXQCI-NEXT: mv a1, a51401; RV32IXQCI-NEXT: ret1402;1403; RV64-LABEL: select_i64_sgt:1404; RV64: # %bb.0:1405; RV64-NEXT: blt a1, a0, .LBB20_21406; RV64-NEXT: # %bb.1:1407; RV64-NEXT: mv a2, a31408; RV64-NEXT: .LBB20_2:1409; RV64-NEXT: mv a0, a21410; RV64-NEXT: ret1411;1412; RV64-MIPS-LABEL: select_i64_sgt:1413; RV64-MIPS: # %bb.0:1414; RV64-MIPS-NEXT: slt a0, a1, a01415; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a31416; RV64-MIPS-NEXT: ret1417 %cond = icmp sgt i64 %a, %b1418 %res = select i1 %cond, i64 %x, i64 %y1419 ret i64 %res1420}1421 1422define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {1423; RV32-LABEL: select_i64_sge:1424; RV32: # %bb.0:1425; RV32-NEXT: beq a1, a3, .LBB21_21426; RV32-NEXT: # %bb.1:1427; RV32-NEXT: slt a0, a1, a31428; RV32-NEXT: bnez a0, .LBB21_31429; RV32-NEXT: j .LBB21_41430; RV32-NEXT: .LBB21_2:1431; RV32-NEXT: sltu a0, a0, a21432; RV32-NEXT: beqz a0, .LBB21_41433; RV32-NEXT: .LBB21_3:1434; RV32-NEXT: mv a4, a61435; RV32-NEXT: mv a5, a71436; RV32-NEXT: .LBB21_4:1437; RV32-NEXT: mv a0, a41438; RV32-NEXT: mv a1, a51439; RV32-NEXT: ret1440;1441; RV32-THEAD-LABEL: select_i64_sge:1442; RV32-THEAD: # %bb.0:1443; RV32-THEAD-NEXT: xor t0, a1, a31444; RV32-THEAD-NEXT: slt a1, a1, a31445; RV32-THEAD-NEXT: sltu a0, a0, a21446; RV32-THEAD-NEXT: th.mvnez a0, a1, t01447; RV32-THEAD-NEXT: th.mvnez a4, a6, a01448; RV32-THEAD-NEXT: th.mvnez a5, a7, a01449; RV32-THEAD-NEXT: mv a0, a41450; RV32-THEAD-NEXT: mv a1, a51451; RV32-THEAD-NEXT: ret1452;1453; RV32-XQCICM-LABEL: select_i64_sge:1454; RV32-XQCICM: # %bb.0:1455; RV32-XQCICM-NEXT: sltu a0, a0, a21456; RV32-XQCICM-NEXT: slt a2, a1, a31457; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01458; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a61459; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a71460; RV32-XQCICM-NEXT: mv a0, a41461; RV32-XQCICM-NEXT: mv a1, a51462; RV32-XQCICM-NEXT: ret1463;1464; RV32-XQCICS-LABEL: select_i64_sge:1465; RV32-XQCICS: # %bb.0:1466; RV32-XQCICS-NEXT: beq a1, a3, .LBB21_21467; RV32-XQCICS-NEXT: # %bb.1:1468; RV32-XQCICS-NEXT: slt a1, a1, a31469; RV32-XQCICS-NEXT: j .LBB21_31470; RV32-XQCICS-NEXT: .LBB21_2:1471; RV32-XQCICS-NEXT: sltu a1, a0, a21472; RV32-XQCICS-NEXT: .LBB21_3:1473; RV32-XQCICS-NEXT: mv a0, a11474; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a71475; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a61476; RV32-XQCICS-NEXT: ret1477;1478; RV32IXQCI-LABEL: select_i64_sge:1479; RV32IXQCI: # %bb.0:1480; RV32IXQCI-NEXT: sltu a0, a0, a21481; RV32IXQCI-NEXT: slt a2, a1, a31482; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01483; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a61484; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a71485; RV32IXQCI-NEXT: mv a0, a41486; RV32IXQCI-NEXT: mv a1, a51487; RV32IXQCI-NEXT: ret1488;1489; RV64-LABEL: select_i64_sge:1490; RV64: # %bb.0:1491; RV64-NEXT: bge a0, a1, .LBB21_21492; RV64-NEXT: # %bb.1:1493; RV64-NEXT: mv a2, a31494; RV64-NEXT: .LBB21_2:1495; RV64-NEXT: mv a0, a21496; RV64-NEXT: ret1497;1498; RV64-MIPS-LABEL: select_i64_sge:1499; RV64-MIPS: # %bb.0:1500; RV64-MIPS-NEXT: slt a0, a0, a11501; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a21502; RV64-MIPS-NEXT: ret1503 %cond = icmp sge i64 %a, %b1504 %res = select i1 %cond, i64 %x, i64 %y1505 ret i64 %res1506}1507 1508define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {1509; RV32-LABEL: select_i64_slt:1510; RV32: # %bb.0:1511; RV32-NEXT: beq a1, a3, .LBB22_21512; RV32-NEXT: # %bb.1:1513; RV32-NEXT: slt a0, a1, a31514; RV32-NEXT: beqz a0, .LBB22_31515; RV32-NEXT: j .LBB22_41516; RV32-NEXT: .LBB22_2:1517; RV32-NEXT: sltu a0, a0, a21518; RV32-NEXT: bnez a0, .LBB22_41519; RV32-NEXT: .LBB22_3:1520; RV32-NEXT: mv a4, a61521; RV32-NEXT: mv a5, a71522; RV32-NEXT: .LBB22_4:1523; RV32-NEXT: mv a0, a41524; RV32-NEXT: mv a1, a51525; RV32-NEXT: ret1526;1527; RV32-THEAD-LABEL: select_i64_slt:1528; RV32-THEAD: # %bb.0:1529; RV32-THEAD-NEXT: xor t0, a1, a31530; RV32-THEAD-NEXT: slt a1, a1, a31531; RV32-THEAD-NEXT: sltu a0, a0, a21532; RV32-THEAD-NEXT: th.mvnez a0, a1, t01533; RV32-THEAD-NEXT: th.mveqz a4, a6, a01534; RV32-THEAD-NEXT: th.mveqz a5, a7, a01535; RV32-THEAD-NEXT: mv a0, a41536; RV32-THEAD-NEXT: mv a1, a51537; RV32-THEAD-NEXT: ret1538;1539; RV32-XQCICM-LABEL: select_i64_slt:1540; RV32-XQCICM: # %bb.0:1541; RV32-XQCICM-NEXT: sltu a0, a0, a21542; RV32-XQCICM-NEXT: slt a2, a1, a31543; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01544; RV32-XQCICM-NEXT: qc.mveqi a4, a2, 0, a61545; RV32-XQCICM-NEXT: qc.mveqi a5, a2, 0, a71546; RV32-XQCICM-NEXT: mv a0, a41547; RV32-XQCICM-NEXT: mv a1, a51548; RV32-XQCICM-NEXT: ret1549;1550; RV32-XQCICS-LABEL: select_i64_slt:1551; RV32-XQCICS: # %bb.0:1552; RV32-XQCICS-NEXT: beq a1, a3, .LBB22_21553; RV32-XQCICS-NEXT: # %bb.1:1554; RV32-XQCICS-NEXT: slt a1, a1, a31555; RV32-XQCICS-NEXT: j .LBB22_31556; RV32-XQCICS-NEXT: .LBB22_2:1557; RV32-XQCICS-NEXT: sltu a1, a0, a21558; RV32-XQCICS-NEXT: .LBB22_3:1559; RV32-XQCICS-NEXT: mv a0, a11560; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a71561; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a61562; RV32-XQCICS-NEXT: ret1563;1564; RV32IXQCI-LABEL: select_i64_slt:1565; RV32IXQCI: # %bb.0:1566; RV32IXQCI-NEXT: sltu a0, a0, a21567; RV32IXQCI-NEXT: slt a2, a1, a31568; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01569; RV32IXQCI-NEXT: qc.mveqi a4, a2, 0, a61570; RV32IXQCI-NEXT: qc.mveqi a5, a2, 0, a71571; RV32IXQCI-NEXT: mv a0, a41572; RV32IXQCI-NEXT: mv a1, a51573; RV32IXQCI-NEXT: ret1574;1575; RV64-LABEL: select_i64_slt:1576; RV64: # %bb.0:1577; RV64-NEXT: blt a0, a1, .LBB22_21578; RV64-NEXT: # %bb.1:1579; RV64-NEXT: mv a2, a31580; RV64-NEXT: .LBB22_2:1581; RV64-NEXT: mv a0, a21582; RV64-NEXT: ret1583;1584; RV64-MIPS-LABEL: select_i64_slt:1585; RV64-MIPS: # %bb.0:1586; RV64-MIPS-NEXT: slt a0, a0, a11587; RV64-MIPS-NEXT: mips.ccmov a0, a0, a2, a31588; RV64-MIPS-NEXT: ret1589 %cond = icmp slt i64 %a, %b1590 %res = select i1 %cond, i64 %x, i64 %y1591 ret i64 %res1592}1593 1594define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {1595; RV32-LABEL: select_i64_sle:1596; RV32: # %bb.0:1597; RV32-NEXT: beq a1, a3, .LBB23_21598; RV32-NEXT: # %bb.1:1599; RV32-NEXT: slt a0, a3, a11600; RV32-NEXT: bnez a0, .LBB23_31601; RV32-NEXT: j .LBB23_41602; RV32-NEXT: .LBB23_2:1603; RV32-NEXT: sltu a0, a2, a01604; RV32-NEXT: beqz a0, .LBB23_41605; RV32-NEXT: .LBB23_3:1606; RV32-NEXT: mv a4, a61607; RV32-NEXT: mv a5, a71608; RV32-NEXT: .LBB23_4:1609; RV32-NEXT: mv a0, a41610; RV32-NEXT: mv a1, a51611; RV32-NEXT: ret1612;1613; RV32-THEAD-LABEL: select_i64_sle:1614; RV32-THEAD: # %bb.0:1615; RV32-THEAD-NEXT: xor t0, a1, a31616; RV32-THEAD-NEXT: slt a1, a3, a11617; RV32-THEAD-NEXT: sltu a0, a2, a01618; RV32-THEAD-NEXT: th.mvnez a0, a1, t01619; RV32-THEAD-NEXT: th.mvnez a4, a6, a01620; RV32-THEAD-NEXT: th.mvnez a5, a7, a01621; RV32-THEAD-NEXT: mv a0, a41622; RV32-THEAD-NEXT: mv a1, a51623; RV32-THEAD-NEXT: ret1624;1625; RV32-XQCICM-LABEL: select_i64_sle:1626; RV32-XQCICM: # %bb.0:1627; RV32-XQCICM-NEXT: sltu a0, a2, a01628; RV32-XQCICM-NEXT: slt a2, a3, a11629; RV32-XQCICM-NEXT: qc.mveq a2, a1, a3, a01630; RV32-XQCICM-NEXT: qc.mvnei a4, a2, 0, a61631; RV32-XQCICM-NEXT: qc.mvnei a5, a2, 0, a71632; RV32-XQCICM-NEXT: mv a0, a41633; RV32-XQCICM-NEXT: mv a1, a51634; RV32-XQCICM-NEXT: ret1635;1636; RV32-XQCICS-LABEL: select_i64_sle:1637; RV32-XQCICS: # %bb.0:1638; RV32-XQCICS-NEXT: beq a1, a3, .LBB23_21639; RV32-XQCICS-NEXT: # %bb.1:1640; RV32-XQCICS-NEXT: slt a1, a3, a11641; RV32-XQCICS-NEXT: j .LBB23_31642; RV32-XQCICS-NEXT: .LBB23_2:1643; RV32-XQCICS-NEXT: sltu a1, a2, a01644; RV32-XQCICS-NEXT: .LBB23_3:1645; RV32-XQCICS-NEXT: mv a0, a11646; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a71647; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a61648; RV32-XQCICS-NEXT: ret1649;1650; RV32IXQCI-LABEL: select_i64_sle:1651; RV32IXQCI: # %bb.0:1652; RV32IXQCI-NEXT: sltu a0, a2, a01653; RV32IXQCI-NEXT: slt a2, a3, a11654; RV32IXQCI-NEXT: qc.mveq a2, a1, a3, a01655; RV32IXQCI-NEXT: qc.mvnei a4, a2, 0, a61656; RV32IXQCI-NEXT: qc.mvnei a5, a2, 0, a71657; RV32IXQCI-NEXT: mv a0, a41658; RV32IXQCI-NEXT: mv a1, a51659; RV32IXQCI-NEXT: ret1660;1661; RV64-LABEL: select_i64_sle:1662; RV64: # %bb.0:1663; RV64-NEXT: bge a1, a0, .LBB23_21664; RV64-NEXT: # %bb.1:1665; RV64-NEXT: mv a2, a31666; RV64-NEXT: .LBB23_2:1667; RV64-NEXT: mv a0, a21668; RV64-NEXT: ret1669;1670; RV64-MIPS-LABEL: select_i64_sle:1671; RV64-MIPS: # %bb.0:1672; RV64-MIPS-NEXT: slt a0, a1, a01673; RV64-MIPS-NEXT: mips.ccmov a0, a0, a3, a21674; RV64-MIPS-NEXT: ret1675 %cond = icmp sle i64 %a, %b1676 %res = select i1 %cond, i64 %x, i64 %y1677 ret i64 %res1678}1679 1680