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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefixes=RV32,RV32I %s4; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s6; RUN: llc -mtriple=riscv32 -mattr=+zicond -target-abi=ilp32 -verify-machineinstrs < %s \7; RUN: | FileCheck -check-prefixes=RV32,RV32ZICOND %s8; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \9; RUN: | FileCheck %s --check-prefixes=RV32IXQCI10; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \11; RUN: | FileCheck -check-prefixes=RV64,RV64I %s12; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \13; RUN: | FileCheck -check-prefixes=RV64,RV64IFD %s14; RUN: llc -mtriple=riscv64 -mattr=+zicond -target-abi=lp64 -verify-machineinstrs < %s \15; RUN: | FileCheck -check-prefixes=RV64,RV64ZICOND %s16 17;; This tests how good we are at materialising constants using `select`. The aim18;; is that we do so without a branch if possible (at the moment our lowering of19;; select always introduces a branch).20;;21;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the22;; constants are either 1 away from each other, or one is a power of two and23;; the other is zero.24 25define signext i32 @select_const_int_easy(i1 zeroext %a) nounwind {26; RV32-LABEL: select_const_int_easy:27; RV32: # %bb.0:28; RV32-NEXT: ret29;30; RV32IXQCI-LABEL: select_const_int_easy:31; RV32IXQCI: # %bb.0:32; RV32IXQCI-NEXT: ret33;34; RV64-LABEL: select_const_int_easy:35; RV64: # %bb.0:36; RV64-NEXT: ret37 %1 = select i1 %a, i32 1, i32 038 ret i32 %139}40 41define signext i32 @select_const_int_one_away(i1 zeroext %a) nounwind {42; RV32-LABEL: select_const_int_one_away:43; RV32: # %bb.0:44; RV32-NEXT: li a1, 445; RV32-NEXT: sub a0, a1, a046; RV32-NEXT: ret47;48; RV32IXQCI-LABEL: select_const_int_one_away:49; RV32IXQCI: # %bb.0:50; RV32IXQCI-NEXT: li a1, 451; RV32IXQCI-NEXT: sub a0, a1, a052; RV32IXQCI-NEXT: ret53;54; RV64-LABEL: select_const_int_one_away:55; RV64: # %bb.0:56; RV64-NEXT: li a1, 457; RV64-NEXT: sub a0, a1, a058; RV64-NEXT: ret59 %1 = select i1 %a, i32 3, i32 460 ret i32 %161}62 63define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {64; RV32-LABEL: select_const_int_pow2_zero:65; RV32: # %bb.0:66; RV32-NEXT: slli a0, a0, 267; RV32-NEXT: ret68;69; RV32IXQCI-LABEL: select_const_int_pow2_zero:70; RV32IXQCI: # %bb.0:71; RV32IXQCI-NEXT: slli a0, a0, 272; RV32IXQCI-NEXT: ret73;74; RV64-LABEL: select_const_int_pow2_zero:75; RV64: # %bb.0:76; RV64-NEXT: slli a0, a0, 277; RV64-NEXT: ret78 %1 = select i1 %a, i32 4, i32 079 ret i32 %180}81 82define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {83; RV32I-LABEL: select_const_int_harder:84; RV32I: # %bb.0:85; RV32I-NEXT: bnez a0, .LBB3_286; RV32I-NEXT: # %bb.1:87; RV32I-NEXT: li a0, 3888; RV32I-NEXT: ret89; RV32I-NEXT: .LBB3_2:90; RV32I-NEXT: li a0, 691; RV32I-NEXT: ret92;93; RV32IF-LABEL: select_const_int_harder:94; RV32IF: # %bb.0:95; RV32IF-NEXT: bnez a0, .LBB3_296; RV32IF-NEXT: # %bb.1:97; RV32IF-NEXT: li a0, 3898; RV32IF-NEXT: ret99; RV32IF-NEXT: .LBB3_2:100; RV32IF-NEXT: li a0, 6101; RV32IF-NEXT: ret102;103; RV32ZICOND-LABEL: select_const_int_harder:104; RV32ZICOND: # %bb.0:105; RV32ZICOND-NEXT: xori a0, a0, 1106; RV32ZICOND-NEXT: slli a0, a0, 5107; RV32ZICOND-NEXT: addi a0, a0, 6108; RV32ZICOND-NEXT: ret109;110; RV32IXQCI-LABEL: select_const_int_harder:111; RV32IXQCI: # %bb.0:112; RV32IXQCI-NEXT: li a1, 38113; RV32IXQCI-NEXT: qc.selectieqi a0, 0, a1, 6114; RV32IXQCI-NEXT: ret115;116; RV64I-LABEL: select_const_int_harder:117; RV64I: # %bb.0:118; RV64I-NEXT: bnez a0, .LBB3_2119; RV64I-NEXT: # %bb.1:120; RV64I-NEXT: li a0, 38121; RV64I-NEXT: ret122; RV64I-NEXT: .LBB3_2:123; RV64I-NEXT: li a0, 6124; RV64I-NEXT: ret125;126; RV64IFD-LABEL: select_const_int_harder:127; RV64IFD: # %bb.0:128; RV64IFD-NEXT: bnez a0, .LBB3_2129; RV64IFD-NEXT: # %bb.1:130; RV64IFD-NEXT: li a0, 38131; RV64IFD-NEXT: ret132; RV64IFD-NEXT: .LBB3_2:133; RV64IFD-NEXT: li a0, 6134; RV64IFD-NEXT: ret135;136; RV64ZICOND-LABEL: select_const_int_harder:137; RV64ZICOND: # %bb.0:138; RV64ZICOND-NEXT: xori a0, a0, 1139; RV64ZICOND-NEXT: slli a0, a0, 5140; RV64ZICOND-NEXT: addiw a0, a0, 6141; RV64ZICOND-NEXT: ret142 %1 = select i1 %a, i32 6, i32 38143 ret i32 %1144}145 146define float @select_const_fp(i1 zeroext %a) nounwind {147; RV32I-LABEL: select_const_fp:148; RV32I: # %bb.0:149; RV32I-NEXT: mv a1, a0150; RV32I-NEXT: lui a0, 263168151; RV32I-NEXT: bnez a1, .LBB4_2152; RV32I-NEXT: # %bb.1:153; RV32I-NEXT: lui a0, 264192154; RV32I-NEXT: .LBB4_2:155; RV32I-NEXT: ret156;157; RV32IF-LABEL: select_const_fp:158; RV32IF: # %bb.0:159; RV32IF-NEXT: bnez a0, .LBB4_2160; RV32IF-NEXT: # %bb.1:161; RV32IF-NEXT: lui a0, 264192162; RV32IF-NEXT: j .LBB4_3163; RV32IF-NEXT: .LBB4_2:164; RV32IF-NEXT: lui a0, 263168165; RV32IF-NEXT: .LBB4_3:166; RV32IF-NEXT: fmv.w.x fa5, a0167; RV32IF-NEXT: fmv.x.w a0, fa5168; RV32IF-NEXT: ret169;170; RV32ZICOND-LABEL: select_const_fp:171; RV32ZICOND: # %bb.0:172; RV32ZICOND-NEXT: lui a1, 1024173; RV32ZICOND-NEXT: czero.nez a0, a1, a0174; RV32ZICOND-NEXT: lui a1, 263168175; RV32ZICOND-NEXT: add a0, a0, a1176; RV32ZICOND-NEXT: ret177;178; RV32IXQCI-LABEL: select_const_fp:179; RV32IXQCI: # %bb.0:180; RV32IXQCI-NEXT: lui a1, 264192181; RV32IXQCI-NEXT: beqz a0, .LBB4_2182; RV32IXQCI-NEXT: # %bb.1:183; RV32IXQCI-NEXT: lui a1, 263168184; RV32IXQCI-NEXT: .LBB4_2:185; RV32IXQCI-NEXT: mv a0, a1186; RV32IXQCI-NEXT: ret187;188; RV64I-LABEL: select_const_fp:189; RV64I: # %bb.0:190; RV64I-NEXT: mv a1, a0191; RV64I-NEXT: lui a0, 263168192; RV64I-NEXT: bnez a1, .LBB4_2193; RV64I-NEXT: # %bb.1:194; RV64I-NEXT: lui a0, 264192195; RV64I-NEXT: .LBB4_2:196; RV64I-NEXT: ret197;198; RV64IFD-LABEL: select_const_fp:199; RV64IFD: # %bb.0:200; RV64IFD-NEXT: bnez a0, .LBB4_2201; RV64IFD-NEXT: # %bb.1:202; RV64IFD-NEXT: lui a0, 264192203; RV64IFD-NEXT: j .LBB4_3204; RV64IFD-NEXT: .LBB4_2:205; RV64IFD-NEXT: lui a0, 263168206; RV64IFD-NEXT: .LBB4_3:207; RV64IFD-NEXT: fmv.w.x fa5, a0208; RV64IFD-NEXT: fmv.x.w a0, fa5209; RV64IFD-NEXT: ret210;211; RV64ZICOND-LABEL: select_const_fp:212; RV64ZICOND: # %bb.0:213; RV64ZICOND-NEXT: lui a1, 1024214; RV64ZICOND-NEXT: czero.nez a0, a1, a0215; RV64ZICOND-NEXT: lui a1, 263168216; RV64ZICOND-NEXT: add a0, a0, a1217; RV64ZICOND-NEXT: ret218 %1 = select i1 %a, float 3.0, float 4.0219 ret float %1220}221 222define signext i32 @select_eq_zero_negone(i32 signext %a, i32 signext %b) nounwind {223; RV32-LABEL: select_eq_zero_negone:224; RV32: # %bb.0:225; RV32-NEXT: xor a0, a0, a1226; RV32-NEXT: snez a0, a0227; RV32-NEXT: addi a0, a0, -1228; RV32-NEXT: ret229;230; RV32IXQCI-LABEL: select_eq_zero_negone:231; RV32IXQCI: # %bb.0:232; RV32IXQCI-NEXT: xor a0, a0, a1233; RV32IXQCI-NEXT: snez a0, a0234; RV32IXQCI-NEXT: addi a0, a0, -1235; RV32IXQCI-NEXT: ret236;237; RV64-LABEL: select_eq_zero_negone:238; RV64: # %bb.0:239; RV64-NEXT: xor a0, a0, a1240; RV64-NEXT: snez a0, a0241; RV64-NEXT: addi a0, a0, -1242; RV64-NEXT: ret243 %1 = icmp eq i32 %a, %b244 %2 = select i1 %1, i32 -1, i32 0245 ret i32 %2246}247 248define signext i32 @select_ne_zero_negone(i32 signext %a, i32 signext %b) nounwind {249; RV32-LABEL: select_ne_zero_negone:250; RV32: # %bb.0:251; RV32-NEXT: xor a0, a0, a1252; RV32-NEXT: seqz a0, a0253; RV32-NEXT: addi a0, a0, -1254; RV32-NEXT: ret255;256; RV32IXQCI-LABEL: select_ne_zero_negone:257; RV32IXQCI: # %bb.0:258; RV32IXQCI-NEXT: xor a0, a0, a1259; RV32IXQCI-NEXT: seqz a0, a0260; RV32IXQCI-NEXT: addi a0, a0, -1261; RV32IXQCI-NEXT: ret262;263; RV64-LABEL: select_ne_zero_negone:264; RV64: # %bb.0:265; RV64-NEXT: xor a0, a0, a1266; RV64-NEXT: seqz a0, a0267; RV64-NEXT: addi a0, a0, -1268; RV64-NEXT: ret269 %1 = icmp ne i32 %a, %b270 %2 = select i1 %1, i32 -1, i32 0271 ret i32 %2272}273 274define signext i32 @select_sgt_zero_negone(i32 signext %a, i32 signext %b) nounwind {275; RV32-LABEL: select_sgt_zero_negone:276; RV32: # %bb.0:277; RV32-NEXT: slt a0, a1, a0278; RV32-NEXT: neg a0, a0279; RV32-NEXT: ret280;281; RV32IXQCI-LABEL: select_sgt_zero_negone:282; RV32IXQCI: # %bb.0:283; RV32IXQCI-NEXT: slt a0, a1, a0284; RV32IXQCI-NEXT: neg a0, a0285; RV32IXQCI-NEXT: ret286;287; RV64-LABEL: select_sgt_zero_negone:288; RV64: # %bb.0:289; RV64-NEXT: slt a0, a1, a0290; RV64-NEXT: neg a0, a0291; RV64-NEXT: ret292 %1 = icmp sgt i32 %a, %b293 %2 = select i1 %1, i32 -1, i32 0294 ret i32 %2295}296 297define signext i32 @select_slt_zero_negone(i32 signext %a, i32 signext %b) nounwind {298; RV32-LABEL: select_slt_zero_negone:299; RV32: # %bb.0:300; RV32-NEXT: slt a0, a0, a1301; RV32-NEXT: neg a0, a0302; RV32-NEXT: ret303;304; RV32IXQCI-LABEL: select_slt_zero_negone:305; RV32IXQCI: # %bb.0:306; RV32IXQCI-NEXT: slt a0, a0, a1307; RV32IXQCI-NEXT: neg a0, a0308; RV32IXQCI-NEXT: ret309;310; RV64-LABEL: select_slt_zero_negone:311; RV64: # %bb.0:312; RV64-NEXT: slt a0, a0, a1313; RV64-NEXT: neg a0, a0314; RV64-NEXT: ret315 %1 = icmp slt i32 %a, %b316 %2 = select i1 %1, i32 -1, i32 0317 ret i32 %2318}319 320define signext i32 @select_sge_zero_negone(i32 signext %a, i32 signext %b) nounwind {321; RV32-LABEL: select_sge_zero_negone:322; RV32: # %bb.0:323; RV32-NEXT: slt a0, a0, a1324; RV32-NEXT: addi a0, a0, -1325; RV32-NEXT: ret326;327; RV32IXQCI-LABEL: select_sge_zero_negone:328; RV32IXQCI: # %bb.0:329; RV32IXQCI-NEXT: slt a0, a0, a1330; RV32IXQCI-NEXT: addi a0, a0, -1331; RV32IXQCI-NEXT: ret332;333; RV64-LABEL: select_sge_zero_negone:334; RV64: # %bb.0:335; RV64-NEXT: slt a0, a0, a1336; RV64-NEXT: addi a0, a0, -1337; RV64-NEXT: ret338 %1 = icmp sge i32 %a, %b339 %2 = select i1 %1, i32 -1, i32 0340 ret i32 %2341}342 343define signext i32 @select_sle_zero_negone(i32 signext %a, i32 signext %b) nounwind {344; RV32-LABEL: select_sle_zero_negone:345; RV32: # %bb.0:346; RV32-NEXT: slt a0, a1, a0347; RV32-NEXT: addi a0, a0, -1348; RV32-NEXT: ret349;350; RV32IXQCI-LABEL: select_sle_zero_negone:351; RV32IXQCI: # %bb.0:352; RV32IXQCI-NEXT: slt a0, a1, a0353; RV32IXQCI-NEXT: addi a0, a0, -1354; RV32IXQCI-NEXT: ret355;356; RV64-LABEL: select_sle_zero_negone:357; RV64: # %bb.0:358; RV64-NEXT: slt a0, a1, a0359; RV64-NEXT: addi a0, a0, -1360; RV64-NEXT: ret361 %1 = icmp sle i32 %a, %b362 %2 = select i1 %1, i32 -1, i32 0363 ret i32 %2364}365 366define signext i32 @select_ugt_zero_negone(i32 signext %a, i32 signext %b) nounwind {367; RV32-LABEL: select_ugt_zero_negone:368; RV32: # %bb.0:369; RV32-NEXT: sltu a0, a1, a0370; RV32-NEXT: neg a0, a0371; RV32-NEXT: ret372;373; RV32IXQCI-LABEL: select_ugt_zero_negone:374; RV32IXQCI: # %bb.0:375; RV32IXQCI-NEXT: sltu a0, a1, a0376; RV32IXQCI-NEXT: neg a0, a0377; RV32IXQCI-NEXT: ret378;379; RV64-LABEL: select_ugt_zero_negone:380; RV64: # %bb.0:381; RV64-NEXT: sltu a0, a1, a0382; RV64-NEXT: neg a0, a0383; RV64-NEXT: ret384 %1 = icmp ugt i32 %a, %b385 %2 = select i1 %1, i32 -1, i32 0386 ret i32 %2387}388 389define signext i32 @select_ult_zero_negone(i32 signext %a, i32 signext %b) nounwind {390; RV32-LABEL: select_ult_zero_negone:391; RV32: # %bb.0:392; RV32-NEXT: sltu a0, a0, a1393; RV32-NEXT: neg a0, a0394; RV32-NEXT: ret395;396; RV32IXQCI-LABEL: select_ult_zero_negone:397; RV32IXQCI: # %bb.0:398; RV32IXQCI-NEXT: sltu a0, a0, a1399; RV32IXQCI-NEXT: neg a0, a0400; RV32IXQCI-NEXT: ret401;402; RV64-LABEL: select_ult_zero_negone:403; RV64: # %bb.0:404; RV64-NEXT: sltu a0, a0, a1405; RV64-NEXT: neg a0, a0406; RV64-NEXT: ret407 %1 = icmp ult i32 %a, %b408 %2 = select i1 %1, i32 -1, i32 0409 ret i32 %2410}411 412define signext i32 @select_uge_zero_negone(i32 signext %a, i32 signext %b) nounwind {413; RV32-LABEL: select_uge_zero_negone:414; RV32: # %bb.0:415; RV32-NEXT: sltu a0, a0, a1416; RV32-NEXT: addi a0, a0, -1417; RV32-NEXT: ret418;419; RV32IXQCI-LABEL: select_uge_zero_negone:420; RV32IXQCI: # %bb.0:421; RV32IXQCI-NEXT: sltu a0, a0, a1422; RV32IXQCI-NEXT: addi a0, a0, -1423; RV32IXQCI-NEXT: ret424;425; RV64-LABEL: select_uge_zero_negone:426; RV64: # %bb.0:427; RV64-NEXT: sltu a0, a0, a1428; RV64-NEXT: addi a0, a0, -1429; RV64-NEXT: ret430 %1 = icmp uge i32 %a, %b431 %2 = select i1 %1, i32 -1, i32 0432 ret i32 %2433}434 435define signext i32 @select_ule_zero_negone(i32 signext %a, i32 signext %b) nounwind {436; RV32-LABEL: select_ule_zero_negone:437; RV32: # %bb.0:438; RV32-NEXT: sltu a0, a1, a0439; RV32-NEXT: addi a0, a0, -1440; RV32-NEXT: ret441;442; RV32IXQCI-LABEL: select_ule_zero_negone:443; RV32IXQCI: # %bb.0:444; RV32IXQCI-NEXT: sltu a0, a1, a0445; RV32IXQCI-NEXT: addi a0, a0, -1446; RV32IXQCI-NEXT: ret447;448; RV64-LABEL: select_ule_zero_negone:449; RV64: # %bb.0:450; RV64-NEXT: sltu a0, a1, a0451; RV64-NEXT: addi a0, a0, -1452; RV64-NEXT: ret453 %1 = icmp ule i32 %a, %b454 %2 = select i1 %1, i32 -1, i32 0455 ret i32 %2456}457 458define i32 @select_eq_1_2(i32 signext %a, i32 signext %b) {459; RV32-LABEL: select_eq_1_2:460; RV32: # %bb.0:461; RV32-NEXT: xor a0, a0, a1462; RV32-NEXT: snez a0, a0463; RV32-NEXT: addi a0, a0, 1464; RV32-NEXT: ret465;466; RV32IXQCI-LABEL: select_eq_1_2:467; RV32IXQCI: # %bb.0:468; RV32IXQCI-NEXT: xor a0, a0, a1469; RV32IXQCI-NEXT: snez a0, a0470; RV32IXQCI-NEXT: addi a0, a0, 1471; RV32IXQCI-NEXT: ret472;473; RV64-LABEL: select_eq_1_2:474; RV64: # %bb.0:475; RV64-NEXT: xor a0, a0, a1476; RV64-NEXT: snez a0, a0477; RV64-NEXT: addi a0, a0, 1478; RV64-NEXT: ret479 %1 = icmp eq i32 %a, %b480 %2 = select i1 %1, i32 1, i32 2481 ret i32 %2482}483 484define i32 @select_ne_1_2(i32 signext %a, i32 signext %b) {485; RV32-LABEL: select_ne_1_2:486; RV32: # %bb.0:487; RV32-NEXT: xor a0, a0, a1488; RV32-NEXT: seqz a0, a0489; RV32-NEXT: addi a0, a0, 1490; RV32-NEXT: ret491;492; RV32IXQCI-LABEL: select_ne_1_2:493; RV32IXQCI: # %bb.0:494; RV32IXQCI-NEXT: xor a0, a0, a1495; RV32IXQCI-NEXT: seqz a0, a0496; RV32IXQCI-NEXT: addi a0, a0, 1497; RV32IXQCI-NEXT: ret498;499; RV64-LABEL: select_ne_1_2:500; RV64: # %bb.0:501; RV64-NEXT: xor a0, a0, a1502; RV64-NEXT: seqz a0, a0503; RV64-NEXT: addi a0, a0, 1504; RV64-NEXT: ret505 %1 = icmp ne i32 %a, %b506 %2 = select i1 %1, i32 1, i32 2507 ret i32 %2508}509 510define i32 @select_eq_10000_10001(i32 signext %a, i32 signext %b) {511; RV32-LABEL: select_eq_10000_10001:512; RV32: # %bb.0:513; RV32-NEXT: xor a0, a0, a1514; RV32-NEXT: lui a1, 2515; RV32-NEXT: seqz a0, a0516; RV32-NEXT: addi a1, a1, 1810517; RV32-NEXT: sub a0, a1, a0518; RV32-NEXT: ret519;520; RV32IXQCI-LABEL: select_eq_10000_10001:521; RV32IXQCI: # %bb.0:522; RV32IXQCI-NEXT: xor a0, a0, a1523; RV32IXQCI-NEXT: lui a1, 2524; RV32IXQCI-NEXT: seqz a0, a0525; RV32IXQCI-NEXT: addi a1, a1, 1810526; RV32IXQCI-NEXT: sub a0, a1, a0527; RV32IXQCI-NEXT: ret528;529; RV64-LABEL: select_eq_10000_10001:530; RV64: # %bb.0:531; RV64-NEXT: xor a0, a0, a1532; RV64-NEXT: lui a1, 2533; RV64-NEXT: seqz a0, a0534; RV64-NEXT: addi a1, a1, 1810535; RV64-NEXT: sub a0, a1, a0536; RV64-NEXT: ret537 %1 = icmp eq i32 %a, %b538 %2 = select i1 %1, i32 10001, i32 10002539 ret i32 %2540}541 542define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {543; RV32-LABEL: select_ne_10001_10002:544; RV32: # %bb.0:545; RV32-NEXT: xor a0, a0, a1546; RV32-NEXT: lui a1, 2547; RV32-NEXT: snez a0, a0548; RV32-NEXT: addi a1, a1, 1810549; RV32-NEXT: sub a0, a1, a0550; RV32-NEXT: ret551;552; RV32IXQCI-LABEL: select_ne_10001_10002:553; RV32IXQCI: # %bb.0:554; RV32IXQCI-NEXT: xor a0, a0, a1555; RV32IXQCI-NEXT: lui a1, 2556; RV32IXQCI-NEXT: snez a0, a0557; RV32IXQCI-NEXT: addi a1, a1, 1810558; RV32IXQCI-NEXT: sub a0, a1, a0559; RV32IXQCI-NEXT: ret560;561; RV64-LABEL: select_ne_10001_10002:562; RV64: # %bb.0:563; RV64-NEXT: xor a0, a0, a1564; RV64-NEXT: lui a1, 2565; RV64-NEXT: snez a0, a0566; RV64-NEXT: addi a1, a1, 1810567; RV64-NEXT: sub a0, a1, a0568; RV64-NEXT: ret569 %1 = icmp ne i32 %a, %b570 %2 = select i1 %1, i32 10001, i32 10002571 ret i32 %2572}573 574define i32 @select_slt_zero_constant1_constant2(i32 signext %x) {575; RV32-LABEL: select_slt_zero_constant1_constant2:576; RV32: # %bb.0:577; RV32-NEXT: srai a0, a0, 31578; RV32-NEXT: andi a0, a0, 10579; RV32-NEXT: addi a0, a0, -3580; RV32-NEXT: ret581;582; RV32IXQCI-LABEL: select_slt_zero_constant1_constant2:583; RV32IXQCI: # %bb.0:584; RV32IXQCI-NEXT: li a1, -3585; RV32IXQCI-NEXT: qc.lilti a1, a0, 0, 7586; RV32IXQCI-NEXT: mv a0, a1587; RV32IXQCI-NEXT: ret588;589; RV64-LABEL: select_slt_zero_constant1_constant2:590; RV64: # %bb.0:591; RV64-NEXT: srai a0, a0, 63592; RV64-NEXT: andi a0, a0, 10593; RV64-NEXT: addi a0, a0, -3594; RV64-NEXT: ret595 %cmp = icmp slt i32 %x, 0596 %cond = select i1 %cmp, i32 7, i32 -3597 ret i32 %cond598}599 600define i32 @select_sgt_negative_one_constant1_constant2(i32 signext %x) {601; RV32-LABEL: select_sgt_negative_one_constant1_constant2:602; RV32: # %bb.0:603; RV32-NEXT: srai a0, a0, 31604; RV32-NEXT: andi a0, a0, -10605; RV32-NEXT: addi a0, a0, 7606; RV32-NEXT: ret607;608; RV32IXQCI-LABEL: select_sgt_negative_one_constant1_constant2:609; RV32IXQCI: # %bb.0:610; RV32IXQCI-NEXT: li a1, -3611; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 7612; RV32IXQCI-NEXT: mv a0, a1613; RV32IXQCI-NEXT: ret614;615; RV64-LABEL: select_sgt_negative_one_constant1_constant2:616; RV64: # %bb.0:617; RV64-NEXT: srai a0, a0, 63618; RV64-NEXT: andi a0, a0, -10619; RV64-NEXT: addi a0, a0, 7620; RV64-NEXT: ret621 %cmp = icmp sgt i32 %x, -1622 %cond = select i1 %cmp, i32 7, i32 -3623 ret i32 %cond624}625 626define i32 @select_nonnegative_lui_addi(i32 signext %x) {627; RV32I-LABEL: select_nonnegative_lui_addi:628; RV32I: # %bb.0:629; RV32I-NEXT: mv a1, a0630; RV32I-NEXT: lui a0, 4631; RV32I-NEXT: bgez a1, .LBB21_2632; RV32I-NEXT: # %bb.1:633; RV32I-NEXT: li a0, 25634; RV32I-NEXT: .LBB21_2:635; RV32I-NEXT: ret636;637; RV32IF-LABEL: select_nonnegative_lui_addi:638; RV32IF: # %bb.0:639; RV32IF-NEXT: mv a1, a0640; RV32IF-NEXT: lui a0, 4641; RV32IF-NEXT: bgez a1, .LBB21_2642; RV32IF-NEXT: # %bb.1:643; RV32IF-NEXT: li a0, 25644; RV32IF-NEXT: .LBB21_2:645; RV32IF-NEXT: ret646;647; RV32ZICOND-LABEL: select_nonnegative_lui_addi:648; RV32ZICOND: # %bb.0:649; RV32ZICOND-NEXT: srli a0, a0, 31650; RV32ZICOND-NEXT: lui a1, 4651; RV32ZICOND-NEXT: addi a1, a1, -25652; RV32ZICOND-NEXT: czero.nez a0, a1, a0653; RV32ZICOND-NEXT: addi a0, a0, 25654; RV32ZICOND-NEXT: ret655;656; RV32IXQCI-LABEL: select_nonnegative_lui_addi:657; RV32IXQCI: # %bb.0:658; RV32IXQCI-NEXT: li a1, 25659; RV32IXQCI-NEXT: bltz a0, .LBB21_2660; RV32IXQCI-NEXT: # %bb.1:661; RV32IXQCI-NEXT: lui a1, 4662; RV32IXQCI-NEXT: .LBB21_2:663; RV32IXQCI-NEXT: mv a0, a1664; RV32IXQCI-NEXT: ret665;666; RV64I-LABEL: select_nonnegative_lui_addi:667; RV64I: # %bb.0:668; RV64I-NEXT: mv a1, a0669; RV64I-NEXT: lui a0, 4670; RV64I-NEXT: bgez a1, .LBB21_2671; RV64I-NEXT: # %bb.1:672; RV64I-NEXT: li a0, 25673; RV64I-NEXT: .LBB21_2:674; RV64I-NEXT: ret675;676; RV64IFD-LABEL: select_nonnegative_lui_addi:677; RV64IFD: # %bb.0:678; RV64IFD-NEXT: mv a1, a0679; RV64IFD-NEXT: lui a0, 4680; RV64IFD-NEXT: bgez a1, .LBB21_2681; RV64IFD-NEXT: # %bb.1:682; RV64IFD-NEXT: li a0, 25683; RV64IFD-NEXT: .LBB21_2:684; RV64IFD-NEXT: ret685;686; RV64ZICOND-LABEL: select_nonnegative_lui_addi:687; RV64ZICOND: # %bb.0:688; RV64ZICOND-NEXT: srli a0, a0, 63689; RV64ZICOND-NEXT: lui a1, 4690; RV64ZICOND-NEXT: addi a1, a1, -25691; RV64ZICOND-NEXT: czero.nez a0, a1, a0692; RV64ZICOND-NEXT: addi a0, a0, 25693; RV64ZICOND-NEXT: ret694 %cmp = icmp sgt i32 %x, -1695 %cond = select i1 %cmp, i32 16384, i32 25696 ret i32 %cond697}698 699define i32 @select_nonnegative_lui_addi_swapped(i32 signext %x) {700; RV32I-LABEL: select_nonnegative_lui_addi_swapped:701; RV32I: # %bb.0:702; RV32I-NEXT: bgez a0, .LBB22_2703; RV32I-NEXT: # %bb.1:704; RV32I-NEXT: lui a0, 4705; RV32I-NEXT: ret706; RV32I-NEXT: .LBB22_2:707; RV32I-NEXT: li a0, 25708; RV32I-NEXT: ret709;710; RV32IF-LABEL: select_nonnegative_lui_addi_swapped:711; RV32IF: # %bb.0:712; RV32IF-NEXT: bgez a0, .LBB22_2713; RV32IF-NEXT: # %bb.1:714; RV32IF-NEXT: lui a0, 4715; RV32IF-NEXT: ret716; RV32IF-NEXT: .LBB22_2:717; RV32IF-NEXT: li a0, 25718; RV32IF-NEXT: ret719;720; RV32ZICOND-LABEL: select_nonnegative_lui_addi_swapped:721; RV32ZICOND: # %bb.0:722; RV32ZICOND-NEXT: srli a0, a0, 31723; RV32ZICOND-NEXT: lui a1, 4724; RV32ZICOND-NEXT: addi a1, a1, -25725; RV32ZICOND-NEXT: czero.eqz a0, a1, a0726; RV32ZICOND-NEXT: addi a0, a0, 25727; RV32ZICOND-NEXT: ret728;729; RV32IXQCI-LABEL: select_nonnegative_lui_addi_swapped:730; RV32IXQCI: # %bb.0:731; RV32IXQCI-NEXT: li a1, 25732; RV32IXQCI-NEXT: bgez a0, .LBB22_2733; RV32IXQCI-NEXT: # %bb.1:734; RV32IXQCI-NEXT: lui a1, 4735; RV32IXQCI-NEXT: .LBB22_2:736; RV32IXQCI-NEXT: mv a0, a1737; RV32IXQCI-NEXT: ret738;739; RV64I-LABEL: select_nonnegative_lui_addi_swapped:740; RV64I: # %bb.0:741; RV64I-NEXT: bgez a0, .LBB22_2742; RV64I-NEXT: # %bb.1:743; RV64I-NEXT: lui a0, 4744; RV64I-NEXT: ret745; RV64I-NEXT: .LBB22_2:746; RV64I-NEXT: li a0, 25747; RV64I-NEXT: ret748;749; RV64IFD-LABEL: select_nonnegative_lui_addi_swapped:750; RV64IFD: # %bb.0:751; RV64IFD-NEXT: bgez a0, .LBB22_2752; RV64IFD-NEXT: # %bb.1:753; RV64IFD-NEXT: lui a0, 4754; RV64IFD-NEXT: ret755; RV64IFD-NEXT: .LBB22_2:756; RV64IFD-NEXT: li a0, 25757; RV64IFD-NEXT: ret758;759; RV64ZICOND-LABEL: select_nonnegative_lui_addi_swapped:760; RV64ZICOND: # %bb.0:761; RV64ZICOND-NEXT: srli a0, a0, 63762; RV64ZICOND-NEXT: lui a1, 4763; RV64ZICOND-NEXT: addi a1, a1, -25764; RV64ZICOND-NEXT: czero.eqz a0, a1, a0765; RV64ZICOND-NEXT: addi a0, a0, 25766; RV64ZICOND-NEXT: ret767 %cmp = icmp sgt i32 %x, -1768 %cond = select i1 %cmp, i32 25, i32 16384769 ret i32 %cond770}771 772 773 774define i32 @diff_shl_addi(i32 signext %x) {775; RV32I-LABEL: diff_shl_addi:776; RV32I: # %bb.0:777; RV32I-NEXT: bgez a0, .LBB23_2778; RV32I-NEXT: # %bb.1:779; RV32I-NEXT: lui a0, 4780; RV32I-NEXT: addi a0, a0, 25781; RV32I-NEXT: ret782; RV32I-NEXT: .LBB23_2:783; RV32I-NEXT: li a0, 25784; RV32I-NEXT: ret785;786; RV32IF-LABEL: diff_shl_addi:787; RV32IF: # %bb.0:788; RV32IF-NEXT: bgez a0, .LBB23_2789; RV32IF-NEXT: # %bb.1:790; RV32IF-NEXT: lui a0, 4791; RV32IF-NEXT: addi a0, a0, 25792; RV32IF-NEXT: ret793; RV32IF-NEXT: .LBB23_2:794; RV32IF-NEXT: li a0, 25795; RV32IF-NEXT: ret796;797; RV32ZICOND-LABEL: diff_shl_addi:798; RV32ZICOND: # %bb.0:799; RV32ZICOND-NEXT: srli a0, a0, 31800; RV32ZICOND-NEXT: slli a0, a0, 14801; RV32ZICOND-NEXT: addi a0, a0, 25802; RV32ZICOND-NEXT: ret803;804; RV32IXQCI-LABEL: diff_shl_addi:805; RV32IXQCI: # %bb.0:806; RV32IXQCI-NEXT: lui a2, 4807; RV32IXQCI-NEXT: li a1, 25808; RV32IXQCI-NEXT: bgez a0, .LBB23_2809; RV32IXQCI-NEXT: # %bb.1:810; RV32IXQCI-NEXT: addi a1, a2, 25811; RV32IXQCI-NEXT: .LBB23_2:812; RV32IXQCI-NEXT: mv a0, a1813; RV32IXQCI-NEXT: ret814;815; RV64I-LABEL: diff_shl_addi:816; RV64I: # %bb.0:817; RV64I-NEXT: bgez a0, .LBB23_2818; RV64I-NEXT: # %bb.1:819; RV64I-NEXT: lui a0, 4820; RV64I-NEXT: addi a0, a0, 25821; RV64I-NEXT: ret822; RV64I-NEXT: .LBB23_2:823; RV64I-NEXT: li a0, 25824; RV64I-NEXT: ret825;826; RV64IFD-LABEL: diff_shl_addi:827; RV64IFD: # %bb.0:828; RV64IFD-NEXT: bgez a0, .LBB23_2829; RV64IFD-NEXT: # %bb.1:830; RV64IFD-NEXT: lui a0, 4831; RV64IFD-NEXT: addi a0, a0, 25832; RV64IFD-NEXT: ret833; RV64IFD-NEXT: .LBB23_2:834; RV64IFD-NEXT: li a0, 25835; RV64IFD-NEXT: ret836;837; RV64ZICOND-LABEL: diff_shl_addi:838; RV64ZICOND: # %bb.0:839; RV64ZICOND-NEXT: srli a0, a0, 63840; RV64ZICOND-NEXT: slli a0, a0, 14841; RV64ZICOND-NEXT: addiw a0, a0, 25842; RV64ZICOND-NEXT: ret843 %cmp = icmp sgt i32 %x, -1844 %cond = select i1 %cmp, i32 25, i32 16409845 ret i32 %cond846}847 848define i32 @diff_shl_addi2(i32 signext %x) {849; RV32I-LABEL: diff_shl_addi2:850; RV32I: # %bb.0:851; RV32I-NEXT: bgez a0, .LBB24_2852; RV32I-NEXT: # %bb.1:853; RV32I-NEXT: li a0, 25854; RV32I-NEXT: ret855; RV32I-NEXT: .LBB24_2:856; RV32I-NEXT: lui a0, 4857; RV32I-NEXT: addi a0, a0, 25858; RV32I-NEXT: ret859;860; RV32IF-LABEL: diff_shl_addi2:861; RV32IF: # %bb.0:862; RV32IF-NEXT: bgez a0, .LBB24_2863; RV32IF-NEXT: # %bb.1:864; RV32IF-NEXT: li a0, 25865; RV32IF-NEXT: ret866; RV32IF-NEXT: .LBB24_2:867; RV32IF-NEXT: lui a0, 4868; RV32IF-NEXT: addi a0, a0, 25869; RV32IF-NEXT: ret870;871; RV32ZICOND-LABEL: diff_shl_addi2:872; RV32ZICOND: # %bb.0:873; RV32ZICOND-NEXT: srli a0, a0, 31874; RV32ZICOND-NEXT: xori a0, a0, 1875; RV32ZICOND-NEXT: slli a0, a0, 14876; RV32ZICOND-NEXT: addi a0, a0, 25877; RV32ZICOND-NEXT: ret878;879; RV32IXQCI-LABEL: diff_shl_addi2:880; RV32IXQCI: # %bb.0:881; RV32IXQCI-NEXT: lui a2, 4882; RV32IXQCI-NEXT: li a1, 25883; RV32IXQCI-NEXT: bltz a0, .LBB24_2884; RV32IXQCI-NEXT: # %bb.1:885; RV32IXQCI-NEXT: addi a1, a2, 25886; RV32IXQCI-NEXT: .LBB24_2:887; RV32IXQCI-NEXT: mv a0, a1888; RV32IXQCI-NEXT: ret889;890; RV64I-LABEL: diff_shl_addi2:891; RV64I: # %bb.0:892; RV64I-NEXT: bgez a0, .LBB24_2893; RV64I-NEXT: # %bb.1:894; RV64I-NEXT: li a0, 25895; RV64I-NEXT: ret896; RV64I-NEXT: .LBB24_2:897; RV64I-NEXT: lui a0, 4898; RV64I-NEXT: addi a0, a0, 25899; RV64I-NEXT: ret900;901; RV64IFD-LABEL: diff_shl_addi2:902; RV64IFD: # %bb.0:903; RV64IFD-NEXT: bgez a0, .LBB24_2904; RV64IFD-NEXT: # %bb.1:905; RV64IFD-NEXT: li a0, 25906; RV64IFD-NEXT: ret907; RV64IFD-NEXT: .LBB24_2:908; RV64IFD-NEXT: lui a0, 4909; RV64IFD-NEXT: addi a0, a0, 25910; RV64IFD-NEXT: ret911;912; RV64ZICOND-LABEL: diff_shl_addi2:913; RV64ZICOND: # %bb.0:914; RV64ZICOND-NEXT: srli a0, a0, 63915; RV64ZICOND-NEXT: xori a0, a0, 1916; RV64ZICOND-NEXT: slli a0, a0, 14917; RV64ZICOND-NEXT: addiw a0, a0, 25918; RV64ZICOND-NEXT: ret919 %cmp = icmp sgt i32 %x, -1920 %cond = select i1 %cmp, i32 16409, i32 25921 ret i32 %cond922}923 924define i32 @diff_pow2_24_16(i32 signext %x) {925; RV32-LABEL: diff_pow2_24_16:926; RV32: # %bb.0:927; RV32-NEXT: srai a0, a0, 31928; RV32-NEXT: andi a0, a0, -8929; RV32-NEXT: addi a0, a0, 24930; RV32-NEXT: ret931;932; RV32IXQCI-LABEL: diff_pow2_24_16:933; RV32IXQCI: # %bb.0:934; RV32IXQCI-NEXT: li a2, 24935; RV32IXQCI-NEXT: li a1, 16936; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2937; RV32IXQCI-NEXT: mv a0, a1938; RV32IXQCI-NEXT: ret939;940; RV64-LABEL: diff_pow2_24_16:941; RV64: # %bb.0:942; RV64-NEXT: srai a0, a0, 63943; RV64-NEXT: andi a0, a0, -8944; RV64-NEXT: addi a0, a0, 24945; RV64-NEXT: ret946 %cmp = icmp sgt i32 %x, -1947 %cond = select i1 %cmp, i32 24, i32 16948 ret i32 %cond949}950 951define i32 @diff_pow2_16_24(i32 signext %x) {952; RV32-LABEL: diff_pow2_16_24:953; RV32: # %bb.0:954; RV32-NEXT: srli a0, a0, 28955; RV32-NEXT: andi a0, a0, 8956; RV32-NEXT: addi a0, a0, 16957; RV32-NEXT: ret958;959; RV32IXQCI-LABEL: diff_pow2_16_24:960; RV32IXQCI: # %bb.0:961; RV32IXQCI-NEXT: li a2, 16962; RV32IXQCI-NEXT: li a1, 24963; RV32IXQCI-NEXT: qc.mvgei a1, a0, 0, a2964; RV32IXQCI-NEXT: mv a0, a1965; RV32IXQCI-NEXT: ret966;967; RV64-LABEL: diff_pow2_16_24:968; RV64: # %bb.0:969; RV64-NEXT: srli a0, a0, 60970; RV64-NEXT: andi a0, a0, 8971; RV64-NEXT: addiw a0, a0, 16972; RV64-NEXT: ret973 %cmp = icmp sgt i32 %x, -1974 %cond = select i1 %cmp, i32 16, i32 24975 ret i32 %cond976}977 978define i32 @zext_or_constant(i32 signext %x) {979; RV32I-LABEL: zext_or_constant:980; RV32I: # %bb.0:981; RV32I-NEXT: bgez a0, .LBB27_2982; RV32I-NEXT: # %bb.1:983; RV32I-NEXT: lui a0, 140984; RV32I-NEXT: addi a0, a0, 417985; RV32I-NEXT: ret986; RV32I-NEXT: .LBB27_2:987; RV32I-NEXT: srli a0, a0, 31988; RV32I-NEXT: xori a0, a0, 1989; RV32I-NEXT: ret990;991; RV32IF-LABEL: zext_or_constant:992; RV32IF: # %bb.0:993; RV32IF-NEXT: bgez a0, .LBB27_2994; RV32IF-NEXT: # %bb.1:995; RV32IF-NEXT: lui a0, 140996; RV32IF-NEXT: addi a0, a0, 417997; RV32IF-NEXT: ret998; RV32IF-NEXT: .LBB27_2:999; RV32IF-NEXT: srli a0, a0, 311000; RV32IF-NEXT: xori a0, a0, 11001; RV32IF-NEXT: ret1002;1003; RV32ZICOND-LABEL: zext_or_constant:1004; RV32ZICOND: # %bb.0:1005; RV32ZICOND-NEXT: srli a0, a0, 311006; RV32ZICOND-NEXT: lui a1, 1401007; RV32ZICOND-NEXT: xori a2, a0, 11008; RV32ZICOND-NEXT: addi a1, a1, 4171009; RV32ZICOND-NEXT: czero.eqz a0, a1, a01010; RV32ZICOND-NEXT: or a0, a2, a01011; RV32ZICOND-NEXT: ret1012;1013; RV32IXQCI-LABEL: zext_or_constant:1014; RV32IXQCI: # %bb.0:1015; RV32IXQCI-NEXT: srli a2, a0, 311016; RV32IXQCI-NEXT: lui a1, 1401017; RV32IXQCI-NEXT: addi a1, a1, 4171018; RV32IXQCI-NEXT: bltz a0, .LBB27_21019; RV32IXQCI-NEXT: # %bb.1:1020; RV32IXQCI-NEXT: xori a1, a2, 11021; RV32IXQCI-NEXT: .LBB27_2:1022; RV32IXQCI-NEXT: mv a0, a11023; RV32IXQCI-NEXT: ret1024;1025; RV64I-LABEL: zext_or_constant:1026; RV64I: # %bb.0:1027; RV64I-NEXT: bgez a0, .LBB27_21028; RV64I-NEXT: # %bb.1:1029; RV64I-NEXT: lui a0, 1401030; RV64I-NEXT: addi a0, a0, 4171031; RV64I-NEXT: ret1032; RV64I-NEXT: .LBB27_2:1033; RV64I-NEXT: srli a0, a0, 631034; RV64I-NEXT: xori a0, a0, 11035; RV64I-NEXT: ret1036;1037; RV64IFD-LABEL: zext_or_constant:1038; RV64IFD: # %bb.0:1039; RV64IFD-NEXT: bgez a0, .LBB27_21040; RV64IFD-NEXT: # %bb.1:1041; RV64IFD-NEXT: lui a0, 1401042; RV64IFD-NEXT: addi a0, a0, 4171043; RV64IFD-NEXT: ret1044; RV64IFD-NEXT: .LBB27_2:1045; RV64IFD-NEXT: srli a0, a0, 631046; RV64IFD-NEXT: xori a0, a0, 11047; RV64IFD-NEXT: ret1048;1049; RV64ZICOND-LABEL: zext_or_constant:1050; RV64ZICOND: # %bb.0:1051; RV64ZICOND-NEXT: srli a0, a0, 631052; RV64ZICOND-NEXT: lui a1, 1401053; RV64ZICOND-NEXT: xori a2, a0, 11054; RV64ZICOND-NEXT: addi a1, a1, 4171055; RV64ZICOND-NEXT: czero.eqz a0, a1, a01056; RV64ZICOND-NEXT: or a0, a2, a01057; RV64ZICOND-NEXT: ret1058 %cmp = icmp sgt i32 %x, -11059 %ext = zext i1 %cmp to i321060 %cond = select i1 %cmp, i32 %ext, i32 5738571061 ret i32 %cond1062}1063 1064define i32 @zext_or_constant2(i32 signext %x) {1065; RV32I-LABEL: zext_or_constant2:1066; RV32I: # %bb.0:1067; RV32I-NEXT: bltz a0, .LBB28_21068; RV32I-NEXT: # %bb.1:1069; RV32I-NEXT: lui a0, 1401070; RV32I-NEXT: addi a0, a0, 4171071; RV32I-NEXT: ret1072; RV32I-NEXT: .LBB28_2:1073; RV32I-NEXT: srli a0, a0, 311074; RV32I-NEXT: xori a0, a0, 11075; RV32I-NEXT: ret1076;1077; RV32IF-LABEL: zext_or_constant2:1078; RV32IF: # %bb.0:1079; RV32IF-NEXT: bltz a0, .LBB28_21080; RV32IF-NEXT: # %bb.1:1081; RV32IF-NEXT: lui a0, 1401082; RV32IF-NEXT: addi a0, a0, 4171083; RV32IF-NEXT: ret1084; RV32IF-NEXT: .LBB28_2:1085; RV32IF-NEXT: srli a0, a0, 311086; RV32IF-NEXT: xori a0, a0, 11087; RV32IF-NEXT: ret1088;1089; RV32ZICOND-LABEL: zext_or_constant2:1090; RV32ZICOND: # %bb.0:1091; RV32ZICOND-NEXT: srli a0, a0, 311092; RV32ZICOND-NEXT: lui a1, 1401093; RV32ZICOND-NEXT: xori a2, a0, 11094; RV32ZICOND-NEXT: addi a1, a1, 4171095; RV32ZICOND-NEXT: czero.nez a1, a1, a01096; RV32ZICOND-NEXT: czero.eqz a0, a2, a01097; RV32ZICOND-NEXT: or a0, a1, a01098; RV32ZICOND-NEXT: ret1099;1100; RV32IXQCI-LABEL: zext_or_constant2:1101; RV32IXQCI: # %bb.0:1102; RV32IXQCI-NEXT: srli a2, a0, 311103; RV32IXQCI-NEXT: lui a1, 1401104; RV32IXQCI-NEXT: addi a1, a1, 4171105; RV32IXQCI-NEXT: bgez a0, .LBB28_21106; RV32IXQCI-NEXT: # %bb.1:1107; RV32IXQCI-NEXT: xori a1, a2, 11108; RV32IXQCI-NEXT: .LBB28_2:1109; RV32IXQCI-NEXT: mv a0, a11110; RV32IXQCI-NEXT: ret1111;1112; RV64I-LABEL: zext_or_constant2:1113; RV64I: # %bb.0:1114; RV64I-NEXT: bltz a0, .LBB28_21115; RV64I-NEXT: # %bb.1:1116; RV64I-NEXT: lui a0, 1401117; RV64I-NEXT: addi a0, a0, 4171118; RV64I-NEXT: ret1119; RV64I-NEXT: .LBB28_2:1120; RV64I-NEXT: srli a0, a0, 631121; RV64I-NEXT: xori a0, a0, 11122; RV64I-NEXT: ret1123;1124; RV64IFD-LABEL: zext_or_constant2:1125; RV64IFD: # %bb.0:1126; RV64IFD-NEXT: bltz a0, .LBB28_21127; RV64IFD-NEXT: # %bb.1:1128; RV64IFD-NEXT: lui a0, 1401129; RV64IFD-NEXT: addi a0, a0, 4171130; RV64IFD-NEXT: ret1131; RV64IFD-NEXT: .LBB28_2:1132; RV64IFD-NEXT: srli a0, a0, 631133; RV64IFD-NEXT: xori a0, a0, 11134; RV64IFD-NEXT: ret1135;1136; RV64ZICOND-LABEL: zext_or_constant2:1137; RV64ZICOND: # %bb.0:1138; RV64ZICOND-NEXT: srli a0, a0, 631139; RV64ZICOND-NEXT: lui a1, 1401140; RV64ZICOND-NEXT: xori a2, a0, 11141; RV64ZICOND-NEXT: addi a1, a1, 4171142; RV64ZICOND-NEXT: czero.nez a1, a1, a01143; RV64ZICOND-NEXT: czero.eqz a0, a2, a01144; RV64ZICOND-NEXT: or a0, a1, a01145; RV64ZICOND-NEXT: ret1146 %cmp = icmp sgt i32 %x, -11147 %ext = zext i1 %cmp to i321148 %cond = select i1 %cmp, i32 573857, i32 %ext1149 ret i32 %cond1150}1151 1152define i32 @sext_or_constant(i32 signext %x) {1153; RV32I-LABEL: sext_or_constant:1154; RV32I: # %bb.0:1155; RV32I-NEXT: bgez a0, .LBB29_21156; RV32I-NEXT: # %bb.1:1157; RV32I-NEXT: lui a0, 1401158; RV32I-NEXT: addi a0, a0, 4171159; RV32I-NEXT: ret1160; RV32I-NEXT: .LBB29_2:1161; RV32I-NEXT: srli a0, a0, 311162; RV32I-NEXT: addi a0, a0, -11163; RV32I-NEXT: ret1164;1165; RV32IF-LABEL: sext_or_constant:1166; RV32IF: # %bb.0:1167; RV32IF-NEXT: bgez a0, .LBB29_21168; RV32IF-NEXT: # %bb.1:1169; RV32IF-NEXT: lui a0, 1401170; RV32IF-NEXT: addi a0, a0, 4171171; RV32IF-NEXT: ret1172; RV32IF-NEXT: .LBB29_2:1173; RV32IF-NEXT: srli a0, a0, 311174; RV32IF-NEXT: addi a0, a0, -11175; RV32IF-NEXT: ret1176;1177; RV32ZICOND-LABEL: sext_or_constant:1178; RV32ZICOND: # %bb.0:1179; RV32ZICOND-NEXT: srli a0, a0, 311180; RV32ZICOND-NEXT: lui a1, 1401181; RV32ZICOND-NEXT: addi a2, a0, -11182; RV32ZICOND-NEXT: addi a1, a1, 4171183; RV32ZICOND-NEXT: czero.eqz a1, a1, a01184; RV32ZICOND-NEXT: czero.nez a0, a2, a01185; RV32ZICOND-NEXT: or a0, a0, a11186; RV32ZICOND-NEXT: ret1187;1188; RV32IXQCI-LABEL: sext_or_constant:1189; RV32IXQCI: # %bb.0:1190; RV32IXQCI-NEXT: srli a2, a0, 311191; RV32IXQCI-NEXT: lui a1, 1401192; RV32IXQCI-NEXT: addi a1, a1, 4171193; RV32IXQCI-NEXT: bltz a0, .LBB29_21194; RV32IXQCI-NEXT: # %bb.1:1195; RV32IXQCI-NEXT: addi a1, a2, -11196; RV32IXQCI-NEXT: .LBB29_2:1197; RV32IXQCI-NEXT: mv a0, a11198; RV32IXQCI-NEXT: ret1199;1200; RV64I-LABEL: sext_or_constant:1201; RV64I: # %bb.0:1202; RV64I-NEXT: bgez a0, .LBB29_21203; RV64I-NEXT: # %bb.1:1204; RV64I-NEXT: lui a0, 1401205; RV64I-NEXT: addi a0, a0, 4171206; RV64I-NEXT: ret1207; RV64I-NEXT: .LBB29_2:1208; RV64I-NEXT: srli a0, a0, 631209; RV64I-NEXT: addi a0, a0, -11210; RV64I-NEXT: ret1211;1212; RV64IFD-LABEL: sext_or_constant:1213; RV64IFD: # %bb.0:1214; RV64IFD-NEXT: bgez a0, .LBB29_21215; RV64IFD-NEXT: # %bb.1:1216; RV64IFD-NEXT: lui a0, 1401217; RV64IFD-NEXT: addi a0, a0, 4171218; RV64IFD-NEXT: ret1219; RV64IFD-NEXT: .LBB29_2:1220; RV64IFD-NEXT: srli a0, a0, 631221; RV64IFD-NEXT: addi a0, a0, -11222; RV64IFD-NEXT: ret1223;1224; RV64ZICOND-LABEL: sext_or_constant:1225; RV64ZICOND: # %bb.0:1226; RV64ZICOND-NEXT: srli a0, a0, 631227; RV64ZICOND-NEXT: lui a1, 1401228; RV64ZICOND-NEXT: addi a2, a0, -11229; RV64ZICOND-NEXT: addi a1, a1, 4171230; RV64ZICOND-NEXT: czero.eqz a1, a1, a01231; RV64ZICOND-NEXT: czero.nez a0, a2, a01232; RV64ZICOND-NEXT: or a0, a0, a11233; RV64ZICOND-NEXT: ret1234 %cmp = icmp sgt i32 %x, -11235 %ext = sext i1 %cmp to i321236 %cond = select i1 %cmp, i32 %ext, i32 5738571237 ret i32 %cond1238}1239 1240define i32 @sext_or_constant2(i32 signext %x) {1241; RV32I-LABEL: sext_or_constant2:1242; RV32I: # %bb.0:1243; RV32I-NEXT: bltz a0, .LBB30_21244; RV32I-NEXT: # %bb.1:1245; RV32I-NEXT: lui a0, 1401246; RV32I-NEXT: addi a0, a0, 4171247; RV32I-NEXT: ret1248; RV32I-NEXT: .LBB30_2:1249; RV32I-NEXT: srli a0, a0, 311250; RV32I-NEXT: addi a0, a0, -11251; RV32I-NEXT: ret1252;1253; RV32IF-LABEL: sext_or_constant2:1254; RV32IF: # %bb.0:1255; RV32IF-NEXT: bltz a0, .LBB30_21256; RV32IF-NEXT: # %bb.1:1257; RV32IF-NEXT: lui a0, 1401258; RV32IF-NEXT: addi a0, a0, 4171259; RV32IF-NEXT: ret1260; RV32IF-NEXT: .LBB30_2:1261; RV32IF-NEXT: srli a0, a0, 311262; RV32IF-NEXT: addi a0, a0, -11263; RV32IF-NEXT: ret1264;1265; RV32ZICOND-LABEL: sext_or_constant2:1266; RV32ZICOND: # %bb.0:1267; RV32ZICOND-NEXT: srli a0, a0, 311268; RV32ZICOND-NEXT: lui a1, 1401269; RV32ZICOND-NEXT: addi a2, a0, -11270; RV32ZICOND-NEXT: addi a1, a1, 4171271; RV32ZICOND-NEXT: czero.nez a1, a1, a01272; RV32ZICOND-NEXT: czero.eqz a0, a2, a01273; RV32ZICOND-NEXT: or a0, a1, a01274; RV32ZICOND-NEXT: ret1275;1276; RV32IXQCI-LABEL: sext_or_constant2:1277; RV32IXQCI: # %bb.0:1278; RV32IXQCI-NEXT: srli a2, a0, 311279; RV32IXQCI-NEXT: lui a1, 1401280; RV32IXQCI-NEXT: addi a1, a1, 4171281; RV32IXQCI-NEXT: bgez a0, .LBB30_21282; RV32IXQCI-NEXT: # %bb.1:1283; RV32IXQCI-NEXT: addi a1, a2, -11284; RV32IXQCI-NEXT: .LBB30_2:1285; RV32IXQCI-NEXT: mv a0, a11286; RV32IXQCI-NEXT: ret1287;1288; RV64I-LABEL: sext_or_constant2:1289; RV64I: # %bb.0:1290; RV64I-NEXT: bltz a0, .LBB30_21291; RV64I-NEXT: # %bb.1:1292; RV64I-NEXT: lui a0, 1401293; RV64I-NEXT: addi a0, a0, 4171294; RV64I-NEXT: ret1295; RV64I-NEXT: .LBB30_2:1296; RV64I-NEXT: srli a0, a0, 631297; RV64I-NEXT: addi a0, a0, -11298; RV64I-NEXT: ret1299;1300; RV64IFD-LABEL: sext_or_constant2:1301; RV64IFD: # %bb.0:1302; RV64IFD-NEXT: bltz a0, .LBB30_21303; RV64IFD-NEXT: # %bb.1:1304; RV64IFD-NEXT: lui a0, 1401305; RV64IFD-NEXT: addi a0, a0, 4171306; RV64IFD-NEXT: ret1307; RV64IFD-NEXT: .LBB30_2:1308; RV64IFD-NEXT: srli a0, a0, 631309; RV64IFD-NEXT: addi a0, a0, -11310; RV64IFD-NEXT: ret1311;1312; RV64ZICOND-LABEL: sext_or_constant2:1313; RV64ZICOND: # %bb.0:1314; RV64ZICOND-NEXT: srli a0, a0, 631315; RV64ZICOND-NEXT: lui a1, 1401316; RV64ZICOND-NEXT: addi a2, a0, -11317; RV64ZICOND-NEXT: addi a1, a1, 4171318; RV64ZICOND-NEXT: czero.nez a1, a1, a01319; RV64ZICOND-NEXT: czero.eqz a0, a2, a01320; RV64ZICOND-NEXT: or a0, a1, a01321; RV64ZICOND-NEXT: ret1322 %cmp = icmp sgt i32 %x, -11323 %ext = sext i1 %cmp to i321324 %cond = select i1 %cmp, i32 573857, i32 %ext1325 ret i32 %cond1326}1327 1328 1329define i32 @select_0_6(i32 signext %x) {1330; RV32-LABEL: select_0_6:1331; RV32: # %bb.0:1332; RV32-NEXT: srai a0, a0, 21333; RV32-NEXT: srli a0, a0, 301334; RV32-NEXT: slli a0, a0, 11335; RV32-NEXT: ret1336;1337; RV32IXQCI-LABEL: select_0_6:1338; RV32IXQCI: # %bb.0:1339; RV32IXQCI-NEXT: li a1, 61340; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 01341; RV32IXQCI-NEXT: mv a0, a11342; RV32IXQCI-NEXT: ret1343;1344; RV64-LABEL: select_0_6:1345; RV64: # %bb.0:1346; RV64-NEXT: srai a0, a0, 21347; RV64-NEXT: srli a0, a0, 621348; RV64-NEXT: slli a0, a0, 11349; RV64-NEXT: ret1350 %cmp = icmp sgt i32 %x, -11351 %cond = select i1 %cmp, i32 0, i32 61352 ret i32 %cond1353}1354 1355define i32 @select_6_0(i32 signext %x) {1356; RV32-LABEL: select_6_0:1357; RV32: # %bb.0:1358; RV32-NEXT: srli a0, a0, 311359; RV32-NEXT: addi a0, a0, -11360; RV32-NEXT: andi a0, a0, 61361; RV32-NEXT: ret1362;1363; RV32IXQCI-LABEL: select_6_0:1364; RV32IXQCI: # %bb.0:1365; RV32IXQCI-NEXT: li a1, 01366; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 61367; RV32IXQCI-NEXT: mv a0, a11368; RV32IXQCI-NEXT: ret1369;1370; RV64-LABEL: select_6_0:1371; RV64: # %bb.0:1372; RV64-NEXT: srli a0, a0, 631373; RV64-NEXT: addi a0, a0, -11374; RV64-NEXT: andi a0, a0, 61375; RV64-NEXT: ret1376 %cmp = icmp sgt i32 %x, -11377 %cond = select i1 %cmp, i32 6, i32 01378 ret i32 %cond1379}1380 1381define i32 @select_0_394(i32 signext %x) {1382; RV32-LABEL: select_0_394:1383; RV32: # %bb.0:1384; RV32-NEXT: srai a0, a0, 311385; RV32-NEXT: andi a0, a0, 3941386; RV32-NEXT: ret1387;1388; RV32IXQCI-LABEL: select_0_394:1389; RV32IXQCI: # %bb.0:1390; RV32IXQCI-NEXT: li a1, 3941391; RV32IXQCI-NEXT: qc.ligei a1, a0, 0, 01392; RV32IXQCI-NEXT: mv a0, a11393; RV32IXQCI-NEXT: ret1394;1395; RV64-LABEL: select_0_394:1396; RV64: # %bb.0:1397; RV64-NEXT: srai a0, a0, 631398; RV64-NEXT: andi a0, a0, 3941399; RV64-NEXT: ret1400 %cmp = icmp sgt i32 %x, -11401 %cond = select i1 %cmp, i32 0, i32 3941402 ret i32 %cond1403}1404 1405define i32 @select_394_0(i32 signext %x) {1406; RV32-LABEL: select_394_0:1407; RV32: # %bb.0:1408; RV32-NEXT: srli a0, a0, 311409; RV32-NEXT: addi a0, a0, -11410; RV32-NEXT: andi a0, a0, 3941411; RV32-NEXT: ret1412;1413; RV32IXQCI-LABEL: select_394_0:1414; RV32IXQCI: # %bb.0:1415; RV32IXQCI-NEXT: li a1, 3941416; RV32IXQCI-NEXT: qc.lilti a1, a0, 0, 01417; RV32IXQCI-NEXT: mv a0, a11418; RV32IXQCI-NEXT: ret1419;1420; RV64-LABEL: select_394_0:1421; RV64: # %bb.0:1422; RV64-NEXT: srli a0, a0, 631423; RV64-NEXT: addi a0, a0, -11424; RV64-NEXT: andi a0, a0, 3941425; RV64-NEXT: ret1426 %cmp = icmp sgt i32 %x, -11427 %cond = select i1 %cmp, i32 394, i32 01428 ret i32 %cond1429}1430