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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=finalize-isel -simplify-mir -o - %s \3# RUN: | FileCheck -check-prefix=RV32I %s4# RUN: llc -mtriple=riscv64 -run-pass=finalize-isel -simplify-mir -o - %s \5# RUN: | FileCheck -check-prefix=RV64I %s6# RUN: llc -mtriple=riscv32 -passes=finalize-isel -simplify-mir -o - %s \7# RUN: | FileCheck -check-prefix=RV32I %s8# RUN: llc -mtriple=riscv64 -passes=finalize-isel -simplify-mir -o - %s \9# RUN: | FileCheck -check-prefix=RV64I %s10 11# Provide dummy definitions of functions and just enough metadata to create a12# DBG_VALUE.13--- |14 define void @cmov_interleaved_bad() {15 ret void16 }17 define void @cmov_interleaved_debug_value() {18 ret void19 }20...21---22# Here we have a sequence of select instructions with a non-select instruction23# in the middle. Because the non-select depends on the result of a previous24# select, we cannot optimize the sequence to share control-flow.25name: cmov_interleaved_bad26alignment: 427tracksRegLiveness: true28registers:29 - { id: 0, class: gpr }30 - { id: 1, class: gpr }31 - { id: 2, class: gpr }32 - { id: 3, class: gpr }33 - { id: 4, class: gpr }34 - { id: 5, class: gpr }35 - { id: 6, class: gpr }36 - { id: 7, class: gpr }37 - { id: 8, class: gpr }38 - { id: 9, class: gpr }39 - { id: 10, class: gpr }40liveins:41 - { reg: '$x10', virtual-reg: '%0' }42 - { reg: '$x11', virtual-reg: '%1' }43 - { reg: '$x12', virtual-reg: '%2' }44 - { reg: '$x13', virtual-reg: '%3' }45body: |46 bb.0:47 liveins: $x10, $x11, $x12, $x1348 49 ; RV32I-LABEL: name: cmov_interleaved_bad50 ; RV32I: successors: %bb.1, %bb.251 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x1352 ; RV32I-NEXT: {{ $}}53 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1354 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1255 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x1156 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x1057 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 158 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x059 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.260 ; RV32I-NEXT: {{ $}}61 ; RV32I-NEXT: .1:62 ; RV32I-NEXT: {{ $}}63 ; RV32I-NEXT: .2:64 ; RV32I-NEXT: successors: %bb.3, %bb.465 ; RV32I-NEXT: {{ $}}66 ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.167 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 168 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.469 ; RV32I-NEXT: {{ $}}70 ; RV32I-NEXT: .3:71 ; RV32I-NEXT: {{ $}}72 ; RV32I-NEXT: .4:73 ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.374 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]75 ; RV32I-NEXT: $x10 = COPY [[ADD]]76 ; RV32I-NEXT: PseudoRET implicit $x1077 ; RV64I-LABEL: name: cmov_interleaved_bad78 ; RV64I: successors: %bb.1, %bb.279 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x1380 ; RV64I-NEXT: {{ $}}81 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1382 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1283 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x1184 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x1085 ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 186 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x087 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.288 ; RV64I-NEXT: {{ $}}89 ; RV64I-NEXT: .1:90 ; RV64I-NEXT: {{ $}}91 ; RV64I-NEXT: .2:92 ; RV64I-NEXT: successors: %bb.3, %bb.493 ; RV64I-NEXT: {{ $}}94 ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.195 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 196 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.497 ; RV64I-NEXT: {{ $}}98 ; RV64I-NEXT: .3:99 ; RV64I-NEXT: {{ $}}100 ; RV64I-NEXT: .4:101 ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.2, [[COPY1]], %bb.3102 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]103 ; RV64I-NEXT: $x10 = COPY [[ADD]]104 ; RV64I-NEXT: PseudoRET implicit $x10105 %3:gpr = COPY $x13106 %2:gpr = COPY $x12107 %1:gpr = COPY $x11108 %0:gpr = COPY $x10109 %5:gpr = ANDI %0, 1110 %6:gpr = COPY $x0111 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2112 %8:gpr = ADDI %7, 1113 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2114 %10:gpr = ADD %7, killed %9115 $x10 = COPY %10116 PseudoRET implicit $x10117 118...119---120# Demonstrate that debug info associated with selects is correctly moved to121# the tail basic block, while debug info associated with non-selects is left122# in the head basic block.123name: cmov_interleaved_debug_value124alignment: 4125tracksRegLiveness: true126registers:127 - { id: 0, class: gpr }128 - { id: 1, class: gpr }129 - { id: 2, class: gpr }130 - { id: 3, class: gpr }131 - { id: 4, class: gpr }132 - { id: 5, class: gpr }133 - { id: 6, class: gpr }134 - { id: 7, class: gpr }135 - { id: 8, class: gpr }136 - { id: 9, class: gpr }137 - { id: 10, class: gpr }138liveins:139 - { reg: '$x10', virtual-reg: '%0' }140 - { reg: '$x11', virtual-reg: '%1' }141 - { reg: '$x12', virtual-reg: '%2' }142 - { reg: '$x13', virtual-reg: '%3' }143body: |144 bb.0:145 liveins: $x10, $x11, $x12, $x13146 147 ; RV32I-LABEL: name: cmov_interleaved_debug_value148 ; RV32I: successors: %bb.1, %bb.2149 ; RV32I-NEXT: liveins: $x10, $x11, $x12, $x13150 ; RV32I-NEXT: {{ $}}151 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13152 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12153 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11154 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10155 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1156 ; RV32I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0157 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1158 ; RV32I-NEXT: DBG_VALUE [[ADDI]], $noreg159 ; RV32I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2160 ; RV32I-NEXT: {{ $}}161 ; RV32I-NEXT: .1:162 ; RV32I-NEXT: {{ $}}163 ; RV32I-NEXT: .2:164 ; RV32I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1165 ; RV32I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1166 ; RV32I-NEXT: DBG_VALUE [[PHI]], $noreg167 ; RV32I-NEXT: DBG_VALUE [[PHI1]], $noreg168 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]169 ; RV32I-NEXT: $x10 = COPY [[ADD]]170 ; RV32I-NEXT: PseudoRET implicit $x10171 ; RV64I-LABEL: name: cmov_interleaved_debug_value172 ; RV64I: successors: %bb.1, %bb.2173 ; RV64I-NEXT: liveins: $x10, $x11, $x12, $x13174 ; RV64I-NEXT: {{ $}}175 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13176 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12177 ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11178 ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10179 ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY3]], 1180 ; RV64I-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0181 ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY3]], 1182 ; RV64I-NEXT: DBG_VALUE [[ADDI]], $noreg183 ; RV64I-NEXT: BNE [[ANDI]], [[COPY4]], %bb.2184 ; RV64I-NEXT: {{ $}}185 ; RV64I-NEXT: .1:186 ; RV64I-NEXT: {{ $}}187 ; RV64I-NEXT: .2:188 ; RV64I-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, [[COPY1]], %bb.1189 ; RV64I-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1190 ; RV64I-NEXT: DBG_VALUE [[PHI]], $noreg191 ; RV64I-NEXT: DBG_VALUE [[PHI1]], $noreg192 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]193 ; RV64I-NEXT: $x10 = COPY [[ADD]]194 ; RV64I-NEXT: PseudoRET implicit $x10195 %3:gpr = COPY $x13196 %2:gpr = COPY $x12197 %1:gpr = COPY $x11198 %0:gpr = COPY $x10199 %5:gpr = ANDI %0, 1200 %6:gpr = COPY $x0201 %7:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %1, %2202 DBG_VALUE %7, $noreg203 %8:gpr = ADDI %0, 1204 DBG_VALUE %8, $noreg205 %9:gpr = Select_GPR_Using_CC_GPR %5, %6, 1, %3, %2206 DBG_VALUE %9, $noreg207 %10:gpr = ADD %7, killed %9208 $x10 = COPY %10209 PseudoRET implicit $x10210 211...212---213