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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=RV32I %s4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=RV64I %s6; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \7; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s8 9;; There are a few different ways to lower (select (or A, B), X, Y). This test10;; ensures that we do so with as few branches as possible.11 12define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {13; RV32I-LABEL: select_of_or:14; RV32I: # %bb.0:15; RV32I-NEXT: or a1, a0, a116; RV32I-NEXT: mv a0, a217; RV32I-NEXT: bnez a1, .LBB0_218; RV32I-NEXT: # %bb.1:19; RV32I-NEXT: mv a0, a320; RV32I-NEXT: .LBB0_2:21; RV32I-NEXT: ret22;23; RV64I-LABEL: select_of_or:24; RV64I: # %bb.0:25; RV64I-NEXT: or a1, a0, a126; RV64I-NEXT: mv a0, a227; RV64I-NEXT: bnez a1, .LBB0_228; RV64I-NEXT: # %bb.1:29; RV64I-NEXT: mv a0, a330; RV64I-NEXT: .LBB0_2:31; RV64I-NEXT: ret32;33; RV64I-CCMOV-LABEL: select_of_or:34; RV64I-CCMOV: # %bb.0:35; RV64I-CCMOV-NEXT: or a0, a0, a136; RV64I-CCMOV-NEXT: mips.ccmov a0, a0, a2, a337; RV64I-CCMOV-NEXT: ret38 %1 = or i1 %a, %b39 %2 = select i1 %1, i32 %c, i32 %d40 ret i32 %241}42 43declare signext i32 @either() nounwind44declare signext i32 @neither() nounwind45 46define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {47; RV32I-LABEL: if_of_or:48; RV32I: # %bb.0:49; RV32I-NEXT: addi sp, sp, -1650; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill51; RV32I-NEXT: bnez a0, .LBB1_352; RV32I-NEXT: # %bb.1:53; RV32I-NEXT: bnez a1, .LBB1_354; RV32I-NEXT: # %bb.2: # %if.else55; RV32I-NEXT: call neither56; RV32I-NEXT: j .LBB1_457; RV32I-NEXT: .LBB1_3: # %if.then58; RV32I-NEXT: call either59; RV32I-NEXT: .LBB1_4: # %if.end60; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload61; RV32I-NEXT: addi sp, sp, 1662; RV32I-NEXT: ret63;64; RV64I-LABEL: if_of_or:65; RV64I: # %bb.0:66; RV64I-NEXT: addi sp, sp, -1667; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill68; RV64I-NEXT: bnez a0, .LBB1_369; RV64I-NEXT: # %bb.1:70; RV64I-NEXT: bnez a1, .LBB1_371; RV64I-NEXT: # %bb.2: # %if.else72; RV64I-NEXT: call neither73; RV64I-NEXT: j .LBB1_474; RV64I-NEXT: .LBB1_3: # %if.then75; RV64I-NEXT: call either76; RV64I-NEXT: .LBB1_4: # %if.end77; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload78; RV64I-NEXT: addi sp, sp, 1679; RV64I-NEXT: ret80;81; RV64I-CCMOV-LABEL: if_of_or:82; RV64I-CCMOV: # %bb.0:83; RV64I-CCMOV-NEXT: addi sp, sp, -1684; RV64I-CCMOV-NEXT: sd ra, 8(sp) # 8-byte Folded Spill85; RV64I-CCMOV-NEXT: bnez a0, .LBB1_386; RV64I-CCMOV-NEXT: # %bb.1:87; RV64I-CCMOV-NEXT: bnez a1, .LBB1_388; RV64I-CCMOV-NEXT: # %bb.2: # %if.else89; RV64I-CCMOV-NEXT: call neither90; RV64I-CCMOV-NEXT: j .LBB1_491; RV64I-CCMOV-NEXT: .LBB1_3: # %if.then92; RV64I-CCMOV-NEXT: call either93; RV64I-CCMOV-NEXT: .LBB1_4: # %if.end94; RV64I-CCMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload95; RV64I-CCMOV-NEXT: addi sp, sp, 1696; RV64I-CCMOV-NEXT: ret97 %1 = or i1 %a, %b98 br i1 %1, label %if.then, label %if.else99 100if.then:101 %2 = tail call i32 @either()102 br label %if.end103 104if.else:105 %3 = tail call i32 @neither()106 br label %if.end107 108if.end:109 %4 = phi i32 [%2, %if.then], [%3, %if.else]110 ret i32 %4111}112