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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7 8define i32 @from_cmpeq(i32 %xx, i32 %y) {9; RV32I-LABEL: from_cmpeq:10; RV32I: # %bb.0:11; RV32I-NEXT: addi a0, a0, -912; RV32I-NEXT: seqz a0, a013; RV32I-NEXT: and a0, a0, a114; RV32I-NEXT: ret15;16; RV64I-LABEL: from_cmpeq:17; RV64I: # %bb.0:18; RV64I-NEXT: addiw a0, a0, -919; RV64I-NEXT: seqz a0, a020; RV64I-NEXT: and a0, a0, a121; RV64I-NEXT: ret22 %x = icmp eq i32 %xx, 923 %masked = and i32 %y, 124 25 %r = select i1 %x, i32 %masked, i32 026 ret i32 %r27}28 29define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) {30; RV32I-LABEL: from_cmpeq_fail_bad_andmask:31; RV32I: # %bb.0:32; RV32I-NEXT: addi a0, a0, -933; RV32I-NEXT: snez a0, a034; RV32I-NEXT: addi a0, a0, -135; RV32I-NEXT: and a0, a1, a036; RV32I-NEXT: andi a0, a0, 337; RV32I-NEXT: ret38;39; RV64I-LABEL: from_cmpeq_fail_bad_andmask:40; RV64I: # %bb.0:41; RV64I-NEXT: addiw a0, a0, -942; RV64I-NEXT: snez a0, a043; RV64I-NEXT: addi a0, a0, -144; RV64I-NEXT: and a0, a1, a045; RV64I-NEXT: andi a0, a0, 346; RV64I-NEXT: ret47 %x = icmp eq i32 %xx, 948 %masked = and i32 %y, 349 %r = select i1 %x, i32 %masked, i32 050 ret i32 %r51}52 53define i32 @from_i1(i1 %x, i32 %y) {54; RV32I-LABEL: from_i1:55; RV32I: # %bb.0:56; RV32I-NEXT: and a0, a0, a157; RV32I-NEXT: andi a0, a0, 158; RV32I-NEXT: ret59;60; RV64I-LABEL: from_i1:61; RV64I: # %bb.0:62; RV64I-NEXT: and a0, a0, a163; RV64I-NEXT: andi a0, a0, 164; RV64I-NEXT: ret65 %masked = and i32 %y, 166 %r = select i1 %x, i32 %masked, i32 067 ret i32 %r68}69 70define i32 @from_trunc_i8(i8 %xx, i32 %y) {71; RV32I-LABEL: from_trunc_i8:72; RV32I: # %bb.0:73; RV32I-NEXT: and a0, a0, a174; RV32I-NEXT: andi a0, a0, 175; RV32I-NEXT: ret76;77; RV64I-LABEL: from_trunc_i8:78; RV64I: # %bb.0:79; RV64I-NEXT: and a0, a0, a180; RV64I-NEXT: andi a0, a0, 181; RV64I-NEXT: ret82 %masked = and i32 %y, 183 %x = trunc i8 %xx to i184 %r = select i1 %x, i32 %masked, i32 085 ret i32 %r86}87 88define i32 @from_trunc_i64(i64 %xx, i32 %y) {89; RV32I-LABEL: from_trunc_i64:90; RV32I: # %bb.0:91; RV32I-NEXT: and a0, a0, a292; RV32I-NEXT: andi a0, a0, 193; RV32I-NEXT: ret94;95; RV64I-LABEL: from_trunc_i64:96; RV64I: # %bb.0:97; RV64I-NEXT: and a0, a0, a198; RV64I-NEXT: andi a0, a0, 199; RV64I-NEXT: ret100 %masked = and i32 %y, 1101 %x = trunc i64 %xx to i1102 %r = select i1 %x, i32 %masked, i32 0103 ret i32 %r104}105 106define i32 @from_i1_fail_bad_select0(i1 %x, i32 %y) {107; RV32I-LABEL: from_i1_fail_bad_select0:108; RV32I: # %bb.0:109; RV32I-NEXT: andi a0, a0, 1110; RV32I-NEXT: bnez a0, .LBB5_2111; RV32I-NEXT: # %bb.1:112; RV32I-NEXT: li a0, 1113; RV32I-NEXT: ret114; RV32I-NEXT: .LBB5_2:115; RV32I-NEXT: andi a0, a1, 1116; RV32I-NEXT: ret117;118; RV64I-LABEL: from_i1_fail_bad_select0:119; RV64I: # %bb.0:120; RV64I-NEXT: andi a0, a0, 1121; RV64I-NEXT: bnez a0, .LBB5_2122; RV64I-NEXT: # %bb.1:123; RV64I-NEXT: li a0, 1124; RV64I-NEXT: ret125; RV64I-NEXT: .LBB5_2:126; RV64I-NEXT: andi a0, a1, 1127; RV64I-NEXT: ret128 %masked = and i32 %y, 1129 %r = select i1 %x, i32 %masked, i32 1130 ret i32 %r131}132 133define i32 @from_i1_fail_bad_select1(i1 %x, i32 %y) {134; RV32I-LABEL: from_i1_fail_bad_select1:135; RV32I: # %bb.0:136; RV32I-NEXT: addi a0, a0, -1137; RV32I-NEXT: and a0, a1, a0138; RV32I-NEXT: andi a0, a0, 1139; RV32I-NEXT: ret140;141; RV64I-LABEL: from_i1_fail_bad_select1:142; RV64I: # %bb.0:143; RV64I-NEXT: addi a0, a0, -1144; RV64I-NEXT: and a0, a1, a0145; RV64I-NEXT: andi a0, a0, 1146; RV64I-NEXT: ret147 %masked = and i32 %y, 1148 %r = select i1 %x, i32 0, i32 %masked149 ret i32 %r150}151